Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	24	72	75.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	24	72	75.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70450

1

T1

1

T2

403

T3

6

auto[1]

79250

1

T1

2

T2

850

T3

6

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	10994	1			T2	82		T17	4		T19	9
endpoints[0x1]	14322	1			T2	97		T17	8		T27	4
endpoints[0x2]	14469	1			T2	105		T27	8		T4	12
endpoints[0x3]	10728	1			T2	98		T4	12		T36	3
endpoints[0x4]	10996	1			T2	115		T4	12		T5	18
endpoints[0x5]	12313	1			T2	102		T4	12		T5	18
endpoints[0x6]	12783	1			T1	3		T2	112		T21	4
endpoints[0x7]	11519	1			T2	105		T18	1		T20	9
endpoints[0x8]	12375	1			T2	104		T61	4		T4	12
endpoints[0x9]	12368	1			T2	106		T61	9		T36	3
endpoints[0xa]	13530	1			T2	122		T3	4		T36	3
endpoints[0xb]	13303	1			T2	105		T3	8		T19	4

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	201	1			T106	5		T107	1		T108	1
ack	39048	1			T1	1		T2	425		T3	3
data1	51649	1			T2	410		T3	6		T17	6
data0	58747	1			T1	2		T2	418		T3	3

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	24	72	75.00	24

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	[auto[0]]	*	--	--	24

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[1]	endpoints[0x0]	15	1			T346	1		T347	1		T348	1
nak	auto[1]	endpoints[0x1]	20	1			T106	1		T349	1		T348	1
nak	auto[1]	endpoints[0x2]	18	1			T107	1		T349	1		T348	1
nak	auto[1]	endpoints[0x3]	18	1			T346	2		T350	2		T351	1
nak	auto[1]	endpoints[0x4]	14	1			T349	4		T347	1		T352	1
nak	auto[1]	endpoints[0x5]	17	1			T106	1		T350	2		T348	2
nak	auto[1]	endpoints[0x6]	21	1			T106	1		T353	1		T351	1
nak	auto[1]	endpoints[0x7]	15	1			T106	1		T346	1		T350	1
nak	auto[1]	endpoints[0x8]	13	1			T346	1		T350	1		T349	1
nak	auto[1]	endpoints[0x9]	20	1			T106	1		T108	1		T354	1
nak	auto[1]	endpoints[0xa]	16	1			T350	1		T353	1		T351	1
nak	auto[1]	endpoints[0xb]	14	1			T351	1		T348	1		T355	1
ack	auto[1]	endpoints[0x0]	3103	1			T2	26		T17	1		T19	2
ack	auto[1]	endpoints[0x1]	3494	1			T2	30		T17	2		T27	1
ack	auto[1]	endpoints[0x2]	3441	1			T2	38		T27	2		T4	4
ack	auto[1]	endpoints[0x3]	3058	1			T2	36		T4	4		T36	1
ack	auto[1]	endpoints[0x4]	3228	1			T2	42		T4	4		T5	6
ack	auto[1]	endpoints[0x5]	3154	1			T2	35		T4	4		T5	6
ack	auto[1]	endpoints[0x6]	3312	1			T1	1		T2	38		T21	1
ack	auto[1]	endpoints[0x7]	3267	1			T2	36		T21	2		T22	1
ack	auto[1]	endpoints[0x8]	3251	1			T2	37		T61	1		T4	4
ack	auto[1]	endpoints[0x9]	3231	1			T2	35		T61	2		T36	1
ack	auto[1]	endpoints[0xa]	3248	1			T2	42		T3	1		T36	1
ack	auto[1]	endpoints[0xb]	3261	1			T2	30		T3	2		T19	1
data1	auto[0]	endpoints[0x0]	1916	1			T2	15		T17	1		T19	2
data1	auto[0]	endpoints[0x1]	3069	1			T2	18		T17	2		T27	1
data1	auto[0]	endpoints[0x2]	3330	1			T2	14		T27	2		T4	2
data1	auto[0]	endpoints[0x3]	1842	1			T2	13		T4	2		T6	15
data1	auto[0]	endpoints[0x4]	1848	1			T2	15		T4	2		T5	1
data1	auto[0]	endpoints[0x5]	2502	1			T2	16		T5	3		T127	2
data1	auto[0]	endpoints[0x6]	2625	1			T2	18		T21	1		T5	3
data1	auto[0]	endpoints[0x7]	2128	1			T2	16		T20	4		T21	2
data1	auto[0]	endpoints[0x8]	2467	1			T2	15		T61	1		T4	2
data1	auto[0]	endpoints[0x9]	2483	1			T2	18		T61	2		T50	1
data1	auto[0]	endpoints[0xa]	3050	1			T2	19		T3	1		T50	3
data1	auto[0]	endpoints[0xb]	2937	1			T2	22		T3	2		T19	1
data1	auto[1]	endpoints[0x0]	1711	1			T2	13		T17	1		T19	2
data1	auto[1]	endpoints[0x1]	1982	1			T2	15		T17	2		T27	1
data1	auto[1]	endpoints[0x2]	1929	1			T2	19		T27	2		T4	2
data1	auto[1]	endpoints[0x3]	1686	1			T2	18		T4	2		T6	35
data1	auto[1]	endpoints[0x4]	1747	1			T2	21		T4	2		T5	4
data1	auto[1]	endpoints[0x5]	1720	1			T2	17		T4	3		T5	3
data1	auto[1]	endpoints[0x6]	1798	1			T2	19		T21	1		T4	3
data1	auto[1]	endpoints[0x7]	1756	1			T2	18		T21	2		T22	1
data1	auto[1]	endpoints[0x8]	1770	1			T2	18		T61	1		T4	2
data1	auto[1]	endpoints[0x9]	1793	1			T2	17		T61	2		T50	6
data1	auto[1]	endpoints[0xa]	1785	1			T2	21		T3	1		T50	4
data1	auto[1]	endpoints[0xb]	1775	1			T2	15		T3	2		T19	1
data0	auto[0]	endpoints[0x0]	2782	1			T2	15		T17	1		T19	2
data0	auto[0]	endpoints[0x1]	4122	1			T2	19		T17	2		T27	1
data0	auto[0]	endpoints[0x2]	4162	1			T2	15		T27	2		T4	2
data0	auto[0]	endpoints[0x3]	2669	1			T2	13		T4	2		T36	1
data0	auto[0]	endpoints[0x4]	2607	1			T2	16		T4	2		T5	5
data0	auto[0]	endpoints[0x5]	3402	1			T2	16		T4	4		T5	3
data0	auto[0]	endpoints[0x6]	3452	1			T1	1		T2	18		T21	1
data0	auto[0]	endpoints[0x7]	2792	1			T2	17		T18	1		T20	5
data0	auto[0]	endpoints[0x8]	3337	1			T2	15		T61	1		T4	2
data0	auto[0]	endpoints[0x9]	3306	1			T2	18		T61	3		T36	1
data0	auto[0]	endpoints[0xa]	3838	1			T2	19		T3	1		T36	1
data0	auto[0]	endpoints[0xb]	3779	1			T2	23		T3	2		T19	1
data0	auto[1]	endpoints[0x0]	1459	1			T2	13		T19	1		T4	2
data0	auto[1]	endpoints[0x1]	1629	1			T2	15		T4	2		T36	1
data0	auto[1]	endpoints[0x2]	1585	1			T2	19		T4	2		T5	3
data0	auto[1]	endpoints[0x3]	1448	1			T2	18		T4	2		T36	1
data0	auto[1]	endpoints[0x4]	1550	1			T2	21		T4	2		T5	2
data0	auto[1]	endpoints[0x5]	1512	1			T2	18		T4	1		T5	3
data0	auto[1]	endpoints[0x6]	1572	1			T1	1		T2	19		T4	1
data0	auto[1]	endpoints[0x7]	1557	1			T2	18		T22	2		T4	2
data0	auto[1]	endpoints[0x8]	1534	1			T2	19		T4	2		T5	2
data0	auto[1]	endpoints[0x9]	1533	1			T2	18		T36	1		T50	1
data0	auto[1]	endpoints[0xa]	1587	1			T2	21		T36	1		T50	3
data0	auto[1]	endpoints[0xb]	1533	1			T2	15		T36	1		T50	4