Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	0	16	100.00	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8582

1

T83

3

T128

1

T138

2

auto[1]

54778

1

T1

1

T2

425

T3

4

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55319

1

T1

1

T2

425

T3

4

auto[1]

8041

1

T18

1

T83

2

T121

1

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57038

1

T1

1

T2

425

T3

4

auto[1]

6322

1

T83

2

T138

2

T129

3

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

4435

1

T138

1

T132

8

T134

3

pkt_types[PidTypeInToken]

58925

1

T1

1

T2

425

T3

4

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

1347

1

T134

1

T135

2

T114

19

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

788

1

T130

2

T114

17

T111

8

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

107

1

T132

5

T134

2

T135

2

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

18

1

T384

1

T449

1

T397

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

1324

1

T135

2

T114

12

T363

2

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

740

1

T114

3

T430

1

T384

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

95

1

T138

1

T132

3

T135

2

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

16

1

T461

1

T412

1

T454

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

3798

1

T83

1

T128

1

T138

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2425

1

T129

3

T114

58

T430

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[0]

54

1

T83

1

T138

1

T430

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[1]

45

1

T83

1

T430

1

T380

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

42650

1

T1

1

T2

425

T3

4

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2247

1

T83

1

T138

1

T125

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

7663

1

T18

1

T121

1

T122

14

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[1]

43

1

T138

1

T503

1

T115

1