Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	172192	1			T1	4		T2	2		T3	5
all_pins[1]	172192	1			T1	4		T2	2		T3	5
all_pins[2]	172192	1			T1	4		T2	2		T3	5
all_pins[3]	172192	1			T1	4		T2	2		T3	5
all_pins[4]	172192	1			T1	4		T2	2		T3	5
all_pins[5]	172192	1			T1	4		T2	2		T3	5
all_pins[6]	172192	1			T1	4		T2	2		T3	5
all_pins[7]	172192	1			T1	4		T2	2		T3	5
all_pins[8]	172192	1			T1	4		T2	2		T3	5
all_pins[9]	172192	1			T1	4		T2	2		T3	5
all_pins[10]	172192	1			T1	4		T2	2		T3	5
all_pins[11]	172192	1			T1	4		T2	2		T3	5
all_pins[12]	172192	1			T1	4		T2	2		T3	5
all_pins[13]	172192	1			T1	4		T2	2		T3	5
all_pins[14]	172192	1			T1	4		T2	2		T3	5
all_pins[15]	172192	1			T1	4		T2	2		T3	5
all_pins[16]	172192	1			T1	4		T2	2		T3	5
all_pins[17]	172192	1			T1	4		T2	2		T3	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5507842	1			T1	127		T2	64		T3	160
values[0x1]	2302	1			T1	1		T36	12		T37	1
transitions[0x0=>0x1]	2034	1			T1	1		T36	12		T37	1
transitions[0x1=>0x0]	2034	1			T1	1		T36	12		T37	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	172091	1			T1	4		T2	2		T3	5
all_pins[0]	values[0x1]	101	1			T360	1		T361	1		T362	1
all_pins[0]	transitions[0x0=>0x1]	89	1			T360	1		T361	1		T362	1
all_pins[0]	transitions[0x1=>0x0]	866	1			T1	1		T36	12		T37	1
all_pins[1]	values[0x0]	171314	1			T1	3		T2	2		T3	5
all_pins[1]	values[0x1]	878	1			T1	1		T36	12		T37	1
all_pins[1]	transitions[0x0=>0x1]	858	1			T1	1		T36	12		T37	1
all_pins[1]	transitions[0x1=>0x0]	110	1			T33	1		T55	1		T56	1
all_pins[2]	values[0x0]	172062	1			T1	4		T2	2		T3	5
all_pins[2]	values[0x1]	130	1			T33	1		T55	1		T56	1
all_pins[2]	transitions[0x0=>0x1]	112	1			T33	1		T55	1		T56	1
all_pins[2]	transitions[0x1=>0x0]	41	1			T58	1		T248	1		T251	2
all_pins[3]	values[0x0]	172133	1			T1	4		T2	2		T3	5
all_pins[3]	values[0x1]	59	1			T58	1		T248	3		T336	1
all_pins[3]	transitions[0x0=>0x1]	44	1			T58	1		T248	3		T336	1
all_pins[3]	transitions[0x1=>0x0]	44	1			T59	1		T249	1		T250	2
all_pins[4]	values[0x0]	172133	1			T1	4		T2	2		T3	5
all_pins[4]	values[0x1]	59	1			T59	1		T249	1		T250	2
all_pins[4]	transitions[0x0=>0x1]	47	1			T59	1		T336	2		T357	3
all_pins[4]	transitions[0x1=>0x0]	51	1			T248	1		T249	1		T250	1
all_pins[5]	values[0x0]	172129	1			T1	4		T2	2		T3	5
all_pins[5]	values[0x1]	63	1			T248	1		T249	2		T250	3
all_pins[5]	transitions[0x0=>0x1]	38	1			T249	1		T250	3		T251	1
all_pins[5]	transitions[0x1=>0x0]	115	1			T34	1		T35	1		T60	1
all_pins[6]	values[0x0]	172052	1			T1	4		T2	2		T3	5
all_pins[6]	values[0x1]	140	1			T34	1		T35	1		T60	1
all_pins[6]	transitions[0x0=>0x1]	121	1			T34	1		T35	1		T60	1
all_pins[6]	transitions[0x1=>0x0]	39	1			T38	1		T250	1		T251	1
all_pins[7]	values[0x0]	172134	1			T1	4		T2	2		T3	5
all_pins[7]	values[0x1]	58	1			T38	1		T250	1		T251	2
all_pins[7]	transitions[0x0=>0x1]	42	1			T38	1		T251	2		T357	2
all_pins[7]	transitions[0x1=>0x0]	71	1			T40	1		T41	1		T46	1
all_pins[8]	values[0x0]	172105	1			T1	4		T2	2		T3	5
all_pins[8]	values[0x1]	87	1			T40	1		T41	1		T46	1
all_pins[8]	transitions[0x0=>0x1]	71	1			T40	1		T41	1		T46	1
all_pins[8]	transitions[0x1=>0x0]	74	1			T52	2		T53	2		T54	2
all_pins[9]	values[0x0]	172102	1			T1	4		T2	2		T3	5
all_pins[9]	values[0x1]	90	1			T52	2		T53	2		T54	2
all_pins[9]	transitions[0x0=>0x1]	76	1			T52	2		T53	2		T54	2
all_pins[9]	transitions[0x1=>0x0]	41	1			T248	6		T250	2		T251	2
all_pins[10]	values[0x0]	172137	1			T1	4		T2	2		T3	5
all_pins[10]	values[0x1]	55	1			T248	6		T250	2		T251	3
all_pins[10]	transitions[0x0=>0x1]	41	1			T248	5		T250	2		T251	3
all_pins[10]	transitions[0x1=>0x0]	108	1			T66	1		T67	1		T68	1
all_pins[11]	values[0x0]	172070	1			T1	4		T2	2		T3	5
all_pins[11]	values[0x1]	122	1			T66	1		T67	1		T68	1
all_pins[11]	transitions[0x0=>0x1]	109	1			T66	1		T67	1		T68	1
all_pins[11]	transitions[0x1=>0x0]	53	1			T72	1		T73	1		T74	1
all_pins[12]	values[0x0]	172126	1			T1	4		T2	2		T3	5
all_pins[12]	values[0x1]	66	1			T72	1		T73	1		T74	1
all_pins[12]	transitions[0x0=>0x1]	57	1			T72	1		T73	1		T74	1
all_pins[12]	transitions[0x1=>0x0]	101	1			T75	1		T76	1		T77	1
all_pins[13]	values[0x0]	172082	1			T1	4		T2	2		T3	5
all_pins[13]	values[0x1]	110	1			T75	1		T76	1		T77	1
all_pins[13]	transitions[0x0=>0x1]	96	1			T75	1		T76	1		T77	1
all_pins[13]	transitions[0x1=>0x0]	58	1			T248	2		T249	3		T251	2
all_pins[14]	values[0x0]	172120	1			T1	4		T2	2		T3	5
all_pins[14]	values[0x1]	72	1			T248	2		T249	3		T251	3
all_pins[14]	transitions[0x0=>0x1]	53	1			T248	2		T249	1		T251	1
all_pins[14]	transitions[0x1=>0x0]	39	1			T248	1		T250	2		T337	1
all_pins[15]	values[0x0]	172134	1			T1	4		T2	2		T3	5
all_pins[15]	values[0x1]	58	1			T248	1		T249	2		T250	2
all_pins[15]	transitions[0x0=>0x1]	42	1			T248	1		T249	2		T250	2
all_pins[15]	transitions[0x1=>0x0]	64	1			T63	4		T64	4		T65	4
all_pins[16]	values[0x0]	172112	1			T1	4		T2	2		T3	5
all_pins[16]	values[0x1]	80	1			T63	4		T64	4		T65	4
all_pins[16]	transitions[0x0=>0x1]	64	1			T63	4		T64	4		T65	4
all_pins[16]	transitions[0x1=>0x0]	58	1			T47	1		T48	1		T49	1
all_pins[17]	values[0x0]	172118	1			T1	4		T2	2		T3	5
all_pins[17]	values[0x1]	74	1			T47	1		T48	1		T49	1
all_pins[17]	transitions[0x0=>0x1]	74	1			T47	1		T48	1		T49	1