Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4759	1			T129	1		T114	68		T110	6
invalid_ep[0xd]	4589	1			T83	1		T129	2		T109	1
invalid_ep[0xe]	4605	1			T83	3		T138	1		T129	1
invalid_ep[0xf]	4660	1			T83	2		T258	1		T109	1
endpoints[0x0]	12113	1			T2	56		T17	3		T19	7
endpoints[0x1]	14830	1			T2	67		T17	6		T27	3
endpoints[0x2]	15462	1			T2	67		T27	6		T4	9
endpoints[0x3]	12032	1			T2	62		T4	9		T36	2
endpoints[0x4]	11901	1			T2	73		T4	9		T5	13
endpoints[0x5]	13281	1			T2	67		T4	9		T5	13
endpoints[0x6]	13756	1			T1	2		T2	74		T21	3
endpoints[0x7]	13026	1			T2	69		T18	2		T20	9
endpoints[0x8]	13114	1			T2	67		T61	3		T4	9
endpoints[0x9]	13376	1			T2	71		T61	7		T36	2
endpoints[0xa]	14602	1			T2	80		T3	3		T36	2
endpoints[0xb]	14135	1			T2	75		T3	7		T19	3

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	22868	1			T3	3		T17	3		T19	3
pkt_types[PidTypeOutToken]	76874	1			T1	1		T2	403		T3	3
pkt_types[PidTypeInToken]	63020	1			T1	1		T2	425		T3	4

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1100	1			T114	18		T430	1		T111	38
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1033	1			T114	15		T430	1		T111	34
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1026	1			T83	1		T114	11		T111	24
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1038	1			T130	1		T114	16		T111	28
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1583	1			T17	1		T19	2		T83	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1753	1			T17	2		T27	1		T62	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1592	1			T27	2		T5	1		T62	2
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1496	1			T4	1		T6	27		T50	3
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1468	1			T5	3		T176	1		T177	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1516	1			T4	3		T83	1		T176	2
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1537	1			T21	1		T4	3		T50	3
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1425	1			T21	2		T4	2		T5	2
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1591	1			T61	1		T5	3		T178	5
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1599	1			T61	3		T83	1		T50	5
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1533	1			T3	1		T50	3		T116	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1578	1			T3	2		T19	1		T138	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1577	1			T114	15		T110	6		T111	36
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1515	1			T129	1		T109	1		T114	12
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1578	1			T83	1		T129	1		T114	9
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1505	1			T114	18		T110	9		T111	29
pkt_types[PidTypeOutToken]	endpoints[0x0]	4818	1			T2	30		T17	1		T19	2
pkt_types[PidTypeOutToken]	endpoints[0x1]	6943	1			T2	37		T17	2		T27	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	7449	1			T2	29		T27	2		T4	4
pkt_types[PidTypeOutToken]	endpoints[0x3]	4716	1			T2	26		T4	3		T36	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	4607	1			T2	31		T4	4		T5	3
pkt_types[PidTypeOutToken]	endpoints[0x5]	5822	1			T2	32		T4	1		T5	6
pkt_types[PidTypeOutToken]	endpoints[0x6]	6035	1			T1	1		T2	36		T21	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	5060	1			T2	33		T18	1		T20	9
pkt_types[PidTypeOutToken]	endpoints[0x8]	5838	1			T2	30		T61	1		T4	4
pkt_types[PidTypeOutToken]	endpoints[0x9]	5788	1			T2	36		T61	2		T36	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	6919	1			T2	38		T3	1		T36	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	6704	1			T2	45		T3	2		T19	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1038	1			T129	1		T114	17		T111	28
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1010	1			T114	11		T111	38		T115	1
pkt_types[PidTypeInToken]	invalid_ep[0xe]	974	1			T114	19		T430	2		T111	30
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1073	1			T83	1		T109	1		T114	16
pkt_types[PidTypeInToken]	endpoints[0x0]	4601	1			T2	26		T17	1		T19	3
pkt_types[PidTypeInToken]	endpoints[0x1]	5019	1			T2	30		T17	2		T27	1
pkt_types[PidTypeInToken]	endpoints[0x2]	5292	1			T2	38		T27	2		T4	5
pkt_types[PidTypeInToken]	endpoints[0x3]	4665	1			T2	36		T4	5		T36	1
pkt_types[PidTypeInToken]	endpoints[0x4]	4725	1			T2	42		T4	5		T5	7
pkt_types[PidTypeInToken]	endpoints[0x5]	4752	1			T2	35		T4	5		T5	7
pkt_types[PidTypeInToken]	endpoints[0x6]	5048	1			T1	1		T2	38		T21	1
pkt_types[PidTypeInToken]	endpoints[0x7]	5498	1			T2	36		T18	1		T21	2
pkt_types[PidTypeInToken]	endpoints[0x8]	4608	1			T2	37		T61	1		T4	5
pkt_types[PidTypeInToken]	endpoints[0x9]	4862	1			T2	35		T61	2		T36	1
pkt_types[PidTypeInToken]	endpoints[0xa]	5076	1			T2	42		T3	1		T36	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4779	1			T2	30		T3	3		T19	1