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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.55 98.11 95.98 97.44 94.92 98.30 98.17 92.94


Total test records in report: 3738
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T3577 /workspace/coverage/default/10.usbdev_fifo_rst.313621293 Aug 18 05:33:33 PM PDT 24 Aug 18 05:33:35 PM PDT 24 152409123 ps
T3578 /workspace/coverage/default/33.usbdev_rx_full.1735545392 Aug 18 05:36:49 PM PDT 24 Aug 18 05:36:51 PM PDT 24 375433475 ps
T3579 /workspace/coverage/default/7.usbdev_rand_bus_resets.292896346 Aug 18 05:32:52 PM PDT 24 Aug 18 05:33:09 PM PDT 24 2115376238 ps
T3580 /workspace/coverage/default/18.usbdev_low_speed_traffic.1453829042 Aug 18 05:34:37 PM PDT 24 Aug 18 05:36:47 PM PDT 24 4677776691 ps
T3581 /workspace/coverage/default/24.usbdev_pkt_received.952294370 Aug 18 05:35:39 PM PDT 24 Aug 18 05:35:40 PM PDT 24 182931771 ps
T3582 /workspace/coverage/default/42.usbdev_phy_config_pinflip.1022653782 Aug 18 05:37:54 PM PDT 24 Aug 18 05:37:55 PM PDT 24 191557685 ps
T3583 /workspace/coverage/default/47.usbdev_link_in_err.3689485525 Aug 18 05:38:23 PM PDT 24 Aug 18 05:38:24 PM PDT 24 245667866 ps
T3584 /workspace/coverage/default/49.usbdev_in_trans.4131601966 Aug 18 05:38:59 PM PDT 24 Aug 18 05:39:00 PM PDT 24 228479851 ps
T3585 /workspace/coverage/default/42.usbdev_in_iso.3060939849 Aug 18 05:38:04 PM PDT 24 Aug 18 05:38:05 PM PDT 24 203431594 ps
T3586 /workspace/coverage/default/29.usbdev_in_trans.693450423 Aug 18 05:36:23 PM PDT 24 Aug 18 05:36:25 PM PDT 24 235984397 ps
T3587 /workspace/coverage/default/361.usbdev_tx_rx_disruption.3047004505 Aug 18 05:40:01 PM PDT 24 Aug 18 05:40:03 PM PDT 24 463831982 ps
T3588 /workspace/coverage/default/8.usbdev_link_resume.358969297 Aug 18 05:32:56 PM PDT 24 Aug 18 05:33:44 PM PDT 24 29163343428 ps
T3589 /workspace/coverage/default/16.usbdev_alert_test.1788370625 Aug 18 05:34:28 PM PDT 24 Aug 18 05:34:29 PM PDT 24 43729915 ps
T3590 /workspace/coverage/default/161.usbdev_tx_rx_disruption.704409409 Aug 18 05:39:24 PM PDT 24 Aug 18 05:39:26 PM PDT 24 458513893 ps
T65 /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.934608220 Aug 18 05:31:27 PM PDT 24 Aug 18 05:31:28 PM PDT 24 456685955 ps
T3591 /workspace/coverage/default/47.usbdev_device_address.231910599 Aug 18 05:38:43 PM PDT 24 Aug 18 05:39:38 PM PDT 24 33480505567 ps
T3592 /workspace/coverage/default/37.usbdev_alert_test.1007885879 Aug 18 05:37:15 PM PDT 24 Aug 18 05:37:16 PM PDT 24 47276398 ps
T3593 /workspace/coverage/default/10.usbdev_random_length_out_transaction.1011937041 Aug 18 05:33:28 PM PDT 24 Aug 18 05:33:29 PM PDT 24 187739046 ps
T3594 /workspace/coverage/default/12.usbdev_alert_test.1811536994 Aug 18 05:33:42 PM PDT 24 Aug 18 05:33:43 PM PDT 24 56019440 ps
T3595 /workspace/coverage/default/50.usbdev_tx_rx_disruption.3723388547 Aug 18 05:38:59 PM PDT 24 Aug 18 05:39:01 PM PDT 24 492640727 ps
T3596 /workspace/coverage/default/25.usbdev_setup_stage.361259300 Aug 18 05:35:31 PM PDT 24 Aug 18 05:35:32 PM PDT 24 154262055 ps
T3597 /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2331971989 Aug 18 05:37:10 PM PDT 24 Aug 18 05:37:24 PM PDT 24 9623837623 ps
T3598 /workspace/coverage/default/4.usbdev_aon_wake_reset.2176672932 Aug 18 05:32:51 PM PDT 24 Aug 18 05:33:16 PM PDT 24 18471539567 ps
T3599 /workspace/coverage/default/29.usbdev_pending_in_trans.1663267357 Aug 18 05:36:14 PM PDT 24 Aug 18 05:36:15 PM PDT 24 187036329 ps
T3600 /workspace/coverage/default/19.usbdev_smoke.52629486 Aug 18 05:35:01 PM PDT 24 Aug 18 05:35:03 PM PDT 24 214406807 ps
T3601 /workspace/coverage/default/32.usbdev_in_iso.2710073330 Aug 18 05:36:59 PM PDT 24 Aug 18 05:37:00 PM PDT 24 186380281 ps
T3602 /workspace/coverage/default/327.usbdev_tx_rx_disruption.1164334734 Aug 18 05:39:51 PM PDT 24 Aug 18 05:39:53 PM PDT 24 571486387 ps
T326 /workspace/coverage/default/2.usbdev_stress_usb_traffic.563258779 Aug 18 05:32:11 PM PDT 24 Aug 18 05:32:38 PM PDT 24 3396581778 ps
T3603 /workspace/coverage/default/30.usbdev_aon_wake_resume.2807547434 Aug 18 05:36:20 PM PDT 24 Aug 18 05:36:51 PM PDT 24 26411926557 ps
T3604 /workspace/coverage/default/2.usbdev_disconnected.1849750742 Aug 18 05:31:55 PM PDT 24 Aug 18 05:31:56 PM PDT 24 175336412 ps
T3605 /workspace/coverage/default/10.usbdev_max_length_in_transaction.435692513 Aug 18 05:33:16 PM PDT 24 Aug 18 05:33:17 PM PDT 24 239303324 ps
T3606 /workspace/coverage/default/5.usbdev_rx_crc_err.578596997 Aug 18 05:32:48 PM PDT 24 Aug 18 05:32:49 PM PDT 24 152046144 ps
T3607 /workspace/coverage/default/19.usbdev_aon_wake_reset.2815858062 Aug 18 05:34:42 PM PDT 24 Aug 18 05:35:00 PM PDT 24 14638031890 ps
T3608 /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2512179998 Aug 18 05:38:25 PM PDT 24 Aug 18 05:38:26 PM PDT 24 177101561 ps
T3609 /workspace/coverage/default/133.usbdev_tx_rx_disruption.155965217 Aug 18 05:39:09 PM PDT 24 Aug 18 05:39:10 PM PDT 24 604173695 ps
T3610 /workspace/coverage/default/12.usbdev_nak_trans.1192725236 Aug 18 05:33:43 PM PDT 24 Aug 18 05:33:44 PM PDT 24 189874714 ps
T3611 /workspace/coverage/default/41.usbdev_alert_test.2950728424 Aug 18 05:37:52 PM PDT 24 Aug 18 05:37:53 PM PDT 24 53756668 ps
T3612 /workspace/coverage/default/48.usbdev_setup_stage.1635807612 Aug 18 05:38:50 PM PDT 24 Aug 18 05:38:51 PM PDT 24 166091098 ps
T3613 /workspace/coverage/default/1.usbdev_random_length_in_transaction.320261876 Aug 18 05:31:55 PM PDT 24 Aug 18 05:31:56 PM PDT 24 217710874 ps
T3614 /workspace/coverage/default/24.usbdev_aon_wake_disconnect.2875905380 Aug 18 05:35:31 PM PDT 24 Aug 18 05:35:53 PM PDT 24 12094299999 ps
T3615 /workspace/coverage/default/42.usbdev_tx_rx_disruption.152398540 Aug 18 05:38:04 PM PDT 24 Aug 18 05:38:06 PM PDT 24 450678628 ps
T3616 /workspace/coverage/default/12.usbdev_in_stall.3816198025 Aug 18 05:33:42 PM PDT 24 Aug 18 05:33:43 PM PDT 24 157370228 ps
T3617 /workspace/coverage/default/42.usbdev_stall_trans.3763245531 Aug 18 05:38:04 PM PDT 24 Aug 18 05:38:05 PM PDT 24 206149667 ps
T3618 /workspace/coverage/default/26.usbdev_phy_config_pinflip.2881192469 Aug 18 05:35:52 PM PDT 24 Aug 18 05:35:53 PM PDT 24 276638098 ps
T3619 /workspace/coverage/default/5.usbdev_out_trans_nak.3617460636 Aug 18 05:32:37 PM PDT 24 Aug 18 05:32:38 PM PDT 24 189496262 ps
T3620 /workspace/coverage/default/15.usbdev_streaming_out.2793438021 Aug 18 05:34:05 PM PDT 24 Aug 18 05:34:24 PM PDT 24 1941844300 ps
T3621 /workspace/coverage/default/35.usbdev_min_length_out_transaction.3971427053 Aug 18 05:36:58 PM PDT 24 Aug 18 05:36:59 PM PDT 24 185832146 ps
T3622 /workspace/coverage/default/387.usbdev_tx_rx_disruption.3442339157 Aug 18 05:40:11 PM PDT 24 Aug 18 05:40:12 PM PDT 24 469392906 ps
T3623 /workspace/coverage/default/111.usbdev_endpoint_types.3766872398 Aug 18 05:38:58 PM PDT 24 Aug 18 05:39:00 PM PDT 24 618231756 ps
T3624 /workspace/coverage/default/21.usbdev_setup_stage.761292620 Aug 18 05:34:58 PM PDT 24 Aug 18 05:35:00 PM PDT 24 198825071 ps
T3625 /workspace/coverage/default/39.usbdev_invalid_sync.120719401 Aug 18 05:37:23 PM PDT 24 Aug 18 05:38:36 PM PDT 24 2753137437 ps
T3626 /workspace/coverage/default/360.usbdev_tx_rx_disruption.1939919476 Aug 18 05:39:58 PM PDT 24 Aug 18 05:40:00 PM PDT 24 651207858 ps
T3627 /workspace/coverage/default/12.usbdev_disconnected.2000018587 Aug 18 05:33:40 PM PDT 24 Aug 18 05:33:41 PM PDT 24 136324398 ps
T3628 /workspace/coverage/default/23.usbdev_disable_endpoint.3598698113 Aug 18 05:35:29 PM PDT 24 Aug 18 05:35:31 PM PDT 24 798190277 ps
T3629 /workspace/coverage/default/28.usbdev_pkt_buffer.3014957231 Aug 18 05:36:08 PM PDT 24 Aug 18 05:36:37 PM PDT 24 11033862586 ps
T3630 /workspace/coverage/default/8.usbdev_random_length_in_transaction.2605457124 Aug 18 05:32:56 PM PDT 24 Aug 18 05:32:57 PM PDT 24 229504730 ps
T3631 /workspace/coverage/default/34.usbdev_low_speed_traffic.3673215853 Aug 18 05:37:01 PM PDT 24 Aug 18 05:39:11 PM PDT 24 4612946640 ps
T3632 /workspace/coverage/default/11.usbdev_out_stall.724594401 Aug 18 05:33:40 PM PDT 24 Aug 18 05:33:41 PM PDT 24 205818543 ps
T3633 /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1628453172 Aug 18 05:34:52 PM PDT 24 Aug 18 05:35:00 PM PDT 24 5291421279 ps
T3634 /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2063774054 Aug 18 05:34:39 PM PDT 24 Aug 18 05:35:33 PM PDT 24 1987350020 ps
T3635 /workspace/coverage/default/49.usbdev_aon_wake_reset.140619006 Aug 18 05:38:55 PM PDT 24 Aug 18 05:39:19 PM PDT 24 19743518082 ps
T3636 /workspace/coverage/default/40.usbdev_link_in_err.2168023810 Aug 18 05:37:46 PM PDT 24 Aug 18 05:37:47 PM PDT 24 217693776 ps
T3637 /workspace/coverage/default/337.usbdev_tx_rx_disruption.140856500 Aug 18 05:40:09 PM PDT 24 Aug 18 05:40:11 PM PDT 24 463419866 ps
T241 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3179327880 Aug 18 05:10:22 PM PDT 24 Aug 18 05:10:25 PM PDT 24 104361433 ps
T248 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.4084574099 Aug 18 05:10:58 PM PDT 24 Aug 18 05:10:59 PM PDT 24 50816031 ps
T271 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.230853051 Aug 18 05:10:33 PM PDT 24 Aug 18 05:10:34 PM PDT 24 89826643 ps
T249 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2512605708 Aug 18 05:10:24 PM PDT 24 Aug 18 05:10:25 PM PDT 24 57663778 ps
T272 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1614705261 Aug 18 05:10:15 PM PDT 24 Aug 18 05:10:17 PM PDT 24 100371468 ps
T242 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1508499689 Aug 18 05:10:33 PM PDT 24 Aug 18 05:10:35 PM PDT 24 143784687 ps
T243 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2328839491 Aug 18 05:10:41 PM PDT 24 Aug 18 05:10:43 PM PDT 24 82977581 ps
T268 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3844720274 Aug 18 05:10:45 PM PDT 24 Aug 18 05:10:47 PM PDT 24 91483650 ps
T250 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1435129185 Aug 18 05:10:54 PM PDT 24 Aug 18 05:10:55 PM PDT 24 48025347 ps
T269 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1039680983 Aug 18 05:10:32 PM PDT 24 Aug 18 05:10:35 PM PDT 24 311730593 ps
T336 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1821119164 Aug 18 05:10:34 PM PDT 24 Aug 18 05:10:35 PM PDT 24 35509621 ps
T317 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4047409272 Aug 18 05:10:45 PM PDT 24 Aug 18 05:10:46 PM PDT 24 62446392 ps
T300 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2260234764 Aug 18 05:10:18 PM PDT 24 Aug 18 05:10:20 PM PDT 24 93320163 ps
T318 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1600687266 Aug 18 05:10:24 PM PDT 24 Aug 18 05:10:25 PM PDT 24 64762089 ps
T319 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1089116273 Aug 18 05:10:43 PM PDT 24 Aug 18 05:10:44 PM PDT 24 113654650 ps
T320 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2509458570 Aug 18 05:10:45 PM PDT 24 Aug 18 05:10:46 PM PDT 24 64254796 ps
T321 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2010255140 Aug 18 05:10:43 PM PDT 24 Aug 18 05:10:45 PM PDT 24 53429982 ps
T251 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1382064159 Aug 18 05:10:54 PM PDT 24 Aug 18 05:10:55 PM PDT 24 34251662 ps
T357 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.4276743542 Aug 18 05:11:00 PM PDT 24 Aug 18 05:11:01 PM PDT 24 114275611 ps
T270 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1262222686 Aug 18 05:10:22 PM PDT 24 Aug 18 05:10:28 PM PDT 24 1251074323 ps
T301 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1048422317 Aug 18 05:10:17 PM PDT 24 Aug 18 05:10:20 PM PDT 24 87814133 ps
T279 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3795298843 Aug 18 05:10:44 PM PDT 24 Aug 18 05:10:46 PM PDT 24 91905442 ps
T322 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.513482190 Aug 18 05:10:34 PM PDT 24 Aug 18 05:10:36 PM PDT 24 189740007 ps
T323 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3294796611 Aug 18 05:10:34 PM PDT 24 Aug 18 05:10:36 PM PDT 24 144695525 ps
T280 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4050817563 Aug 18 05:10:15 PM PDT 24 Aug 18 05:10:18 PM PDT 24 118630873 ps
T3638 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2659282631 Aug 18 05:10:45 PM PDT 24 Aug 18 05:10:47 PM PDT 24 73742542 ps
T283 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3658827805 Aug 18 05:10:18 PM PDT 24 Aug 18 05:10:20 PM PDT 24 133217762 ps
T288 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2228537365 Aug 18 05:10:45 PM PDT 24 Aug 18 05:10:47 PM PDT 24 138652494 ps
T3639 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1364407326 Aug 18 05:10:18 PM PDT 24 Aug 18 05:10:22 PM PDT 24 163256019 ps
T327 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2124082750 Aug 18 05:10:33 PM PDT 24 Aug 18 05:10:35 PM PDT 24 330106225 ps
T3640 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1396298163 Aug 18 05:10:15 PM PDT 24 Aug 18 05:10:24 PM PDT 24 1585159973 ps
T3641 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3394703685 Aug 18 05:10:46 PM PDT 24 Aug 18 05:10:47 PM PDT 24 33797758 ps
T284 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3954402080 Aug 18 05:10:23 PM PDT 24 Aug 18 05:10:25 PM PDT 24 61874794 ps
T358 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1415662993 Aug 18 05:10:16 PM PDT 24 Aug 18 05:10:17 PM PDT 24 97413686 ps
T328 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3533181005 Aug 18 05:10:34 PM PDT 24 Aug 18 05:10:35 PM PDT 24 87257172 ps
T290 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.70253982 Aug 18 05:10:16 PM PDT 24 Aug 18 05:10:18 PM PDT 24 101485516 ps
T329 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2548402708 Aug 18 05:10:47 PM PDT 24 Aug 18 05:10:48 PM PDT 24 149507639 ps
T356 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3434987373 Aug 18 05:10:43 PM PDT 24 Aug 18 05:10:44 PM PDT 24 38596013 ps
T337 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3297007057 Aug 18 05:10:53 PM PDT 24 Aug 18 05:10:54 PM PDT 24 42997724 ps
T285 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4067858319 Aug 18 05:10:22 PM PDT 24 Aug 18 05:10:24 PM PDT 24 144508637 ps
T286 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.77954297 Aug 18 05:10:34 PM PDT 24 Aug 18 05:10:37 PM PDT 24 254598040 ps
T3642 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1134397881 Aug 18 05:10:52 PM PDT 24 Aug 18 05:10:53 PM PDT 24 53227365 ps
T359 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.667089363 Aug 18 05:10:31 PM PDT 24 Aug 18 05:10:31 PM PDT 24 29725276 ps
T302 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2663149471 Aug 18 05:10:17 PM PDT 24 Aug 18 05:10:18 PM PDT 24 73956516 ps
T3643 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.969247286 Aug 18 05:10:14 PM PDT 24 Aug 18 05:10:15 PM PDT 24 41595306 ps
T330 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3077406786 Aug 18 05:10:16 PM PDT 24 Aug 18 05:10:18 PM PDT 24 268673798 ps
T3644 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.950759174 Aug 18 05:10:16 PM PDT 24 Aug 18 05:10:18 PM PDT 24 249852750 ps
T3645 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3960178142 Aug 18 05:10:42 PM PDT 24 Aug 18 05:10:43 PM PDT 24 38118616 ps
T3646 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2485090775 Aug 18 05:10:18 PM PDT 24 Aug 18 05:10:23 PM PDT 24 943621048 ps
T289 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.846582217 Aug 18 05:10:18 PM PDT 24 Aug 18 05:10:20 PM PDT 24 146389800 ps
T3647 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2719705561 Aug 18 05:10:45 PM PDT 24 Aug 18 05:10:46 PM PDT 24 62042313 ps
T278 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3694529567 Aug 18 05:10:04 PM PDT 24 Aug 18 05:10:09 PM PDT 24 681537618 ps
T331 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.403073848 Aug 18 05:10:24 PM PDT 24 Aug 18 05:10:25 PM PDT 24 246195928 ps
T510 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1035191716 Aug 18 05:10:32 PM PDT 24 Aug 18 05:10:35 PM PDT 24 1011944450 ps
T3648 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.4236422236 Aug 18 05:10:45 PM PDT 24 Aug 18 05:10:46 PM PDT 24 43715062 ps
T3649 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1056479479 Aug 18 05:10:34 PM PDT 24 Aug 18 05:10:36 PM PDT 24 150419725 ps
T3650 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1663610683 Aug 18 05:10:22 PM PDT 24 Aug 18 05:10:24 PM PDT 24 81162607 ps
T332 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4037430238 Aug 18 05:10:21 PM PDT 24 Aug 18 05:10:23 PM PDT 24 224760678 ps
T303 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2917258579 Aug 18 05:10:17 PM PDT 24 Aug 18 05:10:19 PM PDT 24 105271839 ps
T514 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2699307442 Aug 18 05:10:18 PM PDT 24 Aug 18 05:10:22 PM PDT 24 607892068 ps
T3651 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3850868365 Aug 18 05:10:03 PM PDT 24 Aug 18 05:10:04 PM PDT 24 62778035 ps
T3652 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4043793976 Aug 18 05:10:47 PM PDT 24 Aug 18 05:10:48 PM PDT 24 52541531 ps
T3653 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2564896699 Aug 18 05:10:22 PM PDT 24 Aug 18 05:10:24 PM PDT 24 540571295 ps
T3654 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2435331936 Aug 18 05:10:52 PM PDT 24 Aug 18 05:10:53 PM PDT 24 62357584 ps
T287 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2466110892 Aug 18 05:10:35 PM PDT 24 Aug 18 05:10:37 PM PDT 24 114999623 ps
T3655 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3306032608 Aug 18 05:10:57 PM PDT 24 Aug 18 05:10:58 PM PDT 24 64402597 ps
T333 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3227704243 Aug 18 05:10:32 PM PDT 24 Aug 18 05:10:35 PM PDT 24 390566474 ps
T3656 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3370339342 Aug 18 05:10:15 PM PDT 24 Aug 18 05:10:18 PM PDT 24 259483632 ps
T3657 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.404873850 Aug 18 05:10:43 PM PDT 24 Aug 18 05:10:45 PM PDT 24 140657768 ps
T3658 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2612912129 Aug 18 05:10:42 PM PDT 24 Aug 18 05:10:43 PM PDT 24 90575091 ps
T3659 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1128979330 Aug 18 05:10:43 PM PDT 24 Aug 18 05:10:44 PM PDT 24 37811469 ps
T3660 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2855750548 Aug 18 05:10:58 PM PDT 24 Aug 18 05:10:59 PM PDT 24 59447239 ps
T334 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1315827608 Aug 18 05:10:23 PM PDT 24 Aug 18 05:10:24 PM PDT 24 106332642 ps
T3661 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.825934102 Aug 18 05:10:06 PM PDT 24 Aug 18 05:10:15 PM PDT 24 1898405293 ps
T3662 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1515643919 Aug 18 05:10:31 PM PDT 24 Aug 18 05:10:32 PM PDT 24 95235830 ps
T3663 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1279501812 Aug 18 05:10:18 PM PDT 24 Aug 18 05:10:26 PM PDT 24 1039244691 ps
T304 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.972930385 Aug 18 05:10:23 PM PDT 24 Aug 18 05:10:24 PM PDT 24 94192230 ps
T3664 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.391406622 Aug 18 05:10:43 PM PDT 24 Aug 18 05:10:44 PM PDT 24 55644602 ps
T3665 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.202336052 Aug 18 05:10:44 PM PDT 24 Aug 18 05:10:45 PM PDT 24 37816579 ps
T3666 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2166045359 Aug 18 05:10:42 PM PDT 24 Aug 18 05:10:44 PM PDT 24 78223462 ps
T3667 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3504624086 Aug 18 05:10:35 PM PDT 24 Aug 18 05:10:36 PM PDT 24 41532472 ps
T3668 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1013089604 Aug 18 05:10:43 PM PDT 24 Aug 18 05:10:44 PM PDT 24 121069718 ps
T511 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1977019338 Aug 18 05:10:16 PM PDT 24 Aug 18 05:10:18 PM PDT 24 304823925 ps
T3669 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3047777621 Aug 18 05:10:42 PM PDT 24 Aug 18 05:10:43 PM PDT 24 38731661 ps
T335 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3696895474 Aug 18 05:10:16 PM PDT 24 Aug 18 05:10:17 PM PDT 24 68894366 ps
T3670 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3305625937 Aug 18 05:10:55 PM PDT 24 Aug 18 05:10:56 PM PDT 24 55288668 ps
T3671 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1524197557 Aug 18 05:10:16 PM PDT 24 Aug 18 05:10:18 PM PDT 24 254803408 ps
T3672 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2718760060 Aug 18 05:10:44 PM PDT 24 Aug 18 05:10:45 PM PDT 24 59448414 ps
T3673 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2622538417 Aug 18 05:10:58 PM PDT 24 Aug 18 05:10:58 PM PDT 24 37221561 ps
T3674 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3088059416 Aug 18 05:10:03 PM PDT 24 Aug 18 05:10:04 PM PDT 24 66687877 ps
T291 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1170672278 Aug 18 05:10:43 PM PDT 24 Aug 18 05:10:46 PM PDT 24 354673733 ps
T3675 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2057219711 Aug 18 05:10:54 PM PDT 24 Aug 18 05:10:55 PM PDT 24 71038342 ps
T3676 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4215010790 Aug 18 05:10:25 PM PDT 24 Aug 18 05:10:26 PM PDT 24 49132810 ps
T3677 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2137111166 Aug 18 05:10:16 PM PDT 24 Aug 18 05:10:18 PM PDT 24 110098106 ps
T305 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.153499375 Aug 18 05:10:03 PM PDT 24 Aug 18 05:10:05 PM PDT 24 102247345 ps
T3678 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3513752062 Aug 18 05:10:53 PM PDT 24 Aug 18 05:10:54 PM PDT 24 99354399 ps
T3679 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2007845260 Aug 18 05:10:44 PM PDT 24 Aug 18 05:10:45 PM PDT 24 80392044 ps
T516 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.382392864 Aug 18 05:10:32 PM PDT 24 Aug 18 05:10:36 PM PDT 24 529835374 ps
T3680 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1106276521 Aug 18 05:10:55 PM PDT 24 Aug 18 05:10:56 PM PDT 24 90080522 ps
T3681 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1023204646 Aug 18 05:10:31 PM PDT 24 Aug 18 05:10:31 PM PDT 24 62489873 ps
T3682 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3303505811 Aug 18 05:10:31 PM PDT 24 Aug 18 05:10:31 PM PDT 24 39442920 ps
T3683 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2955614770 Aug 18 05:10:17 PM PDT 24 Aug 18 05:10:17 PM PDT 24 57334244 ps
T3684 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1423194118 Aug 18 05:10:53 PM PDT 24 Aug 18 05:10:54 PM PDT 24 47099695 ps
T3685 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2145027230 Aug 18 05:10:22 PM PDT 24 Aug 18 05:10:23 PM PDT 24 81852254 ps
T3686 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.216784291 Aug 18 05:10:54 PM PDT 24 Aug 18 05:10:55 PM PDT 24 57973750 ps
T3687 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1061307818 Aug 18 05:10:19 PM PDT 24 Aug 18 05:10:23 PM PDT 24 290733440 ps
T3688 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3787223583 Aug 18 05:10:04 PM PDT 24 Aug 18 05:10:06 PM PDT 24 101007060 ps
T3689 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3881890673 Aug 18 05:10:14 PM PDT 24 Aug 18 05:10:15 PM PDT 24 94422443 ps
T3690 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3817742735 Aug 18 05:10:32 PM PDT 24 Aug 18 05:10:34 PM PDT 24 156779155 ps
T306 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2271947169 Aug 18 05:10:25 PM PDT 24 Aug 18 05:10:27 PM PDT 24 95065870 ps
T3691 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1538389943 Aug 18 05:10:22 PM PDT 24 Aug 18 05:10:24 PM PDT 24 187818848 ps
T3692 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3948224789 Aug 18 05:10:35 PM PDT 24 Aug 18 05:10:39 PM PDT 24 277755565 ps
T515 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.676077973 Aug 18 05:10:15 PM PDT 24 Aug 18 05:10:18 PM PDT 24 1134417157 ps
T3693 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1283001476 Aug 18 05:10:21 PM PDT 24 Aug 18 05:10:24 PM PDT 24 224955506 ps
T508 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.216151459 Aug 18 05:10:17 PM PDT 24 Aug 18 05:10:22 PM PDT 24 1148307428 ps
T3694 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1541903985 Aug 18 05:10:52 PM PDT 24 Aug 18 05:10:53 PM PDT 24 92783604 ps
T3695 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1206169851 Aug 18 05:10:33 PM PDT 24 Aug 18 05:10:34 PM PDT 24 184949451 ps
T3696 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.4008336276 Aug 18 05:10:53 PM PDT 24 Aug 18 05:10:54 PM PDT 24 48972144 ps
T512 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1482194577 Aug 18 05:10:46 PM PDT 24 Aug 18 05:10:49 PM PDT 24 420289509 ps
T3697 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1883094031 Aug 18 05:10:17 PM PDT 24 Aug 18 05:10:18 PM PDT 24 60332595 ps
T3698 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3777293882 Aug 18 05:10:35 PM PDT 24 Aug 18 05:10:37 PM PDT 24 67170644 ps
T3699 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3483646729 Aug 18 05:10:15 PM PDT 24 Aug 18 05:10:17 PM PDT 24 80865945 ps
T3700 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1343679217 Aug 18 05:10:43 PM PDT 24 Aug 18 05:10:45 PM PDT 24 134538904 ps
T3701 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.4216660950 Aug 18 05:10:05 PM PDT 24 Aug 18 05:10:08 PM PDT 24 113688971 ps
T3702 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2589619447 Aug 18 05:10:26 PM PDT 24 Aug 18 05:10:27 PM PDT 24 32830655 ps
T3703 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2067385896 Aug 18 05:10:34 PM PDT 24 Aug 18 05:10:35 PM PDT 24 125416746 ps
T3704 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2087202648 Aug 18 05:10:18 PM PDT 24 Aug 18 05:10:19 PM PDT 24 87859035 ps
T509 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1270374417 Aug 18 05:10:33 PM PDT 24 Aug 18 05:10:39 PM PDT 24 986221871 ps
T3705 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2753635462 Aug 18 05:10:52 PM PDT 24 Aug 18 05:10:53 PM PDT 24 41248575 ps
T3706 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3946898992 Aug 18 05:10:23 PM PDT 24 Aug 18 05:10:24 PM PDT 24 82333453 ps
T3707 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1703144032 Aug 18 05:10:22 PM PDT 24 Aug 18 05:10:23 PM PDT 24 118118423 ps
T513 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1288719726 Aug 18 05:10:23 PM PDT 24 Aug 18 05:10:26 PM PDT 24 1112510625 ps
T310 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1831239536 Aug 18 05:10:46 PM PDT 24 Aug 18 05:10:47 PM PDT 24 86100614 ps
T307 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.645909056 Aug 18 05:10:16 PM PDT 24 Aug 18 05:10:17 PM PDT 24 53718308 ps
T3708 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3589638242 Aug 18 05:10:14 PM PDT 24 Aug 18 05:10:17 PM PDT 24 258211502 ps
T308 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1248959082 Aug 18 05:10:16 PM PDT 24 Aug 18 05:10:20 PM PDT 24 151985614 ps
T3709 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.557796570 Aug 18 05:10:42 PM PDT 24 Aug 18 05:10:45 PM PDT 24 81449182 ps
T3710 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.467921792 Aug 18 05:10:45 PM PDT 24 Aug 18 05:10:48 PM PDT 24 399975224 ps
T3711 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2741001339 Aug 18 05:10:43 PM PDT 24 Aug 18 05:10:44 PM PDT 24 37458029 ps
T3712 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1988743898 Aug 18 05:10:26 PM PDT 24 Aug 18 05:10:28 PM PDT 24 54623346 ps
T3713 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.817849493 Aug 18 05:10:35 PM PDT 24 Aug 18 05:10:36 PM PDT 24 56999025 ps
T3714 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2291558759 Aug 18 05:10:16 PM PDT 24 Aug 18 05:10:17 PM PDT 24 144881253 ps
T309 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2650878902 Aug 18 05:10:35 PM PDT 24 Aug 18 05:10:36 PM PDT 24 147867405 ps
T3715 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3232553602 Aug 18 05:11:00 PM PDT 24 Aug 18 05:11:01 PM PDT 24 36304446 ps
T9 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3752810922 Aug 18 05:10:16 PM PDT 24 Aug 18 05:10:17 PM PDT 24 105211164 ps
T3716 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.926111426 Aug 18 05:10:32 PM PDT 24 Aug 18 05:10:33 PM PDT 24 46753687 ps
T3717 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2342855681 Aug 18 05:10:03 PM PDT 24 Aug 18 05:10:04 PM PDT 24 78139133 ps
T3718 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3157065737 Aug 18 05:10:32 PM PDT 24 Aug 18 05:10:34 PM PDT 24 125146070 ps
T3719 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3799474150 Aug 18 05:10:54 PM PDT 24 Aug 18 05:10:55 PM PDT 24 31275274 ps
T3720 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4071665010 Aug 18 05:10:43 PM PDT 24 Aug 18 05:10:44 PM PDT 24 119287707 ps
T3721 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1428452172 Aug 18 05:10:54 PM PDT 24 Aug 18 05:10:55 PM PDT 24 58084927 ps
T3722 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.365296255 Aug 18 05:10:43 PM PDT 24 Aug 18 05:10:47 PM PDT 24 1025791309 ps
T3723 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1446340038 Aug 18 05:10:42 PM PDT 24 Aug 18 05:10:43 PM PDT 24 43407430 ps
T3724 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1442861758 Aug 18 05:10:17 PM PDT 24 Aug 18 05:10:20 PM PDT 24 155583715 ps
T3725 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3555628303 Aug 18 05:10:44 PM PDT 24 Aug 18 05:10:48 PM PDT 24 612699846 ps
T3726 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3822204121 Aug 18 05:10:42 PM PDT 24 Aug 18 05:10:44 PM PDT 24 91828369 ps
T3727 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3761717767 Aug 18 05:11:01 PM PDT 24 Aug 18 05:11:02 PM PDT 24 42294969 ps
T3728 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2519893184 Aug 18 05:11:01 PM PDT 24 Aug 18 05:11:02 PM PDT 24 42799844 ps
T3729 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.285367267 Aug 18 05:10:24 PM PDT 24 Aug 18 05:10:26 PM PDT 24 188519441 ps
T3730 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.4016791224 Aug 18 05:10:42 PM PDT 24 Aug 18 05:10:47 PM PDT 24 780384649 ps
T3731 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2521617272 Aug 18 05:10:15 PM PDT 24 Aug 18 05:10:20 PM PDT 24 710113339 ps
T311 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3515934731 Aug 18 05:10:35 PM PDT 24 Aug 18 05:10:36 PM PDT 24 65271408 ps
T312 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.334611456 Aug 18 05:10:15 PM PDT 24 Aug 18 05:10:18 PM PDT 24 97993743 ps
T3732 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3846558348 Aug 18 05:10:25 PM PDT 24 Aug 18 05:10:27 PM PDT 24 186919605 ps
T313 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2902131804 Aug 18 05:10:04 PM PDT 24 Aug 18 05:10:07 PM PDT 24 79689602 ps
T314 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.244324810 Aug 18 05:10:19 PM PDT 24 Aug 18 05:10:20 PM PDT 24 95370424 ps
T315 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.248146636 Aug 18 05:10:17 PM PDT 24 Aug 18 05:10:18 PM PDT 24 109064828 ps
T517 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4003288954 Aug 18 05:10:32 PM PDT 24 Aug 18 05:10:37 PM PDT 24 875961327 ps
T3733 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.823586975 Aug 18 05:10:20 PM PDT 24 Aug 18 05:10:21 PM PDT 24 85501783 ps
T3734 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.4207396191 Aug 18 05:10:21 PM PDT 24 Aug 18 05:10:22 PM PDT 24 39949699 ps
T3735 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3064183446 Aug 18 05:10:36 PM PDT 24 Aug 18 05:10:38 PM PDT 24 111811154 ps
T3736 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.375757568 Aug 18 05:10:34 PM PDT 24 Aug 18 05:10:35 PM PDT 24 56223549 ps
T3737 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.519222940 Aug 18 05:10:24 PM PDT 24 Aug 18 05:10:30 PM PDT 24 874929129 ps
T316 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3058679691 Aug 18 05:10:18 PM PDT 24 Aug 18 05:10:23 PM PDT 24 775146924 ps
T3738 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.899508788 Aug 18 05:10:31 PM PDT 24 Aug 18 05:10:33 PM PDT 24 246876459 ps

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.2462626163
Short name T1
Test name
Test status
Simulation time 30754012106 ps
CPU time 39.91 seconds
Started Aug 18 05:35:52 PM PDT 24
Finished Aug 18 05:36:32 PM PDT 24
Peak memory 207800 kb
Host smart-b8062cf8-4ae4-4844-b843-d2b7ccf0ee3d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462626163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.2462626163
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.546689361
Short name T4
Test name
Test status
Simulation time 2152797567 ps
CPU time 60.43 seconds
Started Aug 18 05:36:51 PM PDT 24
Finished Aug 18 05:37:52 PM PDT 24
Peak memory 217680 kb
Host smart-268e95f1-9464-46a5-8f3e-f814108c1d71
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=546689361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.546689361
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/91.usbdev_tx_rx_disruption.3837620864
Short name T61
Test name
Test status
Simulation time 573116756 ps
CPU time 1.68 seconds
Started Aug 18 05:39:14 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207560 kb
Host smart-68088e8c-8a27-47e1-98f4-5ff3024ae22c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837620864 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 91.usbdev_tx_rx_disruption.3837620864
Directory /workspace/91.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.4276743542
Short name T357
Test name
Test status
Simulation time 114275611 ps
CPU time 0.8 seconds
Started Aug 18 05:11:00 PM PDT 24
Finished Aug 18 05:11:01 PM PDT 24
Peak memory 206860 kb
Host smart-87233ba1-8821-469a-9135-8f7a18664417
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4276743542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.4276743542
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.799483409
Short name T132
Test name
Test status
Simulation time 4750440474 ps
CPU time 142.11 seconds
Started Aug 18 05:33:44 PM PDT 24
Finished Aug 18 05:36:06 PM PDT 24
Peak memory 218580 kb
Host smart-37b9d8da-4fdd-4b3e-8d70-e4d698b58d6e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=799483409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.799483409
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_device_address.2326599330
Short name T114
Test name
Test status
Simulation time 21893163848 ps
CPU time 36.1 seconds
Started Aug 18 05:38:28 PM PDT 24
Finished Aug 18 05:39:04 PM PDT 24
Peak memory 207704 kb
Host smart-572c1352-7480-45e0-b9e2-df9f7507f225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23265
99330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.2326599330
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1262222686
Short name T270
Test name
Test status
Simulation time 1251074323 ps
CPU time 5.31 seconds
Started Aug 18 05:10:22 PM PDT 24
Finished Aug 18 05:10:28 PM PDT 24
Peak memory 207188 kb
Host smart-e9d7520e-e300-4c9a-82e2-0178c20bcfc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1262222686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1262222686
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.2335871063
Short name T99
Test name
Test status
Simulation time 8764299343 ps
CPU time 11.87 seconds
Started Aug 18 05:34:34 PM PDT 24
Finished Aug 18 05:34:46 PM PDT 24
Peak memory 215968 kb
Host smart-6e61c41e-7c9d-4fb7-8795-c58fa0dd8107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23358
71063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.2335871063
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1115554498
Short name T14
Test name
Test status
Simulation time 9416434130 ps
CPU time 11.93 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:43 PM PDT 24
Peak memory 207800 kb
Host smart-8050e78e-9f76-4dc4-9e6d-e712bbe992f5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115554498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.1115554498
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1545191168
Short name T240
Test name
Test status
Simulation time 391085740 ps
CPU time 1.23 seconds
Started Aug 18 05:31:52 PM PDT 24
Finished Aug 18 05:31:54 PM PDT 24
Peak memory 224284 kb
Host smart-01e526ce-7b00-4fe3-ae3f-8559bbfefcb9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1545191168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1545191168
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/383.usbdev_tx_rx_disruption.3125572531
Short name T3
Test name
Test status
Simulation time 562282327 ps
CPU time 1.61 seconds
Started Aug 18 05:40:07 PM PDT 24
Finished Aug 18 05:40:09 PM PDT 24
Peak memory 207584 kb
Host smart-353655f6-6622-4139-ada0-22ced41d6fda
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125572531 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 383.usbdev_tx_rx_disruption.3125572531
Directory /workspace/383.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.780075561
Short name T259
Test name
Test status
Simulation time 371587397 ps
CPU time 1.11 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:31:56 PM PDT 24
Peak memory 207488 kb
Host smart-0e0d6291-114f-4541-8992-dcf24d0cd4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78007
5561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.780075561
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1766408525
Short name T106
Test name
Test status
Simulation time 795414643 ps
CPU time 2.16 seconds
Started Aug 18 05:32:16 PM PDT 24
Finished Aug 18 05:32:20 PM PDT 24
Peak memory 207772 kb
Host smart-5a24cf78-b53d-4696-b6fb-15c937fd5a65
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1766408525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1766408525
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.70253982
Short name T290
Test name
Test status
Simulation time 101485516 ps
CPU time 1.35 seconds
Started Aug 18 05:10:16 PM PDT 24
Finished Aug 18 05:10:18 PM PDT 24
Peak memory 215520 kb
Host smart-fa91697d-fcea-42db-99ab-3d9fbd0f1d75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70253982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_
csr_mem_rw_with_rand_reset.70253982
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1149392303
Short name T30
Test name
Test status
Simulation time 85832487 ps
CPU time 0.75 seconds
Started Aug 18 05:33:51 PM PDT 24
Finished Aug 18 05:33:52 PM PDT 24
Peak memory 207488 kb
Host smart-2b76ecba-cb3c-4f8b-b5c7-5b1e0c58fab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11493
92303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1149392303
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1382064159
Short name T251
Test name
Test status
Simulation time 34251662 ps
CPU time 0.73 seconds
Started Aug 18 05:10:54 PM PDT 24
Finished Aug 18 05:10:55 PM PDT 24
Peak memory 206924 kb
Host smart-106b8634-67e8-4259-b6ac-9a6be3858b60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1382064159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1382064159
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2884231595
Short name T90
Test name
Test status
Simulation time 16255479181 ps
CPU time 21.44 seconds
Started Aug 18 05:33:36 PM PDT 24
Finished Aug 18 05:33:58 PM PDT 24
Peak memory 215904 kb
Host smart-d68543ca-e702-453a-862a-ce12927c58dd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884231595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2884231595
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/492.usbdev_tx_rx_disruption.4102802803
Short name T265
Test name
Test status
Simulation time 530942589 ps
CPU time 1.53 seconds
Started Aug 18 05:40:34 PM PDT 24
Finished Aug 18 05:40:36 PM PDT 24
Peak memory 207552 kb
Host smart-cd9de28c-ee64-4e8b-bb44-28f3d703ea77
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102802803 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 492.usbdev_tx_rx_disruption.4102802803
Directory /workspace/492.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.2522530576
Short name T1164
Test name
Test status
Simulation time 31211666097 ps
CPU time 39.4 seconds
Started Aug 18 05:33:19 PM PDT 24
Finished Aug 18 05:33:58 PM PDT 24
Peak memory 207792 kb
Host smart-3ebc77ea-2f47-4d48-b523-6c8245949b38
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522530576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.2522530576
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/153.usbdev_tx_rx_disruption.837230797
Short name T1428
Test name
Test status
Simulation time 479460308 ps
CPU time 1.45 seconds
Started Aug 18 05:39:46 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207576 kb
Host smart-8d14ad5b-5394-404b-8c71-5276114a672a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837230797 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 153.usbdev_tx_rx_disruption.837230797
Directory /workspace/153.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/166.usbdev_tx_rx_disruption.1750192960
Short name T261
Test name
Test status
Simulation time 585058894 ps
CPU time 1.69 seconds
Started Aug 18 05:39:38 PM PDT 24
Finished Aug 18 05:39:40 PM PDT 24
Peak memory 207596 kb
Host smart-faeb7a28-4b91-4067-b09e-e955caee87f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750192960 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 166.usbdev_tx_rx_disruption.1750192960
Directory /workspace/166.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/42.usbdev_device_address.361151859
Short name T111
Test name
Test status
Simulation time 45103940064 ps
CPU time 75.27 seconds
Started Aug 18 05:38:02 PM PDT 24
Finished Aug 18 05:39:17 PM PDT 24
Peak memory 207772 kb
Host smart-cd6d381c-b3f6-4401-a8cc-1655d18523cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36115
1859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.361151859
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1874201122
Short name T2
Test name
Test status
Simulation time 19038206424 ps
CPU time 49.44 seconds
Started Aug 18 05:31:59 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 215992 kb
Host smart-a51d6511-4e6b-456a-8e6a-1b6acf1f4a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18742
01122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1874201122
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_types.3760976417
Short name T83
Test name
Test status
Simulation time 641621753 ps
CPU time 1.58 seconds
Started Aug 18 05:35:39 PM PDT 24
Finished Aug 18 05:35:40 PM PDT 24
Peak memory 207552 kb
Host smart-0b1fb946-4c98-46da-863c-1bed1495d0a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3760976417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_types.3760976417
Directory /workspace/24.usbdev_endpoint_types/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1048422317
Short name T301
Test name
Test status
Simulation time 87814133 ps
CPU time 2.42 seconds
Started Aug 18 05:10:17 PM PDT 24
Finished Aug 18 05:10:20 PM PDT 24
Peak memory 215436 kb
Host smart-0fc54d50-d74f-44ac-829e-afc85fda63d4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1048422317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1048422317
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3179327880
Short name T241
Test name
Test status
Simulation time 104361433 ps
CPU time 2.53 seconds
Started Aug 18 05:10:22 PM PDT 24
Finished Aug 18 05:10:25 PM PDT 24
Peak memory 215672 kb
Host smart-12dfcbc6-558c-4707-8443-7f49328666da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179327880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3179327880
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.278122520
Short name T76
Test name
Test status
Simulation time 219970327 ps
CPU time 0.92 seconds
Started Aug 18 05:37:00 PM PDT 24
Finished Aug 18 05:37:01 PM PDT 24
Peak memory 207520 kb
Host smart-f0e4191c-d997-48b6-b0cc-2a4fe52db3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27812
2520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.278122520
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_rx_full.825594491
Short name T338
Test name
Test status
Simulation time 267180726 ps
CPU time 1.09 seconds
Started Aug 18 05:38:53 PM PDT 24
Finished Aug 18 05:38:55 PM PDT 24
Peak memory 207472 kb
Host smart-75042ff2-b674-4a46-82b5-ceb4d618e293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82559
4491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_full.825594491
Directory /workspace/48.usbdev_rx_full/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_types.2821216805
Short name T434
Test name
Test status
Simulation time 446659657 ps
CPU time 1.42 seconds
Started Aug 18 05:33:44 PM PDT 24
Finished Aug 18 05:33:45 PM PDT 24
Peak memory 207524 kb
Host smart-ed41ebd2-eda5-4b7a-942e-b3495b3786c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2821216805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_types.2821216805
Directory /workspace/12.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.3584557166
Short name T277
Test name
Test status
Simulation time 153310436 ps
CPU time 0.81 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 207452 kb
Host smart-60b6e737-8643-4bb7-b61a-e7d386ee726a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35845
57166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.3584557166
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/110.usbdev_endpoint_types.403011415
Short name T366
Test name
Test status
Simulation time 693066717 ps
CPU time 1.74 seconds
Started Aug 18 05:39:23 PM PDT 24
Finished Aug 18 05:39:25 PM PDT 24
Peak memory 207544 kb
Host smart-569d7bbb-66b0-4b06-a703-09d49c156dcc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=403011415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_endpoint_types.403011415
Directory /workspace/110.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/171.usbdev_endpoint_types.903321461
Short name T395
Test name
Test status
Simulation time 908195623 ps
CPU time 1.87 seconds
Started Aug 18 05:39:30 PM PDT 24
Finished Aug 18 05:39:32 PM PDT 24
Peak memory 207512 kb
Host smart-1a7177b0-2c43-4fc5-87d4-7b88377f997e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=903321461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_endpoint_types.903321461
Directory /workspace/171.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/65.usbdev_endpoint_types.930742236
Short name T410
Test name
Test status
Simulation time 655766973 ps
CPU time 1.82 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207568 kb
Host smart-6931d0ad-dd39-48ea-86a0-421845490863
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=930742236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_endpoint_types.930742236
Directory /workspace/65.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.85588227
Short name T55
Test name
Test status
Simulation time 137701263 ps
CPU time 0.84 seconds
Started Aug 18 05:31:53 PM PDT 24
Finished Aug 18 05:31:54 PM PDT 24
Peak memory 207356 kb
Host smart-9762698c-9802-4690-9623-c148bea6ea81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85588
227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.85588227
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3658827805
Short name T283
Test name
Test status
Simulation time 133217762 ps
CPU time 1.72 seconds
Started Aug 18 05:10:18 PM PDT 24
Finished Aug 18 05:10:20 PM PDT 24
Peak memory 207248 kb
Host smart-d5411eb3-c9a0-443e-9fd7-99413ff34dce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3658827805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3658827805
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3434987373
Short name T356
Test name
Test status
Simulation time 38596013 ps
CPU time 0.72 seconds
Started Aug 18 05:10:43 PM PDT 24
Finished Aug 18 05:10:44 PM PDT 24
Peak memory 206836 kb
Host smart-f7081179-5d57-44ad-bf4f-32552d326a12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3434987373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3434987373
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/default/101.usbdev_endpoint_types.570934462
Short name T417
Test name
Test status
Simulation time 744404224 ps
CPU time 1.81 seconds
Started Aug 18 05:39:11 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207504 kb
Host smart-e337676e-d8d8-4769-8c67-aecfca2480b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=570934462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_endpoint_types.570934462
Directory /workspace/101.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/94.usbdev_endpoint_types.1140082454
Short name T422
Test name
Test status
Simulation time 949393632 ps
CPU time 1.92 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207512 kb
Host smart-d06160f7-f170-447c-bbdf-51ca67b0ecf1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1140082454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_endpoint_types.1140082454
Directory /workspace/94.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/28.usbdev_device_address.2949164693
Short name T183
Test name
Test status
Simulation time 24292604693 ps
CPU time 39.79 seconds
Started Aug 18 05:35:58 PM PDT 24
Finished Aug 18 05:36:38 PM PDT 24
Peak memory 207860 kb
Host smart-7174be49-04ce-480c-9239-d691524d6c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29491
64693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.2949164693
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.64376471
Short name T134
Test name
Test status
Simulation time 2764900203 ps
CPU time 74.99 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:38:30 PM PDT 24
Peak memory 224208 kb
Host smart-3d20d774-19be-4517-b22a-cb6314efd7fc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=64376471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.64376471
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/117.usbdev_endpoint_types.165338344
Short name T450
Test name
Test status
Simulation time 452938507 ps
CPU time 1.49 seconds
Started Aug 18 05:39:12 PM PDT 24
Finished Aug 18 05:39:14 PM PDT 24
Peak memory 207540 kb
Host smart-1fec1b19-477e-4502-855a-a503b9bdc1c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=165338344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_endpoint_types.165338344
Directory /workspace/117.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/129.usbdev_endpoint_types.2499844227
Short name T438
Test name
Test status
Simulation time 464976051 ps
CPU time 1.38 seconds
Started Aug 18 05:39:14 PM PDT 24
Finished Aug 18 05:39:15 PM PDT 24
Peak memory 207456 kb
Host smart-df8f50c2-a189-45ca-bb63-ca5b2873d357
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2499844227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_endpoint_types.2499844227
Directory /workspace/129.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/168.usbdev_endpoint_types.3114814689
Short name T377
Test name
Test status
Simulation time 442622504 ps
CPU time 1.39 seconds
Started Aug 18 05:39:50 PM PDT 24
Finished Aug 18 05:39:52 PM PDT 24
Peak memory 207560 kb
Host smart-d688cf75-c23d-4067-9f20-aa8403383192
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3114814689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_endpoint_types.3114814689
Directory /workspace/168.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/173.usbdev_endpoint_types.4259439494
Short name T486
Test name
Test status
Simulation time 697223042 ps
CPU time 1.57 seconds
Started Aug 18 05:39:50 PM PDT 24
Finished Aug 18 05:39:52 PM PDT 24
Peak memory 207560 kb
Host smart-484768fd-a22d-467e-9704-527822f7e5be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4259439494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_endpoint_types.4259439494
Directory /workspace/173.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_types.2577352418
Short name T418
Test name
Test status
Simulation time 762349449 ps
CPU time 1.89 seconds
Started Aug 18 05:32:17 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 207528 kb
Host smart-9476a092-8c61-4473-8f18-c134ca6338e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2577352418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_types.2577352418
Directory /workspace/3.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/170.usbdev_tx_rx_disruption.73688088
Short name T71
Test name
Test status
Simulation time 556366430 ps
CPU time 1.71 seconds
Started Aug 18 05:39:19 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207544 kb
Host smart-0b7e1c18-0979-4670-aa20-a4e3406cc688
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73688088 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 170.usbdev_tx_rx_disruption.73688088
Directory /workspace/170.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1526333720
Short name T44
Test name
Test status
Simulation time 397526759 ps
CPU time 1.48 seconds
Started Aug 18 05:31:50 PM PDT 24
Finished Aug 18 05:31:51 PM PDT 24
Peak memory 207580 kb
Host smart-fbadb9a1-99c9-4037-b86b-be64c69e8951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15263
33720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1526333720
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4003288954
Short name T517
Test name
Test status
Simulation time 875961327 ps
CPU time 4.86 seconds
Started Aug 18 05:10:32 PM PDT 24
Finished Aug 18 05:10:37 PM PDT 24
Peak memory 207156 kb
Host smart-729e0a5f-7876-4e69-b1d5-4e6c204eadcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4003288954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.4003288954
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.2056137923
Short name T348
Test name
Test status
Simulation time 1361753883 ps
CPU time 3.47 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:33:44 PM PDT 24
Peak memory 207732 kb
Host smart-ffd4ba22-e81e-4331-947a-372376aedd7d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2056137923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2056137923
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/130.usbdev_endpoint_types.347870603
Short name T365
Test name
Test status
Simulation time 510743562 ps
CPU time 1.59 seconds
Started Aug 18 05:39:31 PM PDT 24
Finished Aug 18 05:39:33 PM PDT 24
Peak memory 207540 kb
Host smart-e813c820-17af-4284-8c49-01b23c10cd33
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=347870603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_endpoint_types.347870603
Directory /workspace/130.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/161.usbdev_endpoint_types.3538815791
Short name T476
Test name
Test status
Simulation time 487991764 ps
CPU time 1.51 seconds
Started Aug 18 05:39:20 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207452 kb
Host smart-d1d27cf1-2f26-4b40-803d-796fb76f814a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3538815791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_endpoint_types.3538815791
Directory /workspace/161.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/182.usbdev_endpoint_types.67688975
Short name T441
Test name
Test status
Simulation time 553254942 ps
CPU time 1.51 seconds
Started Aug 18 05:39:41 PM PDT 24
Finished Aug 18 05:39:43 PM PDT 24
Peak memory 207544 kb
Host smart-7536e6b1-dbe2-4406-a0df-c195c81362b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=67688975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_endpoint_types.67688975
Directory /workspace/182.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/60.usbdev_endpoint_types.2254043942
Short name T370
Test name
Test status
Simulation time 711080259 ps
CPU time 1.71 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207516 kb
Host smart-93a7f367-9438-4f2c-848e-91b77ee73228
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2254043942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_endpoint_types.2254043942
Directory /workspace/60.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.2856158172
Short name T1147
Test name
Test status
Simulation time 71792175 ps
CPU time 0.69 seconds
Started Aug 18 05:33:56 PM PDT 24
Finished Aug 18 05:33:57 PM PDT 24
Peak memory 207368 kb
Host smart-365172a2-6af4-427f-8f87-0a8ab3fc769c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2856158172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.2856158172
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.2985245188
Short name T78
Test name
Test status
Simulation time 4060627820 ps
CPU time 31.99 seconds
Started Aug 18 05:32:00 PM PDT 24
Finished Aug 18 05:32:32 PM PDT 24
Peak memory 224124 kb
Host smart-74c58225-6372-4232-9fff-d88200133f15
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985245188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.2985245188
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1435129185
Short name T250
Test name
Test status
Simulation time 48025347 ps
CPU time 0.74 seconds
Started Aug 18 05:10:54 PM PDT 24
Finished Aug 18 05:10:55 PM PDT 24
Peak memory 206820 kb
Host smart-bd05834e-fb00-42c9-ba58-d5ee54540b50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1435129185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1435129185
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/default/126.usbdev_endpoint_types.311223767
Short name T414
Test name
Test status
Simulation time 498125288 ps
CPU time 1.52 seconds
Started Aug 18 05:39:08 PM PDT 24
Finished Aug 18 05:39:10 PM PDT 24
Peak memory 207512 kb
Host smart-ae6f7db9-4632-4a9c-87dd-baf292274032
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=311223767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_endpoint_types.311223767
Directory /workspace/126.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/141.usbdev_endpoint_types.2766749598
Short name T457
Test name
Test status
Simulation time 582978088 ps
CPU time 1.61 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207572 kb
Host smart-da9250f2-d2f2-425b-90f3-ee1b3b1b09b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2766749598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_endpoint_types.2766749598
Directory /workspace/141.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3758734956
Short name T362
Test name
Test status
Simulation time 150601706 ps
CPU time 0.86 seconds
Started Aug 18 05:34:26 PM PDT 24
Finished Aug 18 05:34:27 PM PDT 24
Peak memory 207576 kb
Host smart-7e3cba6e-a03b-4a58-a23a-8d2838945623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37587
34956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3758734956
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/162.usbdev_endpoint_types.1996771924
Short name T474
Test name
Test status
Simulation time 669671727 ps
CPU time 1.79 seconds
Started Aug 18 05:39:14 PM PDT 24
Finished Aug 18 05:39:16 PM PDT 24
Peak memory 207452 kb
Host smart-6655e7d6-e61c-47f7-a7d4-3028cd9febf8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1996771924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_endpoint_types.1996771924
Directory /workspace/162.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1495998993
Short name T1721
Test name
Test status
Simulation time 1222585740 ps
CPU time 3.12 seconds
Started Aug 18 05:32:21 PM PDT 24
Finished Aug 18 05:32:24 PM PDT 24
Peak memory 207736 kb
Host smart-e4bc4a75-949c-4f4a-a72f-9d147edf0de8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1495998993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1495998993
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_types.1226779035
Short name T480
Test name
Test status
Simulation time 346209205 ps
CPU time 1.24 seconds
Started Aug 18 05:38:08 PM PDT 24
Finished Aug 18 05:38:09 PM PDT 24
Peak memory 207536 kb
Host smart-8052b55a-1ca7-448d-bec2-f4ac2665a609
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1226779035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_types.1226779035
Directory /workspace/45.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/76.usbdev_endpoint_types.3595757436
Short name T467
Test name
Test status
Simulation time 264875284 ps
CPU time 1.01 seconds
Started Aug 18 05:39:15 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207544 kb
Host smart-51336cd4-dafb-47c1-aab9-f472c8ab4b45
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3595757436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_endpoint_types.3595757436
Directory /workspace/76.usbdev_endpoint_types/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1283001476
Short name T3693
Test name
Test status
Simulation time 224955506 ps
CPU time 2.6 seconds
Started Aug 18 05:10:21 PM PDT 24
Finished Aug 18 05:10:24 PM PDT 24
Peak memory 223500 kb
Host smart-8676baa1-6085-4e3e-b3d5-8d355b8d6442
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1283001476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1283001476
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/default/27.usbdev_device_address.3372548123
Short name T524
Test name
Test status
Simulation time 38421499150 ps
CPU time 60.71 seconds
Started Aug 18 05:35:55 PM PDT 24
Finished Aug 18 05:36:56 PM PDT 24
Peak memory 207716 kb
Host smart-903c7de4-db6a-40d6-bb02-6e64a7600b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33725
48123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.3372548123
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.2080028868
Short name T54
Test name
Test status
Simulation time 137954947 ps
CPU time 0.83 seconds
Started Aug 18 05:31:29 PM PDT 24
Finished Aug 18 05:31:30 PM PDT 24
Peak memory 207424 kb
Host smart-81ad4c33-b895-4217-ab68-04ff56bd1bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20800
28868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.2080028868
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1994496146
Short name T518
Test name
Test status
Simulation time 5100299236 ps
CPU time 142.17 seconds
Started Aug 18 05:31:46 PM PDT 24
Finished Aug 18 05:34:09 PM PDT 24
Peak memory 215976 kb
Host smart-1c745aae-1ba0-48fe-bcd0-4e9fdc616915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19944
96146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1994496146
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_types.1846387320
Short name T3558
Test name
Test status
Simulation time 383923054 ps
CPU time 1.14 seconds
Started Aug 18 05:33:28 PM PDT 24
Finished Aug 18 05:33:29 PM PDT 24
Peak memory 207496 kb
Host smart-d342b804-b1a9-4b2d-8459-54c8731fca60
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1846387320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_types.1846387320
Directory /workspace/10.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/108.usbdev_endpoint_types.4248600091
Short name T411
Test name
Test status
Simulation time 319652359 ps
CPU time 1.26 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:38:57 PM PDT 24
Peak memory 207512 kb
Host smart-5e6c064b-ce97-4c89-926d-910519a84aee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4248600091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_endpoint_types.4248600091
Directory /workspace/108.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/133.usbdev_endpoint_types.912661417
Short name T430
Test name
Test status
Simulation time 588851122 ps
CPU time 1.5 seconds
Started Aug 18 05:39:02 PM PDT 24
Finished Aug 18 05:39:04 PM PDT 24
Peak memory 207500 kb
Host smart-8d9a66b7-fcaf-4eb0-8cd4-386a6ab84183
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=912661417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_endpoint_types.912661417
Directory /workspace/133.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/135.usbdev_endpoint_types.374251191
Short name T378
Test name
Test status
Simulation time 495695429 ps
CPU time 1.37 seconds
Started Aug 18 05:39:08 PM PDT 24
Finished Aug 18 05:39:10 PM PDT 24
Peak memory 207508 kb
Host smart-79ca02c4-c56c-45f5-a007-d8c3e9d96824
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=374251191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_endpoint_types.374251191
Directory /workspace/135.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/165.usbdev_endpoint_types.856658011
Short name T447
Test name
Test status
Simulation time 631040690 ps
CPU time 1.66 seconds
Started Aug 18 05:39:48 PM PDT 24
Finished Aug 18 05:39:49 PM PDT 24
Peak memory 207524 kb
Host smart-25d415c2-7a5f-4d11-a784-74b5bdd3f386
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=856658011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_endpoint_types.856658011
Directory /workspace/165.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/169.usbdev_endpoint_types.822898884
Short name T427
Test name
Test status
Simulation time 390432445 ps
CPU time 1.15 seconds
Started Aug 18 05:39:37 PM PDT 24
Finished Aug 18 05:39:38 PM PDT 24
Peak memory 207492 kb
Host smart-6c17e779-62a7-45f0-85fe-f39abcc2386c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=822898884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_endpoint_types.822898884
Directory /workspace/169.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_types.568213643
Short name T459
Test name
Test status
Simulation time 614368481 ps
CPU time 1.47 seconds
Started Aug 18 05:32:47 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207532 kb
Host smart-e7d35635-86d2-4f58-826c-0aec3dba26e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=568213643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_types.568213643
Directory /workspace/7.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3329356033
Short name T174
Test name
Test status
Simulation time 254885216 ps
CPU time 1.02 seconds
Started Aug 18 05:31:48 PM PDT 24
Finished Aug 18 05:31:49 PM PDT 24
Peak memory 207476 kb
Host smart-0d05f146-d36b-47b3-861a-003a76b61309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33293
56033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3329356033
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.3173002340
Short name T560
Test name
Test status
Simulation time 5336447098 ps
CPU time 57.93 seconds
Started Aug 18 05:31:51 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 215832 kb
Host smart-006e6b71-fd4e-40fb-8547-fb8f38356471
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173002340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.3173002340
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.3344453171
Short name T185
Test name
Test status
Simulation time 6452205930 ps
CPU time 30.61 seconds
Started Aug 18 05:32:25 PM PDT 24
Finished Aug 18 05:32:55 PM PDT 24
Peak memory 218752 kb
Host smart-f68bb72e-cd33-4c08-86e5-95e3078a2cc9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344453171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.3344453171
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1380724257
Short name T1175
Test name
Test status
Simulation time 16562913420 ps
CPU time 28.23 seconds
Started Aug 18 05:33:53 PM PDT 24
Finished Aug 18 05:34:22 PM PDT 24
Peak memory 207752 kb
Host smart-27056500-9274-43e5-893d-c4a8a1cf72fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13807
24257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1380724257
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1614456527
Short name T774
Test name
Test status
Simulation time 38788149 ps
CPU time 0.69 seconds
Started Aug 18 05:37:12 PM PDT 24
Finished Aug 18 05:37:13 PM PDT 24
Peak memory 207536 kb
Host smart-558e86e9-7223-4783-89ec-85c15f04b07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16144
56527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1614456527
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.1464279424
Short name T79
Test name
Test status
Simulation time 8745267878 ps
CPU time 142.42 seconds
Started Aug 18 05:32:39 PM PDT 24
Finished Aug 18 05:35:01 PM PDT 24
Peak memory 224108 kb
Host smart-0b51b929-94ff-46ea-ba76-36ba5a867a8b
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464279424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.1464279424
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.216151459
Short name T508
Test name
Test status
Simulation time 1148307428 ps
CPU time 4.97 seconds
Started Aug 18 05:10:17 PM PDT 24
Finished Aug 18 05:10:22 PM PDT 24
Peak memory 207148 kb
Host smart-1c3af8b1-7d9c-4236-9c8d-58a0305a3b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=216151459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.216151459
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.281724821
Short name T537
Test name
Test status
Simulation time 106106763702 ps
CPU time 158.25 seconds
Started Aug 18 05:31:50 PM PDT 24
Finished Aug 18 05:34:28 PM PDT 24
Peak memory 207688 kb
Host smart-a94a4c64-a7b5-481d-9e5c-2b07f570c257
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=281724821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.281724821
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.1037698310
Short name T542
Test name
Test status
Simulation time 120948759707 ps
CPU time 193.81 seconds
Started Aug 18 05:31:37 PM PDT 24
Finished Aug 18 05:34:51 PM PDT 24
Peak memory 207836 kb
Host smart-cf5b125c-aaa8-43a4-ab6e-b6eebd036eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037698310 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.1037698310
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.88227887
Short name T131
Test name
Test status
Simulation time 2639666048 ps
CPU time 20.38 seconds
Started Aug 18 05:32:08 PM PDT 24
Finished Aug 18 05:32:28 PM PDT 24
Peak memory 218068 kb
Host smart-a101d954-1e07-4e99-9dae-5486eb61122c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=88227887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.88227887
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.375367655
Short name T18
Test name
Test status
Simulation time 285624831 ps
CPU time 1.29 seconds
Started Aug 18 05:33:12 PM PDT 24
Finished Aug 18 05:33:14 PM PDT 24
Peak memory 215844 kb
Host smart-8d77d7bc-50d9-426b-98a8-209bc923bfaf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=375367655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.375367655
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/116.usbdev_endpoint_types.3796928983
Short name T408
Test name
Test status
Simulation time 452174556 ps
CPU time 1.33 seconds
Started Aug 18 05:39:33 PM PDT 24
Finished Aug 18 05:39:35 PM PDT 24
Peak memory 207508 kb
Host smart-f8a3e512-8f72-4d3f-a060-733db0737053
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3796928983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_endpoint_types.3796928983
Directory /workspace/116.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_max_non_iso_usb_traffic.1387348354
Short name T535
Test name
Test status
Simulation time 2710858142 ps
CPU time 26.2 seconds
Started Aug 18 05:33:54 PM PDT 24
Finished Aug 18 05:34:20 PM PDT 24
Peak memory 224112 kb
Host smart-9542ecf4-96cf-41d5-ad1a-66ef6b1ab3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13873
48354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_non_iso_usb_traffic.1387348354
Directory /workspace/13.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/139.usbdev_endpoint_types.1100079929
Short name T371
Test name
Test status
Simulation time 285306397 ps
CPU time 1.02 seconds
Started Aug 18 05:39:01 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207520 kb
Host smart-4e647b7b-9057-4843-8799-fec7e92e700a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1100079929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_endpoint_types.1100079929
Directory /workspace/139.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_types.4181903018
Short name T504
Test name
Test status
Simulation time 405680556 ps
CPU time 1.27 seconds
Started Aug 18 05:34:03 PM PDT 24
Finished Aug 18 05:34:05 PM PDT 24
Peak memory 207548 kb
Host smart-69963e7d-0066-4497-9916-9a149fe55256
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4181903018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_types.4181903018
Directory /workspace/15.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/158.usbdev_endpoint_types.3579066710
Short name T367
Test name
Test status
Simulation time 717871336 ps
CPU time 1.77 seconds
Started Aug 18 05:39:20 PM PDT 24
Finished Aug 18 05:39:22 PM PDT 24
Peak memory 207548 kb
Host smart-86e9ffb6-7201-4c97-a135-a00ff29da67b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3579066710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_endpoint_types.3579066710
Directory /workspace/158.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1440329886
Short name T651
Test name
Test status
Simulation time 153474772 ps
CPU time 0.85 seconds
Started Aug 18 05:34:25 PM PDT 24
Finished Aug 18 05:34:26 PM PDT 24
Peak memory 207484 kb
Host smart-a36cc22f-da33-4180-8d49-0e0ae1e591e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14403
29886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1440329886
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_types.3351031729
Short name T388
Test name
Test status
Simulation time 299295936 ps
CPU time 1.36 seconds
Started Aug 18 05:34:30 PM PDT 24
Finished Aug 18 05:34:32 PM PDT 24
Peak memory 207516 kb
Host smart-cb5aeeee-cd8c-41f5-bd89-6ff3aef66f7b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3351031729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_types.3351031729
Directory /workspace/17.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/184.usbdev_endpoint_types.805502152
Short name T399
Test name
Test status
Simulation time 747898834 ps
CPU time 1.63 seconds
Started Aug 18 05:39:49 PM PDT 24
Finished Aug 18 05:39:50 PM PDT 24
Peak memory 207504 kb
Host smart-7dfecceb-d5b9-4292-bcf9-85b42e437b86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=805502152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_endpoint_types.805502152
Directory /workspace/184.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/187.usbdev_endpoint_types.3499187416
Short name T479
Test name
Test status
Simulation time 562612952 ps
CPU time 1.49 seconds
Started Aug 18 05:39:50 PM PDT 24
Finished Aug 18 05:39:52 PM PDT 24
Peak memory 207460 kb
Host smart-86510f0c-0481-4887-abee-fd5de65c4526
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3499187416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_endpoint_types.3499187416
Directory /workspace/187.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/193.usbdev_endpoint_types.2871930750
Short name T384
Test name
Test status
Simulation time 431540051 ps
CPU time 1.2 seconds
Started Aug 18 05:39:41 PM PDT 24
Finished Aug 18 05:39:42 PM PDT 24
Peak memory 207540 kb
Host smart-69c2d514-2f5c-482b-9e33-686e2451c503
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2871930750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_endpoint_types.2871930750
Directory /workspace/193.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/29.usbdev_rx_full.696120400
Short name T345
Test name
Test status
Simulation time 323931475 ps
CPU time 1.2 seconds
Started Aug 18 05:36:10 PM PDT 24
Finished Aug 18 05:36:11 PM PDT 24
Peak memory 207360 kb
Host smart-9c2fd53e-394a-475e-a9ad-85c7db1d9e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69612
0400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_full.696120400
Directory /workspace/29.usbdev_rx_full/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_types.2192119358
Short name T451
Test name
Test status
Simulation time 504917126 ps
CPU time 1.38 seconds
Started Aug 18 05:38:09 PM PDT 24
Finished Aug 18 05:38:10 PM PDT 24
Peak memory 207460 kb
Host smart-8b9ddd6a-78a9-4d86-b701-b3db1699b0be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2192119358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_types.2192119358
Directory /workspace/43.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/44.usbdev_rx_full.1152644238
Short name T343
Test name
Test status
Simulation time 255948249 ps
CPU time 1.08 seconds
Started Aug 18 05:38:25 PM PDT 24
Finished Aug 18 05:38:26 PM PDT 24
Peak memory 207476 kb
Host smart-9e9bc31d-cbc0-47df-aa5b-fbe744b8a9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11526
44238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_full.1152644238
Directory /workspace/44.usbdev_rx_full/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3168636202
Short name T871
Test name
Test status
Simulation time 136007776 ps
CPU time 0.83 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:34:40 PM PDT 24
Peak memory 207456 kb
Host smart-3edab904-de7d-458b-8fed-2b9efabee6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31686
36202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3168636202
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/143.usbdev_tx_rx_disruption.2822420106
Short name T717
Test name
Test status
Simulation time 500515301 ps
CPU time 1.54 seconds
Started Aug 18 05:39:11 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207560 kb
Host smart-ee2e7ee1-80e3-4e59-afdd-116f076c3661
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822420106 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.usbdev_tx_rx_disruption.2822420106
Directory /workspace/143.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.2582145051
Short name T1591
Test name
Test status
Simulation time 25812174978 ps
CPU time 36.98 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:35:16 PM PDT 24
Peak memory 216000 kb
Host smart-e7637aea-fba1-49b8-931d-278661158009
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582145051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_resume.2582145051
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.4129838211
Short name T85
Test name
Test status
Simulation time 164595391 ps
CPU time 0.88 seconds
Started Aug 18 05:32:13 PM PDT 24
Finished Aug 18 05:32:14 PM PDT 24
Peak memory 207464 kb
Host smart-b69ed96f-6318-466b-80e5-575bcdea27d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41298
38211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.4129838211
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3752810922
Short name T9
Test name
Test status
Simulation time 105211164 ps
CPU time 0.94 seconds
Started Aug 18 05:10:16 PM PDT 24
Finished Aug 18 05:10:17 PM PDT 24
Peak memory 207024 kb
Host smart-12866efd-a0b7-4c62-8e01-4c7fd4fd7a81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3752810922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3752810922
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.801197965
Short name T3565
Test name
Test status
Simulation time 143716374 ps
CPU time 0.84 seconds
Started Aug 18 05:31:50 PM PDT 24
Finished Aug 18 05:31:51 PM PDT 24
Peak memory 207468 kb
Host smart-a291e261-8267-4a6c-bd9e-82f0976c5d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80119
7965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.801197965
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_device_address.2902448559
Short name T1503
Test name
Test status
Simulation time 22655302996 ps
CPU time 43.78 seconds
Started Aug 18 05:31:37 PM PDT 24
Finished Aug 18 05:32:20 PM PDT 24
Peak memory 207772 kb
Host smart-4764c7d0-be97-449d-bf61-6093bd47ec05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29024
48559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.2902448559
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.2478079954
Short name T58
Test name
Test status
Simulation time 4155480886 ps
CPU time 10.4 seconds
Started Aug 18 05:31:52 PM PDT 24
Finished Aug 18 05:32:02 PM PDT 24
Peak memory 207768 kb
Host smart-88b91c54-66f3-4c53-a8d0-6bd71618a949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24780
79954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.2478079954
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.934608220
Short name T65
Test name
Test status
Simulation time 456685955 ps
CPU time 1.47 seconds
Started Aug 18 05:31:27 PM PDT 24
Finished Aug 18 05:31:28 PM PDT 24
Peak memory 207472 kb
Host smart-b03e166d-bc96-4e84-bb73-22ff2b6397b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93460
8220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.934608220
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.2433727058
Short name T59
Test name
Test status
Simulation time 217956166 ps
CPU time 0.89 seconds
Started Aug 18 05:31:53 PM PDT 24
Finished Aug 18 05:31:54 PM PDT 24
Peak memory 207456 kb
Host smart-1047509a-2b3c-4450-9aff-3249e0b5e614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24337
27058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.2433727058
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.1107931653
Short name T3182
Test name
Test status
Simulation time 163999944 ps
CPU time 0.84 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:31:55 PM PDT 24
Peak memory 207488 kb
Host smart-bab14816-4e38-4922-bee8-024f41590f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11079
31653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.1107931653
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.783834496
Short name T38
Test name
Test status
Simulation time 172833689 ps
CPU time 0.92 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:31:59 PM PDT 24
Peak memory 206912 kb
Host smart-67a2410d-3a25-4133-9713-532760605b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78383
4496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.783834496
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/372.usbdev_tx_rx_disruption.3028331617
Short name T1615
Test name
Test status
Simulation time 629289483 ps
CPU time 1.83 seconds
Started Aug 18 05:40:25 PM PDT 24
Finished Aug 18 05:40:32 PM PDT 24
Peak memory 207584 kb
Host smart-1864517c-e1cc-42c2-94f0-851cf984d1a5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028331617 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 372.usbdev_tx_rx_disruption.3028331617
Directory /workspace/372.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.1469483271
Short name T3101
Test name
Test status
Simulation time 5000533830 ps
CPU time 45.36 seconds
Started Aug 18 05:33:16 PM PDT 24
Finished Aug 18 05:34:02 PM PDT 24
Peak memory 218180 kb
Host smart-c8776b98-a6a6-4bc8-837b-37c0fe36f14f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469483271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1469483271
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2137111166
Short name T3677
Test name
Test status
Simulation time 110098106 ps
CPU time 1.41 seconds
Started Aug 18 05:10:16 PM PDT 24
Finished Aug 18 05:10:18 PM PDT 24
Peak memory 215468 kb
Host smart-bd9b0b62-c255-4b2d-81ca-5f82dcaaffcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137111166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2137111166
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2277505710
Short name T145
Test name
Test status
Simulation time 207416640 ps
CPU time 0.94 seconds
Started Aug 18 05:31:59 PM PDT 24
Finished Aug 18 05:32:00 PM PDT 24
Peak memory 207476 kb
Host smart-e325f0e7-13da-4e6e-abda-02da54e4460c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22775
05710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2277505710
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2848540457
Short name T162
Test name
Test status
Simulation time 234406301 ps
CPU time 0.97 seconds
Started Aug 18 05:33:34 PM PDT 24
Finished Aug 18 05:33:36 PM PDT 24
Peak memory 207488 kb
Host smart-4c6eda93-182e-49de-9b20-738a1b044911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28485
40457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2848540457
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/108.usbdev_tx_rx_disruption.3195230856
Short name T1370
Test name
Test status
Simulation time 490500957 ps
CPU time 1.52 seconds
Started Aug 18 05:39:04 PM PDT 24
Finished Aug 18 05:39:05 PM PDT 24
Peak memory 207580 kb
Host smart-08f51d95-3ed3-48c0-b952-1f06cee18bea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195230856 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.usbdev_tx_rx_disruption.3195230856
Directory /workspace/108.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.148275738
Short name T3520
Test name
Test status
Simulation time 183574785 ps
CPU time 0.93 seconds
Started Aug 18 05:33:38 PM PDT 24
Finished Aug 18 05:33:40 PM PDT 24
Peak memory 207412 kb
Host smart-82a4cfb3-71dc-41b9-85dc-faf0efea3247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14827
5738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.148275738
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2638116274
Short name T778
Test name
Test status
Simulation time 238064350 ps
CPU time 1.89 seconds
Started Aug 18 05:33:39 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 207656 kb
Host smart-85fb0aee-8243-49d4-8716-e1ad95312352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26381
16274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2638116274
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1192725236
Short name T3610
Test name
Test status
Simulation time 189874714 ps
CPU time 0.86 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:33:44 PM PDT 24
Peak memory 207492 kb
Host smart-81d54c2b-a52e-487d-bb45-3395ad5beb27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11927
25236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1192725236
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2463124349
Short name T156
Test name
Test status
Simulation time 226306607 ps
CPU time 1.07 seconds
Started Aug 18 05:33:57 PM PDT 24
Finished Aug 18 05:33:58 PM PDT 24
Peak memory 207528 kb
Host smart-3b2f87ce-0470-4831-bdbb-993111a7ae75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24631
24349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2463124349
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.260151997
Short name T949
Test name
Test status
Simulation time 7393061034 ps
CPU time 83.81 seconds
Started Aug 18 05:33:56 PM PDT 24
Finished Aug 18 05:35:20 PM PDT 24
Peak memory 207712 kb
Host smart-16e61b71-1b97-4274-840c-fb2d5308c4b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=260151997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.260151997
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1530409946
Short name T153
Test name
Test status
Simulation time 255864378 ps
CPU time 0.98 seconds
Started Aug 18 05:34:15 PM PDT 24
Finished Aug 18 05:34:16 PM PDT 24
Peak memory 207216 kb
Host smart-d78cab8c-08fa-4ed4-a9d3-cd349b554016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15304
09946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1530409946
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2696161828
Short name T158
Test name
Test status
Simulation time 257388844 ps
CPU time 1.04 seconds
Started Aug 18 05:34:18 PM PDT 24
Finished Aug 18 05:34:19 PM PDT 24
Peak memory 207416 kb
Host smart-721c057e-2273-47e5-b1f9-657ab0773ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26961
61828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2696161828
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.3198834167
Short name T2677
Test name
Test status
Simulation time 228486028 ps
CPU time 1.01 seconds
Started Aug 18 05:34:36 PM PDT 24
Finished Aug 18 05:34:38 PM PDT 24
Peak memory 207508 kb
Host smart-5fa4db85-a9d4-45a2-814c-0650beec0aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31988
34167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3198834167
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.447736070
Short name T3434
Test name
Test status
Simulation time 205125896 ps
CPU time 0.9 seconds
Started Aug 18 05:32:06 PM PDT 24
Finished Aug 18 05:32:07 PM PDT 24
Peak memory 207504 kb
Host smart-7e676d5d-6f9f-4986-80ba-87fa9875ac64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44773
6070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.447736070
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.511977113
Short name T164
Test name
Test status
Simulation time 184494729 ps
CPU time 0.89 seconds
Started Aug 18 05:36:04 PM PDT 24
Finished Aug 18 05:36:05 PM PDT 24
Peak memory 207468 kb
Host smart-ce175844-368f-4f93-ae6e-7a1ae928b0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51197
7113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.511977113
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.153499375
Short name T305
Test name
Test status
Simulation time 102247345 ps
CPU time 2.01 seconds
Started Aug 18 05:10:03 PM PDT 24
Finished Aug 18 05:10:05 PM PDT 24
Peak memory 207028 kb
Host smart-7dd321b6-66c3-4893-b28c-ecbf10b8be87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=153499375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.153499375
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.825934102
Short name T3661
Test name
Test status
Simulation time 1898405293 ps
CPU time 8.61 seconds
Started Aug 18 05:10:06 PM PDT 24
Finished Aug 18 05:10:15 PM PDT 24
Peak memory 207204 kb
Host smart-a6549888-3ffe-4b71-9825-ad484c7c6a47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=825934102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.825934102
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3088059416
Short name T3674
Test name
Test status
Simulation time 66687877 ps
CPU time 0.89 seconds
Started Aug 18 05:10:03 PM PDT 24
Finished Aug 18 05:10:04 PM PDT 24
Peak memory 206880 kb
Host smart-1f173e96-5fa1-4e36-aaf1-075d63a20d8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3088059416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3088059416
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2342855681
Short name T3717
Test name
Test status
Simulation time 78139133 ps
CPU time 1.11 seconds
Started Aug 18 05:10:03 PM PDT 24
Finished Aug 18 05:10:04 PM PDT 24
Peak memory 206904 kb
Host smart-e11a1c61-2688-460d-836f-f8d580863ad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2342855681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2342855681
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3850868365
Short name T3651
Test name
Test status
Simulation time 62778035 ps
CPU time 0.81 seconds
Started Aug 18 05:10:03 PM PDT 24
Finished Aug 18 05:10:04 PM PDT 24
Peak memory 206932 kb
Host smart-49524211-1596-40c3-9160-999536ee4c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3850868365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3850868365
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2902131804
Short name T313
Test name
Test status
Simulation time 79689602 ps
CPU time 2.24 seconds
Started Aug 18 05:10:04 PM PDT 24
Finished Aug 18 05:10:07 PM PDT 24
Peak memory 215332 kb
Host smart-627cfae6-37fc-4fa2-b1c2-a613db746559
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2902131804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2902131804
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3787223583
Short name T3688
Test name
Test status
Simulation time 101007060 ps
CPU time 2.42 seconds
Started Aug 18 05:10:04 PM PDT 24
Finished Aug 18 05:10:06 PM PDT 24
Peak memory 207116 kb
Host smart-077e44cb-c79f-4eb8-b084-45fc09b3ca46
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3787223583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3787223583
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1524197557
Short name T3671
Test name
Test status
Simulation time 254803408 ps
CPU time 1.89 seconds
Started Aug 18 05:10:16 PM PDT 24
Finished Aug 18 05:10:18 PM PDT 24
Peak memory 207224 kb
Host smart-a8cc9690-0089-4cc8-92e7-e2725be1ca65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1524197557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1524197557
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.4216660950
Short name T3701
Test name
Test status
Simulation time 113688971 ps
CPU time 3.04 seconds
Started Aug 18 05:10:05 PM PDT 24
Finished Aug 18 05:10:08 PM PDT 24
Peak memory 223292 kb
Host smart-b3d6ecbe-e921-4fed-b0e1-2e277f422966
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4216660950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.4216660950
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3694529567
Short name T278
Test name
Test status
Simulation time 681537618 ps
CPU time 4.6 seconds
Started Aug 18 05:10:04 PM PDT 24
Finished Aug 18 05:10:09 PM PDT 24
Peak memory 207176 kb
Host smart-061a0aa4-9f2c-4ede-ac5f-cd542beab791
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3694529567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3694529567
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1614705261
Short name T272
Test name
Test status
Simulation time 100371468 ps
CPU time 1.99 seconds
Started Aug 18 05:10:15 PM PDT 24
Finished Aug 18 05:10:17 PM PDT 24
Peak memory 207096 kb
Host smart-30589db1-0a02-4648-9656-2492c3da5f99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1614705261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1614705261
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1396298163
Short name T3640
Test name
Test status
Simulation time 1585159973 ps
CPU time 9.42 seconds
Started Aug 18 05:10:15 PM PDT 24
Finished Aug 18 05:10:24 PM PDT 24
Peak memory 207160 kb
Host smart-d542d18d-06b0-4e16-85eb-f28caa07100d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1396298163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1396298163
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2663149471
Short name T302
Test name
Test status
Simulation time 73956516 ps
CPU time 0.8 seconds
Started Aug 18 05:10:17 PM PDT 24
Finished Aug 18 05:10:18 PM PDT 24
Peak memory 206888 kb
Host smart-941de285-25bf-4538-8e01-02a48d331ae0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2663149471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2663149471
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1442861758
Short name T3724
Test name
Test status
Simulation time 155583715 ps
CPU time 2.09 seconds
Started Aug 18 05:10:17 PM PDT 24
Finished Aug 18 05:10:20 PM PDT 24
Peak memory 215444 kb
Host smart-3349e2a8-54fe-42c0-a2d1-acffbaf336ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442861758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1442861758
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.645909056
Short name T307
Test name
Test status
Simulation time 53718308 ps
CPU time 0.84 seconds
Started Aug 18 05:10:16 PM PDT 24
Finished Aug 18 05:10:17 PM PDT 24
Peak memory 206808 kb
Host smart-a1f44d25-302d-4eef-9424-005a13d1f6df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=645909056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.645909056
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1415662993
Short name T358
Test name
Test status
Simulation time 97413686 ps
CPU time 0.81 seconds
Started Aug 18 05:10:16 PM PDT 24
Finished Aug 18 05:10:17 PM PDT 24
Peak memory 206940 kb
Host smart-2d0a2d6c-dfc6-4972-9831-8672f062bc8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1415662993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1415662993
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2917258579
Short name T303
Test name
Test status
Simulation time 105271839 ps
CPU time 1.51 seconds
Started Aug 18 05:10:17 PM PDT 24
Finished Aug 18 05:10:19 PM PDT 24
Peak memory 207056 kb
Host smart-69b8d60c-1a3f-4b01-b8c4-80289017ebfa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2917258579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2917258579
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3370339342
Short name T3656
Test name
Test status
Simulation time 259483632 ps
CPU time 2.7 seconds
Started Aug 18 05:10:15 PM PDT 24
Finished Aug 18 05:10:18 PM PDT 24
Peak memory 206980 kb
Host smart-a58547a8-7546-4a81-aa92-31a071da3651
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3370339342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3370339342
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2291558759
Short name T3714
Test name
Test status
Simulation time 144881253 ps
CPU time 1.25 seconds
Started Aug 18 05:10:16 PM PDT 24
Finished Aug 18 05:10:17 PM PDT 24
Peak memory 207284 kb
Host smart-e099b34b-5e2e-4ec9-99b7-c384c062c152
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2291558759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2291558759
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.375757568
Short name T3736
Test name
Test status
Simulation time 56223549 ps
CPU time 1.15 seconds
Started Aug 18 05:10:34 PM PDT 24
Finished Aug 18 05:10:35 PM PDT 24
Peak memory 215300 kb
Host smart-9426e7b3-afe6-4321-805d-32efdfdb4301
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375757568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.375757568
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2650878902
Short name T309
Test name
Test status
Simulation time 147867405 ps
CPU time 0.95 seconds
Started Aug 18 05:10:35 PM PDT 24
Finished Aug 18 05:10:36 PM PDT 24
Peak memory 206996 kb
Host smart-2cd5635e-ff51-40de-a1d1-e32237de572c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2650878902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2650878902
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.926111426
Short name T3716
Test name
Test status
Simulation time 46753687 ps
CPU time 0.75 seconds
Started Aug 18 05:10:32 PM PDT 24
Finished Aug 18 05:10:33 PM PDT 24
Peak memory 206880 kb
Host smart-3202f093-f6c7-41d1-8a12-b276d371aae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=926111426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.926111426
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.513482190
Short name T322
Test name
Test status
Simulation time 189740007 ps
CPU time 1.2 seconds
Started Aug 18 05:10:34 PM PDT 24
Finished Aug 18 05:10:36 PM PDT 24
Peak memory 207056 kb
Host smart-aa20eabd-4965-4379-bce2-3762edf0fa26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=513482190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.513482190
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.77954297
Short name T286
Test name
Test status
Simulation time 254598040 ps
CPU time 3.06 seconds
Started Aug 18 05:10:34 PM PDT 24
Finished Aug 18 05:10:37 PM PDT 24
Peak memory 223112 kb
Host smart-d76e643a-f72f-48bb-9a34-f2169de02121
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=77954297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.77954297
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2067385896
Short name T3703
Test name
Test status
Simulation time 125416746 ps
CPU time 1.34 seconds
Started Aug 18 05:10:34 PM PDT 24
Finished Aug 18 05:10:35 PM PDT 24
Peak memory 215492 kb
Host smart-b0c901ea-f191-433f-af6a-f6572b961214
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067385896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2067385896
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1515643919
Short name T3662
Test name
Test status
Simulation time 95235830 ps
CPU time 0.86 seconds
Started Aug 18 05:10:31 PM PDT 24
Finished Aug 18 05:10:32 PM PDT 24
Peak memory 206984 kb
Host smart-d8706500-0cb6-40ea-92b4-3a31860d5f7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1515643919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1515643919
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3303505811
Short name T3682
Test name
Test status
Simulation time 39442920 ps
CPU time 0.72 seconds
Started Aug 18 05:10:31 PM PDT 24
Finished Aug 18 05:10:31 PM PDT 24
Peak memory 206820 kb
Host smart-45a69419-6db0-446d-9f12-f49f2bea4028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3303505811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3303505811
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1206169851
Short name T3695
Test name
Test status
Simulation time 184949451 ps
CPU time 1.73 seconds
Started Aug 18 05:10:33 PM PDT 24
Finished Aug 18 05:10:34 PM PDT 24
Peak memory 207308 kb
Host smart-0f956943-49d8-435f-bc35-a89b43071586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1206169851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1206169851
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3157065737
Short name T3718
Test name
Test status
Simulation time 125146070 ps
CPU time 1.79 seconds
Started Aug 18 05:10:32 PM PDT 24
Finished Aug 18 05:10:34 PM PDT 24
Peak memory 207104 kb
Host smart-75c0ae55-1958-4bcf-abf0-18ca06975509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3157065737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3157065737
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.382392864
Short name T516
Test name
Test status
Simulation time 529835374 ps
CPU time 4.23 seconds
Started Aug 18 05:10:32 PM PDT 24
Finished Aug 18 05:10:36 PM PDT 24
Peak memory 207168 kb
Host smart-5fe06e33-aba9-4aac-8b3c-6fd101832d21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=382392864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.382392864
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3064183446
Short name T3735
Test name
Test status
Simulation time 111811154 ps
CPU time 2.1 seconds
Started Aug 18 05:10:36 PM PDT 24
Finished Aug 18 05:10:38 PM PDT 24
Peak memory 215556 kb
Host smart-c62b8a4c-fba1-4339-bf01-b668af4cf765
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064183446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.3064183446
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3515934731
Short name T311
Test name
Test status
Simulation time 65271408 ps
CPU time 0.85 seconds
Started Aug 18 05:10:35 PM PDT 24
Finished Aug 18 05:10:36 PM PDT 24
Peak memory 206912 kb
Host smart-574574cb-4968-4a11-94f8-c9609d439aab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3515934731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3515934731
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.667089363
Short name T359
Test name
Test status
Simulation time 29725276 ps
CPU time 0.73 seconds
Started Aug 18 05:10:31 PM PDT 24
Finished Aug 18 05:10:31 PM PDT 24
Peak memory 206852 kb
Host smart-9627691b-834a-45b1-8aa2-97cf1e2ae17b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=667089363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.667089363
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3294796611
Short name T323
Test name
Test status
Simulation time 144695525 ps
CPU time 1.51 seconds
Started Aug 18 05:10:34 PM PDT 24
Finished Aug 18 05:10:36 PM PDT 24
Peak memory 207264 kb
Host smart-19bca808-2ef6-4965-8c9a-56744a715bb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3294796611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3294796611
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1508499689
Short name T242
Test name
Test status
Simulation time 143784687 ps
CPU time 1.87 seconds
Started Aug 18 05:10:33 PM PDT 24
Finished Aug 18 05:10:35 PM PDT 24
Peak memory 214724 kb
Host smart-90b8d59f-8c42-486f-a27a-507aba5f80e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1508499689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1508499689
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1039680983
Short name T269
Test name
Test status
Simulation time 311730593 ps
CPU time 2.59 seconds
Started Aug 18 05:10:32 PM PDT 24
Finished Aug 18 05:10:35 PM PDT 24
Peak memory 207312 kb
Host smart-ed6f32cc-098a-42e8-abde-81794439741a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1039680983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1039680983
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1056479479
Short name T3649
Test name
Test status
Simulation time 150419725 ps
CPU time 2 seconds
Started Aug 18 05:10:34 PM PDT 24
Finished Aug 18 05:10:36 PM PDT 24
Peak memory 215572 kb
Host smart-ae2d8b0b-8bd2-4bd1-a64d-a389ff3fb812
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056479479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1056479479
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.817849493
Short name T3713
Test name
Test status
Simulation time 56999025 ps
CPU time 0.84 seconds
Started Aug 18 05:10:35 PM PDT 24
Finished Aug 18 05:10:36 PM PDT 24
Peak memory 206904 kb
Host smart-8351783e-23d8-44fa-847d-b7c27035f668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=817849493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.817849493
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3504624086
Short name T3667
Test name
Test status
Simulation time 41532472 ps
CPU time 0.7 seconds
Started Aug 18 05:10:35 PM PDT 24
Finished Aug 18 05:10:36 PM PDT 24
Peak memory 206564 kb
Host smart-9315586f-4774-464e-acf2-2380a011455e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3504624086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3504624086
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2124082750
Short name T327
Test name
Test status
Simulation time 330106225 ps
CPU time 1.85 seconds
Started Aug 18 05:10:33 PM PDT 24
Finished Aug 18 05:10:35 PM PDT 24
Peak memory 206516 kb
Host smart-4c4628d6-10c6-42ad-bca4-e7ab741375c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2124082750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2124082750
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2466110892
Short name T287
Test name
Test status
Simulation time 114999623 ps
CPU time 1.5 seconds
Started Aug 18 05:10:35 PM PDT 24
Finished Aug 18 05:10:37 PM PDT 24
Peak memory 207268 kb
Host smart-e11f1761-e823-4130-90c9-86e3448afb6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2466110892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2466110892
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1270374417
Short name T509
Test name
Test status
Simulation time 986221871 ps
CPU time 5.29 seconds
Started Aug 18 05:10:33 PM PDT 24
Finished Aug 18 05:10:39 PM PDT 24
Peak memory 207304 kb
Host smart-4111abc1-9493-469d-beb5-0032ec0e2b96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1270374417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1270374417
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2328839491
Short name T243
Test name
Test status
Simulation time 82977581 ps
CPU time 1.28 seconds
Started Aug 18 05:10:41 PM PDT 24
Finished Aug 18 05:10:43 PM PDT 24
Peak memory 215344 kb
Host smart-3f1feb5f-4925-4a80-a9c4-555f73f2563c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328839491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2328839491
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.391406622
Short name T3664
Test name
Test status
Simulation time 55644602 ps
CPU time 0.83 seconds
Started Aug 18 05:10:43 PM PDT 24
Finished Aug 18 05:10:44 PM PDT 24
Peak memory 206796 kb
Host smart-3bc3475a-1482-4e3f-a5a3-4364552fb0ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=391406622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.391406622
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1023204646
Short name T3681
Test name
Test status
Simulation time 62489873 ps
CPU time 0.75 seconds
Started Aug 18 05:10:31 PM PDT 24
Finished Aug 18 05:10:31 PM PDT 24
Peak memory 206904 kb
Host smart-fcc55f9e-8450-4ff4-9514-49bf2d4f1afe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1023204646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1023204646
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2612912129
Short name T3658
Test name
Test status
Simulation time 90575091 ps
CPU time 1.11 seconds
Started Aug 18 05:10:42 PM PDT 24
Finished Aug 18 05:10:43 PM PDT 24
Peak memory 207264 kb
Host smart-79c7e25f-0487-43cf-b34e-afd85e6f9d10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2612912129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2612912129
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3948224789
Short name T3692
Test name
Test status
Simulation time 277755565 ps
CPU time 3.37 seconds
Started Aug 18 05:10:35 PM PDT 24
Finished Aug 18 05:10:39 PM PDT 24
Peak memory 220720 kb
Host smart-2e610d02-4256-484b-af9c-37b1f137ba80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3948224789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3948224789
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3227704243
Short name T333
Test name
Test status
Simulation time 390566474 ps
CPU time 2.9 seconds
Started Aug 18 05:10:32 PM PDT 24
Finished Aug 18 05:10:35 PM PDT 24
Peak memory 207168 kb
Host smart-c8ed9ab0-faab-4e09-98b0-3a03e5ee1f8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3227704243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3227704243
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2166045359
Short name T3666
Test name
Test status
Simulation time 78223462 ps
CPU time 1.34 seconds
Started Aug 18 05:10:42 PM PDT 24
Finished Aug 18 05:10:44 PM PDT 24
Peak memory 215552 kb
Host smart-6cc4b62d-e9c2-4cf9-812e-78f082fdc754
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166045359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2166045359
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1831239536
Short name T310
Test name
Test status
Simulation time 86100614 ps
CPU time 1.05 seconds
Started Aug 18 05:10:46 PM PDT 24
Finished Aug 18 05:10:47 PM PDT 24
Peak memory 206996 kb
Host smart-d25853e2-1464-4cfd-838f-2f80445932b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1831239536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1831239536
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2741001339
Short name T3711
Test name
Test status
Simulation time 37458029 ps
CPU time 0.74 seconds
Started Aug 18 05:10:43 PM PDT 24
Finished Aug 18 05:10:44 PM PDT 24
Peak memory 206928 kb
Host smart-f65e7c80-bb90-46e0-801f-9f3981882776
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2741001339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2741001339
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1089116273
Short name T319
Test name
Test status
Simulation time 113654650 ps
CPU time 1.56 seconds
Started Aug 18 05:10:43 PM PDT 24
Finished Aug 18 05:10:44 PM PDT 24
Peak memory 207084 kb
Host smart-97579584-2a91-4c3c-bf38-dbd2ae7e411d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1089116273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1089116273
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3844720274
Short name T268
Test name
Test status
Simulation time 91483650 ps
CPU time 2.02 seconds
Started Aug 18 05:10:45 PM PDT 24
Finished Aug 18 05:10:47 PM PDT 24
Peak memory 207240 kb
Host smart-c4edbb86-3954-4d84-91e7-8f8ab2200ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3844720274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3844720274
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.4016791224
Short name T3730
Test name
Test status
Simulation time 780384649 ps
CPU time 4.86 seconds
Started Aug 18 05:10:42 PM PDT 24
Finished Aug 18 05:10:47 PM PDT 24
Peak memory 207260 kb
Host smart-3ff3d19c-d83b-4b42-b92d-55b6d5a8907f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4016791224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.4016791224
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2228537365
Short name T288
Test name
Test status
Simulation time 138652494 ps
CPU time 1.92 seconds
Started Aug 18 05:10:45 PM PDT 24
Finished Aug 18 05:10:47 PM PDT 24
Peak memory 215548 kb
Host smart-11b26bf4-ee32-4de1-8ffb-a2eb4cd2e931
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228537365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2228537365
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2509458570
Short name T320
Test name
Test status
Simulation time 64254796 ps
CPU time 0.87 seconds
Started Aug 18 05:10:45 PM PDT 24
Finished Aug 18 05:10:46 PM PDT 24
Peak memory 206868 kb
Host smart-3a81706a-6a59-4b3b-8f4f-fb4b71a8a3a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2509458570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2509458570
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4071665010
Short name T3720
Test name
Test status
Simulation time 119287707 ps
CPU time 1.12 seconds
Started Aug 18 05:10:43 PM PDT 24
Finished Aug 18 05:10:44 PM PDT 24
Peak memory 207204 kb
Host smart-7c424032-0dd8-4230-aa7c-679700f8bac9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4071665010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.4071665010
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.557796570
Short name T3709
Test name
Test status
Simulation time 81449182 ps
CPU time 1.95 seconds
Started Aug 18 05:10:42 PM PDT 24
Finished Aug 18 05:10:45 PM PDT 24
Peak memory 207240 kb
Host smart-41e8aca5-c1af-4a07-941f-60b52cd28f26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=557796570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.557796570
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3555628303
Short name T3725
Test name
Test status
Simulation time 612699846 ps
CPU time 4.6 seconds
Started Aug 18 05:10:44 PM PDT 24
Finished Aug 18 05:10:48 PM PDT 24
Peak memory 207224 kb
Host smart-b5ca66b7-9567-44c4-ad3d-c9ca5f0ddc21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3555628303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3555628303
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3795298843
Short name T279
Test name
Test status
Simulation time 91905442 ps
CPU time 2.13 seconds
Started Aug 18 05:10:44 PM PDT 24
Finished Aug 18 05:10:46 PM PDT 24
Peak memory 215596 kb
Host smart-3cb193c4-98b9-4c08-846a-315bde59bd57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795298843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3795298843
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2718760060
Short name T3672
Test name
Test status
Simulation time 59448414 ps
CPU time 0.89 seconds
Started Aug 18 05:10:44 PM PDT 24
Finished Aug 18 05:10:45 PM PDT 24
Peak memory 206700 kb
Host smart-31297ab4-5407-4580-aa76-53821e95c2d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2718760060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2718760060
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3960178142
Short name T3645
Test name
Test status
Simulation time 38118616 ps
CPU time 0.71 seconds
Started Aug 18 05:10:42 PM PDT 24
Finished Aug 18 05:10:43 PM PDT 24
Peak memory 206852 kb
Host smart-0de6bece-cae9-4d5a-b240-9fcef184f6a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3960178142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3960178142
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2548402708
Short name T329
Test name
Test status
Simulation time 149507639 ps
CPU time 1.15 seconds
Started Aug 18 05:10:47 PM PDT 24
Finished Aug 18 05:10:48 PM PDT 24
Peak memory 207008 kb
Host smart-23bbfaac-c951-4fe5-96eb-754d2cf0d8f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2548402708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2548402708
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1343679217
Short name T3700
Test name
Test status
Simulation time 134538904 ps
CPU time 1.79 seconds
Started Aug 18 05:10:43 PM PDT 24
Finished Aug 18 05:10:45 PM PDT 24
Peak memory 215352 kb
Host smart-da5cfa0a-948c-45d2-a1fc-308f00fdbe8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1343679217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1343679217
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.365296255
Short name T3722
Test name
Test status
Simulation time 1025791309 ps
CPU time 3.69 seconds
Started Aug 18 05:10:43 PM PDT 24
Finished Aug 18 05:10:47 PM PDT 24
Peak memory 207220 kb
Host smart-cfb7b1f6-a242-433f-8184-6a3b0113a186
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=365296255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.365296255
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1013089604
Short name T3668
Test name
Test status
Simulation time 121069718 ps
CPU time 1.27 seconds
Started Aug 18 05:10:43 PM PDT 24
Finished Aug 18 05:10:44 PM PDT 24
Peak memory 215512 kb
Host smart-95311b83-fe1a-4dd0-b75e-04d9c6f98991
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013089604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1013089604
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4047409272
Short name T317
Test name
Test status
Simulation time 62446392 ps
CPU time 1.06 seconds
Started Aug 18 05:10:45 PM PDT 24
Finished Aug 18 05:10:46 PM PDT 24
Peak memory 206908 kb
Host smart-dc4cc70c-128c-4f4c-a746-240fa7c8dc6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4047409272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.4047409272
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.202336052
Short name T3665
Test name
Test status
Simulation time 37816579 ps
CPU time 0.74 seconds
Started Aug 18 05:10:44 PM PDT 24
Finished Aug 18 05:10:45 PM PDT 24
Peak memory 206924 kb
Host smart-e184a3d4-2ced-4d5e-a571-bd9bc9676849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=202336052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.202336052
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2010255140
Short name T321
Test name
Test status
Simulation time 53429982 ps
CPU time 1.04 seconds
Started Aug 18 05:10:43 PM PDT 24
Finished Aug 18 05:10:45 PM PDT 24
Peak memory 207264 kb
Host smart-1915ce94-814b-4ce8-90bb-71c37c2fbac1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2010255140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2010255140
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1170672278
Short name T291
Test name
Test status
Simulation time 354673733 ps
CPU time 3.39 seconds
Started Aug 18 05:10:43 PM PDT 24
Finished Aug 18 05:10:46 PM PDT 24
Peak memory 222968 kb
Host smart-3c4d54dd-ea19-4b6b-a11e-c1524e09e650
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1170672278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1170672278
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1482194577
Short name T512
Test name
Test status
Simulation time 420289509 ps
CPU time 2.8 seconds
Started Aug 18 05:10:46 PM PDT 24
Finished Aug 18 05:10:49 PM PDT 24
Peak memory 207280 kb
Host smart-5a21572a-bc5b-445f-8711-4894683aaabf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1482194577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1482194577
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3822204121
Short name T3726
Test name
Test status
Simulation time 91828369 ps
CPU time 1.36 seconds
Started Aug 18 05:10:42 PM PDT 24
Finished Aug 18 05:10:44 PM PDT 24
Peak memory 215432 kb
Host smart-6233727e-b4ce-490f-ac86-1b3cc8f155b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822204121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3822204121
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3394703685
Short name T3641
Test name
Test status
Simulation time 33797758 ps
CPU time 0.86 seconds
Started Aug 18 05:10:46 PM PDT 24
Finished Aug 18 05:10:47 PM PDT 24
Peak memory 206944 kb
Host smart-37e7ef98-35f7-46d6-a987-8b5b79c45444
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3394703685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3394703685
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2719705561
Short name T3647
Test name
Test status
Simulation time 62042313 ps
CPU time 0.75 seconds
Started Aug 18 05:10:45 PM PDT 24
Finished Aug 18 05:10:46 PM PDT 24
Peak memory 206804 kb
Host smart-295cca5d-9c9f-4f13-a816-7e0cb670a9f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2719705561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2719705561
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2659282631
Short name T3638
Test name
Test status
Simulation time 73742542 ps
CPU time 1.39 seconds
Started Aug 18 05:10:45 PM PDT 24
Finished Aug 18 05:10:47 PM PDT 24
Peak memory 207156 kb
Host smart-60820711-2e13-4d41-bf34-8a66eb05ccf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2659282631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2659282631
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.404873850
Short name T3657
Test name
Test status
Simulation time 140657768 ps
CPU time 1.76 seconds
Started Aug 18 05:10:43 PM PDT 24
Finished Aug 18 05:10:45 PM PDT 24
Peak memory 207192 kb
Host smart-1af39a18-a6b8-4502-96af-baea0b31f92a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=404873850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.404873850
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.467921792
Short name T3710
Test name
Test status
Simulation time 399975224 ps
CPU time 2.94 seconds
Started Aug 18 05:10:45 PM PDT 24
Finished Aug 18 05:10:48 PM PDT 24
Peak memory 207164 kb
Host smart-df018235-46ed-4a02-8993-815d0d10a7aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=467921792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.467921792
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.950759174
Short name T3644
Test name
Test status
Simulation time 249852750 ps
CPU time 2.17 seconds
Started Aug 18 05:10:16 PM PDT 24
Finished Aug 18 05:10:18 PM PDT 24
Peak memory 207112 kb
Host smart-51f348c6-a175-49dd-b955-731747519db5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=950759174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.950759174
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1279501812
Short name T3663
Test name
Test status
Simulation time 1039244691 ps
CPU time 8.18 seconds
Started Aug 18 05:10:18 PM PDT 24
Finished Aug 18 05:10:26 PM PDT 24
Peak memory 207248 kb
Host smart-a482fd29-ed1b-4e9f-b2be-f881ff42252d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1279501812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1279501812
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3696895474
Short name T335
Test name
Test status
Simulation time 68894366 ps
CPU time 0.86 seconds
Started Aug 18 05:10:16 PM PDT 24
Finished Aug 18 05:10:17 PM PDT 24
Peak memory 206900 kb
Host smart-57fbc733-18ad-48ad-979e-6817fab4c6e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3696895474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3696895474
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.823586975
Short name T3733
Test name
Test status
Simulation time 85501783 ps
CPU time 0.76 seconds
Started Aug 18 05:10:20 PM PDT 24
Finished Aug 18 05:10:21 PM PDT 24
Peak memory 206924 kb
Host smart-01f4ae9f-854a-4114-a2c3-71d88af02fe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=823586975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.823586975
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2521617272
Short name T3731
Test name
Test status
Simulation time 710113339 ps
CPU time 4.72 seconds
Started Aug 18 05:10:15 PM PDT 24
Finished Aug 18 05:10:20 PM PDT 24
Peak memory 207028 kb
Host smart-a3d50d71-1ed5-42a2-a99e-e4318f57cd20
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2521617272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2521617272
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3077406786
Short name T330
Test name
Test status
Simulation time 268673798 ps
CPU time 1.9 seconds
Started Aug 18 05:10:16 PM PDT 24
Finished Aug 18 05:10:18 PM PDT 24
Peak memory 207208 kb
Host smart-b6c70572-72af-4b52-a7a8-758daa953995
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3077406786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3077406786
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.846582217
Short name T289
Test name
Test status
Simulation time 146389800 ps
CPU time 2.07 seconds
Started Aug 18 05:10:18 PM PDT 24
Finished Aug 18 05:10:20 PM PDT 24
Peak memory 207172 kb
Host smart-97a9f078-9683-4e8a-a8b4-27701b84aa83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=846582217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.846582217
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2699307442
Short name T514
Test name
Test status
Simulation time 607892068 ps
CPU time 4.3 seconds
Started Aug 18 05:10:18 PM PDT 24
Finished Aug 18 05:10:22 PM PDT 24
Peak memory 207296 kb
Host smart-8eeb1f6a-7cbb-48f4-b0d8-ae833ebb2ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2699307442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2699307442
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1446340038
Short name T3723
Test name
Test status
Simulation time 43407430 ps
CPU time 0.7 seconds
Started Aug 18 05:10:42 PM PDT 24
Finished Aug 18 05:10:43 PM PDT 24
Peak memory 206900 kb
Host smart-02190f43-1d88-4bea-ad8e-d16b02b3a7b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1446340038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1446340038
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1128979330
Short name T3659
Test name
Test status
Simulation time 37811469 ps
CPU time 0.74 seconds
Started Aug 18 05:10:43 PM PDT 24
Finished Aug 18 05:10:44 PM PDT 24
Peak memory 206792 kb
Host smart-bfc71667-bbb0-48d1-984a-3d82b8df4f39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1128979330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1128979330
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.4236422236
Short name T3648
Test name
Test status
Simulation time 43715062 ps
CPU time 0.71 seconds
Started Aug 18 05:10:45 PM PDT 24
Finished Aug 18 05:10:46 PM PDT 24
Peak memory 206824 kb
Host smart-2655ec96-d39e-423b-a339-00bed8dd5c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4236422236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.4236422236
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3047777621
Short name T3669
Test name
Test status
Simulation time 38731661 ps
CPU time 0.71 seconds
Started Aug 18 05:10:42 PM PDT 24
Finished Aug 18 05:10:43 PM PDT 24
Peak memory 206940 kb
Host smart-da4b657f-6e53-4e22-9465-9613bd3600e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3047777621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3047777621
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2007845260
Short name T3679
Test name
Test status
Simulation time 80392044 ps
CPU time 0.81 seconds
Started Aug 18 05:10:44 PM PDT 24
Finished Aug 18 05:10:45 PM PDT 24
Peak memory 206796 kb
Host smart-ef1b7146-55ca-4fd6-80d8-ae3f18000d9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2007845260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2007845260
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4043793976
Short name T3652
Test name
Test status
Simulation time 52541531 ps
CPU time 0.78 seconds
Started Aug 18 05:10:47 PM PDT 24
Finished Aug 18 05:10:48 PM PDT 24
Peak memory 206912 kb
Host smart-703f2d85-affe-41b9-8c82-8d4341a56462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4043793976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4043793976
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2622538417
Short name T3673
Test name
Test status
Simulation time 37221561 ps
CPU time 0.72 seconds
Started Aug 18 05:10:58 PM PDT 24
Finished Aug 18 05:10:58 PM PDT 24
Peak memory 206908 kb
Host smart-7c289b0e-8db7-4c26-9005-f26b47f38290
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2622538417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2622538417
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2057219711
Short name T3675
Test name
Test status
Simulation time 71038342 ps
CPU time 0.79 seconds
Started Aug 18 05:10:54 PM PDT 24
Finished Aug 18 05:10:55 PM PDT 24
Peak memory 206820 kb
Host smart-aa0a63c9-8b4a-4ea2-adbe-275540bedb11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2057219711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2057219711
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1248959082
Short name T308
Test name
Test status
Simulation time 151985614 ps
CPU time 3.33 seconds
Started Aug 18 05:10:16 PM PDT 24
Finished Aug 18 05:10:20 PM PDT 24
Peak memory 207052 kb
Host smart-389dc4cb-f936-4772-b88a-bf5f5688511f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1248959082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1248959082
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2485090775
Short name T3646
Test name
Test status
Simulation time 943621048 ps
CPU time 4.51 seconds
Started Aug 18 05:10:18 PM PDT 24
Finished Aug 18 05:10:23 PM PDT 24
Peak memory 207120 kb
Host smart-826f9052-9b10-4274-a14a-bbc2a9f4ef4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2485090775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2485090775
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2955614770
Short name T3683
Test name
Test status
Simulation time 57334244 ps
CPU time 0.85 seconds
Started Aug 18 05:10:17 PM PDT 24
Finished Aug 18 05:10:17 PM PDT 24
Peak memory 207016 kb
Host smart-f9a9ad32-8764-4d80-b639-603812f944c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2955614770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2955614770
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3483646729
Short name T3699
Test name
Test status
Simulation time 80865945 ps
CPU time 2.19 seconds
Started Aug 18 05:10:15 PM PDT 24
Finished Aug 18 05:10:17 PM PDT 24
Peak memory 215552 kb
Host smart-06ca5c0e-f542-45ec-874c-78bad3efdd6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483646729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3483646729
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1883094031
Short name T3697
Test name
Test status
Simulation time 60332595 ps
CPU time 0.86 seconds
Started Aug 18 05:10:17 PM PDT 24
Finished Aug 18 05:10:18 PM PDT 24
Peak memory 206912 kb
Host smart-fc686032-5621-4bb8-8c04-000ae8c18c3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1883094031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1883094031
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.969247286
Short name T3643
Test name
Test status
Simulation time 41595306 ps
CPU time 0.7 seconds
Started Aug 18 05:10:14 PM PDT 24
Finished Aug 18 05:10:15 PM PDT 24
Peak memory 206904 kb
Host smart-f8766627-4f7b-47c7-b205-f6ecf28461c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=969247286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.969247286
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2260234764
Short name T300
Test name
Test status
Simulation time 93320163 ps
CPU time 2.24 seconds
Started Aug 18 05:10:18 PM PDT 24
Finished Aug 18 05:10:20 PM PDT 24
Peak memory 215332 kb
Host smart-15bc3eff-d25c-4b56-b69d-2326f4d0e307
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2260234764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2260234764
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3589638242
Short name T3708
Test name
Test status
Simulation time 258211502 ps
CPU time 2.56 seconds
Started Aug 18 05:10:14 PM PDT 24
Finished Aug 18 05:10:17 PM PDT 24
Peak memory 207100 kb
Host smart-73b0d7e5-0804-43c4-a089-e897cd6e9b62
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3589638242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3589638242
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3881890673
Short name T3689
Test name
Test status
Simulation time 94422443 ps
CPU time 1.44 seconds
Started Aug 18 05:10:14 PM PDT 24
Finished Aug 18 05:10:15 PM PDT 24
Peak memory 207168 kb
Host smart-feba4f21-fe79-4732-ba9c-961f43287c1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3881890673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3881890673
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4050817563
Short name T280
Test name
Test status
Simulation time 118630873 ps
CPU time 2.64 seconds
Started Aug 18 05:10:15 PM PDT 24
Finished Aug 18 05:10:18 PM PDT 24
Peak memory 223072 kb
Host smart-b7610cbb-82eb-4686-99b6-d5fd237722ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4050817563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.4050817563
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.676077973
Short name T515
Test name
Test status
Simulation time 1134417157 ps
CPU time 3.62 seconds
Started Aug 18 05:10:15 PM PDT 24
Finished Aug 18 05:10:18 PM PDT 24
Peak memory 207104 kb
Host smart-028a96c8-e98c-40e4-8d75-c95e4c0285de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=676077973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.676077973
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3297007057
Short name T337
Test name
Test status
Simulation time 42997724 ps
CPU time 0.7 seconds
Started Aug 18 05:10:53 PM PDT 24
Finished Aug 18 05:10:54 PM PDT 24
Peak memory 206924 kb
Host smart-ce1f3568-0cc3-43c6-8750-5491daf708e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3297007057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3297007057
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3305625937
Short name T3670
Test name
Test status
Simulation time 55288668 ps
CPU time 0.79 seconds
Started Aug 18 05:10:55 PM PDT 24
Finished Aug 18 05:10:56 PM PDT 24
Peak memory 206780 kb
Host smart-b4592ef8-c323-4e66-ba48-97d0d7cf7c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3305625937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3305625937
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3799474150
Short name T3719
Test name
Test status
Simulation time 31275274 ps
CPU time 0.69 seconds
Started Aug 18 05:10:54 PM PDT 24
Finished Aug 18 05:10:55 PM PDT 24
Peak memory 206816 kb
Host smart-b80371a1-14ac-4747-9299-23c69e737952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3799474150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3799474150
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1106276521
Short name T3680
Test name
Test status
Simulation time 90080522 ps
CPU time 0.81 seconds
Started Aug 18 05:10:55 PM PDT 24
Finished Aug 18 05:10:56 PM PDT 24
Peak memory 206824 kb
Host smart-04682f07-73bc-4349-afd3-4de21aa9afaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1106276521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1106276521
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.216784291
Short name T3686
Test name
Test status
Simulation time 57973750 ps
CPU time 0.75 seconds
Started Aug 18 05:10:54 PM PDT 24
Finished Aug 18 05:10:55 PM PDT 24
Peak memory 206924 kb
Host smart-b96087bb-be9e-4db8-8f15-4b6bd5c71b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=216784291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.216784291
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1134397881
Short name T3642
Test name
Test status
Simulation time 53227365 ps
CPU time 0.73 seconds
Started Aug 18 05:10:52 PM PDT 24
Finished Aug 18 05:10:53 PM PDT 24
Peak memory 206892 kb
Host smart-0327c3c3-4d9d-4e9f-a2e8-8f4005f94016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1134397881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1134397881
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2519893184
Short name T3728
Test name
Test status
Simulation time 42799844 ps
CPU time 0.73 seconds
Started Aug 18 05:11:01 PM PDT 24
Finished Aug 18 05:11:02 PM PDT 24
Peak memory 206864 kb
Host smart-14ba0aee-2dc6-456a-9715-64a0e61f8d99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2519893184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2519893184
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3761717767
Short name T3727
Test name
Test status
Simulation time 42294969 ps
CPU time 0.73 seconds
Started Aug 18 05:11:01 PM PDT 24
Finished Aug 18 05:11:02 PM PDT 24
Peak memory 206864 kb
Host smart-c228a903-dd69-4f61-a8c5-e920f17607f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3761717767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3761717767
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2435331936
Short name T3654
Test name
Test status
Simulation time 62357584 ps
CPU time 0.75 seconds
Started Aug 18 05:10:52 PM PDT 24
Finished Aug 18 05:10:53 PM PDT 24
Peak memory 206936 kb
Host smart-9fafec2c-4dd8-42d9-bd21-d85fcbf2670d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2435331936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2435331936
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.4008336276
Short name T3696
Test name
Test status
Simulation time 48972144 ps
CPU time 0.74 seconds
Started Aug 18 05:10:53 PM PDT 24
Finished Aug 18 05:10:54 PM PDT 24
Peak memory 206904 kb
Host smart-e0496413-4ec4-4cf0-91e9-9ce3d107ddf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4008336276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.4008336276
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2271947169
Short name T306
Test name
Test status
Simulation time 95065870 ps
CPU time 1.89 seconds
Started Aug 18 05:10:25 PM PDT 24
Finished Aug 18 05:10:27 PM PDT 24
Peak memory 207028 kb
Host smart-49f98934-9f80-4d4e-91c0-3690071a4d71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2271947169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2271947169
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3058679691
Short name T316
Test name
Test status
Simulation time 775146924 ps
CPU time 4.68 seconds
Started Aug 18 05:10:18 PM PDT 24
Finished Aug 18 05:10:23 PM PDT 24
Peak memory 207152 kb
Host smart-7c62630a-60ec-4d05-a9be-9ca2551adcb8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3058679691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3058679691
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.244324810
Short name T314
Test name
Test status
Simulation time 95370424 ps
CPU time 0.91 seconds
Started Aug 18 05:10:19 PM PDT 24
Finished Aug 18 05:10:20 PM PDT 24
Peak memory 206920 kb
Host smart-7390957a-1fe6-48a6-8ff7-e3a7c9a1cc93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=244324810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.244324810
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.248146636
Short name T315
Test name
Test status
Simulation time 109064828 ps
CPU time 1.09 seconds
Started Aug 18 05:10:17 PM PDT 24
Finished Aug 18 05:10:18 PM PDT 24
Peak memory 206904 kb
Host smart-7a4fea1f-f176-4a09-9d2e-ba05a36acf32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=248146636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.248146636
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2087202648
Short name T3704
Test name
Test status
Simulation time 87859035 ps
CPU time 0.79 seconds
Started Aug 18 05:10:18 PM PDT 24
Finished Aug 18 05:10:19 PM PDT 24
Peak memory 206936 kb
Host smart-593ca40d-4c1c-4e38-9450-20deac7cb5d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2087202648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2087202648
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.334611456
Short name T312
Test name
Test status
Simulation time 97993743 ps
CPU time 2.23 seconds
Started Aug 18 05:10:15 PM PDT 24
Finished Aug 18 05:10:18 PM PDT 24
Peak memory 215292 kb
Host smart-d8a8b013-4fd5-49bb-973b-cbc98b42b315
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=334611456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.334611456
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1364407326
Short name T3639
Test name
Test status
Simulation time 163256019 ps
CPU time 4.17 seconds
Started Aug 18 05:10:18 PM PDT 24
Finished Aug 18 05:10:22 PM PDT 24
Peak memory 206896 kb
Host smart-b5c0fddd-3b02-41c2-9694-562cef5ba14b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1364407326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1364407326
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1663610683
Short name T3650
Test name
Test status
Simulation time 81162607 ps
CPU time 1.03 seconds
Started Aug 18 05:10:22 PM PDT 24
Finished Aug 18 05:10:24 PM PDT 24
Peak memory 207244 kb
Host smart-1ad8e9ac-cda3-4216-b3e2-f7ce669117d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1663610683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1663610683
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1061307818
Short name T3687
Test name
Test status
Simulation time 290733440 ps
CPU time 3.68 seconds
Started Aug 18 05:10:19 PM PDT 24
Finished Aug 18 05:10:23 PM PDT 24
Peak memory 220184 kb
Host smart-3541af96-e11d-461d-bdee-74ae5f4c76b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1061307818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1061307818
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1977019338
Short name T511
Test name
Test status
Simulation time 304823925 ps
CPU time 2.63 seconds
Started Aug 18 05:10:16 PM PDT 24
Finished Aug 18 05:10:18 PM PDT 24
Peak memory 207240 kb
Host smart-90de9d91-976c-4105-bf44-3be3bd14e193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1977019338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1977019338
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2753635462
Short name T3705
Test name
Test status
Simulation time 41248575 ps
CPU time 0.71 seconds
Started Aug 18 05:10:52 PM PDT 24
Finished Aug 18 05:10:53 PM PDT 24
Peak memory 206796 kb
Host smart-a9299651-e93d-4cf5-b719-69d8981ded04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2753635462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2753635462
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1541903985
Short name T3694
Test name
Test status
Simulation time 92783604 ps
CPU time 0.82 seconds
Started Aug 18 05:10:52 PM PDT 24
Finished Aug 18 05:10:53 PM PDT 24
Peak memory 206848 kb
Host smart-99ca815a-a296-456d-a3e4-2b686b879287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1541903985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1541903985
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2855750548
Short name T3660
Test name
Test status
Simulation time 59447239 ps
CPU time 0.81 seconds
Started Aug 18 05:10:58 PM PDT 24
Finished Aug 18 05:10:59 PM PDT 24
Peak memory 206872 kb
Host smart-7c137e2d-4585-4183-842f-30d1f8449943
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2855750548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2855750548
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.4084574099
Short name T248
Test name
Test status
Simulation time 50816031 ps
CPU time 0.81 seconds
Started Aug 18 05:10:58 PM PDT 24
Finished Aug 18 05:10:59 PM PDT 24
Peak memory 206872 kb
Host smart-2d95c6e8-f068-4728-94b3-f9c4797e3638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4084574099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.4084574099
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1428452172
Short name T3721
Test name
Test status
Simulation time 58084927 ps
CPU time 0.77 seconds
Started Aug 18 05:10:54 PM PDT 24
Finished Aug 18 05:10:55 PM PDT 24
Peak memory 206708 kb
Host smart-fb6653ec-b668-494e-9281-821b3adc6f30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1428452172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1428452172
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3513752062
Short name T3678
Test name
Test status
Simulation time 99354399 ps
CPU time 0.84 seconds
Started Aug 18 05:10:53 PM PDT 24
Finished Aug 18 05:10:54 PM PDT 24
Peak memory 206940 kb
Host smart-a6bd94aa-e658-4c80-be99-4a0d8a762aa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3513752062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3513752062
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3232553602
Short name T3715
Test name
Test status
Simulation time 36304446 ps
CPU time 0.72 seconds
Started Aug 18 05:11:00 PM PDT 24
Finished Aug 18 05:11:01 PM PDT 24
Peak memory 206864 kb
Host smart-99f5fca5-813c-4156-9374-d6d4d628bab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3232553602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3232553602
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1423194118
Short name T3684
Test name
Test status
Simulation time 47099695 ps
CPU time 0.75 seconds
Started Aug 18 05:10:53 PM PDT 24
Finished Aug 18 05:10:54 PM PDT 24
Peak memory 206820 kb
Host smart-d42a6b56-080e-417b-8776-fa7268751631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1423194118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1423194118
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3306032608
Short name T3655
Test name
Test status
Simulation time 64402597 ps
CPU time 0.71 seconds
Started Aug 18 05:10:57 PM PDT 24
Finished Aug 18 05:10:58 PM PDT 24
Peak memory 206912 kb
Host smart-75824713-0c13-4ab2-8622-4afc8be0717e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3306032608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3306032608
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1703144032
Short name T3707
Test name
Test status
Simulation time 118118423 ps
CPU time 1.24 seconds
Started Aug 18 05:10:22 PM PDT 24
Finished Aug 18 05:10:23 PM PDT 24
Peak memory 223364 kb
Host smart-20cd82cc-1450-4e36-bd07-9a712ca34c30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703144032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1703144032
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1600687266
Short name T318
Test name
Test status
Simulation time 64762089 ps
CPU time 0.97 seconds
Started Aug 18 05:10:24 PM PDT 24
Finished Aug 18 05:10:25 PM PDT 24
Peak memory 207004 kb
Host smart-336330b7-b21c-48f7-9139-b7bd7e18e878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1600687266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1600687266
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2589619447
Short name T3702
Test name
Test status
Simulation time 32830655 ps
CPU time 0.72 seconds
Started Aug 18 05:10:26 PM PDT 24
Finished Aug 18 05:10:27 PM PDT 24
Peak memory 206936 kb
Host smart-ceba3c66-62ef-4a84-8570-f01e2f4590c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2589619447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2589619447
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.285367267
Short name T3729
Test name
Test status
Simulation time 188519441 ps
CPU time 1.55 seconds
Started Aug 18 05:10:24 PM PDT 24
Finished Aug 18 05:10:26 PM PDT 24
Peak memory 207220 kb
Host smart-e7201596-84f9-498e-86fc-6c2d8fb2b6ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=285367267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.285367267
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3846558348
Short name T3732
Test name
Test status
Simulation time 186919605 ps
CPU time 1.96 seconds
Started Aug 18 05:10:25 PM PDT 24
Finished Aug 18 05:10:27 PM PDT 24
Peak memory 215500 kb
Host smart-df7f10d9-dc6c-41e6-adc8-8612a88e6144
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846558348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3846558348
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2145027230
Short name T3685
Test name
Test status
Simulation time 81852254 ps
CPU time 1.01 seconds
Started Aug 18 05:10:22 PM PDT 24
Finished Aug 18 05:10:23 PM PDT 24
Peak memory 206884 kb
Host smart-395a08b0-c2d6-4c80-a2ec-0122eeb98c78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2145027230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2145027230
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.4207396191
Short name T3734
Test name
Test status
Simulation time 39949699 ps
CPU time 0.76 seconds
Started Aug 18 05:10:21 PM PDT 24
Finished Aug 18 05:10:22 PM PDT 24
Peak memory 206924 kb
Host smart-ca9f1fbd-5a60-4643-a679-d056b0f76ab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4207396191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.4207396191
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.403073848
Short name T331
Test name
Test status
Simulation time 246195928 ps
CPU time 1.55 seconds
Started Aug 18 05:10:24 PM PDT 24
Finished Aug 18 05:10:25 PM PDT 24
Peak memory 207156 kb
Host smart-b28675bd-1ffd-42aa-ac9e-a4030305c579
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=403073848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.403073848
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1988743898
Short name T3712
Test name
Test status
Simulation time 54623346 ps
CPU time 1.51 seconds
Started Aug 18 05:10:26 PM PDT 24
Finished Aug 18 05:10:28 PM PDT 24
Peak memory 207252 kb
Host smart-f56f67a7-36e2-4841-b793-b984a681e407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1988743898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1988743898
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2564896699
Short name T3653
Test name
Test status
Simulation time 540571295 ps
CPU time 2.73 seconds
Started Aug 18 05:10:22 PM PDT 24
Finished Aug 18 05:10:24 PM PDT 24
Peak memory 207256 kb
Host smart-03b74479-2241-4e38-ac4c-6045e0e8c975
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2564896699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2564896699
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3946898992
Short name T3706
Test name
Test status
Simulation time 82333453 ps
CPU time 1.22 seconds
Started Aug 18 05:10:23 PM PDT 24
Finished Aug 18 05:10:24 PM PDT 24
Peak memory 215404 kb
Host smart-4b36486f-1e7d-4566-99f1-521b8610870d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946898992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3946898992
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1315827608
Short name T334
Test name
Test status
Simulation time 106332642 ps
CPU time 0.92 seconds
Started Aug 18 05:10:23 PM PDT 24
Finished Aug 18 05:10:24 PM PDT 24
Peak memory 207020 kb
Host smart-525b90e2-9f97-4769-82b7-a0035248ba62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1315827608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1315827608
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2512605708
Short name T249
Test name
Test status
Simulation time 57663778 ps
CPU time 0.74 seconds
Started Aug 18 05:10:24 PM PDT 24
Finished Aug 18 05:10:25 PM PDT 24
Peak memory 206816 kb
Host smart-870dd8a6-121e-4c29-bfe6-bb2199648829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2512605708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2512605708
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1538389943
Short name T3691
Test name
Test status
Simulation time 187818848 ps
CPU time 1.28 seconds
Started Aug 18 05:10:22 PM PDT 24
Finished Aug 18 05:10:24 PM PDT 24
Peak memory 207100 kb
Host smart-a8f1e260-9267-4357-b0c6-8f3beb0cc827
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1538389943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1538389943
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3954402080
Short name T284
Test name
Test status
Simulation time 61874794 ps
CPU time 1.59 seconds
Started Aug 18 05:10:23 PM PDT 24
Finished Aug 18 05:10:25 PM PDT 24
Peak memory 207160 kb
Host smart-c3dd830e-6fd0-4d8e-b8b7-9b6ce4132802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3954402080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3954402080
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1288719726
Short name T513
Test name
Test status
Simulation time 1112510625 ps
CPU time 3.44 seconds
Started Aug 18 05:10:23 PM PDT 24
Finished Aug 18 05:10:26 PM PDT 24
Peak memory 207152 kb
Host smart-a91bd232-ce5f-4e17-97f1-26220946f1c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1288719726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1288719726
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3817742735
Short name T3690
Test name
Test status
Simulation time 156779155 ps
CPU time 1.7 seconds
Started Aug 18 05:10:32 PM PDT 24
Finished Aug 18 05:10:34 PM PDT 24
Peak memory 218316 kb
Host smart-04477dce-2d95-4d60-a71a-94fb2e3bae3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817742735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3817742735
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.972930385
Short name T304
Test name
Test status
Simulation time 94192230 ps
CPU time 1.03 seconds
Started Aug 18 05:10:23 PM PDT 24
Finished Aug 18 05:10:24 PM PDT 24
Peak memory 207016 kb
Host smart-0c9c94fb-122f-4151-b3ef-09a2fc6751fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=972930385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.972930385
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4215010790
Short name T3676
Test name
Test status
Simulation time 49132810 ps
CPU time 0.74 seconds
Started Aug 18 05:10:25 PM PDT 24
Finished Aug 18 05:10:26 PM PDT 24
Peak memory 206936 kb
Host smart-e9fc698f-739d-4d51-9f0f-a05ba6df8a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4215010790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.4215010790
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4037430238
Short name T332
Test name
Test status
Simulation time 224760678 ps
CPU time 1.76 seconds
Started Aug 18 05:10:21 PM PDT 24
Finished Aug 18 05:10:23 PM PDT 24
Peak memory 207168 kb
Host smart-334394c1-e206-4665-8e8a-9baa5ee97f7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4037430238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.4037430238
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4067858319
Short name T285
Test name
Test status
Simulation time 144508637 ps
CPU time 1.45 seconds
Started Aug 18 05:10:22 PM PDT 24
Finished Aug 18 05:10:24 PM PDT 24
Peak memory 207320 kb
Host smart-56021a7d-2e54-46c4-8da5-cb72aa67c811
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4067858319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.4067858319
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.519222940
Short name T3737
Test name
Test status
Simulation time 874929129 ps
CPU time 5.37 seconds
Started Aug 18 05:10:24 PM PDT 24
Finished Aug 18 05:10:30 PM PDT 24
Peak memory 207172 kb
Host smart-9f750f87-eee1-47f7-a54e-b4d1f9b80f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=519222940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.519222940
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.899508788
Short name T3738
Test name
Test status
Simulation time 246876459 ps
CPU time 1.88 seconds
Started Aug 18 05:10:31 PM PDT 24
Finished Aug 18 05:10:33 PM PDT 24
Peak memory 215452 kb
Host smart-3dfc7d6e-7b44-4e1c-b764-f6baf7935058
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899508788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.899508788
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3533181005
Short name T328
Test name
Test status
Simulation time 87257172 ps
CPU time 1.02 seconds
Started Aug 18 05:10:34 PM PDT 24
Finished Aug 18 05:10:35 PM PDT 24
Peak memory 206932 kb
Host smart-1690bd22-3d33-4637-beee-2fe212b04586
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3533181005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3533181005
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1821119164
Short name T336
Test name
Test status
Simulation time 35509621 ps
CPU time 0.7 seconds
Started Aug 18 05:10:34 PM PDT 24
Finished Aug 18 05:10:35 PM PDT 24
Peak memory 206720 kb
Host smart-0fd284f9-9dbd-4eee-b20d-fac69c9639ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1821119164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1821119164
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.230853051
Short name T271
Test name
Test status
Simulation time 89826643 ps
CPU time 1.15 seconds
Started Aug 18 05:10:33 PM PDT 24
Finished Aug 18 05:10:34 PM PDT 24
Peak memory 207304 kb
Host smart-eec0b1e8-a256-40ef-a091-e29dc25b9f3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=230853051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.230853051
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3777293882
Short name T3698
Test name
Test status
Simulation time 67170644 ps
CPU time 1.6 seconds
Started Aug 18 05:10:35 PM PDT 24
Finished Aug 18 05:10:37 PM PDT 24
Peak memory 207168 kb
Host smart-8ca0a410-47d0-4e83-b305-59417201e291
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3777293882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3777293882
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1035191716
Short name T510
Test name
Test status
Simulation time 1011944450 ps
CPU time 3.24 seconds
Started Aug 18 05:10:32 PM PDT 24
Finished Aug 18 05:10:35 PM PDT 24
Peak memory 207264 kb
Host smart-e2af3d03-d824-4131-a5b3-ef1d061bdd9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1035191716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1035191716
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.3086523694
Short name T1416
Test name
Test status
Simulation time 43152027 ps
CPU time 0.71 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:31:58 PM PDT 24
Peak memory 207448 kb
Host smart-80969ac1-8484-4af4-83b7-cbb5d58a6ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3086523694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.3086523694
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2341036263
Short name T3275
Test name
Test status
Simulation time 12197683285 ps
CPU time 16.27 seconds
Started Aug 18 05:31:48 PM PDT 24
Finished Aug 18 05:32:04 PM PDT 24
Peak memory 207832 kb
Host smart-eb352a8a-4c2c-475d-b527-26ddfdc9ba5d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341036263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.2341036263
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.3476605512
Short name T1862
Test name
Test status
Simulation time 14617377390 ps
CPU time 20.77 seconds
Started Aug 18 05:31:39 PM PDT 24
Finished Aug 18 05:31:59 PM PDT 24
Peak memory 216012 kb
Host smart-800d0b89-f426-444d-bae3-94badb62c3fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476605512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.3476605512
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3802706673
Short name T2576
Test name
Test status
Simulation time 26222239958 ps
CPU time 32.23 seconds
Started Aug 18 05:31:37 PM PDT 24
Finished Aug 18 05:32:10 PM PDT 24
Peak memory 215996 kb
Host smart-e4ba2415-016e-4fa8-b90c-da52434779f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802706673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.3802706673
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2235622558
Short name T1531
Test name
Test status
Simulation time 157478877 ps
CPU time 0.86 seconds
Started Aug 18 05:31:38 PM PDT 24
Finished Aug 18 05:31:39 PM PDT 24
Peak memory 207464 kb
Host smart-fb9e0287-2fb3-4ea4-b5fc-e74ac1d53aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22356
22558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2235622558
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.3145913515
Short name T1267
Test name
Test status
Simulation time 140652433 ps
CPU time 0.86 seconds
Started Aug 18 05:31:42 PM PDT 24
Finished Aug 18 05:31:43 PM PDT 24
Peak memory 207576 kb
Host smart-ec144fb9-5ea3-4578-8d0b-c8152c2eba1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31459
13515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.3145913515
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.3785970663
Short name T2271
Test name
Test status
Simulation time 493675178 ps
CPU time 1.67 seconds
Started Aug 18 05:31:44 PM PDT 24
Finished Aug 18 05:31:45 PM PDT 24
Peak memory 207444 kb
Host smart-07d8974f-68c7-4acc-a74f-1164ecbb2d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37859
70663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.3785970663
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.1671491492
Short name T1599
Test name
Test status
Simulation time 743865293 ps
CPU time 2.1 seconds
Started Aug 18 05:31:48 PM PDT 24
Finished Aug 18 05:31:51 PM PDT 24
Peak memory 207568 kb
Host smart-a2661788-c216-407b-ba07-e959aa8cb416
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1671491492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.1671491492
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.3915242284
Short name T3048
Test name
Test status
Simulation time 275763023 ps
CPU time 4.35 seconds
Started Aug 18 05:31:41 PM PDT 24
Finished Aug 18 05:31:46 PM PDT 24
Peak memory 207696 kb
Host smart-6aa0cfa1-9bba-460e-88c2-3356088a6eeb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915242284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.3915242284
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.4237610450
Short name T1924
Test name
Test status
Simulation time 659376685 ps
CPU time 1.93 seconds
Started Aug 18 05:31:35 PM PDT 24
Finished Aug 18 05:31:37 PM PDT 24
Peak memory 207504 kb
Host smart-cda944a3-6a80-4a23-beae-1226a228a275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42376
10450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.4237610450
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.3801280710
Short name T2939
Test name
Test status
Simulation time 146591697 ps
CPU time 0.83 seconds
Started Aug 18 05:31:43 PM PDT 24
Finished Aug 18 05:31:44 PM PDT 24
Peak memory 207464 kb
Host smart-6e50e139-a2a0-44ca-846a-0d1641b13b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38012
80710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.3801280710
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.2848104191
Short name T2811
Test name
Test status
Simulation time 99940744 ps
CPU time 0.83 seconds
Started Aug 18 05:31:51 PM PDT 24
Finished Aug 18 05:31:52 PM PDT 24
Peak memory 207424 kb
Host smart-4592f7f2-bd4f-4819-b929-adb4b5ef9a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28481
04191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2848104191
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.2756718225
Short name T36
Test name
Test status
Simulation time 897748493 ps
CPU time 2.28 seconds
Started Aug 18 05:31:37 PM PDT 24
Finished Aug 18 05:31:40 PM PDT 24
Peak memory 207748 kb
Host smart-119be6c3-9d8b-4424-b08f-c62502bab781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27567
18225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2756718225
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_types.3380832251
Short name T423
Test name
Test status
Simulation time 490698175 ps
CPU time 1.3 seconds
Started Aug 18 05:31:37 PM PDT 24
Finished Aug 18 05:31:38 PM PDT 24
Peak memory 207448 kb
Host smart-01938a91-f247-4ccb-93cb-18e484d277fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3380832251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_types.3380832251
Directory /workspace/0.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.84125020
Short name T3393
Test name
Test status
Simulation time 282564231 ps
CPU time 2.43 seconds
Started Aug 18 05:31:48 PM PDT 24
Finished Aug 18 05:31:50 PM PDT 24
Peak memory 207672 kb
Host smart-f1269200-2965-48bf-a4d5-f04e333fa7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84125
020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.84125020
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.3631308260
Short name T822
Test name
Test status
Simulation time 118205190829 ps
CPU time 213.9 seconds
Started Aug 18 05:31:48 PM PDT 24
Finished Aug 18 05:35:22 PM PDT 24
Peak memory 207724 kb
Host smart-b2f8ad14-8397-4d59-ae41-316b5df841fd
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3631308260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.3631308260
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2326972868
Short name T2430
Test name
Test status
Simulation time 109115494035 ps
CPU time 176.09 seconds
Started Aug 18 05:31:43 PM PDT 24
Finished Aug 18 05:34:39 PM PDT 24
Peak memory 207772 kb
Host smart-f1756577-22b4-4c1b-863f-4a31cc370124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326972868 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2326972868
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.3469856158
Short name T2840
Test name
Test status
Simulation time 102168044327 ps
CPU time 149.45 seconds
Started Aug 18 05:31:39 PM PDT 24
Finished Aug 18 05:34:09 PM PDT 24
Peak memory 207768 kb
Host smart-f959a2f2-44a2-4982-8e21-6ce107c7d963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34698
56158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.3469856158
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1029803090
Short name T613
Test name
Test status
Simulation time 209026954 ps
CPU time 1.09 seconds
Started Aug 18 05:31:55 PM PDT 24
Finished Aug 18 05:31:56 PM PDT 24
Peak memory 216908 kb
Host smart-72a9aeb7-4983-493a-87a4-499488333ce6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1029803090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1029803090
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.164619985
Short name T1879
Test name
Test status
Simulation time 182953566 ps
CPU time 0.88 seconds
Started Aug 18 05:31:49 PM PDT 24
Finished Aug 18 05:31:50 PM PDT 24
Peak memory 207352 kb
Host smart-4a62e8d8-34e6-4e3c-9f97-8a54f7e88be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16461
9985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.164619985
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2927158243
Short name T3525
Test name
Test status
Simulation time 243046556 ps
CPU time 0.99 seconds
Started Aug 18 05:31:40 PM PDT 24
Finished Aug 18 05:31:41 PM PDT 24
Peak memory 207460 kb
Host smart-1b0bcf68-daa2-43a7-9eb0-9168b8c35c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29271
58243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2927158243
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.401272567
Short name T3049
Test name
Test status
Simulation time 4675660214 ps
CPU time 34.26 seconds
Started Aug 18 05:31:47 PM PDT 24
Finished Aug 18 05:32:22 PM PDT 24
Peak memory 218056 kb
Host smart-5c9b8371-2cf4-40fb-96a9-352c1a39349a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=401272567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.401272567
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.1677233022
Short name T1859
Test name
Test status
Simulation time 6089035532 ps
CPU time 38.14 seconds
Started Aug 18 05:31:46 PM PDT 24
Finished Aug 18 05:32:24 PM PDT 24
Peak memory 207792 kb
Host smart-eb6e07ed-42c8-4110-922a-31ff96f96336
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1677233022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.1677233022
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3008524207
Short name T2666
Test name
Test status
Simulation time 233243607 ps
CPU time 0.97 seconds
Started Aug 18 05:31:53 PM PDT 24
Finished Aug 18 05:31:54 PM PDT 24
Peak memory 207508 kb
Host smart-53b8fa2c-bdc2-4243-9c31-db2f268fe58f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30085
24207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3008524207
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.1053859370
Short name T64
Test name
Test status
Simulation time 503639636 ps
CPU time 1.56 seconds
Started Aug 18 05:31:47 PM PDT 24
Finished Aug 18 05:31:49 PM PDT 24
Peak memory 207584 kb
Host smart-bdb12ba0-ad5d-4e00-987e-0a967db72c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10538
59370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.1053859370
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.910766227
Short name T2786
Test name
Test status
Simulation time 24487741036 ps
CPU time 32.65 seconds
Started Aug 18 05:31:47 PM PDT 24
Finished Aug 18 05:32:20 PM PDT 24
Peak memory 207672 kb
Host smart-2c9fadd9-4cce-4a9e-9b01-54c142e9169e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91076
6227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.910766227
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1629650264
Short name T95
Test name
Test status
Simulation time 8517020179 ps
CPU time 11.49 seconds
Started Aug 18 05:31:48 PM PDT 24
Finished Aug 18 05:32:00 PM PDT 24
Peak memory 207824 kb
Host smart-3441f15d-e9ec-4fc9-8679-515ad3c9af08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16296
50264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1629650264
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.336567784
Short name T1183
Test name
Test status
Simulation time 5115497473 ps
CPU time 150.79 seconds
Started Aug 18 05:31:53 PM PDT 24
Finished Aug 18 05:34:24 PM PDT 24
Peak memory 218436 kb
Host smart-bfcee232-25d3-4746-899c-90088bb93055
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=336567784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.336567784
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.3449327703
Short name T3378
Test name
Test status
Simulation time 2320482065 ps
CPU time 23.2 seconds
Started Aug 18 05:31:50 PM PDT 24
Finished Aug 18 05:32:13 PM PDT 24
Peak memory 216932 kb
Host smart-2e3eac24-3b95-48e2-b19a-15936734f8f0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3449327703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3449327703
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1180689569
Short name T3169
Test name
Test status
Simulation time 234381301 ps
CPU time 0.96 seconds
Started Aug 18 05:31:46 PM PDT 24
Finished Aug 18 05:31:47 PM PDT 24
Peak memory 207484 kb
Host smart-92f55ae2-cecd-4812-a60a-c1c247e8b2a8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1180689569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1180689569
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1589333597
Short name T953
Test name
Test status
Simulation time 197898954 ps
CPU time 0.92 seconds
Started Aug 18 05:31:46 PM PDT 24
Finished Aug 18 05:31:48 PM PDT 24
Peak memory 207476 kb
Host smart-a410203c-75b7-4ea8-89b6-8b9902dc3491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15893
33597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1589333597
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_non_iso_usb_traffic.3321660493
Short name T3321
Test name
Test status
Simulation time 3525325327 ps
CPU time 101.01 seconds
Started Aug 18 05:31:39 PM PDT 24
Finished Aug 18 05:33:20 PM PDT 24
Peak memory 215900 kb
Host smart-bbd583ed-7f71-41f6-ab47-96e3e04ce8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33216
60493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_non_iso_usb_traffic.3321660493
Directory /workspace/0.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2094180929
Short name T1829
Test name
Test status
Simulation time 3680411905 ps
CPU time 103.46 seconds
Started Aug 18 05:31:47 PM PDT 24
Finished Aug 18 05:33:31 PM PDT 24
Peak memory 223960 kb
Host smart-d21b4dc2-41d3-41fb-8ddc-dd9fb8e35cf9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2094180929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2094180929
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.3638853369
Short name T1881
Test name
Test status
Simulation time 2581410247 ps
CPU time 19.17 seconds
Started Aug 18 05:31:34 PM PDT 24
Finished Aug 18 05:31:53 PM PDT 24
Peak memory 216032 kb
Host smart-cf200071-890b-44f7-a6fa-bb54bacdcb39
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3638853369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.3638853369
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.49173600
Short name T1979
Test name
Test status
Simulation time 153156621 ps
CPU time 0.84 seconds
Started Aug 18 05:31:45 PM PDT 24
Finished Aug 18 05:31:46 PM PDT 24
Peak memory 207436 kb
Host smart-72e80cdf-fd23-419c-97e4-df599d3931aa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=49173600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.49173600
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1614214771
Short name T3373
Test name
Test status
Simulation time 232777165 ps
CPU time 0.99 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:31:58 PM PDT 24
Peak memory 207504 kb
Host smart-90185e10-ec59-446f-897b-5f472a8e1f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16142
14771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1614214771
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.426141544
Short name T63
Test name
Test status
Simulation time 409516060 ps
CPU time 1.43 seconds
Started Aug 18 05:31:43 PM PDT 24
Finished Aug 18 05:31:44 PM PDT 24
Peak memory 207420 kb
Host smart-0521727d-e039-49f1-b421-1ed2a55d3510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42614
1544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.426141544
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.836196530
Short name T3046
Test name
Test status
Simulation time 169448705 ps
CPU time 0.98 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:31:55 PM PDT 24
Peak memory 207420 kb
Host smart-b64e8c9f-f4e1-457a-bf37-b827e39181f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83619
6530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.836196530
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3055989644
Short name T708
Test name
Test status
Simulation time 155345654 ps
CPU time 0.88 seconds
Started Aug 18 05:31:56 PM PDT 24
Finished Aug 18 05:31:57 PM PDT 24
Peak memory 207412 kb
Host smart-b925e7b3-09cf-4db7-85da-d57ebff1f14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30559
89644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3055989644
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2139646890
Short name T579
Test name
Test status
Simulation time 185015518 ps
CPU time 0.92 seconds
Started Aug 18 05:31:52 PM PDT 24
Finished Aug 18 05:31:53 PM PDT 24
Peak memory 207476 kb
Host smart-64c37cdb-57f6-413d-bb52-49b399cbc9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21396
46890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2139646890
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.1584250664
Short name T2433
Test name
Test status
Simulation time 146516132 ps
CPU time 0.87 seconds
Started Aug 18 05:31:50 PM PDT 24
Finished Aug 18 05:31:51 PM PDT 24
Peak memory 207568 kb
Host smart-cd8708f6-85b9-473f-8412-b1e65b51e6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15842
50664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.1584250664
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.4003006663
Short name T1970
Test name
Test status
Simulation time 161762611 ps
CPU time 0.91 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:31:59 PM PDT 24
Peak memory 207636 kb
Host smart-95d38ec8-c89c-459f-9c3a-b83bc78e6686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40030
06663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.4003006663
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.3964055853
Short name T2183
Test name
Test status
Simulation time 286279017 ps
CPU time 1.07 seconds
Started Aug 18 05:31:51 PM PDT 24
Finished Aug 18 05:31:52 PM PDT 24
Peak memory 207584 kb
Host smart-a6b99e5c-01f4-415e-9305-b589122c56ce
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3964055853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.3964055853
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.3848688669
Short name T722
Test name
Test status
Simulation time 250119260 ps
CPU time 1.2 seconds
Started Aug 18 05:31:51 PM PDT 24
Finished Aug 18 05:31:53 PM PDT 24
Peak memory 207456 kb
Host smart-6ef64416-cf54-4687-8383-fea6cb880b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38486
88669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.3848688669
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1754248746
Short name T1143
Test name
Test status
Simulation time 244944149 ps
CPU time 1.07 seconds
Started Aug 18 05:31:55 PM PDT 24
Finished Aug 18 05:31:57 PM PDT 24
Peak memory 207456 kb
Host smart-2413e0a8-b497-421f-be23-cc335d88f85f
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1754248746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1754248746
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.99744775
Short name T980
Test name
Test status
Simulation time 218458395 ps
CPU time 0.99 seconds
Started Aug 18 05:31:53 PM PDT 24
Finished Aug 18 05:31:55 PM PDT 24
Peak memory 207364 kb
Host smart-635b6a3a-d847-4259-8daa-fb10a0d0567f
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=99744775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.99744775
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2839171864
Short name T3128
Test name
Test status
Simulation time 140870646 ps
CPU time 0.83 seconds
Started Aug 18 05:31:48 PM PDT 24
Finished Aug 18 05:31:49 PM PDT 24
Peak memory 207456 kb
Host smart-27b04579-58e9-4df9-81e9-b4f84d14b122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28391
71864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2839171864
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1060762448
Short name T1734
Test name
Test status
Simulation time 58237592 ps
CPU time 0.7 seconds
Started Aug 18 05:31:56 PM PDT 24
Finished Aug 18 05:31:57 PM PDT 24
Peak memory 207544 kb
Host smart-c8e69627-2b7f-4cab-9d96-8d13348b3769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10607
62448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1060762448
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.1407768014
Short name T1792
Test name
Test status
Simulation time 11468307758 ps
CPU time 28.33 seconds
Started Aug 18 05:31:51 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 215928 kb
Host smart-1d19e2e4-5bbc-4775-b52d-fefb8f851572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14077
68014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.1407768014
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2721961504
Short name T3226
Test name
Test status
Simulation time 242963632 ps
CPU time 0.96 seconds
Started Aug 18 05:31:52 PM PDT 24
Finished Aug 18 05:31:53 PM PDT 24
Peak memory 207584 kb
Host smart-3f23e263-7864-4aca-b6d8-1a8a8a6a83a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27219
61504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2721961504
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1644483762
Short name T1062
Test name
Test status
Simulation time 208364081 ps
CPU time 0.95 seconds
Started Aug 18 05:31:51 PM PDT 24
Finished Aug 18 05:31:53 PM PDT 24
Peak memory 207468 kb
Host smart-5e3b162e-caa5-46a1-a181-91d6484b1625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16444
83762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1644483762
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.3724383124
Short name T883
Test name
Test status
Simulation time 3447151639 ps
CPU time 94.07 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:33:28 PM PDT 24
Peak memory 218536 kb
Host smart-dbb70659-2511-457d-aeef-16b7bfe79550
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724383124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.3724383124
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.1695990146
Short name T2742
Test name
Test status
Simulation time 7173235107 ps
CPU time 29.18 seconds
Started Aug 18 05:31:49 PM PDT 24
Finished Aug 18 05:32:23 PM PDT 24
Peak memory 219276 kb
Host smart-1805945d-93c1-442c-bd90-c72453cb8776
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1695990146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.1695990146
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.2569902742
Short name T57
Test name
Test status
Simulation time 5802056631 ps
CPU time 72.39 seconds
Started Aug 18 05:31:53 PM PDT 24
Finished Aug 18 05:33:06 PM PDT 24
Peak memory 219220 kb
Host smart-93d0420a-5897-41a7-bcb2-82097179b3e1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569902742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.2569902742
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.1345970384
Short name T1724
Test name
Test status
Simulation time 257052622 ps
CPU time 1.06 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:31:56 PM PDT 24
Peak memory 207524 kb
Host smart-807d2061-b35e-4470-b81a-0b46c08a0e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13459
70384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.1345970384
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.3069660364
Short name T2015
Test name
Test status
Simulation time 170800806 ps
CPU time 0.86 seconds
Started Aug 18 05:31:46 PM PDT 24
Finished Aug 18 05:31:48 PM PDT 24
Peak memory 207504 kb
Host smart-3b2d3586-6a89-447d-b78e-8a1719b312a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30696
60364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.3069660364
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.3051141517
Short name T3304
Test name
Test status
Simulation time 20163690295 ps
CPU time 22.62 seconds
Started Aug 18 05:31:45 PM PDT 24
Finished Aug 18 05:32:07 PM PDT 24
Peak memory 207584 kb
Host smart-62ce16a7-ca13-4d81-b1de-e9421f467a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30511
41517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.3051141517
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.3320877444
Short name T3051
Test name
Test status
Simulation time 141298834 ps
CPU time 0.8 seconds
Started Aug 18 05:31:50 PM PDT 24
Finished Aug 18 05:31:51 PM PDT 24
Peak memory 207452 kb
Host smart-bf0721c9-68f9-4b68-867b-017b01f3f3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33208
77444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.3320877444
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.698441049
Short name T2551
Test name
Test status
Simulation time 385391426 ps
CPU time 1.24 seconds
Started Aug 18 05:31:52 PM PDT 24
Finished Aug 18 05:31:54 PM PDT 24
Peak memory 207476 kb
Host smart-91a51b08-8fb6-491b-829b-48d8a0fcbdb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69844
1049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.698441049
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2310356307
Short name T252
Test name
Test status
Simulation time 428251028 ps
CPU time 1.24 seconds
Started Aug 18 05:31:59 PM PDT 24
Finished Aug 18 05:32:00 PM PDT 24
Peak memory 223348 kb
Host smart-a8e14b89-83a9-44fe-8716-a06f80166b90
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2310356307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2310356307
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.62830282
Short name T3324
Test name
Test status
Simulation time 205015871 ps
CPU time 0.99 seconds
Started Aug 18 05:31:52 PM PDT 24
Finished Aug 18 05:31:54 PM PDT 24
Peak memory 207456 kb
Host smart-0e6b5c4a-2ffb-429f-ab17-9a8e4886f80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62830
282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.62830282
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2070110100
Short name T931
Test name
Test status
Simulation time 157213188 ps
CPU time 0.85 seconds
Started Aug 18 05:31:52 PM PDT 24
Finished Aug 18 05:31:53 PM PDT 24
Peak memory 207444 kb
Host smart-160cb9df-88ab-4d39-afd3-543f8ec15f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20701
10100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2070110100
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1307675269
Short name T2752
Test name
Test status
Simulation time 160597016 ps
CPU time 0.88 seconds
Started Aug 18 05:31:49 PM PDT 24
Finished Aug 18 05:31:50 PM PDT 24
Peak memory 207492 kb
Host smart-913f3cf0-db85-4d26-bb87-42bc9e2b7008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13076
75269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1307675269
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3910809670
Short name T2634
Test name
Test status
Simulation time 246424640 ps
CPU time 1.11 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:31:55 PM PDT 24
Peak memory 207492 kb
Host smart-f3a5e184-3da3-4b41-860c-7d14652af728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39108
09670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3910809670
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.4282358108
Short name T3053
Test name
Test status
Simulation time 2379568096 ps
CPU time 69.19 seconds
Started Aug 18 05:31:44 PM PDT 24
Finished Aug 18 05:32:54 PM PDT 24
Peak memory 217776 kb
Host smart-fdb759d5-0413-474c-bcf9-b2b50b444669
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4282358108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.4282358108
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3924806423
Short name T2775
Test name
Test status
Simulation time 222731805 ps
CPU time 0.93 seconds
Started Aug 18 05:31:51 PM PDT 24
Finished Aug 18 05:31:53 PM PDT 24
Peak memory 207368 kb
Host smart-a1d2fd92-3fc3-4a9a-9841-8df88ecedbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39248
06423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3924806423
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.705860224
Short name T1263
Test name
Test status
Simulation time 169179176 ps
CPU time 0.89 seconds
Started Aug 18 05:31:46 PM PDT 24
Finished Aug 18 05:31:48 PM PDT 24
Peak memory 207488 kb
Host smart-37d0d247-c544-4474-b18c-b1bd23ed5a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70586
0224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.705860224
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.338773825
Short name T2793
Test name
Test status
Simulation time 269192452 ps
CPU time 1.1 seconds
Started Aug 18 05:31:53 PM PDT 24
Finished Aug 18 05:31:54 PM PDT 24
Peak memory 207496 kb
Host smart-4a71a0fa-1f6e-44ce-922c-5687d9a348f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33877
3825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.338773825
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.882371923
Short name T2037
Test name
Test status
Simulation time 4251104844 ps
CPU time 42.2 seconds
Started Aug 18 05:31:51 PM PDT 24
Finished Aug 18 05:32:33 PM PDT 24
Peak memory 217620 kb
Host smart-b4caaacc-9b31-4dc9-97ae-7c9b4477ab9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88237
1923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.882371923
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.2733332724
Short name T2604
Test name
Test status
Simulation time 1511649586 ps
CPU time 9.96 seconds
Started Aug 18 05:31:41 PM PDT 24
Finished Aug 18 05:31:51 PM PDT 24
Peak memory 207668 kb
Host smart-b796669c-53de-4db5-84f1-92bd8e06794c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733332724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host
_handshake.2733332724
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/0.usbdev_tx_rx_disruption.4076870322
Short name T3371
Test name
Test status
Simulation time 481344462 ps
CPU time 1.48 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:31:55 PM PDT 24
Peak memory 207492 kb
Host smart-eae3f7ef-5317-4adf-b01a-7647d8bcceda
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076870322 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.usbdev_tx_rx_disruption.4076870322
Directory /workspace/0.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.467508728
Short name T1897
Test name
Test status
Simulation time 65845254 ps
CPU time 0.7 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:32:03 PM PDT 24
Peak memory 207464 kb
Host smart-335b5c27-3a03-413b-a8a6-d36a9f32fa28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=467508728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.467508728
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1782920248
Short name T3034
Test name
Test status
Simulation time 9325110111 ps
CPU time 12.29 seconds
Started Aug 18 05:31:55 PM PDT 24
Finished Aug 18 05:32:07 PM PDT 24
Peak memory 207784 kb
Host smart-718ee264-b938-4193-bae6-b73f607d5359
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782920248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.1782920248
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.4149576480
Short name T275
Test name
Test status
Simulation time 14352495981 ps
CPU time 21.39 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 216000 kb
Host smart-5d147734-db5b-49f0-9e6a-d7724d8a8fc6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149576480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.4149576480
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.4123211224
Short name T8
Test name
Test status
Simulation time 30831016828 ps
CPU time 43.23 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:32:42 PM PDT 24
Peak memory 207816 kb
Host smart-0096c7ef-1d0a-4707-89ea-97b42c8a2c69
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123211224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.4123211224
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1958037833
Short name T2624
Test name
Test status
Simulation time 169495910 ps
CPU time 0.87 seconds
Started Aug 18 05:32:02 PM PDT 24
Finished Aug 18 05:32:03 PM PDT 24
Peak memory 207496 kb
Host smart-68e214e0-245b-409b-85d2-10a137f5c133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19580
37833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1958037833
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.1477701819
Short name T84
Test name
Test status
Simulation time 156293733 ps
CPU time 0.89 seconds
Started Aug 18 05:31:52 PM PDT 24
Finished Aug 18 05:31:53 PM PDT 24
Peak memory 207596 kb
Host smart-821ca5a6-f082-42ff-8413-3c77e0856de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14777
01819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.1477701819
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1189194254
Short name T2506
Test name
Test status
Simulation time 209110428 ps
CPU time 0.9 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:32:00 PM PDT 24
Peak memory 207596 kb
Host smart-95c32c10-dfb6-4240-a36c-b8b835e7a54a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11891
94254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1189194254
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.363537558
Short name T3201
Test name
Test status
Simulation time 577064386 ps
CPU time 1.78 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:31:57 PM PDT 24
Peak memory 207680 kb
Host smart-0733a893-a28a-4d0f-94f4-88d90c42f098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36353
7558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.363537558
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1150522302
Short name T1472
Test name
Test status
Simulation time 324411058 ps
CPU time 1.11 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:32:00 PM PDT 24
Peak memory 207544 kb
Host smart-ce08db76-1a8f-4b20-9599-49e5460941e1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1150522302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1150522302
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.1479293865
Short name T1100
Test name
Test status
Simulation time 19993134009 ps
CPU time 36.21 seconds
Started Aug 18 05:32:12 PM PDT 24
Finished Aug 18 05:32:48 PM PDT 24
Peak memory 207776 kb
Host smart-432fd315-4e08-4e17-84cb-86642a64cbed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14792
93865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.1479293865
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.1527887996
Short name T1845
Test name
Test status
Simulation time 2106680233 ps
CPU time 18.2 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:32:16 PM PDT 24
Peak memory 207708 kb
Host smart-3d13b69f-4111-4e6a-8489-8518a06d8eb8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527887996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.1527887996
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.1594972570
Short name T3398
Test name
Test status
Simulation time 580561576 ps
CPU time 1.57 seconds
Started Aug 18 05:31:59 PM PDT 24
Finished Aug 18 05:32:01 PM PDT 24
Peak memory 207492 kb
Host smart-b892bb3f-e149-4d43-8c96-156410d2dc3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15949
72570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.1594972570
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_enable.1155227231
Short name T2221
Test name
Test status
Simulation time 37693588 ps
CPU time 0.71 seconds
Started Aug 18 05:31:49 PM PDT 24
Finished Aug 18 05:31:50 PM PDT 24
Peak memory 207364 kb
Host smart-86c88ecb-ecd7-4451-8b66-9e9669de0af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11552
27231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1155227231
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.3280951032
Short name T1115
Test name
Test status
Simulation time 846693159 ps
CPU time 2.4 seconds
Started Aug 18 05:31:49 PM PDT 24
Finished Aug 18 05:31:51 PM PDT 24
Peak memory 207748 kb
Host smart-fe8c99f2-beb7-4546-acd9-003d9ab3f624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32809
51032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.3280951032
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_types.220684494
Short name T419
Test name
Test status
Simulation time 751261972 ps
CPU time 1.86 seconds
Started Aug 18 05:31:56 PM PDT 24
Finished Aug 18 05:32:04 PM PDT 24
Peak memory 207492 kb
Host smart-b054513f-efdd-4fa6-9e3d-364a3d0621e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=220684494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_types.220684494
Directory /workspace/1.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2192818944
Short name T1574
Test name
Test status
Simulation time 218498249 ps
CPU time 2.41 seconds
Started Aug 18 05:32:10 PM PDT 24
Finished Aug 18 05:32:12 PM PDT 24
Peak memory 207648 kb
Host smart-2eca386a-5882-4167-87e0-4127c610b0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21928
18944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2192818944
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.602956175
Short name T2398
Test name
Test status
Simulation time 84211286905 ps
CPU time 124.46 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:34:03 PM PDT 24
Peak memory 207224 kb
Host smart-ca8f9294-9c6a-449e-a4cb-7d8b88ca7cd7
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=602956175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.602956175
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.923559463
Short name T2727
Test name
Test status
Simulation time 99237877698 ps
CPU time 162.58 seconds
Started Aug 18 05:32:02 PM PDT 24
Finished Aug 18 05:34:44 PM PDT 24
Peak memory 207792 kb
Host smart-b101049d-85a5-42c8-921a-e7a673191e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923559463 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.923559463
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.3828361273
Short name T1971
Test name
Test status
Simulation time 118092232123 ps
CPU time 217.7 seconds
Started Aug 18 05:32:07 PM PDT 24
Finished Aug 18 05:35:45 PM PDT 24
Peak memory 207736 kb
Host smart-3b50671e-2bc1-41d4-aca1-5a5c0a39ccca
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3828361273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.3828361273
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.3805275478
Short name T2318
Test name
Test status
Simulation time 110204592117 ps
CPU time 204.45 seconds
Started Aug 18 05:31:59 PM PDT 24
Finished Aug 18 05:35:23 PM PDT 24
Peak memory 207756 kb
Host smart-f31333a7-1c0f-49d4-b58a-4f65955b8a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805275478 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.3805275478
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.4266969191
Short name T1342
Test name
Test status
Simulation time 96161237867 ps
CPU time 141.54 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:34:15 PM PDT 24
Peak memory 207656 kb
Host smart-e763d43c-55f5-4519-953f-0db6b2443496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42669
69191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.4266969191
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.517070392
Short name T679
Test name
Test status
Simulation time 221943556 ps
CPU time 1.28 seconds
Started Aug 18 05:32:00 PM PDT 24
Finished Aug 18 05:32:01 PM PDT 24
Peak memory 215920 kb
Host smart-18b60a80-b444-41f9-b5da-0323fa58a68e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=517070392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.517070392
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.4272168622
Short name T1192
Test name
Test status
Simulation time 194156216 ps
CPU time 0.9 seconds
Started Aug 18 05:32:05 PM PDT 24
Finished Aug 18 05:32:06 PM PDT 24
Peak memory 207384 kb
Host smart-a50469e5-55fc-429d-aa9b-5dc02cdc4488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42721
68622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.4272168622
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3673008476
Short name T1001
Test name
Test status
Simulation time 200013168 ps
CPU time 0.99 seconds
Started Aug 18 05:31:59 PM PDT 24
Finished Aug 18 05:32:01 PM PDT 24
Peak memory 207504 kb
Host smart-9bfae75e-d15e-4afc-ac34-778143ce9c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36730
08476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3673008476
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.3062665587
Short name T1715
Test name
Test status
Simulation time 10273118686 ps
CPU time 73.83 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:33:12 PM PDT 24
Peak memory 207788 kb
Host smart-06eac8ee-4e2a-4f31-af1c-69db02fb6425
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3062665587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.3062665587
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.1683874149
Short name T519
Test name
Test status
Simulation time 169789052 ps
CPU time 0.86 seconds
Started Aug 18 05:32:11 PM PDT 24
Finished Aug 18 05:32:12 PM PDT 24
Peak memory 207508 kb
Host smart-e5cc84b5-3d29-461d-916d-83b41132868d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16838
74149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.1683874149
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.959675830
Short name T2486
Test name
Test status
Simulation time 26830859409 ps
CPU time 44.63 seconds
Started Aug 18 05:31:51 PM PDT 24
Finished Aug 18 05:32:36 PM PDT 24
Peak memory 207628 kb
Host smart-f4ae162b-6e2d-48d4-a064-988d5a3b697b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95967
5830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.959675830
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.3315602400
Short name T96
Test name
Test status
Simulation time 11357860063 ps
CPU time 16.41 seconds
Started Aug 18 05:31:59 PM PDT 24
Finished Aug 18 05:32:16 PM PDT 24
Peak memory 207756 kb
Host smart-a80d1b5d-37bb-426d-9af7-6da0cb40559c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33156
02400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.3315602400
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.1716011872
Short name T1768
Test name
Test status
Simulation time 2930420856 ps
CPU time 23.2 seconds
Started Aug 18 05:31:59 PM PDT 24
Finished Aug 18 05:32:23 PM PDT 24
Peak memory 219068 kb
Host smart-610a0484-66b0-4b7a-bf41-568c096a1cdc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1716011872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.1716011872
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1349421412
Short name T937
Test name
Test status
Simulation time 1998277014 ps
CPU time 15.41 seconds
Started Aug 18 05:31:51 PM PDT 24
Finished Aug 18 05:32:07 PM PDT 24
Peak memory 215904 kb
Host smart-070b4fd1-546a-42dc-a683-dc702717156c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1349421412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1349421412
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.2626568503
Short name T3113
Test name
Test status
Simulation time 243220537 ps
CPU time 1.03 seconds
Started Aug 18 05:31:59 PM PDT 24
Finished Aug 18 05:32:00 PM PDT 24
Peak memory 207416 kb
Host smart-01e3d321-b303-430c-b534-467ba768cc49
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2626568503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.2626568503
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.620252061
Short name T634
Test name
Test status
Simulation time 215818892 ps
CPU time 0.97 seconds
Started Aug 18 05:31:52 PM PDT 24
Finished Aug 18 05:31:54 PM PDT 24
Peak memory 207444 kb
Host smart-6083f6a6-61e6-4a27-92b8-c6130b1c055d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62025
2061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.620252061
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_non_iso_usb_traffic.1336383262
Short name T5
Test name
Test status
Simulation time 2091681870 ps
CPU time 58.61 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:32:56 PM PDT 24
Peak memory 217348 kb
Host smart-78c6a80e-e44c-4363-89ac-358327741144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13363
83262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_non_iso_usb_traffic.1336383262
Directory /workspace/1.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.3832959968
Short name T122
Test name
Test status
Simulation time 2003791502 ps
CPU time 21.11 seconds
Started Aug 18 05:32:11 PM PDT 24
Finished Aug 18 05:32:39 PM PDT 24
Peak memory 224104 kb
Host smart-4b95b830-080c-435d-b664-0030f7324ed8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3832959968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.3832959968
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3310401122
Short name T1047
Test name
Test status
Simulation time 2968666521 ps
CPU time 81.19 seconds
Started Aug 18 05:32:00 PM PDT 24
Finished Aug 18 05:33:21 PM PDT 24
Peak memory 217524 kb
Host smart-fcfe47c7-8097-4d0b-93ea-9fed31eba017
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3310401122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3310401122
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.3731551323
Short name T2251
Test name
Test status
Simulation time 159479025 ps
CPU time 0.89 seconds
Started Aug 18 05:31:56 PM PDT 24
Finished Aug 18 05:31:58 PM PDT 24
Peak memory 207420 kb
Host smart-7c8b35a6-cbec-40d1-8a55-2cab8d997aa7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3731551323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.3731551323
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.333335629
Short name T573
Test name
Test status
Simulation time 145726889 ps
CPU time 0.84 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:31:58 PM PDT 24
Peak memory 207372 kb
Host smart-b4c5bdc5-7348-4cc9-9dbf-9e4f2e9d0836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33333
5629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.333335629
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.2035486680
Short name T2004
Test name
Test status
Simulation time 155464307 ps
CPU time 0.87 seconds
Started Aug 18 05:31:59 PM PDT 24
Finished Aug 18 05:32:01 PM PDT 24
Peak memory 207508 kb
Host smart-be839cd7-402d-4c81-912c-c4b3d903d34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20354
86680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.2035486680
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.4178327666
Short name T1851
Test name
Test status
Simulation time 179801724 ps
CPU time 0.9 seconds
Started Aug 18 05:32:07 PM PDT 24
Finished Aug 18 05:32:08 PM PDT 24
Peak memory 207476 kb
Host smart-080fa89f-6373-47c7-b2fd-a8a44023a222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41783
27666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.4178327666
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.640826901
Short name T1630
Test name
Test status
Simulation time 169425024 ps
CPU time 0.94 seconds
Started Aug 18 05:31:55 PM PDT 24
Finished Aug 18 05:31:56 PM PDT 24
Peak memory 207436 kb
Host smart-39740c20-2134-4f3b-82f2-b4fdb5acc76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64082
6901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.640826901
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3220035252
Short name T2864
Test name
Test status
Simulation time 170704568 ps
CPU time 0.86 seconds
Started Aug 18 05:31:55 PM PDT 24
Finished Aug 18 05:31:57 PM PDT 24
Peak memory 207536 kb
Host smart-7efab24f-1f04-4d2f-8b61-1f534aa41ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32200
35252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3220035252
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.2200659421
Short name T1612
Test name
Test status
Simulation time 260693896 ps
CPU time 1.05 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:31:59 PM PDT 24
Peak memory 207592 kb
Host smart-cfee68f1-410f-4ff1-b416-18b6f8beba41
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2200659421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.2200659421
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.802124759
Short name T1944
Test name
Test status
Simulation time 261109003 ps
CPU time 1.13 seconds
Started Aug 18 05:32:03 PM PDT 24
Finished Aug 18 05:32:04 PM PDT 24
Peak memory 207408 kb
Host smart-b42f0ab6-eb67-4285-a29d-cb30308460a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80212
4759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.802124759
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1726676687
Short name T3557
Test name
Test status
Simulation time 165058550 ps
CPU time 0.86 seconds
Started Aug 18 05:31:53 PM PDT 24
Finished Aug 18 05:31:54 PM PDT 24
Peak memory 207400 kb
Host smart-fa13dbbb-b464-4ae3-85d3-fe6f96a9ebe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17266
76687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1726676687
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1344664547
Short name T2935
Test name
Test status
Simulation time 36590504 ps
CPU time 0.67 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:31:59 PM PDT 24
Peak memory 207504 kb
Host smart-0f9a1714-0062-47dc-b029-7982149c57c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13446
64547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1344664547
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.143832915
Short name T1483
Test name
Test status
Simulation time 157903770 ps
CPU time 0.91 seconds
Started Aug 18 05:32:15 PM PDT 24
Finished Aug 18 05:32:16 PM PDT 24
Peak memory 207496 kb
Host smart-b15d9b17-d6e3-4bd6-9b61-beae59e2cc08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14383
2915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.143832915
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2848265617
Short name T2931
Test name
Test status
Simulation time 215406496 ps
CPU time 0.92 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:31:59 PM PDT 24
Peak memory 207424 kb
Host smart-ce4a77ea-3a37-49c2-b109-a224c8462db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28482
65617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2848265617
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2402420292
Short name T2924
Test name
Test status
Simulation time 3089221997 ps
CPU time 17.86 seconds
Started Aug 18 05:31:55 PM PDT 24
Finished Aug 18 05:32:13 PM PDT 24
Peak memory 218180 kb
Host smart-8efb4ad2-b661-4860-b1ed-09ed2422c975
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2402420292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2402420292
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.546483145
Short name T1953
Test name
Test status
Simulation time 7030939250 ps
CPU time 90.12 seconds
Started Aug 18 05:31:56 PM PDT 24
Finished Aug 18 05:33:26 PM PDT 24
Peak memory 215960 kb
Host smart-f2d744cd-a57f-4a2e-8b05-f46306fd511c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=546483145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.546483145
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.320261876
Short name T3613
Test name
Test status
Simulation time 217710874 ps
CPU time 0.98 seconds
Started Aug 18 05:31:55 PM PDT 24
Finished Aug 18 05:31:56 PM PDT 24
Peak memory 207424 kb
Host smart-afab3c95-939c-49da-8e46-8cafaad96400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32026
1876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.320261876
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.642664335
Short name T1638
Test name
Test status
Simulation time 175183819 ps
CPU time 0.86 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:31:56 PM PDT 24
Peak memory 207452 kb
Host smart-debbb0fc-0061-4e71-aea5-5319ea0ccbaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64266
4335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.642664335
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_resume_link_active.916639146
Short name T3383
Test name
Test status
Simulation time 20158032712 ps
CPU time 28.43 seconds
Started Aug 18 05:32:06 PM PDT 24
Finished Aug 18 05:32:35 PM PDT 24
Peak memory 207548 kb
Host smart-483372e7-f3a6-465f-8de4-f6bde0119184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91663
9146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_resume_link_active.916639146
Directory /workspace/1.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.2436049706
Short name T704
Test name
Test status
Simulation time 152031638 ps
CPU time 0.89 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:31:58 PM PDT 24
Peak memory 207496 kb
Host smart-a39a2d31-6191-49f2-9310-43be43675402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24360
49706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.2436049706
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_full.1916399327
Short name T1376
Test name
Test status
Simulation time 351837158 ps
CPU time 1.26 seconds
Started Aug 18 05:31:53 PM PDT 24
Finished Aug 18 05:31:55 PM PDT 24
Peak memory 207420 kb
Host smart-c54938fa-e669-49d2-860c-9afb4dbc38e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19163
99327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_full.1916399327
Directory /workspace/1.usbdev_rx_full/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.1829062577
Short name T73
Test name
Test status
Simulation time 232981926 ps
CPU time 0.97 seconds
Started Aug 18 05:32:12 PM PDT 24
Finished Aug 18 05:32:13 PM PDT 24
Peak memory 207492 kb
Host smart-23656b40-c403-4354-bafc-fba03cf4c020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18290
62577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.1829062577
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.4071466975
Short name T2878
Test name
Test status
Simulation time 385994009 ps
CPU time 1.33 seconds
Started Aug 18 05:31:55 PM PDT 24
Finished Aug 18 05:31:57 PM PDT 24
Peak memory 207572 kb
Host smart-1c93af1f-48a4-49a7-97db-1058f6a91ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40714
66975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.4071466975
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.1778760209
Short name T2620
Test name
Test status
Simulation time 199288204 ps
CPU time 0.94 seconds
Started Aug 18 05:31:55 PM PDT 24
Finished Aug 18 05:31:57 PM PDT 24
Peak memory 207432 kb
Host smart-66910835-29a4-4e95-8259-3bcc2f325fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17787
60209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.1778760209
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.645994514
Short name T695
Test name
Test status
Simulation time 158026962 ps
CPU time 0.83 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:31:58 PM PDT 24
Peak memory 207304 kb
Host smart-cf8d989e-60dc-4b39-8ab3-b1e21e23bd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64599
4514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.645994514
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1507322840
Short name T2098
Test name
Test status
Simulation time 181125185 ps
CPU time 0.88 seconds
Started Aug 18 05:31:52 PM PDT 24
Finished Aug 18 05:31:53 PM PDT 24
Peak memory 207532 kb
Host smart-e86fbfa1-81fa-4bc3-9426-379072647d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15073
22840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1507322840
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2450819970
Short name T671
Test name
Test status
Simulation time 246391312 ps
CPU time 1.09 seconds
Started Aug 18 05:32:00 PM PDT 24
Finished Aug 18 05:32:01 PM PDT 24
Peak memory 207456 kb
Host smart-0a7e12a0-ab2c-4fdb-a4bf-208a3e611301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24508
19970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2450819970
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.1344361469
Short name T1521
Test name
Test status
Simulation time 3821403970 ps
CPU time 28.08 seconds
Started Aug 18 05:31:53 PM PDT 24
Finished Aug 18 05:32:27 PM PDT 24
Peak memory 224016 kb
Host smart-e5a29534-a45f-44e7-9ec4-49664e232bdb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1344361469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.1344361469
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1051394262
Short name T3421
Test name
Test status
Simulation time 177422162 ps
CPU time 0.99 seconds
Started Aug 18 05:32:01 PM PDT 24
Finished Aug 18 05:32:02 PM PDT 24
Peak memory 207444 kb
Host smart-58aa9e24-7a26-4e46-92c7-a11f8ad3b2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10513
94262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1051394262
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.2155695478
Short name T1794
Test name
Test status
Simulation time 158544374 ps
CPU time 0.84 seconds
Started Aug 18 05:31:53 PM PDT 24
Finished Aug 18 05:31:54 PM PDT 24
Peak memory 207488 kb
Host smart-e60c1e9f-fea9-4dd0-9cbe-abd9707be737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21556
95478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.2155695478
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.748606001
Short name T1590
Test name
Test status
Simulation time 608261116 ps
CPU time 1.74 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:31:56 PM PDT 24
Peak memory 207548 kb
Host smart-58651ef3-f22b-4f4c-8ed9-1f06af92ca12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74860
6001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.748606001
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.3423255307
Short name T3508
Test name
Test status
Simulation time 3345939573 ps
CPU time 97.96 seconds
Started Aug 18 05:31:52 PM PDT 24
Finished Aug 18 05:33:30 PM PDT 24
Peak memory 215888 kb
Host smart-d5ffed3f-1881-4c6e-a5b4-4114f3047b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34232
55307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.3423255307
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.1651237618
Short name T1749
Test name
Test status
Simulation time 460915673 ps
CPU time 8.13 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:32:05 PM PDT 24
Peak memory 207600 kb
Host smart-ba7cd960-6dfe-4c48-ad35-ede780734d45
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651237618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.1651237618
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_tx_rx_disruption.3457896092
Short name T1681
Test name
Test status
Simulation time 491065717 ps
CPU time 1.52 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:32:00 PM PDT 24
Peak memory 207456 kb
Host smart-8ffd9131-7e40-4702-b814-d1928fc64e79
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457896092 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.usbdev_tx_rx_disruption.3457896092
Directory /workspace/1.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.2254785650
Short name T2556
Test name
Test status
Simulation time 75179761 ps
CPU time 0.73 seconds
Started Aug 18 05:33:30 PM PDT 24
Finished Aug 18 05:33:31 PM PDT 24
Peak memory 207468 kb
Host smart-225c5757-4b99-4c6f-86e5-792dd2890d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2254785650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.2254785650
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.2996862571
Short name T2107
Test name
Test status
Simulation time 10309615644 ps
CPU time 13.34 seconds
Started Aug 18 05:33:34 PM PDT 24
Finished Aug 18 05:33:47 PM PDT 24
Peak memory 207808 kb
Host smart-1bcb192a-0ac0-4833-8f29-bf637b814486
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996862571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.2996862571
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.2111730803
Short name T2814
Test name
Test status
Simulation time 20626341969 ps
CPU time 25.1 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:38 PM PDT 24
Peak memory 207788 kb
Host smart-70f423ea-db34-4fe1-b569-d1ce9acd495a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111730803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2111730803
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.4112838726
Short name T684
Test name
Test status
Simulation time 184120296 ps
CPU time 0.87 seconds
Started Aug 18 05:33:23 PM PDT 24
Finished Aug 18 05:33:24 PM PDT 24
Peak memory 207636 kb
Host smart-9c86e58e-3994-4003-a29d-56a8563eaf08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41128
38726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.4112838726
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3506769459
Short name T2709
Test name
Test status
Simulation time 143340530 ps
CPU time 0.84 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 207480 kb
Host smart-7de626e3-20c8-476c-b834-2cc2a8c99006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35067
69459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3506769459
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.610407397
Short name T1328
Test name
Test status
Simulation time 251890117 ps
CPU time 1.16 seconds
Started Aug 18 05:33:24 PM PDT 24
Finished Aug 18 05:33:25 PM PDT 24
Peak memory 207472 kb
Host smart-2ae9dc49-dcbf-42f9-a461-acfdab146b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61040
7397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.610407397
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.716681258
Short name T1835
Test name
Test status
Simulation time 1284852630 ps
CPU time 3.44 seconds
Started Aug 18 05:33:36 PM PDT 24
Finished Aug 18 05:33:39 PM PDT 24
Peak memory 207756 kb
Host smart-ae431c08-30a0-4d79-81df-90b8082954b0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=716681258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.716681258
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.4230673051
Short name T210
Test name
Test status
Simulation time 35645479012 ps
CPU time 60.28 seconds
Started Aug 18 05:33:25 PM PDT 24
Finished Aug 18 05:34:25 PM PDT 24
Peak memory 207784 kb
Host smart-24b4646c-6b2e-464d-bd89-dee44cfb82a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42306
73051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.4230673051
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.3232082190
Short name T2962
Test name
Test status
Simulation time 2981130114 ps
CPU time 26.04 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:40 PM PDT 24
Peak memory 207784 kb
Host smart-6a03d6ef-d650-429b-be5f-044cf56feacf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232082190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.3232082190
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.1666261830
Short name T3156
Test name
Test status
Simulation time 472761679 ps
CPU time 1.43 seconds
Started Aug 18 05:33:18 PM PDT 24
Finished Aug 18 05:33:19 PM PDT 24
Peak memory 207496 kb
Host smart-3f2b8af1-3f9d-4a90-8f0e-fdcd6ef67d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16662
61830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.1666261830
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2762814156
Short name T2014
Test name
Test status
Simulation time 152390496 ps
CPU time 0.85 seconds
Started Aug 18 05:33:24 PM PDT 24
Finished Aug 18 05:33:25 PM PDT 24
Peak memory 207512 kb
Host smart-843b8647-f493-4bbd-81ed-78ee778867e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27628
14156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2762814156
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.4094430359
Short name T2956
Test name
Test status
Simulation time 46639456 ps
CPU time 0.7 seconds
Started Aug 18 05:33:17 PM PDT 24
Finished Aug 18 05:33:18 PM PDT 24
Peak memory 207468 kb
Host smart-d83392b7-10a5-4ce4-90c7-b468e5a0861c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40944
30359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.4094430359
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.1011709886
Short name T2277
Test name
Test status
Simulation time 776187149 ps
CPU time 2.25 seconds
Started Aug 18 05:33:15 PM PDT 24
Finished Aug 18 05:33:17 PM PDT 24
Peak memory 207772 kb
Host smart-38d6750b-40cd-4413-be28-813e9366bb6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10117
09886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.1011709886
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.313621293
Short name T3577
Test name
Test status
Simulation time 152409123 ps
CPU time 1.55 seconds
Started Aug 18 05:33:33 PM PDT 24
Finished Aug 18 05:33:35 PM PDT 24
Peak memory 207632 kb
Host smart-5ffd67ba-6f3f-472c-850e-46b05fbaae52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31362
1293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.313621293
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1206880807
Short name T2261
Test name
Test status
Simulation time 199040537 ps
CPU time 0.88 seconds
Started Aug 18 05:33:16 PM PDT 24
Finished Aug 18 05:33:17 PM PDT 24
Peak memory 207440 kb
Host smart-24acad2e-e59b-48b6-8e9e-a960a94601a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12068
80807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1206880807
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.1365741418
Short name T2717
Test name
Test status
Simulation time 238735586 ps
CPU time 1.02 seconds
Started Aug 18 05:33:34 PM PDT 24
Finished Aug 18 05:33:35 PM PDT 24
Peak memory 207480 kb
Host smart-af3ab7d9-58f8-4fa9-8b83-b71eaa969929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13657
41418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.1365741418
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.2448700412
Short name T110
Test name
Test status
Simulation time 4004611301 ps
CPU time 29.4 seconds
Started Aug 18 05:33:37 PM PDT 24
Finished Aug 18 05:34:07 PM PDT 24
Peak memory 224168 kb
Host smart-2da43190-18e7-4daa-bf56-81a513ae1c57
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2448700412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.2448700412
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.625900911
Short name T3100
Test name
Test status
Simulation time 13095592922 ps
CPU time 83.88 seconds
Started Aug 18 05:33:23 PM PDT 24
Finished Aug 18 05:34:47 PM PDT 24
Peak memory 207804 kb
Host smart-7d583541-6b8b-4085-aa13-027cf22424c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=625900911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.625900911
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.1438445386
Short name T1349
Test name
Test status
Simulation time 162554635 ps
CPU time 0.89 seconds
Started Aug 18 05:33:32 PM PDT 24
Finished Aug 18 05:33:33 PM PDT 24
Peak memory 207584 kb
Host smart-49c618f9-a6a3-4806-aaea-b6981fcdeafc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14384
45386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.1438445386
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.1381368513
Short name T3526
Test name
Test status
Simulation time 8326388204 ps
CPU time 12.96 seconds
Started Aug 18 05:33:16 PM PDT 24
Finished Aug 18 05:33:29 PM PDT 24
Peak memory 216116 kb
Host smart-2e858991-6f6d-4471-828f-5b2a72eb7acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13813
68513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.1381368513
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1301322909
Short name T1111
Test name
Test status
Simulation time 6339681749 ps
CPU time 8.14 seconds
Started Aug 18 05:33:28 PM PDT 24
Finished Aug 18 05:33:37 PM PDT 24
Peak memory 207752 kb
Host smart-9069b0d8-21fc-4785-a851-5a142789d987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13013
22909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1301322909
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.367722796
Short name T1740
Test name
Test status
Simulation time 3328581319 ps
CPU time 33.11 seconds
Started Aug 18 05:33:38 PM PDT 24
Finished Aug 18 05:34:11 PM PDT 24
Peak memory 216000 kb
Host smart-47baec65-6f84-4659-8222-53409442ceb5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=367722796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.367722796
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.1094944640
Short name T1804
Test name
Test status
Simulation time 2921604733 ps
CPU time 84.18 seconds
Started Aug 18 05:33:21 PM PDT 24
Finished Aug 18 05:34:46 PM PDT 24
Peak memory 217296 kb
Host smart-9d7b5cde-1d12-4951-ad73-45b9b4f140ba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1094944640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.1094944640
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.435692513
Short name T3605
Test name
Test status
Simulation time 239303324 ps
CPU time 1.01 seconds
Started Aug 18 05:33:16 PM PDT 24
Finished Aug 18 05:33:17 PM PDT 24
Peak memory 207464 kb
Host smart-e6c21e19-7320-4758-be37-6408d38e0984
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=435692513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.435692513
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3200636154
Short name T3402
Test name
Test status
Simulation time 197390771 ps
CPU time 0.95 seconds
Started Aug 18 05:33:22 PM PDT 24
Finished Aug 18 05:33:23 PM PDT 24
Peak memory 207500 kb
Host smart-935b8503-300e-46c0-a729-7afff9aeaa35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32006
36154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3200636154
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_non_iso_usb_traffic.2765917696
Short name T1180
Test name
Test status
Simulation time 3007585300 ps
CPU time 29.26 seconds
Started Aug 18 05:33:36 PM PDT 24
Finished Aug 18 05:34:06 PM PDT 24
Peak memory 215916 kb
Host smart-1cfa42a9-652b-4f26-b913-31f269752e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27659
17696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_non_iso_usb_traffic.2765917696
Directory /workspace/10.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1181746109
Short name T734
Test name
Test status
Simulation time 2058917957 ps
CPU time 61.69 seconds
Started Aug 18 05:33:39 PM PDT 24
Finished Aug 18 05:34:41 PM PDT 24
Peak memory 217384 kb
Host smart-9aff9fac-7894-41fb-91be-07fe97e77f1f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1181746109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1181746109
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.888092676
Short name T3093
Test name
Test status
Simulation time 3509706976 ps
CPU time 26.83 seconds
Started Aug 18 05:33:35 PM PDT 24
Finished Aug 18 05:34:02 PM PDT 24
Peak memory 217676 kb
Host smart-79fa0d51-8155-4b01-8ac3-26f77c3d0a27
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=888092676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.888092676
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.2971480928
Short name T2335
Test name
Test status
Simulation time 162029572 ps
CPU time 0.92 seconds
Started Aug 18 05:33:23 PM PDT 24
Finished Aug 18 05:33:24 PM PDT 24
Peak memory 207472 kb
Host smart-4d4d5290-1508-4b94-ad53-0545c5cde8b4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2971480928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.2971480928
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2315304539
Short name T2330
Test name
Test status
Simulation time 149082143 ps
CPU time 0.84 seconds
Started Aug 18 05:33:26 PM PDT 24
Finished Aug 18 05:33:27 PM PDT 24
Peak memory 207412 kb
Host smart-854fcced-37be-4755-a390-211762a4f805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23153
04539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2315304539
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2759701014
Short name T1913
Test name
Test status
Simulation time 164684751 ps
CPU time 0.86 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 207432 kb
Host smart-1f365b9f-3020-4ff8-ad1a-7fea9a7bcc13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27597
01014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2759701014
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2531922552
Short name T805
Test name
Test status
Simulation time 166470771 ps
CPU time 0.85 seconds
Started Aug 18 05:33:51 PM PDT 24
Finished Aug 18 05:33:52 PM PDT 24
Peak memory 207480 kb
Host smart-e0e0b504-6b7a-4f61-94ac-4b638c83fb50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25319
22552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2531922552
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2404776944
Short name T3163
Test name
Test status
Simulation time 163059362 ps
CPU time 0.93 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207568 kb
Host smart-4988c14d-a5f1-4c4e-8f11-8e973e258a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24047
76944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2404776944
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1397181693
Short name T3406
Test name
Test status
Simulation time 158586457 ps
CPU time 0.9 seconds
Started Aug 18 05:33:38 PM PDT 24
Finished Aug 18 05:33:39 PM PDT 24
Peak memory 207496 kb
Host smart-535090e6-578a-43ab-884f-2723b311b334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13971
81693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1397181693
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.2291518280
Short name T1450
Test name
Test status
Simulation time 191265138 ps
CPU time 0.94 seconds
Started Aug 18 05:33:35 PM PDT 24
Finished Aug 18 05:33:36 PM PDT 24
Peak memory 207568 kb
Host smart-2d01ccf1-25fd-4926-b847-d769d5823fa6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2291518280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.2291518280
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1559501215
Short name T2096
Test name
Test status
Simulation time 143801849 ps
CPU time 0.83 seconds
Started Aug 18 05:33:34 PM PDT 24
Finished Aug 18 05:33:35 PM PDT 24
Peak memory 207468 kb
Host smart-f9d96191-49c6-4f63-bea1-f0a441d4047b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15595
01215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1559501215
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2513266329
Short name T31
Test name
Test status
Simulation time 48551357 ps
CPU time 0.7 seconds
Started Aug 18 05:33:31 PM PDT 24
Finished Aug 18 05:33:32 PM PDT 24
Peak memory 207532 kb
Host smart-41eabaf9-b477-4f38-a9d1-c834ce5036da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25132
66329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2513266329
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.220076865
Short name T2654
Test name
Test status
Simulation time 22102065259 ps
CPU time 61 seconds
Started Aug 18 05:33:34 PM PDT 24
Finished Aug 18 05:34:36 PM PDT 24
Peak memory 215944 kb
Host smart-452ce6de-bdb3-4306-b787-fb4ec8072026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22007
6865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.220076865
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2691867034
Short name T2554
Test name
Test status
Simulation time 223141911 ps
CPU time 0.95 seconds
Started Aug 18 05:33:23 PM PDT 24
Finished Aug 18 05:33:24 PM PDT 24
Peak memory 207596 kb
Host smart-6e02c319-1294-4efb-9286-730e17ab6a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26918
67034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2691867034
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1064082830
Short name T2975
Test name
Test status
Simulation time 224374163 ps
CPU time 0.98 seconds
Started Aug 18 05:33:26 PM PDT 24
Finished Aug 18 05:33:27 PM PDT 24
Peak memory 207468 kb
Host smart-516257a6-c7cd-44d4-80c1-321f1245e9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10640
82830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1064082830
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.801856760
Short name T1717
Test name
Test status
Simulation time 216304748 ps
CPU time 0.95 seconds
Started Aug 18 05:33:39 PM PDT 24
Finished Aug 18 05:33:40 PM PDT 24
Peak memory 207468 kb
Host smart-cda08902-b626-4b35-bf96-137bfa94eafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80185
6760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.801856760
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.1011937041
Short name T3593
Test name
Test status
Simulation time 187739046 ps
CPU time 0.97 seconds
Started Aug 18 05:33:28 PM PDT 24
Finished Aug 18 05:33:29 PM PDT 24
Peak memory 207496 kb
Host smart-a037db05-765e-4138-a9c8-1ce7d0abbe61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10119
37041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.1011937041
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_resume_link_active.3066894786
Short name T2656
Test name
Test status
Simulation time 20161473912 ps
CPU time 27.62 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:34:08 PM PDT 24
Peak memory 207604 kb
Host smart-f27b156b-7919-4060-b219-743e1ccb220f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30668
94786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_resume_link_active.3066894786
Directory /workspace/10.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.390144478
Short name T1064
Test name
Test status
Simulation time 138177129 ps
CPU time 0.82 seconds
Started Aug 18 05:33:22 PM PDT 24
Finished Aug 18 05:33:23 PM PDT 24
Peak memory 207472 kb
Host smart-ebd25dae-d087-4100-985c-453f77e9e89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39014
4478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.390144478
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_rx_full.2152930508
Short name T2199
Test name
Test status
Simulation time 329301556 ps
CPU time 1.15 seconds
Started Aug 18 05:33:36 PM PDT 24
Finished Aug 18 05:33:37 PM PDT 24
Peak memory 207412 kb
Host smart-aa66a80d-4c8e-455d-95c5-c2060fcb3088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21529
30508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_full.2152930508
Directory /workspace/10.usbdev_rx_full/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.158904444
Short name T2273
Test name
Test status
Simulation time 154859902 ps
CPU time 0.83 seconds
Started Aug 18 05:33:38 PM PDT 24
Finished Aug 18 05:33:38 PM PDT 24
Peak memory 207476 kb
Host smart-daa57763-8f79-496c-a844-e3dea52a1e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15890
4444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.158904444
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.217536122
Short name T2998
Test name
Test status
Simulation time 156097061 ps
CPU time 0.84 seconds
Started Aug 18 05:33:36 PM PDT 24
Finished Aug 18 05:33:37 PM PDT 24
Peak memory 207540 kb
Host smart-04025dad-7c63-43ee-bd2e-eedf47544cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21753
6122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.217536122
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2583566448
Short name T1123
Test name
Test status
Simulation time 216733068 ps
CPU time 1.02 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:42 PM PDT 24
Peak memory 207364 kb
Host smart-9236ae2f-2a4d-4e04-beff-6af144a41d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25835
66448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2583566448
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2430241570
Short name T621
Test name
Test status
Simulation time 1691500269 ps
CPU time 12.98 seconds
Started Aug 18 05:33:26 PM PDT 24
Finished Aug 18 05:33:39 PM PDT 24
Peak memory 207724 kb
Host smart-e2804f6d-20e1-45fb-a154-0526e40e5fa1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2430241570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2430241570
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3261749529
Short name T1083
Test name
Test status
Simulation time 156190066 ps
CPU time 0.84 seconds
Started Aug 18 05:33:38 PM PDT 24
Finished Aug 18 05:33:39 PM PDT 24
Peak memory 207420 kb
Host smart-61d6efbd-c4ac-444e-9fb5-afd6cf202edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32617
49529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3261749529
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2510436517
Short name T3145
Test name
Test status
Simulation time 196331456 ps
CPU time 0.9 seconds
Started Aug 18 05:33:38 PM PDT 24
Finished Aug 18 05:33:39 PM PDT 24
Peak memory 207568 kb
Host smart-822cddb0-5702-4344-99ed-68f6503e01a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25104
36517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2510436517
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.644986225
Short name T1547
Test name
Test status
Simulation time 877232850 ps
CPU time 2.45 seconds
Started Aug 18 05:33:32 PM PDT 24
Finished Aug 18 05:33:34 PM PDT 24
Peak memory 207692 kb
Host smart-391e5cf7-68a9-4bc7-97a4-f05f99ee7551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64498
6225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.644986225
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.2649682624
Short name T1317
Test name
Test status
Simulation time 2273896948 ps
CPU time 17.64 seconds
Started Aug 18 05:33:50 PM PDT 24
Finished Aug 18 05:34:08 PM PDT 24
Peak memory 217572 kb
Host smart-750c95a7-45ac-4be4-8743-7d505ede33ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26496
82624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.2649682624
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.856451248
Short name T2045
Test name
Test status
Simulation time 2222399396 ps
CPU time 14.72 seconds
Started Aug 18 05:33:16 PM PDT 24
Finished Aug 18 05:33:30 PM PDT 24
Peak memory 207760 kb
Host smart-c7f593bc-2b1b-4bb5-8b13-d59a33974bfb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856451248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_host
_handshake.856451248
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_tx_rx_disruption.3312708357
Short name T2849
Test name
Test status
Simulation time 561620461 ps
CPU time 1.75 seconds
Started Aug 18 05:33:37 PM PDT 24
Finished Aug 18 05:33:39 PM PDT 24
Peak memory 207544 kb
Host smart-ec6ce544-3cb2-4d84-8208-83e362d097ab
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312708357 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.usbdev_tx_rx_disruption.3312708357
Directory /workspace/10.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/100.usbdev_endpoint_types.1570993903
Short name T369
Test name
Test status
Simulation time 440794040 ps
CPU time 1.34 seconds
Started Aug 18 05:39:33 PM PDT 24
Finished Aug 18 05:39:34 PM PDT 24
Peak memory 207552 kb
Host smart-f56a4dfa-5850-49af-8aa3-e19787ebb8bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1570993903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_endpoint_types.1570993903
Directory /workspace/100.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/100.usbdev_tx_rx_disruption.2864855820
Short name T1595
Test name
Test status
Simulation time 596087434 ps
CPU time 1.84 seconds
Started Aug 18 05:39:06 PM PDT 24
Finished Aug 18 05:39:08 PM PDT 24
Peak memory 207476 kb
Host smart-4d906a17-489c-47ad-b48a-eb33699d700c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864855820 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.usbdev_tx_rx_disruption.2864855820
Directory /workspace/100.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/101.usbdev_tx_rx_disruption.3407568993
Short name T2755
Test name
Test status
Simulation time 532326959 ps
CPU time 1.58 seconds
Started Aug 18 05:39:08 PM PDT 24
Finished Aug 18 05:39:10 PM PDT 24
Peak memory 207552 kb
Host smart-fbbbb38d-47bc-4cbb-86b2-874a365705a6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407568993 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 101.usbdev_tx_rx_disruption.3407568993
Directory /workspace/101.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/102.usbdev_endpoint_types.1171380157
Short name T3363
Test name
Test status
Simulation time 278405159 ps
CPU time 1.06 seconds
Started Aug 18 05:39:07 PM PDT 24
Finished Aug 18 05:39:08 PM PDT 24
Peak memory 207492 kb
Host smart-0c68d931-f30e-4748-bad2-ccd2c4cddde3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1171380157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.1171380157
Directory /workspace/102.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/102.usbdev_tx_rx_disruption.3886784352
Short name T1870
Test name
Test status
Simulation time 530431342 ps
CPU time 1.67 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207732 kb
Host smart-45897516-8c23-4c48-8f08-42cbbbf2934d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886784352 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.usbdev_tx_rx_disruption.3886784352
Directory /workspace/102.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/103.usbdev_endpoint_types.1400509718
Short name T2787
Test name
Test status
Simulation time 383729355 ps
CPU time 1.24 seconds
Started Aug 18 05:38:57 PM PDT 24
Finished Aug 18 05:38:59 PM PDT 24
Peak memory 207508 kb
Host smart-7859bad6-1492-4ee9-9ff9-65df7b5ec1d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1400509718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_endpoint_types.1400509718
Directory /workspace/103.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/103.usbdev_tx_rx_disruption.1145673509
Short name T1295
Test name
Test status
Simulation time 546740141 ps
CPU time 1.53 seconds
Started Aug 18 05:39:16 PM PDT 24
Finished Aug 18 05:39:18 PM PDT 24
Peak memory 207552 kb
Host smart-7f04e8e5-5e97-416f-85ee-03ac74c60339
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145673509 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.usbdev_tx_rx_disruption.1145673509
Directory /workspace/103.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/104.usbdev_endpoint_types.1399721631
Short name T498
Test name
Test status
Simulation time 299895880 ps
CPU time 1.21 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207544 kb
Host smart-be05512f-8569-4212-b411-0cd72cdc319c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1399721631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_endpoint_types.1399721631
Directory /workspace/104.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/104.usbdev_tx_rx_disruption.2311265574
Short name T2946
Test name
Test status
Simulation time 621891600 ps
CPU time 1.74 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:38:57 PM PDT 24
Peak memory 207480 kb
Host smart-7f0d66cf-6ac7-4b14-a75e-096156134312
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311265574 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.usbdev_tx_rx_disruption.2311265574
Directory /workspace/104.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/105.usbdev_endpoint_types.3255048206
Short name T1207
Test name
Test status
Simulation time 255463269 ps
CPU time 0.99 seconds
Started Aug 18 05:39:01 PM PDT 24
Finished Aug 18 05:39:03 PM PDT 24
Peak memory 207460 kb
Host smart-48e2dc5b-d76d-4832-a84d-cacddf63e2b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3255048206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_endpoint_types.3255048206
Directory /workspace/105.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/105.usbdev_tx_rx_disruption.500143630
Short name T2835
Test name
Test status
Simulation time 456082638 ps
CPU time 1.59 seconds
Started Aug 18 05:39:06 PM PDT 24
Finished Aug 18 05:39:08 PM PDT 24
Peak memory 207584 kb
Host smart-8a2fb7aa-26ab-4143-9ac2-1d29181127b7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500143630 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 105.usbdev_tx_rx_disruption.500143630
Directory /workspace/105.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/106.usbdev_endpoint_types.4233483973
Short name T2910
Test name
Test status
Simulation time 223371786 ps
CPU time 1.08 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207464 kb
Host smart-b624a2b1-db74-43af-9eaa-aeed30a56a78
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4233483973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_endpoint_types.4233483973
Directory /workspace/106.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/106.usbdev_tx_rx_disruption.3256724812
Short name T2533
Test name
Test status
Simulation time 621795318 ps
CPU time 1.85 seconds
Started Aug 18 05:39:04 PM PDT 24
Finished Aug 18 05:39:06 PM PDT 24
Peak memory 207500 kb
Host smart-58207cca-a8a6-4802-8d77-96cb0d9a0570
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256724812 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 106.usbdev_tx_rx_disruption.3256724812
Directory /workspace/106.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/107.usbdev_endpoint_types.2247136395
Short name T3570
Test name
Test status
Simulation time 180142375 ps
CPU time 0.92 seconds
Started Aug 18 05:39:19 PM PDT 24
Finished Aug 18 05:39:20 PM PDT 24
Peak memory 207548 kb
Host smart-40afbd32-3ba2-47c1-baf7-447bfaa17f8f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2247136395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_endpoint_types.2247136395
Directory /workspace/107.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/107.usbdev_tx_rx_disruption.4264331973
Short name T3031
Test name
Test status
Simulation time 468440310 ps
CPU time 1.45 seconds
Started Aug 18 05:39:15 PM PDT 24
Finished Aug 18 05:39:17 PM PDT 24
Peak memory 207560 kb
Host smart-b744e003-99df-42a1-8859-b9d4ef893aff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264331973 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 107.usbdev_tx_rx_disruption.4264331973
Directory /workspace/107.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/109.usbdev_endpoint_types.2255539961
Short name T401
Test name
Test status
Simulation time 515541708 ps
CPU time 1.53 seconds
Started Aug 18 05:39:25 PM PDT 24
Finished Aug 18 05:39:26 PM PDT 24
Peak memory 207552 kb
Host smart-78703c52-950a-412e-b9bf-60bb51fcd894
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2255539961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_endpoint_types.2255539961
Directory /workspace/109.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/109.usbdev_tx_rx_disruption.1477862925
Short name T3562
Test name
Test status
Simulation time 562561412 ps
CPU time 1.67 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207472 kb
Host smart-5ad096f6-27d5-4e3d-a7b0-9912194d66c7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477862925 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.usbdev_tx_rx_disruption.1477862925
Directory /workspace/109.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.460095753
Short name T2661
Test name
Test status
Simulation time 83361994 ps
CPU time 0.77 seconds
Started Aug 18 05:33:39 PM PDT 24
Finished Aug 18 05:33:40 PM PDT 24
Peak memory 207444 kb
Host smart-d891dc92-2291-4284-a835-03669ad39aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=460095753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.460095753
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.174289245
Short name T94
Test name
Test status
Simulation time 9946846081 ps
CPU time 12.95 seconds
Started Aug 18 05:33:24 PM PDT 24
Finished Aug 18 05:33:37 PM PDT 24
Peak memory 207836 kb
Host smart-fb77f921-8112-48c3-9b5d-5c7f035aa6bb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174289245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_ao
n_wake_disconnect.174289245
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1365546123
Short name T2934
Test name
Test status
Simulation time 26050279659 ps
CPU time 34.79 seconds
Started Aug 18 05:33:33 PM PDT 24
Finished Aug 18 05:34:08 PM PDT 24
Peak memory 216012 kb
Host smart-47e3849a-ab7f-49da-a62b-2a58e8bab267
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365546123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.1365546123
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.319274988
Short name T1760
Test name
Test status
Simulation time 152948230 ps
CPU time 0.85 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:42 PM PDT 24
Peak memory 207452 kb
Host smart-0c1148f5-7735-4802-9a3d-61477a44c787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31927
4988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.319274988
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.1025685387
Short name T1044
Test name
Test status
Simulation time 231543618 ps
CPU time 0.96 seconds
Started Aug 18 05:33:28 PM PDT 24
Finished Aug 18 05:33:29 PM PDT 24
Peak memory 207568 kb
Host smart-3f947a2b-d11d-4b1d-9289-c22924d6a781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10256
85387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.1025685387
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.1183746534
Short name T3540
Test name
Test status
Simulation time 502964264 ps
CPU time 1.72 seconds
Started Aug 18 05:33:29 PM PDT 24
Finished Aug 18 05:33:31 PM PDT 24
Peak memory 207536 kb
Host smart-7a166a80-75fe-4601-8d59-424f8c9d912e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11837
46534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.1183746534
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2317523389
Short name T649
Test name
Test status
Simulation time 367464019 ps
CPU time 1.24 seconds
Started Aug 18 05:33:27 PM PDT 24
Finished Aug 18 05:33:29 PM PDT 24
Peak memory 207480 kb
Host smart-951ed44d-7906-4449-acd2-2abd8b465762
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2317523389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2317523389
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.1640947552
Short name T1928
Test name
Test status
Simulation time 45684283394 ps
CPU time 86.06 seconds
Started Aug 18 05:33:34 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 207740 kb
Host smart-18b749d2-e5f2-429c-94dc-f040ba4d56b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16409
47552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.1640947552
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.2792067360
Short name T3272
Test name
Test status
Simulation time 346154168 ps
CPU time 4.3 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:45 PM PDT 24
Peak memory 207708 kb
Host smart-0d7bced0-44e7-4433-85d0-6e8fdb139a86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792067360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.2792067360
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.4280199687
Short name T1777
Test name
Test status
Simulation time 693670568 ps
CPU time 1.85 seconds
Started Aug 18 05:33:25 PM PDT 24
Finished Aug 18 05:33:27 PM PDT 24
Peak memory 207536 kb
Host smart-b8c52e1b-74d3-476c-b326-ac41e599c0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42801
99687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.4280199687
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.3972381625
Short name T3268
Test name
Test status
Simulation time 134402407 ps
CPU time 0.8 seconds
Started Aug 18 05:33:30 PM PDT 24
Finished Aug 18 05:33:31 PM PDT 24
Peak memory 207508 kb
Host smart-ddd507d1-97c2-49fc-aa52-d1785129f260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39723
81625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.3972381625
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1047858578
Short name T1861
Test name
Test status
Simulation time 31435251 ps
CPU time 0.75 seconds
Started Aug 18 05:33:36 PM PDT 24
Finished Aug 18 05:33:37 PM PDT 24
Peak memory 207360 kb
Host smart-dfde3ffe-7676-493e-b711-ced7b2b3043d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10478
58578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1047858578
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.3254941145
Short name T2026
Test name
Test status
Simulation time 858984148 ps
CPU time 2.15 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:33:45 PM PDT 24
Peak memory 207768 kb
Host smart-9b7f6066-777f-4208-9eb9-6c0075d49df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32549
41145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3254941145
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_types.3453013063
Short name T2791
Test name
Test status
Simulation time 159637549 ps
CPU time 0.88 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:33:44 PM PDT 24
Peak memory 207496 kb
Host smart-dfd9e3cf-de8d-4502-b0df-73b4caa4ae6d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3453013063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_types.3453013063
Directory /workspace/11.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.2491097999
Short name T2155
Test name
Test status
Simulation time 165997167 ps
CPU time 1.5 seconds
Started Aug 18 05:33:38 PM PDT 24
Finished Aug 18 05:33:40 PM PDT 24
Peak memory 207568 kb
Host smart-04a02599-5311-4c9d-a86b-741c183d49b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24910
97999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.2491097999
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.450058733
Short name T2640
Test name
Test status
Simulation time 199692945 ps
CPU time 1.01 seconds
Started Aug 18 05:33:38 PM PDT 24
Finished Aug 18 05:33:39 PM PDT 24
Peak memory 215856 kb
Host smart-5d1f0055-d136-4f1c-8be7-69ccbfe49ecb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=450058733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.450058733
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1024693498
Short name T1283
Test name
Test status
Simulation time 145846587 ps
CPU time 0.81 seconds
Started Aug 18 05:33:29 PM PDT 24
Finished Aug 18 05:33:30 PM PDT 24
Peak memory 207472 kb
Host smart-c70387ce-e1fa-4df3-88a1-50f3aad2ab24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10246
93498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1024693498
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3060706885
Short name T625
Test name
Test status
Simulation time 191131649 ps
CPU time 0.92 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 207464 kb
Host smart-adbdd715-6de7-424c-8e55-376d8ef61848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30607
06885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3060706885
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.346609689
Short name T3401
Test name
Test status
Simulation time 3451446749 ps
CPU time 97.89 seconds
Started Aug 18 05:33:34 PM PDT 24
Finished Aug 18 05:35:13 PM PDT 24
Peak memory 218464 kb
Host smart-eceb9be5-91ba-446e-b4e8-066496fc7b97
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=346609689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.346609689
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.770024117
Short name T622
Test name
Test status
Simulation time 5512041334 ps
CPU time 40.06 seconds
Started Aug 18 05:33:44 PM PDT 24
Finished Aug 18 05:34:25 PM PDT 24
Peak memory 207756 kb
Host smart-50d8a171-419e-4c02-8317-e37ff446519b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=770024117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.770024117
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.3532782341
Short name T2046
Test name
Test status
Simulation time 201718609 ps
CPU time 0.96 seconds
Started Aug 18 05:33:35 PM PDT 24
Finished Aug 18 05:33:36 PM PDT 24
Peak memory 207580 kb
Host smart-7f75d065-e34f-4df3-9e7d-d1cf29f7325d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35327
82341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.3532782341
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.1848914923
Short name T1825
Test name
Test status
Simulation time 26379727915 ps
CPU time 46.32 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:34:27 PM PDT 24
Peak memory 207800 kb
Host smart-82552cf1-0ca4-4030-b207-44207f826646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18489
14923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.1848914923
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.883289181
Short name T2172
Test name
Test status
Simulation time 6206557546 ps
CPU time 8.16 seconds
Started Aug 18 05:33:38 PM PDT 24
Finished Aug 18 05:33:46 PM PDT 24
Peak memory 216124 kb
Host smart-e3343756-bde5-4263-89a1-d7f198e39368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88328
9181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.883289181
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.4106492823
Short name T939
Test name
Test status
Simulation time 4880185843 ps
CPU time 49.44 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:34:31 PM PDT 24
Peak memory 215940 kb
Host smart-ad50b126-9092-4059-ac41-c3766f984669
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4106492823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.4106492823
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.4014899044
Short name T1711
Test name
Test status
Simulation time 2818442545 ps
CPU time 21.12 seconds
Started Aug 18 05:33:46 PM PDT 24
Finished Aug 18 05:34:08 PM PDT 24
Peak memory 215944 kb
Host smart-bc0a90b2-3d4d-4b51-91d7-dacd8818bee0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4014899044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.4014899044
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.637126888
Short name T1510
Test name
Test status
Simulation time 243902583 ps
CPU time 1.03 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207468 kb
Host smart-d5c0ddb4-1fef-4ef8-a191-34ae80f81bf7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=637126888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.637126888
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2059716099
Short name T2194
Test name
Test status
Simulation time 194649415 ps
CPU time 0.93 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 207504 kb
Host smart-a587ae91-becd-4ede-9f6b-566c0198e2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20597
16099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2059716099
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_non_iso_usb_traffic.176032471
Short name T1814
Test name
Test status
Simulation time 3270836011 ps
CPU time 33.09 seconds
Started Aug 18 05:33:39 PM PDT 24
Finished Aug 18 05:34:12 PM PDT 24
Peak memory 217940 kb
Host smart-c3937575-6840-43bb-8044-feb1bfa74bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17603
2471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_non_iso_usb_traffic.176032471
Directory /workspace/11.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.3631770073
Short name T1224
Test name
Test status
Simulation time 2632353267 ps
CPU time 74.18 seconds
Started Aug 18 05:33:50 PM PDT 24
Finished Aug 18 05:35:04 PM PDT 24
Peak memory 218104 kb
Host smart-d6c37499-f5f1-4c59-9a2b-5f183bf4ed5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3631770073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.3631770073
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.170850900
Short name T783
Test name
Test status
Simulation time 2957574195 ps
CPU time 78.69 seconds
Started Aug 18 05:33:38 PM PDT 24
Finished Aug 18 05:34:57 PM PDT 24
Peak memory 224144 kb
Host smart-1b8604ca-2fd7-4e4c-8634-17061c9c6350
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=170850900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.170850900
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.3653942175
Short name T3280
Test name
Test status
Simulation time 169051184 ps
CPU time 0.86 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 207452 kb
Host smart-6b2171af-0ecb-4ae1-8161-0453c14ec3a3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3653942175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.3653942175
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3496679238
Short name T578
Test name
Test status
Simulation time 144769642 ps
CPU time 0.84 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:33:44 PM PDT 24
Peak memory 207492 kb
Host smart-217fedec-ea0b-4f64-bf57-f1a631ac3928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34966
79238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3496679238
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.452308234
Short name T1774
Test name
Test status
Simulation time 212473510 ps
CPU time 0.91 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207456 kb
Host smart-4db5e931-b01b-4ccb-993e-0a5968f9169b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45230
8234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.452308234
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.724594401
Short name T3632
Test name
Test status
Simulation time 205818543 ps
CPU time 0.91 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 207492 kb
Host smart-dbc184ae-b97e-406d-a83d-dfcaadc19048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72459
4401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.724594401
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1989587884
Short name T3174
Test name
Test status
Simulation time 181166774 ps
CPU time 0.88 seconds
Started Aug 18 05:33:56 PM PDT 24
Finished Aug 18 05:33:57 PM PDT 24
Peak memory 207532 kb
Host smart-d59abf75-8cc0-4cc5-9a95-d6c7f8eaef9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19895
87884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1989587884
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3475187441
Short name T1601
Test name
Test status
Simulation time 163736052 ps
CPU time 0.87 seconds
Started Aug 18 05:33:35 PM PDT 24
Finished Aug 18 05:33:36 PM PDT 24
Peak memory 207448 kb
Host smart-2318230c-0131-47fd-b323-ef1a5c2e5d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34751
87441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3475187441
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.479538410
Short name T810
Test name
Test status
Simulation time 255084506 ps
CPU time 1.11 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207580 kb
Host smart-56f55739-3902-401d-9c6e-9ba0bef6b423
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=479538410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.479538410
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2481558342
Short name T2907
Test name
Test status
Simulation time 147157984 ps
CPU time 0.85 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:42 PM PDT 24
Peak memory 207448 kb
Host smart-ee4d160d-a90b-4688-9ebf-75dd94b489cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24815
58342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2481558342
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1561061597
Short name T3395
Test name
Test status
Simulation time 73943917 ps
CPU time 0.72 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 207532 kb
Host smart-2ec538ce-26ab-42e3-b2f9-64262c1a5915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15610
61597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1561061597
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3679604684
Short name T1284
Test name
Test status
Simulation time 20004108976 ps
CPU time 55.27 seconds
Started Aug 18 05:33:34 PM PDT 24
Finished Aug 18 05:34:30 PM PDT 24
Peak memory 215956 kb
Host smart-96421b3d-949c-45e9-a1be-06de2b1c7b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36796
04684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3679604684
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3856961429
Short name T3258
Test name
Test status
Simulation time 178569438 ps
CPU time 0.9 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207564 kb
Host smart-0030a9ed-bfd3-403f-8fcb-3dc32375423a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38569
61429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3856961429
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2176235899
Short name T2103
Test name
Test status
Simulation time 239784518 ps
CPU time 0.98 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207480 kb
Host smart-60b5d8ec-6024-46f9-ad8b-aee6c9dfa398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21762
35899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2176235899
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.4288464285
Short name T605
Test name
Test status
Simulation time 171793642 ps
CPU time 0.94 seconds
Started Aug 18 05:33:39 PM PDT 24
Finished Aug 18 05:33:40 PM PDT 24
Peak memory 207456 kb
Host smart-05c7540f-d5c8-4b16-b298-9a3024e0adf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42884
64285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.4288464285
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.3945786350
Short name T2763
Test name
Test status
Simulation time 208870044 ps
CPU time 0.89 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:42 PM PDT 24
Peak memory 207504 kb
Host smart-c5cbbf08-0714-46b3-9bd9-1e636de9a5fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39457
86350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.3945786350
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_resume_link_active.2129777641
Short name T2327
Test name
Test status
Simulation time 20210758570 ps
CPU time 25.74 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:34:09 PM PDT 24
Peak memory 207572 kb
Host smart-c629635d-28f0-454d-9671-35adb255f625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21297
77641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_resume_link_active.2129777641
Directory /workspace/11.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.3973547921
Short name T1466
Test name
Test status
Simulation time 167781333 ps
CPU time 0.83 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:42 PM PDT 24
Peak memory 207456 kb
Host smart-ee0055a5-ed9d-42ad-8257-1adb4d3a1765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39735
47921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.3973547921
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_rx_full.1594409782
Short name T341
Test name
Test status
Simulation time 256084569 ps
CPU time 1.11 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 207460 kb
Host smart-07219440-2da5-46f1-ab11-c53b71800d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15944
09782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_full.1594409782
Directory /workspace/11.usbdev_rx_full/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1209589870
Short name T256
Test name
Test status
Simulation time 166465815 ps
CPU time 0.85 seconds
Started Aug 18 05:33:45 PM PDT 24
Finished Aug 18 05:33:46 PM PDT 24
Peak memory 207524 kb
Host smart-fd2fc084-e404-465a-814e-843d21973705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12095
89870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1209589870
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2845090461
Short name T1016
Test name
Test status
Simulation time 160239576 ps
CPU time 0.86 seconds
Started Aug 18 05:33:51 PM PDT 24
Finished Aug 18 05:33:52 PM PDT 24
Peak memory 207440 kb
Host smart-20618c04-880e-4e65-a95d-db52f550ef7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28450
90461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2845090461
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2159514197
Short name T1039
Test name
Test status
Simulation time 244097054 ps
CPU time 1.1 seconds
Started Aug 18 05:33:45 PM PDT 24
Finished Aug 18 05:33:46 PM PDT 24
Peak memory 207488 kb
Host smart-f28cb286-f068-4238-9c92-61c015a62eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21595
14197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2159514197
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.2728594816
Short name T975
Test name
Test status
Simulation time 3040181277 ps
CPU time 30.19 seconds
Started Aug 18 05:33:44 PM PDT 24
Finished Aug 18 05:34:15 PM PDT 24
Peak memory 215924 kb
Host smart-e2aefc4f-6f16-47ba-8495-55d008571711
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2728594816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.2728594816
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3820360432
Short name T2274
Test name
Test status
Simulation time 219415394 ps
CPU time 0.9 seconds
Started Aug 18 05:33:59 PM PDT 24
Finished Aug 18 05:34:00 PM PDT 24
Peak memory 207500 kb
Host smart-88f8e3c7-a18e-4db4-81f8-acc690b2a218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38203
60432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3820360432
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.938602293
Short name T3135
Test name
Test status
Simulation time 182760082 ps
CPU time 0.96 seconds
Started Aug 18 05:33:39 PM PDT 24
Finished Aug 18 05:33:40 PM PDT 24
Peak memory 207504 kb
Host smart-9b2c6e85-70e7-4349-8a1e-0f637c77fb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93860
2293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.938602293
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.1728154307
Short name T1746
Test name
Test status
Simulation time 311667451 ps
CPU time 1.15 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 207544 kb
Host smart-89518e75-bb8c-44f6-a847-b4bc854d251d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17281
54307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.1728154307
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1398736134
Short name T676
Test name
Test status
Simulation time 2691918898 ps
CPU time 26.06 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:34:08 PM PDT 24
Peak memory 224164 kb
Host smart-f5e3da6a-4549-421f-bd84-f336d96aa5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13987
36134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1398736134
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.2603254011
Short name T1109
Test name
Test status
Simulation time 1543012237 ps
CPU time 13.68 seconds
Started Aug 18 05:33:33 PM PDT 24
Finished Aug 18 05:33:47 PM PDT 24
Peak memory 207668 kb
Host smart-b4719d7f-40fc-4869-9566-81aea0960130
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603254011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.2603254011
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/11.usbdev_tx_rx_disruption.4224031856
Short name T2818
Test name
Test status
Simulation time 643591096 ps
CPU time 1.7 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207540 kb
Host smart-be511915-d834-4180-8f09-24834a87bed2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224031856 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.usbdev_tx_rx_disruption.4224031856
Directory /workspace/11.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/110.usbdev_tx_rx_disruption.2916551164
Short name T664
Test name
Test status
Simulation time 587634730 ps
CPU time 1.7 seconds
Started Aug 18 05:39:06 PM PDT 24
Finished Aug 18 05:39:08 PM PDT 24
Peak memory 207588 kb
Host smart-060b2ec6-e6aa-4259-880e-370ad84fe52d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916551164 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.usbdev_tx_rx_disruption.2916551164
Directory /workspace/110.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/111.usbdev_endpoint_types.3766872398
Short name T3623
Test name
Test status
Simulation time 618231756 ps
CPU time 1.68 seconds
Started Aug 18 05:38:58 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207508 kb
Host smart-b85d9b6e-7972-49aa-9824-eecfb1aa2bd2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3766872398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_endpoint_types.3766872398
Directory /workspace/111.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/111.usbdev_tx_rx_disruption.3172424649
Short name T1096
Test name
Test status
Simulation time 532879845 ps
CPU time 1.45 seconds
Started Aug 18 05:39:12 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207584 kb
Host smart-0c6d911d-3c5b-4cd3-91fd-03482b4149bb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172424649 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.usbdev_tx_rx_disruption.3172424649
Directory /workspace/111.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/112.usbdev_endpoint_types.1185882136
Short name T376
Test name
Test status
Simulation time 549613479 ps
CPU time 1.33 seconds
Started Aug 18 05:39:27 PM PDT 24
Finished Aug 18 05:39:28 PM PDT 24
Peak memory 207540 kb
Host smart-1cda14fb-30bd-4548-bfb1-892f5f4e4720
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1185882136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_endpoint_types.1185882136
Directory /workspace/112.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/112.usbdev_tx_rx_disruption.3169881692
Short name T1771
Test name
Test status
Simulation time 432404633 ps
CPU time 1.56 seconds
Started Aug 18 05:39:24 PM PDT 24
Finished Aug 18 05:39:31 PM PDT 24
Peak memory 207548 kb
Host smart-2f09d581-146f-49f6-9da9-8e1b54211147
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169881692 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 112.usbdev_tx_rx_disruption.3169881692
Directory /workspace/112.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/113.usbdev_endpoint_types.3854201611
Short name T3212
Test name
Test status
Simulation time 257865485 ps
CPU time 1.06 seconds
Started Aug 18 05:39:14 PM PDT 24
Finished Aug 18 05:39:15 PM PDT 24
Peak memory 207556 kb
Host smart-fd51bc4b-71c8-4abe-8431-f01a412e7c9b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3854201611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_endpoint_types.3854201611
Directory /workspace/113.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/113.usbdev_tx_rx_disruption.2349893630
Short name T3262
Test name
Test status
Simulation time 481116628 ps
CPU time 1.51 seconds
Started Aug 18 05:39:11 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207568 kb
Host smart-38eb0f5f-eb98-46a6-8f34-de18c48eee1e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349893630 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 113.usbdev_tx_rx_disruption.2349893630
Directory /workspace/113.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/114.usbdev_endpoint_types.1905224349
Short name T373
Test name
Test status
Simulation time 330304154 ps
CPU time 1.23 seconds
Started Aug 18 05:39:16 PM PDT 24
Finished Aug 18 05:39:17 PM PDT 24
Peak memory 207540 kb
Host smart-d1faa915-ca13-4ef6-bb1d-fadcef4762da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1905224349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_endpoint_types.1905224349
Directory /workspace/114.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/114.usbdev_tx_rx_disruption.251554511
Short name T224
Test name
Test status
Simulation time 575696668 ps
CPU time 1.64 seconds
Started Aug 18 05:39:32 PM PDT 24
Finished Aug 18 05:39:34 PM PDT 24
Peak memory 207580 kb
Host smart-d75646eb-fbc8-4a6b-9725-d99ab1b4ed95
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251554511 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 114.usbdev_tx_rx_disruption.251554511
Directory /workspace/114.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/115.usbdev_endpoint_types.380549452
Short name T3159
Test name
Test status
Simulation time 659321470 ps
CPU time 1.73 seconds
Started Aug 18 05:39:14 PM PDT 24
Finished Aug 18 05:39:16 PM PDT 24
Peak memory 207524 kb
Host smart-688ff0aa-eaab-4851-b130-798371cc361b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=380549452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_endpoint_types.380549452
Directory /workspace/115.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/115.usbdev_tx_rx_disruption.4003451482
Short name T1532
Test name
Test status
Simulation time 486908388 ps
CPU time 1.57 seconds
Started Aug 18 05:39:19 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207476 kb
Host smart-628ab2bc-7b8c-4d97-b8d6-aca6ec6d578a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003451482 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 115.usbdev_tx_rx_disruption.4003451482
Directory /workspace/115.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/116.usbdev_tx_rx_disruption.2321279199
Short name T1045
Test name
Test status
Simulation time 584715427 ps
CPU time 1.43 seconds
Started Aug 18 05:39:19 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207604 kb
Host smart-0cc17154-595d-47de-a078-104deb75a560
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321279199 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.usbdev_tx_rx_disruption.2321279199
Directory /workspace/116.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/117.usbdev_tx_rx_disruption.3795046245
Short name T2967
Test name
Test status
Simulation time 569452606 ps
CPU time 1.57 seconds
Started Aug 18 05:39:07 PM PDT 24
Finished Aug 18 05:39:08 PM PDT 24
Peak memory 207592 kb
Host smart-226296a8-ce34-416d-beb8-408eabe79d2e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795046245 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 117.usbdev_tx_rx_disruption.3795046245
Directory /workspace/117.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/118.usbdev_endpoint_types.1678942990
Short name T454
Test name
Test status
Simulation time 463754998 ps
CPU time 1.32 seconds
Started Aug 18 05:39:13 PM PDT 24
Finished Aug 18 05:39:14 PM PDT 24
Peak memory 207540 kb
Host smart-01ce2130-1d37-472c-b671-a2c4ee205f0e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1678942990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_endpoint_types.1678942990
Directory /workspace/118.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/118.usbdev_tx_rx_disruption.353105128
Short name T2042
Test name
Test status
Simulation time 589970194 ps
CPU time 1.64 seconds
Started Aug 18 05:39:06 PM PDT 24
Finished Aug 18 05:39:08 PM PDT 24
Peak memory 207560 kb
Host smart-2e131d86-ae59-4a6c-8623-30b879763741
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353105128 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 118.usbdev_tx_rx_disruption.353105128
Directory /workspace/118.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/119.usbdev_endpoint_types.650632234
Short name T487
Test name
Test status
Simulation time 374010359 ps
CPU time 1.18 seconds
Started Aug 18 05:39:16 PM PDT 24
Finished Aug 18 05:39:17 PM PDT 24
Peak memory 207536 kb
Host smart-968202ce-5477-44ec-a2bb-ab2cbabb8c64
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=650632234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_endpoint_types.650632234
Directory /workspace/119.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/119.usbdev_tx_rx_disruption.1303221444
Short name T1555
Test name
Test status
Simulation time 445720868 ps
CPU time 1.44 seconds
Started Aug 18 05:39:01 PM PDT 24
Finished Aug 18 05:39:03 PM PDT 24
Peak memory 207568 kb
Host smart-a3e8c051-bcb4-4cd2-b21e-e558d9fc41d1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303221444 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.usbdev_tx_rx_disruption.1303221444
Directory /workspace/119.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.1811536994
Short name T3594
Test name
Test status
Simulation time 56019440 ps
CPU time 0.76 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207380 kb
Host smart-7acff2fa-9e13-4ff6-8667-97a32bf25c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1811536994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.1811536994
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.1810278157
Short name T1561
Test name
Test status
Simulation time 5277837938 ps
CPU time 7.4 seconds
Started Aug 18 05:33:39 PM PDT 24
Finished Aug 18 05:33:47 PM PDT 24
Peak memory 216000 kb
Host smart-2d7e8934-58f3-48a9-8dad-bef97e4365a3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810278157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_disconnect.1810278157
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.4284842093
Short name T3173
Test name
Test status
Simulation time 14338548441 ps
CPU time 17.24 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:33:58 PM PDT 24
Peak memory 216000 kb
Host smart-6714d681-dbea-4218-beb8-f192c5a2bc99
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284842093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.4284842093
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.616342784
Short name T2011
Test name
Test status
Simulation time 30834688909 ps
CPU time 35.13 seconds
Started Aug 18 05:33:48 PM PDT 24
Finished Aug 18 05:34:24 PM PDT 24
Peak memory 207792 kb
Host smart-e3e7b6cc-b801-451a-a00a-652ddbcf1f5d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616342784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ao
n_wake_resume.616342784
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2293640699
Short name T742
Test name
Test status
Simulation time 175183239 ps
CPU time 0.87 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:42 PM PDT 24
Peak memory 207484 kb
Host smart-9c750194-8424-49bc-98e4-1823f5696f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22936
40699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2293640699
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.328609890
Short name T1677
Test name
Test status
Simulation time 159906585 ps
CPU time 0.85 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207452 kb
Host smart-ab5b808e-4209-4f39-9ca1-b5a3bd492b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32860
9890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.328609890
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.3235614704
Short name T896
Test name
Test status
Simulation time 187607466 ps
CPU time 0.93 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:42 PM PDT 24
Peak memory 207528 kb
Host smart-51e37b1f-1438-463e-b8ae-c1e36e704dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32356
14704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3235614704
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.1465548239
Short name T1558
Test name
Test status
Simulation time 661686225 ps
CPU time 5.14 seconds
Started Aug 18 05:33:33 PM PDT 24
Finished Aug 18 05:33:39 PM PDT 24
Peak memory 207704 kb
Host smart-89da12a8-2de9-4355-a1f4-c32ce3207ef7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465548239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.1465548239
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3131544904
Short name T2387
Test name
Test status
Simulation time 832750668 ps
CPU time 1.95 seconds
Started Aug 18 05:33:50 PM PDT 24
Finished Aug 18 05:33:52 PM PDT 24
Peak memory 207548 kb
Host smart-c5acc044-7f66-472c-88cb-f451bdcc208e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31315
44904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3131544904
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2000018587
Short name T3627
Test name
Test status
Simulation time 136324398 ps
CPU time 0.85 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 207496 kb
Host smart-3dbc68e0-8145-41af-8f27-cb9decf24ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20000
18587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2000018587
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.3401834302
Short name T3028
Test name
Test status
Simulation time 40852574 ps
CPU time 0.7 seconds
Started Aug 18 05:33:52 PM PDT 24
Finished Aug 18 05:33:53 PM PDT 24
Peak memory 207348 kb
Host smart-6a47c73c-2cae-4916-a5a4-a57c4d6be5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34018
34302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3401834302
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1403523157
Short name T2156
Test name
Test status
Simulation time 999024377 ps
CPU time 2.44 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:33:45 PM PDT 24
Peak memory 207728 kb
Host smart-68689832-62a6-4c54-8d48-9ece0487f1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14035
23157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1403523157
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3015238231
Short name T1244
Test name
Test status
Simulation time 216326553 ps
CPU time 1.18 seconds
Started Aug 18 05:33:54 PM PDT 24
Finished Aug 18 05:33:56 PM PDT 24
Peak memory 215880 kb
Host smart-8f026613-a873-409c-a5d2-c794a8842319
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3015238231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3015238231
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3816198025
Short name T3616
Test name
Test status
Simulation time 157370228 ps
CPU time 0.9 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207468 kb
Host smart-42ca4428-9346-4413-8bd6-b6ec3e32e1eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38161
98025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3816198025
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3755122515
Short name T3162
Test name
Test status
Simulation time 173780385 ps
CPU time 0.94 seconds
Started Aug 18 05:33:44 PM PDT 24
Finished Aug 18 05:33:45 PM PDT 24
Peak memory 207392 kb
Host smart-2a00ae8a-e548-4a3f-a8c3-e96853b2f6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37551
22515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3755122515
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.3247780413
Short name T1261
Test name
Test status
Simulation time 5357047864 ps
CPU time 51.68 seconds
Started Aug 18 05:33:47 PM PDT 24
Finished Aug 18 05:34:39 PM PDT 24
Peak memory 217932 kb
Host smart-6bfdf8f2-ae7e-4de4-8358-f54e461833ac
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3247780413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.3247780413
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.2029719093
Short name T1679
Test name
Test status
Simulation time 14693484862 ps
CPU time 104.72 seconds
Started Aug 18 05:33:37 PM PDT 24
Finished Aug 18 05:35:22 PM PDT 24
Peak memory 207804 kb
Host smart-65fb8e6c-08fb-4e59-955d-3525ed1cb693
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2029719093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.2029719093
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.1983757849
Short name T2412
Test name
Test status
Simulation time 189622984 ps
CPU time 0.96 seconds
Started Aug 18 05:33:44 PM PDT 24
Finished Aug 18 05:33:45 PM PDT 24
Peak memory 207548 kb
Host smart-9ae5e880-88ff-4855-96e6-eebba51fb548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19837
57849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.1983757849
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2367387420
Short name T1467
Test name
Test status
Simulation time 25879970428 ps
CPU time 42.5 seconds
Started Aug 18 05:33:44 PM PDT 24
Finished Aug 18 05:34:26 PM PDT 24
Peak memory 216136 kb
Host smart-6ecbed17-2863-455a-a0f7-6090bb7d3564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23673
87420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2367387420
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2793920657
Short name T2865
Test name
Test status
Simulation time 5608126266 ps
CPU time 7.1 seconds
Started Aug 18 05:33:55 PM PDT 24
Finished Aug 18 05:34:02 PM PDT 24
Peak memory 207796 kb
Host smart-638f5f3f-09d4-4333-b138-871e6d9f5904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27939
20657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2793920657
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.472679720
Short name T2413
Test name
Test status
Simulation time 2276379564 ps
CPU time 61.39 seconds
Started Aug 18 05:33:47 PM PDT 24
Finished Aug 18 05:34:49 PM PDT 24
Peak memory 215996 kb
Host smart-17146a42-a1ec-484e-86b8-f8c857029454
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=472679720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.472679720
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.2219052701
Short name T2542
Test name
Test status
Simulation time 3941624334 ps
CPU time 114.7 seconds
Started Aug 18 05:33:46 PM PDT 24
Finished Aug 18 05:35:41 PM PDT 24
Peak memory 217204 kb
Host smart-4f61d3e1-1378-4ebb-b5d5-113c00590f57
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2219052701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.2219052701
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.1120607924
Short name T2659
Test name
Test status
Simulation time 253372588 ps
CPU time 1.06 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207468 kb
Host smart-46a24b0e-16c0-41d8-b710-ef5090d21ea8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1120607924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.1120607924
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1562009508
Short name T3461
Test name
Test status
Simulation time 197843993 ps
CPU time 0.93 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:33:44 PM PDT 24
Peak memory 207500 kb
Host smart-e2c59ed2-f96a-454d-98a4-15b93e1bbf6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15620
09508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1562009508
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_non_iso_usb_traffic.2363620918
Short name T2507
Test name
Test status
Simulation time 2961794592 ps
CPU time 81.85 seconds
Started Aug 18 05:33:53 PM PDT 24
Finished Aug 18 05:35:15 PM PDT 24
Peak memory 217540 kb
Host smart-69e78100-0752-4c32-ac56-3d8ce2b41831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23636
20918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_non_iso_usb_traffic.2363620918
Directory /workspace/12.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.4082302647
Short name T2754
Test name
Test status
Simulation time 2519791586 ps
CPU time 68.55 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:34:52 PM PDT 24
Peak memory 224020 kb
Host smart-95d74e44-4d32-4de1-9463-c78b947d3f9e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4082302647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.4082302647
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.145553440
Short name T884
Test name
Test status
Simulation time 4261268916 ps
CPU time 34.13 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:34:16 PM PDT 24
Peak memory 217756 kb
Host smart-e9873e8f-4257-458d-ae9b-606577259e2f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=145553440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.145553440
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.661245511
Short name T2426
Test name
Test status
Simulation time 168392954 ps
CPU time 0.97 seconds
Started Aug 18 05:33:47 PM PDT 24
Finished Aug 18 05:33:48 PM PDT 24
Peak memory 207504 kb
Host smart-b367575c-6971-4d93-b1c6-497468f629c7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=661245511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.661245511
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.494365736
Short name T585
Test name
Test status
Simulation time 152059332 ps
CPU time 0.9 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207508 kb
Host smart-2fdc1d70-43bd-48cc-a35f-241688677222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49436
5736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.494365736
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.2342117022
Short name T2363
Test name
Test status
Simulation time 149604796 ps
CPU time 0.84 seconds
Started Aug 18 05:33:45 PM PDT 24
Finished Aug 18 05:33:46 PM PDT 24
Peak memory 207440 kb
Host smart-e4b20628-d0a3-4f06-b8b3-65a1b3615495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23421
17022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.2342117022
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1993340502
Short name T1656
Test name
Test status
Simulation time 175883425 ps
CPU time 0.97 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:42 PM PDT 24
Peak memory 207468 kb
Host smart-4989804f-1d69-40ef-bc91-70abb44f5a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19933
40502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1993340502
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1283936559
Short name T713
Test name
Test status
Simulation time 152166723 ps
CPU time 0.81 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207576 kb
Host smart-5803bd54-4156-4b2b-ba9c-d9176bf08d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12839
36559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1283936559
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1887422376
Short name T3236
Test name
Test status
Simulation time 152026312 ps
CPU time 0.85 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:42 PM PDT 24
Peak memory 207468 kb
Host smart-c8924cfb-4c5b-4844-bee1-83db9d401751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18874
22376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1887422376
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.1336941738
Short name T1098
Test name
Test status
Simulation time 223935690 ps
CPU time 1.01 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:34:06 PM PDT 24
Peak memory 207440 kb
Host smart-f204116d-553a-4301-ae30-f8d706896565
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1336941738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.1336941738
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.982702305
Short name T2219
Test name
Test status
Simulation time 148062882 ps
CPU time 0.82 seconds
Started Aug 18 05:33:39 PM PDT 24
Finished Aug 18 05:33:40 PM PDT 24
Peak memory 207476 kb
Host smart-51faba99-739c-4ccd-9913-9483728cd8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98270
2305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.982702305
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.341974622
Short name T3518
Test name
Test status
Simulation time 44955227 ps
CPU time 0.67 seconds
Started Aug 18 05:33:53 PM PDT 24
Finished Aug 18 05:33:54 PM PDT 24
Peak memory 207528 kb
Host smart-8ae698b7-d181-47d9-8807-fbd3f7b2342c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34197
4622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.341974622
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1576257274
Short name T1803
Test name
Test status
Simulation time 21633824158 ps
CPU time 54.13 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 215976 kb
Host smart-2330c985-057f-4d49-bb14-b3de9a1dbd89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15762
57274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1576257274
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2851742150
Short name T3155
Test name
Test status
Simulation time 158981601 ps
CPU time 0.89 seconds
Started Aug 18 05:34:02 PM PDT 24
Finished Aug 18 05:34:03 PM PDT 24
Peak memory 207448 kb
Host smart-3a532ac1-e84a-4e07-8f83-bf6a3020ab47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28517
42150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2851742150
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.979071376
Short name T677
Test name
Test status
Simulation time 221240063 ps
CPU time 0.99 seconds
Started Aug 18 05:33:53 PM PDT 24
Finished Aug 18 05:33:54 PM PDT 24
Peak memory 207440 kb
Host smart-4ade5b0c-345f-478d-b79a-a2e60d618174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97907
1376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.979071376
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1726094092
Short name T3271
Test name
Test status
Simulation time 235704196 ps
CPU time 1 seconds
Started Aug 18 05:34:03 PM PDT 24
Finished Aug 18 05:34:04 PM PDT 24
Peak memory 207448 kb
Host smart-6eb56241-eafa-4db9-8d66-1b9944f15f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17260
94092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1726094092
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.1023475514
Short name T1167
Test name
Test status
Simulation time 150427273 ps
CPU time 0.84 seconds
Started Aug 18 05:34:00 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 207404 kb
Host smart-0466f2d2-0a4c-4193-b9b4-bf315403ba12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10234
75514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.1023475514
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_resume_link_active.3720957477
Short name T2463
Test name
Test status
Simulation time 20191092011 ps
CPU time 25.68 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:34:09 PM PDT 24
Peak memory 207608 kb
Host smart-efe2607e-fe68-4a55-810e-e04c38aee179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37209
57477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_resume_link_active.3720957477
Directory /workspace/12.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/12.usbdev_rx_full.2339875960
Short name T2601
Test name
Test status
Simulation time 275826859 ps
CPU time 1.24 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:33:45 PM PDT 24
Peak memory 207448 kb
Host smart-f26f6061-2bfd-45e5-ad4a-e334d47b1619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23398
75960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_full.2339875960
Directory /workspace/12.usbdev_rx_full/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.929519631
Short name T3479
Test name
Test status
Simulation time 164982553 ps
CPU time 0.86 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:33:44 PM PDT 24
Peak memory 207452 kb
Host smart-817da1c4-b5ef-4ec7-83f8-754907668cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92951
9631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.929519631
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2426533930
Short name T2534
Test name
Test status
Simulation time 160045162 ps
CPU time 0.86 seconds
Started Aug 18 05:33:44 PM PDT 24
Finished Aug 18 05:33:45 PM PDT 24
Peak memory 207480 kb
Host smart-02c4d4c5-a952-41c5-8b2f-f745c10f03c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24265
33930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2426533930
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.177092971
Short name T719
Test name
Test status
Simulation time 228724191 ps
CPU time 1.08 seconds
Started Aug 18 05:33:56 PM PDT 24
Finished Aug 18 05:33:57 PM PDT 24
Peak memory 207396 kb
Host smart-222dceec-e53c-4cd6-8b46-bc27230d794c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17709
2971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.177092971
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2026959179
Short name T178
Test name
Test status
Simulation time 2303329829 ps
CPU time 23.02 seconds
Started Aug 18 05:34:01 PM PDT 24
Finished Aug 18 05:34:25 PM PDT 24
Peak memory 223936 kb
Host smart-46e91e0d-271d-4aba-8cf1-5d430dd00eaf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2026959179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2026959179
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2157600015
Short name T3077
Test name
Test status
Simulation time 215521428 ps
CPU time 0.94 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:33:44 PM PDT 24
Peak memory 207444 kb
Host smart-dfcac49a-75f1-4450-b67a-5946874881a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21576
00015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2157600015
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2543350010
Short name T3291
Test name
Test status
Simulation time 193835161 ps
CPU time 0.96 seconds
Started Aug 18 05:33:44 PM PDT 24
Finished Aug 18 05:33:46 PM PDT 24
Peak memory 207604 kb
Host smart-8feb623c-bce6-4f2d-bf8d-fd65dfca9adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25433
50010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2543350010
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.607604623
Short name T1287
Test name
Test status
Simulation time 991943044 ps
CPU time 2.49 seconds
Started Aug 18 05:33:50 PM PDT 24
Finished Aug 18 05:33:53 PM PDT 24
Peak memory 207748 kb
Host smart-dc8e004c-e37f-421f-a561-13fe69ef4220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60760
4623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.607604623
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.3160504296
Short name T2821
Test name
Test status
Simulation time 4052674023 ps
CPU time 30.76 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:34:13 PM PDT 24
Peak memory 217604 kb
Host smart-8f962f51-daa8-4e51-a01e-7b3f745380a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31605
04296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3160504296
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.3226344187
Short name T520
Test name
Test status
Simulation time 602143403 ps
CPU time 5.11 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:47 PM PDT 24
Peak memory 207672 kb
Host smart-c036f326-3952-4f5d-b2b6-ff4bbf1a1108
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226344187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.3226344187
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/12.usbdev_tx_rx_disruption.1731303790
Short name T1573
Test name
Test status
Simulation time 556163153 ps
CPU time 1.72 seconds
Started Aug 18 05:33:47 PM PDT 24
Finished Aug 18 05:33:49 PM PDT 24
Peak memory 207544 kb
Host smart-4552b001-eb1e-4a7f-b34b-c0f2a6e58d49
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731303790 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.usbdev_tx_rx_disruption.1731303790
Directory /workspace/12.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/120.usbdev_endpoint_types.4074165269
Short name T488
Test name
Test status
Simulation time 187680080 ps
CPU time 0.93 seconds
Started Aug 18 05:39:12 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207544 kb
Host smart-4850d776-0128-4d62-ad4e-30fcdae8f6e9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4074165269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_endpoint_types.4074165269
Directory /workspace/120.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/120.usbdev_tx_rx_disruption.1273136366
Short name T2193
Test name
Test status
Simulation time 630296674 ps
CPU time 1.79 seconds
Started Aug 18 05:39:10 PM PDT 24
Finished Aug 18 05:39:12 PM PDT 24
Peak memory 207532 kb
Host smart-fce1cdaa-16c8-47f1-9ad0-c1df937a7338
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273136366 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.usbdev_tx_rx_disruption.1273136366
Directory /workspace/120.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/121.usbdev_endpoint_types.2029549878
Short name T499
Test name
Test status
Simulation time 190233124 ps
CPU time 0.88 seconds
Started Aug 18 05:39:16 PM PDT 24
Finished Aug 18 05:39:17 PM PDT 24
Peak memory 207540 kb
Host smart-2589d0fc-5ac3-4459-9fef-b4ba7bcd3f5c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2029549878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_endpoint_types.2029549878
Directory /workspace/121.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/121.usbdev_tx_rx_disruption.2347979998
Short name T2434
Test name
Test status
Simulation time 562216751 ps
CPU time 1.71 seconds
Started Aug 18 05:39:17 PM PDT 24
Finished Aug 18 05:39:19 PM PDT 24
Peak memory 207580 kb
Host smart-10ccdfea-3450-4bad-8329-9c7ef674009e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347979998 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.usbdev_tx_rx_disruption.2347979998
Directory /workspace/121.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/122.usbdev_endpoint_types.882969051
Short name T2393
Test name
Test status
Simulation time 678996770 ps
CPU time 1.62 seconds
Started Aug 18 05:39:19 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207452 kb
Host smart-6343773d-895c-4ed3-9a5a-185116a51d70
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=882969051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_endpoint_types.882969051
Directory /workspace/122.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/122.usbdev_tx_rx_disruption.4168302196
Short name T1511
Test name
Test status
Simulation time 590413799 ps
CPU time 1.54 seconds
Started Aug 18 05:39:19 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207512 kb
Host smart-8c19f919-a012-4197-bf3d-dbc1272b2c1b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168302196 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.usbdev_tx_rx_disruption.4168302196
Directory /workspace/122.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/123.usbdev_endpoint_types.704410597
Short name T129
Test name
Test status
Simulation time 362062513 ps
CPU time 1.19 seconds
Started Aug 18 05:39:46 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207508 kb
Host smart-4e28d96d-1913-47d0-ab7f-6644e039de12
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=704410597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_endpoint_types.704410597
Directory /workspace/123.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/123.usbdev_tx_rx_disruption.3029245110
Short name T3032
Test name
Test status
Simulation time 583623845 ps
CPU time 1.56 seconds
Started Aug 18 05:39:16 PM PDT 24
Finished Aug 18 05:39:17 PM PDT 24
Peak memory 207568 kb
Host smart-a8672865-acc4-4e8e-a982-5adfed3176d4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029245110 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 123.usbdev_tx_rx_disruption.3029245110
Directory /workspace/123.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/124.usbdev_endpoint_types.1024684853
Short name T461
Test name
Test status
Simulation time 754117572 ps
CPU time 1.78 seconds
Started Aug 18 05:39:03 PM PDT 24
Finished Aug 18 05:39:05 PM PDT 24
Peak memory 207456 kb
Host smart-0aa73c5a-b10c-45fa-994d-3b6505770425
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1024684853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_endpoint_types.1024684853
Directory /workspace/124.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/124.usbdev_tx_rx_disruption.2982029935
Short name T70
Test name
Test status
Simulation time 461346254 ps
CPU time 1.45 seconds
Started Aug 18 05:39:11 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207540 kb
Host smart-a4b1b04e-dd05-4c75-8e55-15a5d99cd025
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982029935 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 124.usbdev_tx_rx_disruption.2982029935
Directory /workspace/124.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/125.usbdev_endpoint_types.3718012946
Short name T855
Test name
Test status
Simulation time 273745180 ps
CPU time 1.01 seconds
Started Aug 18 05:39:08 PM PDT 24
Finished Aug 18 05:39:09 PM PDT 24
Peak memory 207460 kb
Host smart-da896630-813d-43e9-bf3a-56494eaadf3c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3718012946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_endpoint_types.3718012946
Directory /workspace/125.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/125.usbdev_tx_rx_disruption.3123351374
Short name T2890
Test name
Test status
Simulation time 626816317 ps
CPU time 1.74 seconds
Started Aug 18 05:39:15 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207564 kb
Host smart-5c338620-2fee-40aa-ad6e-f63084698617
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123351374 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.usbdev_tx_rx_disruption.3123351374
Directory /workspace/125.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/126.usbdev_tx_rx_disruption.2401457672
Short name T3279
Test name
Test status
Simulation time 469050789 ps
CPU time 1.42 seconds
Started Aug 18 05:39:21 PM PDT 24
Finished Aug 18 05:39:22 PM PDT 24
Peak memory 207588 kb
Host smart-f223565a-5d39-4f67-8b1a-4fa88e01e6e4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401457672 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.usbdev_tx_rx_disruption.2401457672
Directory /workspace/126.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/127.usbdev_endpoint_types.1246928571
Short name T3165
Test name
Test status
Simulation time 376754702 ps
CPU time 1.17 seconds
Started Aug 18 05:39:18 PM PDT 24
Finished Aug 18 05:39:19 PM PDT 24
Peak memory 207512 kb
Host smart-90e1417c-b660-467a-a27f-a0427dbb8c03
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1246928571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_endpoint_types.1246928571
Directory /workspace/127.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/127.usbdev_tx_rx_disruption.1202316372
Short name T2017
Test name
Test status
Simulation time 530822909 ps
CPU time 1.62 seconds
Started Aug 18 05:39:22 PM PDT 24
Finished Aug 18 05:39:23 PM PDT 24
Peak memory 207612 kb
Host smart-ab9b98aa-dfda-4340-b814-02c73b4fd9f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202316372 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 127.usbdev_tx_rx_disruption.1202316372
Directory /workspace/127.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/128.usbdev_endpoint_types.4205144426
Short name T1560
Test name
Test status
Simulation time 152758765 ps
CPU time 0.86 seconds
Started Aug 18 05:39:42 PM PDT 24
Finished Aug 18 05:39:43 PM PDT 24
Peak memory 207524 kb
Host smart-2350ccab-f573-46a0-8aee-582b15d4a314
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4205144426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_endpoint_types.4205144426
Directory /workspace/128.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/128.usbdev_tx_rx_disruption.3140596579
Short name T1578
Test name
Test status
Simulation time 496469965 ps
CPU time 1.59 seconds
Started Aug 18 05:39:26 PM PDT 24
Finished Aug 18 05:39:27 PM PDT 24
Peak memory 207580 kb
Host smart-f1eeaa69-bbfd-4b59-9265-a1f44ec2fbe9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140596579 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 128.usbdev_tx_rx_disruption.3140596579
Directory /workspace/128.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/129.usbdev_tx_rx_disruption.2500708728
Short name T3257
Test name
Test status
Simulation time 556211839 ps
CPU time 1.66 seconds
Started Aug 18 05:39:01 PM PDT 24
Finished Aug 18 05:39:03 PM PDT 24
Peak memory 207564 kb
Host smart-971bc914-ae0b-415e-95e6-a5d8c446faa8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500708728 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.usbdev_tx_rx_disruption.2500708728
Directory /workspace/129.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.943060157
Short name T247
Test name
Test status
Simulation time 6295067094 ps
CPU time 10.17 seconds
Started Aug 18 05:33:44 PM PDT 24
Finished Aug 18 05:33:54 PM PDT 24
Peak memory 215976 kb
Host smart-e5abad66-d70e-44d5-9533-db6264434501
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943060157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_ao
n_wake_disconnect.943060157
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3792087396
Short name T2616
Test name
Test status
Simulation time 18374096205 ps
CPU time 21.62 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:34:04 PM PDT 24
Peak memory 207748 kb
Host smart-15c74d0b-b365-4c84-821e-6063609f8044
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792087396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3792087396
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.2200478271
Short name T1056
Test name
Test status
Simulation time 30796870923 ps
CPU time 41.73 seconds
Started Aug 18 05:33:44 PM PDT 24
Finished Aug 18 05:34:26 PM PDT 24
Peak memory 207732 kb
Host smart-a85c8dbe-0b34-40a9-8fbc-d18ce320bd5b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200478271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_resume.2200478271
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2292433710
Short name T1331
Test name
Test status
Simulation time 205196938 ps
CPU time 0.93 seconds
Started Aug 18 05:33:53 PM PDT 24
Finished Aug 18 05:33:54 PM PDT 24
Peak memory 207508 kb
Host smart-e97ad31f-3077-4b18-bfbc-95ed885e7716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22924
33710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2292433710
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.2492055298
Short name T1260
Test name
Test status
Simulation time 144063459 ps
CPU time 0.84 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207444 kb
Host smart-4caab02a-5592-4f0a-933a-1deb31b15ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24920
55298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.2492055298
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3950882055
Short name T2933
Test name
Test status
Simulation time 391755729 ps
CPU time 1.45 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:44 PM PDT 24
Peak memory 207492 kb
Host smart-c5c84811-8bb6-4247-be3c-ceb94ba37d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39508
82055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3950882055
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3662670331
Short name T1491
Test name
Test status
Simulation time 436629788 ps
CPU time 1.28 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207416 kb
Host smart-d260db54-fd00-402c-a845-67ca10d8b69d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3662670331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3662670331
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.3163815271
Short name T1744
Test name
Test status
Simulation time 41983499240 ps
CPU time 63.93 seconds
Started Aug 18 05:33:47 PM PDT 24
Finished Aug 18 05:34:51 PM PDT 24
Peak memory 207772 kb
Host smart-baaecae2-65c4-4c09-b0e0-1ce2152f21cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31638
15271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.3163815271
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.1093430639
Short name T1933
Test name
Test status
Simulation time 165437916 ps
CPU time 0.9 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207512 kb
Host smart-728648d7-fdfc-4f72-bf42-3ac5fb473931
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093430639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.1093430639
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1679896144
Short name T1690
Test name
Test status
Simulation time 1018124254 ps
CPU time 2.22 seconds
Started Aug 18 05:33:56 PM PDT 24
Finished Aug 18 05:33:58 PM PDT 24
Peak memory 207488 kb
Host smart-3f205616-9d06-4f43-bc26-1fe79361b34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16798
96144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1679896144
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.920163738
Short name T3136
Test name
Test status
Simulation time 136393621 ps
CPU time 0.87 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:33:44 PM PDT 24
Peak memory 207504 kb
Host smart-5bd07013-2309-4cbe-9286-4c7451e5f16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92016
3738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.920163738
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.856875837
Short name T3365
Test name
Test status
Simulation time 76855279 ps
CPU time 0.76 seconds
Started Aug 18 05:33:44 PM PDT 24
Finished Aug 18 05:33:45 PM PDT 24
Peak memory 207408 kb
Host smart-cf4a0561-9aa3-4d5f-b9f8-4d09244cc5b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85687
5837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.856875837
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.4276558647
Short name T665
Test name
Test status
Simulation time 902917190 ps
CPU time 2.39 seconds
Started Aug 18 05:33:45 PM PDT 24
Finished Aug 18 05:33:48 PM PDT 24
Peak memory 207680 kb
Host smart-0c9eed9e-83f6-4cff-a399-7f03904ee5ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42765
58647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.4276558647
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_types.673961073
Short name T483
Test name
Test status
Simulation time 398023778 ps
CPU time 1.29 seconds
Started Aug 18 05:33:43 PM PDT 24
Finished Aug 18 05:33:44 PM PDT 24
Peak memory 207544 kb
Host smart-6575f7fa-4637-4df9-ad04-1f1a843c5e53
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=673961073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_types.673961073
Directory /workspace/13.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1285593800
Short name T2405
Test name
Test status
Simulation time 391382223 ps
CPU time 2.86 seconds
Started Aug 18 05:33:47 PM PDT 24
Finished Aug 18 05:33:50 PM PDT 24
Peak memory 207680 kb
Host smart-b58b32a9-77e9-4a1a-bb10-f7f1082a743c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12855
93800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1285593800
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3275636370
Short name T1786
Test name
Test status
Simulation time 200231878 ps
CPU time 1.05 seconds
Started Aug 18 05:33:54 PM PDT 24
Finished Aug 18 05:33:55 PM PDT 24
Peak memory 215840 kb
Host smart-975783c0-7f6b-4b1c-b488-f0b60181a5ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3275636370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3275636370
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.653193220
Short name T126
Test name
Test status
Simulation time 138373750 ps
CPU time 0.85 seconds
Started Aug 18 05:33:47 PM PDT 24
Finished Aug 18 05:33:48 PM PDT 24
Peak memory 207420 kb
Host smart-bfd8a9ca-5c94-4111-bd5f-a0272e0dfade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65319
3220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.653193220
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1674121203
Short name T3366
Test name
Test status
Simulation time 198595194 ps
CPU time 0.95 seconds
Started Aug 18 05:33:47 PM PDT 24
Finished Aug 18 05:33:48 PM PDT 24
Peak memory 207408 kb
Host smart-63b194e0-9601-462d-9dcc-0343e58dc6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16741
21203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1674121203
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.1365382277
Short name T3524
Test name
Test status
Simulation time 3740421651 ps
CPU time 27.57 seconds
Started Aug 18 05:33:45 PM PDT 24
Finished Aug 18 05:34:13 PM PDT 24
Peak memory 218128 kb
Host smart-62abf1af-1446-45b2-aa78-003471a4f521
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1365382277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.1365382277
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.423306240
Short name T1798
Test name
Test status
Simulation time 12504124771 ps
CPU time 156.12 seconds
Started Aug 18 05:33:45 PM PDT 24
Finished Aug 18 05:36:22 PM PDT 24
Peak memory 207792 kb
Host smart-50eb61e8-b6c0-4aa6-93ef-58bcefdb372a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=423306240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.423306240
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2437417525
Short name T1477
Test name
Test status
Simulation time 278864137 ps
CPU time 1.06 seconds
Started Aug 18 05:33:48 PM PDT 24
Finished Aug 18 05:33:50 PM PDT 24
Peak memory 207596 kb
Host smart-ce36693e-2248-4d18-8dc0-e9d9d0f13111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24374
17525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2437417525
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.507215861
Short name T1621
Test name
Test status
Simulation time 15129044694 ps
CPU time 19.98 seconds
Started Aug 18 05:33:45 PM PDT 24
Finished Aug 18 05:34:05 PM PDT 24
Peak memory 207684 kb
Host smart-e04deba4-eaa0-4a7b-98bb-b481ea73c3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50721
5861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.507215861
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.1673861972
Short name T93
Test name
Test status
Simulation time 8495700910 ps
CPU time 10.49 seconds
Started Aug 18 05:33:53 PM PDT 24
Finished Aug 18 05:34:04 PM PDT 24
Peak memory 207732 kb
Host smart-9fd24d1c-4adb-43eb-b2b7-9a960efb48bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16738
61972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.1673861972
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.2640668959
Short name T3452
Test name
Test status
Simulation time 2234964593 ps
CPU time 61.34 seconds
Started Aug 18 05:33:49 PM PDT 24
Finished Aug 18 05:34:50 PM PDT 24
Peak memory 215828 kb
Host smart-59f9003f-5769-4aaf-b1b9-99e7a18765d4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2640668959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.2640668959
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.3792153022
Short name T823
Test name
Test status
Simulation time 301552763 ps
CPU time 1.02 seconds
Started Aug 18 05:33:41 PM PDT 24
Finished Aug 18 05:33:42 PM PDT 24
Peak memory 207504 kb
Host smart-0bfd6f25-6b62-44c7-8fbb-937e4f8e804e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3792153022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.3792153022
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1120509140
Short name T2266
Test name
Test status
Simulation time 189951680 ps
CPU time 0.96 seconds
Started Aug 18 05:34:01 PM PDT 24
Finished Aug 18 05:34:02 PM PDT 24
Peak memory 207496 kb
Host smart-6ddf9792-8dd5-4a93-b2a9-7b108378561d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11205
09140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1120509140
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.1490959911
Short name T614
Test name
Test status
Simulation time 2415362341 ps
CPU time 26.48 seconds
Started Aug 18 05:33:45 PM PDT 24
Finished Aug 18 05:34:12 PM PDT 24
Peak memory 224116 kb
Host smart-9d35718c-8b55-4fa4-a3a1-3087a82aac38
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1490959911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.1490959911
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.3224969654
Short name T6
Test name
Test status
Simulation time 2475004966 ps
CPU time 72.75 seconds
Started Aug 18 05:33:59 PM PDT 24
Finished Aug 18 05:35:11 PM PDT 24
Peak memory 224012 kb
Host smart-2e5aa07a-928c-4270-9864-f3c9b201ccb5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3224969654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.3224969654
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.129185208
Short name T555
Test name
Test status
Simulation time 152971358 ps
CPU time 0.92 seconds
Started Aug 18 05:33:53 PM PDT 24
Finished Aug 18 05:33:54 PM PDT 24
Peak memory 207388 kb
Host smart-3beff319-d4a7-47c8-af3d-946319d4ddb4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=129185208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.129185208
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2826935303
Short name T2731
Test name
Test status
Simulation time 195221340 ps
CPU time 0.92 seconds
Started Aug 18 05:33:50 PM PDT 24
Finished Aug 18 05:33:51 PM PDT 24
Peak memory 207420 kb
Host smart-720aab90-5421-4d10-9fa2-baee0f9f8c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28269
35303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2826935303
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.2056469985
Short name T1296
Test name
Test status
Simulation time 154682167 ps
CPU time 0.88 seconds
Started Aug 18 05:33:44 PM PDT 24
Finished Aug 18 05:33:45 PM PDT 24
Peak memory 207500 kb
Host smart-af005f04-6410-4a2b-9c06-011c067fb9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20564
69985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.2056469985
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1564894651
Short name T1936
Test name
Test status
Simulation time 181798645 ps
CPU time 0.97 seconds
Started Aug 18 05:34:02 PM PDT 24
Finished Aug 18 05:34:03 PM PDT 24
Peak memory 207396 kb
Host smart-9a1662fd-2272-4676-a5e8-cd26034b8d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15648
94651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1564894651
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2250447432
Short name T2420
Test name
Test status
Simulation time 147269349 ps
CPU time 0.88 seconds
Started Aug 18 05:33:42 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 207596 kb
Host smart-717f6046-c01a-4c05-a860-b76c23d6a5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22504
47432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2250447432
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2503874892
Short name T1514
Test name
Test status
Simulation time 162110137 ps
CPU time 0.87 seconds
Started Aug 18 05:33:51 PM PDT 24
Finished Aug 18 05:33:52 PM PDT 24
Peak memory 207472 kb
Host smart-f68aaf9a-b033-4fad-8f53-06297afa3246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25038
74892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2503874892
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3467771361
Short name T1982
Test name
Test status
Simulation time 223491839 ps
CPU time 1.11 seconds
Started Aug 18 05:34:06 PM PDT 24
Finished Aug 18 05:34:07 PM PDT 24
Peak memory 207568 kb
Host smart-71e9fb4e-255b-4cd7-ae7a-d07022ab5ac4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3467771361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3467771361
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.940589779
Short name T3120
Test name
Test status
Simulation time 148147982 ps
CPU time 0.85 seconds
Started Aug 18 05:34:03 PM PDT 24
Finished Aug 18 05:34:04 PM PDT 24
Peak memory 207452 kb
Host smart-ef7ed601-2768-4dec-88a8-0478c805d774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94058
9779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.940589779
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1492703831
Short name T2714
Test name
Test status
Simulation time 6028739811 ps
CPU time 15.14 seconds
Started Aug 18 05:34:02 PM PDT 24
Finished Aug 18 05:34:17 PM PDT 24
Peak memory 215912 kb
Host smart-b6c92f44-1707-4560-90e9-a4cf2326e440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14927
03831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1492703831
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3869251051
Short name T877
Test name
Test status
Simulation time 192539862 ps
CPU time 0.93 seconds
Started Aug 18 05:33:59 PM PDT 24
Finished Aug 18 05:34:00 PM PDT 24
Peak memory 207448 kb
Host smart-5adfa9ca-a0d1-4c1e-856b-06e95329999d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38692
51051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3869251051
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3437182083
Short name T3171
Test name
Test status
Simulation time 236207570 ps
CPU time 0.97 seconds
Started Aug 18 05:33:55 PM PDT 24
Finished Aug 18 05:33:56 PM PDT 24
Peak memory 207476 kb
Host smart-6aeb4f5d-d43e-45af-9042-3fb0ca7a4e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34371
82083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3437182083
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.3113104020
Short name T2241
Test name
Test status
Simulation time 272676482 ps
CPU time 1.07 seconds
Started Aug 18 05:33:55 PM PDT 24
Finished Aug 18 05:33:56 PM PDT 24
Peak memory 207512 kb
Host smart-350e007d-3a9d-4da8-aa02-d1ef98ce5c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31131
04020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.3113104020
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.3951769060
Short name T2142
Test name
Test status
Simulation time 176351283 ps
CPU time 0.92 seconds
Started Aug 18 05:33:56 PM PDT 24
Finished Aug 18 05:33:57 PM PDT 24
Peak memory 207416 kb
Host smart-0d0c8803-0cf6-4cb4-8d82-3fd9e342e701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39517
69060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.3951769060
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_resume_link_active.341373183
Short name T2697
Test name
Test status
Simulation time 20159669910 ps
CPU time 28.36 seconds
Started Aug 18 05:34:01 PM PDT 24
Finished Aug 18 05:34:29 PM PDT 24
Peak memory 207532 kb
Host smart-edf49d79-a4cd-49b2-b8bc-9044aed475ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34137
3183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_resume_link_active.341373183
Directory /workspace/13.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2528729532
Short name T3514
Test name
Test status
Simulation time 171944740 ps
CPU time 0.9 seconds
Started Aug 18 05:33:52 PM PDT 24
Finished Aug 18 05:33:53 PM PDT 24
Peak memory 207412 kb
Host smart-af696167-4b2d-46a7-bf74-d8edfbc4b6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25287
29532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2528729532
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_rx_full.1179630675
Short name T3265
Test name
Test status
Simulation time 245950671 ps
CPU time 1.1 seconds
Started Aug 18 05:33:56 PM PDT 24
Finished Aug 18 05:33:58 PM PDT 24
Peak memory 207460 kb
Host smart-66cf73f6-f8e8-40b2-aa8a-8fff7afb1cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11796
30675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_full.1179630675
Directory /workspace/13.usbdev_rx_full/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.2883762432
Short name T723
Test name
Test status
Simulation time 152741666 ps
CPU time 0.84 seconds
Started Aug 18 05:33:56 PM PDT 24
Finished Aug 18 05:33:57 PM PDT 24
Peak memory 207552 kb
Host smart-0ce1cc3c-ce2a-45be-8a05-31a12812627a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28837
62432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.2883762432
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.4185118271
Short name T2765
Test name
Test status
Simulation time 161505955 ps
CPU time 0.86 seconds
Started Aug 18 05:34:01 PM PDT 24
Finished Aug 18 05:34:02 PM PDT 24
Peak memory 207416 kb
Host smart-01961982-300b-42ce-a8d0-370b9c64e9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41851
18271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.4185118271
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2049310994
Short name T2390
Test name
Test status
Simulation time 215557432 ps
CPU time 1.07 seconds
Started Aug 18 05:34:01 PM PDT 24
Finished Aug 18 05:34:02 PM PDT 24
Peak memory 207500 kb
Host smart-a890b95b-6fca-4304-adde-549b8a96c2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20493
10994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2049310994
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.1291308332
Short name T2538
Test name
Test status
Simulation time 2588996683 ps
CPU time 25.45 seconds
Started Aug 18 05:33:57 PM PDT 24
Finished Aug 18 05:34:23 PM PDT 24
Peak memory 217236 kb
Host smart-25c32346-884a-4976-b60e-a0d3335f76da
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1291308332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.1291308332
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.318946069
Short name T1104
Test name
Test status
Simulation time 167667502 ps
CPU time 0.83 seconds
Started Aug 18 05:33:54 PM PDT 24
Finished Aug 18 05:33:55 PM PDT 24
Peak memory 207508 kb
Host smart-8e1a0e3b-e1ec-4188-95b2-f9ceeb597c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31894
6069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.318946069
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.221739746
Short name T3487
Test name
Test status
Simulation time 192164863 ps
CPU time 0.93 seconds
Started Aug 18 05:33:53 PM PDT 24
Finished Aug 18 05:33:54 PM PDT 24
Peak memory 207456 kb
Host smart-b2a9360d-f333-461d-af4e-5a57da4be516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22173
9746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.221739746
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.2846188120
Short name T1488
Test name
Test status
Simulation time 1321342791 ps
CPU time 2.96 seconds
Started Aug 18 05:33:53 PM PDT 24
Finished Aug 18 05:33:56 PM PDT 24
Peak memory 207668 kb
Host smart-5c040275-9214-4db2-9ef4-2675a291d0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28461
88120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.2846188120
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.2155766037
Short name T3026
Test name
Test status
Simulation time 2751997573 ps
CPU time 27.26 seconds
Started Aug 18 05:33:56 PM PDT 24
Finished Aug 18 05:34:24 PM PDT 24
Peak memory 217676 kb
Host smart-866f2bda-b2b6-4095-afea-6e2bd4fe6fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21557
66037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.2155766037
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.1106553445
Short name T3059
Test name
Test status
Simulation time 7736473030 ps
CPU time 54.03 seconds
Started Aug 18 05:34:03 PM PDT 24
Finished Aug 18 05:34:57 PM PDT 24
Peak memory 207712 kb
Host smart-f4576526-34b4-46af-a6b0-3408629ed2be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106553445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.1106553445
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/13.usbdev_tx_rx_disruption.2103683649
Short name T2521
Test name
Test status
Simulation time 599930258 ps
CPU time 1.74 seconds
Started Aug 18 05:33:57 PM PDT 24
Finished Aug 18 05:33:58 PM PDT 24
Peak memory 207568 kb
Host smart-cfbe503b-2a65-4d0b-ba2c-eb54056bc33f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103683649 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.usbdev_tx_rx_disruption.2103683649
Directory /workspace/13.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/130.usbdev_tx_rx_disruption.937710920
Short name T2104
Test name
Test status
Simulation time 497544423 ps
CPU time 1.69 seconds
Started Aug 18 05:39:04 PM PDT 24
Finished Aug 18 05:39:06 PM PDT 24
Peak memory 207560 kb
Host smart-063d071a-ec63-48f3-b530-3a084766bd5c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937710920 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 130.usbdev_tx_rx_disruption.937710920
Directory /workspace/130.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/131.usbdev_endpoint_types.1386623153
Short name T2466
Test name
Test status
Simulation time 303782496 ps
CPU time 1.05 seconds
Started Aug 18 05:39:16 PM PDT 24
Finished Aug 18 05:39:18 PM PDT 24
Peak memory 207524 kb
Host smart-d41e271d-12d7-4b85-b98d-e207e4dbd64b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1386623153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_endpoint_types.1386623153
Directory /workspace/131.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/131.usbdev_tx_rx_disruption.1788421684
Short name T195
Test name
Test status
Simulation time 497801892 ps
CPU time 1.5 seconds
Started Aug 18 05:39:25 PM PDT 24
Finished Aug 18 05:39:27 PM PDT 24
Peak memory 207572 kb
Host smart-71e4e8be-337d-4943-ad5c-40c51ed02b48
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788421684 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.usbdev_tx_rx_disruption.1788421684
Directory /workspace/131.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/132.usbdev_endpoint_types.1127703337
Short name T130
Test name
Test status
Simulation time 784950483 ps
CPU time 1.72 seconds
Started Aug 18 05:39:27 PM PDT 24
Finished Aug 18 05:39:29 PM PDT 24
Peak memory 207500 kb
Host smart-80bc28c9-da6e-4907-ab9b-1424c41d9aca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1127703337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_endpoint_types.1127703337
Directory /workspace/132.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/132.usbdev_tx_rx_disruption.1665661972
Short name T2789
Test name
Test status
Simulation time 458855210 ps
CPU time 1.4 seconds
Started Aug 18 05:39:10 PM PDT 24
Finished Aug 18 05:39:11 PM PDT 24
Peak memory 207524 kb
Host smart-0867384b-02f0-4db4-bee8-954f82b3e6a5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665661972 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.usbdev_tx_rx_disruption.1665661972
Directory /workspace/132.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/133.usbdev_tx_rx_disruption.155965217
Short name T3609
Test name
Test status
Simulation time 604173695 ps
CPU time 1.67 seconds
Started Aug 18 05:39:09 PM PDT 24
Finished Aug 18 05:39:10 PM PDT 24
Peak memory 207552 kb
Host smart-b386f925-7169-40bc-8beb-e265fec42825
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155965217 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 133.usbdev_tx_rx_disruption.155965217
Directory /workspace/133.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/134.usbdev_endpoint_types.3716667378
Short name T1530
Test name
Test status
Simulation time 257488052 ps
CPU time 1.12 seconds
Started Aug 18 05:39:19 PM PDT 24
Finished Aug 18 05:39:20 PM PDT 24
Peak memory 207460 kb
Host smart-2977392e-4e88-476f-b2f7-0a474dc4fbd8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3716667378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_endpoint_types.3716667378
Directory /workspace/134.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/134.usbdev_tx_rx_disruption.839059024
Short name T1772
Test name
Test status
Simulation time 621983342 ps
CPU time 1.7 seconds
Started Aug 18 05:39:13 PM PDT 24
Finished Aug 18 05:39:15 PM PDT 24
Peak memory 207556 kb
Host smart-69445196-5580-47f7-a4a1-033c706eee9a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839059024 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 134.usbdev_tx_rx_disruption.839059024
Directory /workspace/134.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/135.usbdev_tx_rx_disruption.1683059578
Short name T891
Test name
Test status
Simulation time 539363805 ps
CPU time 1.7 seconds
Started Aug 18 05:39:09 PM PDT 24
Finished Aug 18 05:39:11 PM PDT 24
Peak memory 207592 kb
Host smart-6c96a253-49bd-47fb-832e-937e992728a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683059578 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.usbdev_tx_rx_disruption.1683059578
Directory /workspace/135.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/136.usbdev_endpoint_types.2889907336
Short name T258
Test name
Test status
Simulation time 293311872 ps
CPU time 1.09 seconds
Started Aug 18 05:39:29 PM PDT 24
Finished Aug 18 05:39:30 PM PDT 24
Peak memory 207532 kb
Host smart-167aa73c-5fb1-42f7-8850-2bb6f4d31ad5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2889907336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_endpoint_types.2889907336
Directory /workspace/136.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/136.usbdev_tx_rx_disruption.3798223568
Short name T221
Test name
Test status
Simulation time 441607402 ps
CPU time 1.38 seconds
Started Aug 18 05:39:19 PM PDT 24
Finished Aug 18 05:39:20 PM PDT 24
Peak memory 207376 kb
Host smart-db76941f-a93c-40ee-9888-73572a543529
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798223568 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 136.usbdev_tx_rx_disruption.3798223568
Directory /workspace/136.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/137.usbdev_endpoint_types.4264861210
Short name T2095
Test name
Test status
Simulation time 516487482 ps
CPU time 1.44 seconds
Started Aug 18 05:39:24 PM PDT 24
Finished Aug 18 05:39:25 PM PDT 24
Peak memory 207540 kb
Host smart-3a029b94-9312-488b-9bb3-9492b170cd6f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4264861210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_endpoint_types.4264861210
Directory /workspace/137.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/137.usbdev_tx_rx_disruption.4141702485
Short name T2930
Test name
Test status
Simulation time 485910354 ps
CPU time 1.56 seconds
Started Aug 18 05:39:37 PM PDT 24
Finished Aug 18 05:39:38 PM PDT 24
Peak memory 207588 kb
Host smart-0fc7f5be-4131-4da9-96b3-4cf696541f8d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141702485 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.usbdev_tx_rx_disruption.4141702485
Directory /workspace/137.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/138.usbdev_endpoint_types.1482021547
Short name T485
Test name
Test status
Simulation time 347213040 ps
CPU time 1.19 seconds
Started Aug 18 05:39:11 PM PDT 24
Finished Aug 18 05:39:12 PM PDT 24
Peak memory 207560 kb
Host smart-cdf83f09-d234-4e3f-92fa-4732c6670790
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1482021547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_endpoint_types.1482021547
Directory /workspace/138.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/138.usbdev_tx_rx_disruption.2279158570
Short name T2158
Test name
Test status
Simulation time 443564444 ps
CPU time 1.38 seconds
Started Aug 18 05:39:14 PM PDT 24
Finished Aug 18 05:39:15 PM PDT 24
Peak memory 207540 kb
Host smart-ebe9494b-5c3b-4c4e-92bb-6394048c2383
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279158570 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.usbdev_tx_rx_disruption.2279158570
Directory /workspace/138.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/139.usbdev_tx_rx_disruption.1373564509
Short name T1714
Test name
Test status
Simulation time 535053386 ps
CPU time 1.73 seconds
Started Aug 18 05:39:15 PM PDT 24
Finished Aug 18 05:39:17 PM PDT 24
Peak memory 207572 kb
Host smart-0fe9f760-8f10-4fbe-a58d-0475e7b9a564
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373564509 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 139.usbdev_tx_rx_disruption.1373564509
Directory /workspace/139.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.186913325
Short name T1471
Test name
Test status
Simulation time 48000040 ps
CPU time 0.68 seconds
Started Aug 18 05:34:03 PM PDT 24
Finished Aug 18 05:34:04 PM PDT 24
Peak memory 207444 kb
Host smart-3594141a-9394-447d-bf0c-be778484a721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=186913325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.186913325
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.2234039165
Short name T2267
Test name
Test status
Simulation time 4713790044 ps
CPU time 6.42 seconds
Started Aug 18 05:33:54 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 215916 kb
Host smart-f80f7cba-3fdb-4d98-b5dd-dbe04352fc55
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234039165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.2234039165
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.3987103642
Short name T1245
Test name
Test status
Simulation time 19181398688 ps
CPU time 25.61 seconds
Started Aug 18 05:34:04 PM PDT 24
Finished Aug 18 05:34:30 PM PDT 24
Peak memory 207772 kb
Host smart-2e8259af-0e09-4a69-83da-56d1826a7c4c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987103642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3987103642
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2668875631
Short name T2231
Test name
Test status
Simulation time 26100724013 ps
CPU time 41.1 seconds
Started Aug 18 05:33:59 PM PDT 24
Finished Aug 18 05:34:40 PM PDT 24
Peak memory 216004 kb
Host smart-9ff343b1-5b56-4e65-b840-ee024e2d3964
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668875631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.2668875631
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3826416088
Short name T866
Test name
Test status
Simulation time 184332433 ps
CPU time 0.87 seconds
Started Aug 18 05:33:57 PM PDT 24
Finished Aug 18 05:33:58 PM PDT 24
Peak memory 207476 kb
Host smart-720c7b35-ad7f-4a33-9148-9c9f16e0a393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38264
16088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3826416088
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.45234676
Short name T1533
Test name
Test status
Simulation time 156161474 ps
CPU time 0.88 seconds
Started Aug 18 05:33:58 PM PDT 24
Finished Aug 18 05:33:59 PM PDT 24
Peak memory 207500 kb
Host smart-a6eb4855-ce61-4f33-8867-a288380ebfbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45234
676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.45234676
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.221699611
Short name T2369
Test name
Test status
Simulation time 533103760 ps
CPU time 1.69 seconds
Started Aug 18 05:33:56 PM PDT 24
Finished Aug 18 05:33:58 PM PDT 24
Peak memory 207560 kb
Host smart-bcc7a6a3-3656-41ce-90c8-fcd434aa667e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22169
9611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.221699611
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3495393369
Short name T1158
Test name
Test status
Simulation time 1178036213 ps
CPU time 2.95 seconds
Started Aug 18 05:33:58 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 207680 kb
Host smart-b1444de7-841f-4104-89df-fab691e90414
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3495393369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3495393369
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.1939045124
Short name T3214
Test name
Test status
Simulation time 17633253263 ps
CPU time 30.06 seconds
Started Aug 18 05:33:53 PM PDT 24
Finished Aug 18 05:34:23 PM PDT 24
Peak memory 207800 kb
Host smart-b36310ee-95bb-48e0-aada-cbeda19088e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19390
45124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.1939045124
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.1961553287
Short name T1939
Test name
Test status
Simulation time 621852391 ps
CPU time 4.93 seconds
Started Aug 18 05:34:06 PM PDT 24
Finished Aug 18 05:34:11 PM PDT 24
Peak memory 207760 kb
Host smart-806eb680-a3d3-4907-9fd1-b202e692c3fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961553287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.1961553287
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.2528734386
Short name T1203
Test name
Test status
Simulation time 768208065 ps
CPU time 1.8 seconds
Started Aug 18 05:33:58 PM PDT 24
Finished Aug 18 05:34:00 PM PDT 24
Peak memory 207412 kb
Host smart-5e9e9583-b1b8-4a82-a88e-244fb1f058ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25287
34386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.2528734386
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.1337290031
Short name T2025
Test name
Test status
Simulation time 139578308 ps
CPU time 0.8 seconds
Started Aug 18 05:34:03 PM PDT 24
Finished Aug 18 05:34:04 PM PDT 24
Peak memory 207536 kb
Host smart-820771cb-c2de-4bfc-bffd-f392b098d772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13372
90031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.1337290031
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.379254715
Short name T2341
Test name
Test status
Simulation time 55598360 ps
CPU time 0.72 seconds
Started Aug 18 05:34:00 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 207356 kb
Host smart-2ca95a48-e27e-4be2-a012-d7fb85c6de27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37925
4715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.379254715
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.3971465327
Short name T1730
Test name
Test status
Simulation time 687240303 ps
CPU time 1.96 seconds
Started Aug 18 05:34:04 PM PDT 24
Finished Aug 18 05:34:06 PM PDT 24
Peak memory 207776 kb
Host smart-545dfe68-bc7c-44a9-86ae-463408617f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39714
65327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3971465327
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_types.2266046685
Short name T3417
Test name
Test status
Simulation time 317147313 ps
CPU time 1.23 seconds
Started Aug 18 05:33:57 PM PDT 24
Finished Aug 18 05:33:59 PM PDT 24
Peak memory 207512 kb
Host smart-ae2658d2-fc55-4125-ac90-591aea106ff4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2266046685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_types.2266046685
Directory /workspace/14.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.356174742
Short name T3175
Test name
Test status
Simulation time 308870905 ps
CPU time 2.1 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:34:08 PM PDT 24
Peak memory 207704 kb
Host smart-089e64ac-a56d-4b42-9be0-95bb8f0199f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35617
4742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.356174742
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1505275399
Short name T2769
Test name
Test status
Simulation time 235761755 ps
CPU time 1.3 seconds
Started Aug 18 05:34:01 PM PDT 24
Finished Aug 18 05:34:02 PM PDT 24
Peak memory 215848 kb
Host smart-e0542873-8799-42c7-a42b-e8bd08efe9ff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1505275399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1505275399
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2081807758
Short name T2764
Test name
Test status
Simulation time 150449679 ps
CPU time 0.87 seconds
Started Aug 18 05:33:55 PM PDT 24
Finished Aug 18 05:33:56 PM PDT 24
Peak memory 207368 kb
Host smart-193c7304-f9ee-4796-8bd7-ae41313b8b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20818
07758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2081807758
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.413864453
Short name T960
Test name
Test status
Simulation time 232036157 ps
CPU time 0.97 seconds
Started Aug 18 05:34:03 PM PDT 24
Finished Aug 18 05:34:04 PM PDT 24
Peak memory 207472 kb
Host smart-eeb0de1e-ca0d-447c-9a3b-cf4b86a9728b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41386
4453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.413864453
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.2614376000
Short name T534
Test name
Test status
Simulation time 4399698136 ps
CPU time 130.2 seconds
Started Aug 18 05:33:58 PM PDT 24
Finished Aug 18 05:36:09 PM PDT 24
Peak memory 224076 kb
Host smart-0fcd1496-cdbb-45e5-bfaa-3fcb92b75060
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2614376000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.2614376000
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.298128263
Short name T3213
Test name
Test status
Simulation time 242009081 ps
CPU time 1.06 seconds
Started Aug 18 05:33:54 PM PDT 24
Finished Aug 18 05:33:56 PM PDT 24
Peak memory 207504 kb
Host smart-19857269-00a6-44b4-b4f4-a13249833d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29812
8263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.298128263
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.1425297430
Short name T981
Test name
Test status
Simulation time 12696892394 ps
CPU time 17.25 seconds
Started Aug 18 05:34:03 PM PDT 24
Finished Aug 18 05:34:20 PM PDT 24
Peak memory 207844 kb
Host smart-2703f0e6-ad67-43d3-9a4c-9c6d6607fbab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14252
97430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.1425297430
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.2489712488
Short name T2498
Test name
Test status
Simulation time 5298553899 ps
CPU time 8.63 seconds
Started Aug 18 05:33:59 PM PDT 24
Finished Aug 18 05:34:08 PM PDT 24
Peak memory 207696 kb
Host smart-8fef9e9e-b7ed-4e72-aea5-71425467107b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24897
12488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.2489712488
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.1911248444
Short name T396
Test name
Test status
Simulation time 5284826375 ps
CPU time 41.47 seconds
Started Aug 18 05:34:03 PM PDT 24
Finished Aug 18 05:34:44 PM PDT 24
Peak memory 219204 kb
Host smart-153c1dbc-8871-4893-b746-e9462adf2bfd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1911248444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.1911248444
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.2624856050
Short name T1195
Test name
Test status
Simulation time 2592138973 ps
CPU time 19.52 seconds
Started Aug 18 05:34:00 PM PDT 24
Finished Aug 18 05:34:19 PM PDT 24
Peak memory 217384 kb
Host smart-898f3707-d6be-4593-8c36-7c413ca009c2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2624856050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.2624856050
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.852502052
Short name T1795
Test name
Test status
Simulation time 235748146 ps
CPU time 1.03 seconds
Started Aug 18 05:34:00 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 207412 kb
Host smart-73e8d9da-56c8-473d-8ade-75708cab97c4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=852502052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.852502052
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3842049059
Short name T2005
Test name
Test status
Simulation time 188894819 ps
CPU time 0.95 seconds
Started Aug 18 05:34:06 PM PDT 24
Finished Aug 18 05:34:07 PM PDT 24
Peak memory 207368 kb
Host smart-c6670c34-802b-4e6b-a298-025f712688d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38420
49059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3842049059
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_non_iso_usb_traffic.3678755931
Short name T3263
Test name
Test status
Simulation time 1621849849 ps
CPU time 15.51 seconds
Started Aug 18 05:34:06 PM PDT 24
Finished Aug 18 05:34:22 PM PDT 24
Peak memory 217444 kb
Host smart-0e634f64-1146-4a0e-bdf8-f9fd1e76253e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36787
55931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_non_iso_usb_traffic.3678755931
Directory /workspace/14.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3639902429
Short name T568
Test name
Test status
Simulation time 2517183300 ps
CPU time 20.46 seconds
Started Aug 18 05:33:57 PM PDT 24
Finished Aug 18 05:34:17 PM PDT 24
Peak memory 224140 kb
Host smart-ed95a651-5b9c-4e0b-8a4a-dd9c23b29d0f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3639902429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3639902429
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2239850806
Short name T2809
Test name
Test status
Simulation time 2894420738 ps
CPU time 82.65 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:35:28 PM PDT 24
Peak memory 217392 kb
Host smart-f1495e46-5539-4e22-9a67-3c42ab43f63b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2239850806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2239850806
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.2463978019
Short name T2747
Test name
Test status
Simulation time 199856988 ps
CPU time 0.88 seconds
Started Aug 18 05:34:00 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 207488 kb
Host smart-4172f69f-ea52-4d14-9bbf-03674bb40b93
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2463978019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.2463978019
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1028290845
Short name T903
Test name
Test status
Simulation time 158229210 ps
CPU time 0.89 seconds
Started Aug 18 05:34:03 PM PDT 24
Finished Aug 18 05:34:04 PM PDT 24
Peak memory 207364 kb
Host smart-c8f40370-047e-46e4-80d3-211a1050db13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10282
90845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1028290845
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1856390124
Short name T171
Test name
Test status
Simulation time 267372393 ps
CPU time 1.09 seconds
Started Aug 18 05:34:02 PM PDT 24
Finished Aug 18 05:34:03 PM PDT 24
Peak memory 207476 kb
Host smart-087226f9-5c51-483a-90df-a7d085711d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18563
90124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1856390124
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.1214451332
Short name T3355
Test name
Test status
Simulation time 179476952 ps
CPU time 0.96 seconds
Started Aug 18 05:34:04 PM PDT 24
Finished Aug 18 05:34:05 PM PDT 24
Peak memory 207448 kb
Host smart-0f4eec79-78f1-424f-9f23-5037030a9c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12144
51332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1214451332
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.4231868272
Short name T1651
Test name
Test status
Simulation time 177250167 ps
CPU time 0.97 seconds
Started Aug 18 05:34:02 PM PDT 24
Finished Aug 18 05:34:03 PM PDT 24
Peak memory 207508 kb
Host smart-e5646e10-163f-4890-9790-3856d654ccaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42318
68272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.4231868272
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2933918412
Short name T2927
Test name
Test status
Simulation time 143660189 ps
CPU time 0.83 seconds
Started Aug 18 05:33:55 PM PDT 24
Finished Aug 18 05:33:56 PM PDT 24
Peak memory 207572 kb
Host smart-8c3e37bf-d662-4592-bc65-bc34d29869f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29339
18412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2933918412
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.4032891150
Short name T3108
Test name
Test status
Simulation time 154610306 ps
CPU time 0.86 seconds
Started Aug 18 05:34:00 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 207488 kb
Host smart-9c8f27b0-26ba-4c67-9eb3-81007ea93671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40328
91150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.4032891150
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.2158568353
Short name T2145
Test name
Test status
Simulation time 203857261 ps
CPU time 1.03 seconds
Started Aug 18 05:34:03 PM PDT 24
Finished Aug 18 05:34:05 PM PDT 24
Peak memory 207588 kb
Host smart-4e10be2e-64c6-467d-b00f-5c8708b65e17
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2158568353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.2158568353
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3823647548
Short name T3066
Test name
Test status
Simulation time 149099763 ps
CPU time 0.91 seconds
Started Aug 18 05:34:03 PM PDT 24
Finished Aug 18 05:34:04 PM PDT 24
Peak memory 207432 kb
Host smart-61c69181-fdfa-444d-b88e-7ad8baef5941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38236
47548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3823647548
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1672482943
Short name T1035
Test name
Test status
Simulation time 52224024 ps
CPU time 0.71 seconds
Started Aug 18 05:33:59 PM PDT 24
Finished Aug 18 05:33:59 PM PDT 24
Peak memory 207488 kb
Host smart-6e9f3cfb-a116-454e-ad93-4d899a2838f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16724
82943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1672482943
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.92162624
Short name T2262
Test name
Test status
Simulation time 18008571624 ps
CPU time 46.69 seconds
Started Aug 18 05:34:02 PM PDT 24
Finished Aug 18 05:34:49 PM PDT 24
Peak memory 215980 kb
Host smart-d03afae5-c70c-4954-a27f-0a3d455324ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92162
624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.92162624
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.493343053
Short name T1438
Test name
Test status
Simulation time 157874067 ps
CPU time 0.92 seconds
Started Aug 18 05:34:00 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 207580 kb
Host smart-93f40e29-9c90-4e55-9228-d5776e2fc353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49334
3053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.493343053
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3555535939
Short name T1304
Test name
Test status
Simulation time 192269182 ps
CPU time 0.93 seconds
Started Aug 18 05:34:03 PM PDT 24
Finished Aug 18 05:34:04 PM PDT 24
Peak memory 207472 kb
Host smart-fb44c28b-7114-4f7e-911c-a707301356c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35555
35939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3555535939
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3815325370
Short name T2105
Test name
Test status
Simulation time 175937839 ps
CPU time 0.89 seconds
Started Aug 18 05:34:02 PM PDT 24
Finished Aug 18 05:34:03 PM PDT 24
Peak memory 207400 kb
Host smart-4bdc097f-de07-4eba-aaa0-411aefe09063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38153
25370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3815325370
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.386189774
Short name T1327
Test name
Test status
Simulation time 189753731 ps
CPU time 0.99 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:34:06 PM PDT 24
Peak memory 207420 kb
Host smart-2d7f906b-0399-4951-a143-211369d1c2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38618
9774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.386189774
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_resume_link_active.25357622
Short name T1128
Test name
Test status
Simulation time 20162098350 ps
CPU time 24.33 seconds
Started Aug 18 05:34:01 PM PDT 24
Finished Aug 18 05:34:25 PM PDT 24
Peak memory 207576 kb
Host smart-1f1f814d-a8af-4034-a862-cd3137d852b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25357
622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_resume_link_active.25357622
Directory /workspace/14.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.1781949802
Short name T67
Test name
Test status
Simulation time 158360431 ps
CPU time 0.89 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:34:06 PM PDT 24
Peak memory 207488 kb
Host smart-e8c0ab2c-f76e-4be9-9b3e-32fa68c1ff43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17819
49802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.1781949802
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_rx_full.4057894431
Short name T967
Test name
Test status
Simulation time 301085929 ps
CPU time 1.2 seconds
Started Aug 18 05:34:06 PM PDT 24
Finished Aug 18 05:34:07 PM PDT 24
Peak memory 207456 kb
Host smart-6a8380d7-07a5-42e3-88ad-3c1b9e20f547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40578
94431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_full.4057894431
Directory /workspace/14.usbdev_rx_full/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.4018457254
Short name T769
Test name
Test status
Simulation time 149877198 ps
CPU time 0.84 seconds
Started Aug 18 05:34:00 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 207500 kb
Host smart-4f6daa12-5c62-446e-accd-e92c4175555c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40184
57254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.4018457254
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2981564878
Short name T3240
Test name
Test status
Simulation time 163893995 ps
CPU time 0.89 seconds
Started Aug 18 05:34:00 PM PDT 24
Finished Aug 18 05:34:06 PM PDT 24
Peak memory 207480 kb
Host smart-ce562aee-659e-4610-a946-5b836e39d173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29815
64878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2981564878
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3203493398
Short name T3413
Test name
Test status
Simulation time 228694368 ps
CPU time 1.03 seconds
Started Aug 18 05:34:08 PM PDT 24
Finished Aug 18 05:34:09 PM PDT 24
Peak memory 207460 kb
Host smart-c4120d85-d2f6-482d-93de-f2eae89bd594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32034
93398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3203493398
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.3211217853
Short name T218
Test name
Test status
Simulation time 1714837349 ps
CPU time 44.17 seconds
Started Aug 18 05:34:06 PM PDT 24
Finished Aug 18 05:34:50 PM PDT 24
Peak memory 215580 kb
Host smart-9de3252d-b026-47c6-aa6b-2a582294b3f9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3211217853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.3211217853
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.900383363
Short name T1733
Test name
Test status
Simulation time 148610242 ps
CPU time 0.86 seconds
Started Aug 18 05:34:00 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 207488 kb
Host smart-69ff66c2-5d50-4069-ae59-7d286213d3bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90038
3363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.900383363
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3172440249
Short name T3367
Test name
Test status
Simulation time 177612610 ps
CPU time 0.94 seconds
Started Aug 18 05:34:01 PM PDT 24
Finished Aug 18 05:34:02 PM PDT 24
Peak memory 207584 kb
Host smart-d0c47329-153b-4ee3-a50f-2156f85185ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31724
40249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3172440249
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2190322123
Short name T3572
Test name
Test status
Simulation time 1331511533 ps
CPU time 3.4 seconds
Started Aug 18 05:33:57 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 207748 kb
Host smart-ab1aaf09-e844-4660-8a10-1a3e97d3b266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21903
22123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2190322123
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.3402011656
Short name T2181
Test name
Test status
Simulation time 4198336658 ps
CPU time 43.68 seconds
Started Aug 18 05:34:02 PM PDT 24
Finished Aug 18 05:34:46 PM PDT 24
Peak memory 217656 kb
Host smart-f3ed57fe-146c-46a9-b76d-5d8247809110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34020
11656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3402011656
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.2982093279
Short name T576
Test name
Test status
Simulation time 306525190 ps
CPU time 4.4 seconds
Started Aug 18 05:34:04 PM PDT 24
Finished Aug 18 05:34:09 PM PDT 24
Peak memory 207392 kb
Host smart-051dc142-6fb9-40ba-bf62-e8a3f7fcebaf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982093279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.2982093279
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/14.usbdev_tx_rx_disruption.584453353
Short name T2916
Test name
Test status
Simulation time 588672273 ps
CPU time 1.96 seconds
Started Aug 18 05:34:08 PM PDT 24
Finished Aug 18 05:34:10 PM PDT 24
Peak memory 207536 kb
Host smart-9b33ecea-c728-4c0e-b2f1-dc392b70e6d7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584453353 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.usbdev_tx_rx_disruption.584453353
Directory /workspace/14.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/140.usbdev_endpoint_types.2459318224
Short name T466
Test name
Test status
Simulation time 587669619 ps
CPU time 1.46 seconds
Started Aug 18 05:39:10 PM PDT 24
Finished Aug 18 05:39:17 PM PDT 24
Peak memory 207456 kb
Host smart-dad6a563-482e-475d-8349-7c582bc7aa63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2459318224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_endpoint_types.2459318224
Directory /workspace/140.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/140.usbdev_tx_rx_disruption.895755978
Short name T2461
Test name
Test status
Simulation time 552961690 ps
CPU time 1.6 seconds
Started Aug 18 05:39:14 PM PDT 24
Finished Aug 18 05:39:15 PM PDT 24
Peak memory 207580 kb
Host smart-f61daaad-f173-46f3-817c-6eed2cbe7868
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895755978 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 140.usbdev_tx_rx_disruption.895755978
Directory /workspace/140.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/141.usbdev_tx_rx_disruption.3847795295
Short name T1773
Test name
Test status
Simulation time 577946577 ps
CPU time 1.68 seconds
Started Aug 18 05:39:10 PM PDT 24
Finished Aug 18 05:39:12 PM PDT 24
Peak memory 207540 kb
Host smart-e50b14c3-90aa-40ef-876a-ca23bf6567bd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847795295 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 141.usbdev_tx_rx_disruption.3847795295
Directory /workspace/141.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/142.usbdev_endpoint_types.2317310811
Short name T507
Test name
Test status
Simulation time 250990053 ps
CPU time 1.09 seconds
Started Aug 18 05:39:16 PM PDT 24
Finished Aug 18 05:39:18 PM PDT 24
Peak memory 207424 kb
Host smart-339130bb-4f22-46ce-8c96-916250549f10
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2317310811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_endpoint_types.2317310811
Directory /workspace/142.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/142.usbdev_tx_rx_disruption.1662420699
Short name T2860
Test name
Test status
Simulation time 490426715 ps
CPU time 1.45 seconds
Started Aug 18 05:39:18 PM PDT 24
Finished Aug 18 05:39:20 PM PDT 24
Peak memory 207568 kb
Host smart-f4fb9e52-f458-4fce-b80b-f135ae1d87ea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662420699 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.usbdev_tx_rx_disruption.1662420699
Directory /workspace/142.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/143.usbdev_endpoint_types.1101839957
Short name T493
Test name
Test status
Simulation time 439961728 ps
CPU time 1.41 seconds
Started Aug 18 05:39:27 PM PDT 24
Finished Aug 18 05:39:28 PM PDT 24
Peak memory 207540 kb
Host smart-3a7c533c-33e9-41a2-a10b-1718acf28db2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1101839957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_endpoint_types.1101839957
Directory /workspace/143.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/144.usbdev_endpoint_types.3695990831
Short name T2230
Test name
Test status
Simulation time 373210529 ps
CPU time 1.14 seconds
Started Aug 18 05:39:19 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207564 kb
Host smart-17be54d2-2513-44f0-8914-818b819d0fc0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3695990831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_endpoint_types.3695990831
Directory /workspace/144.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/144.usbdev_tx_rx_disruption.2748367081
Short name T973
Test name
Test status
Simulation time 532197808 ps
CPU time 1.61 seconds
Started Aug 18 05:39:29 PM PDT 24
Finished Aug 18 05:39:31 PM PDT 24
Peak memory 207564 kb
Host smart-1e1c08bd-c917-46d8-b20e-72dd8c20c9f8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748367081 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 144.usbdev_tx_rx_disruption.2748367081
Directory /workspace/144.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/145.usbdev_endpoint_types.4135636610
Short name T3551
Test name
Test status
Simulation time 356048223 ps
CPU time 1.15 seconds
Started Aug 18 05:39:30 PM PDT 24
Finished Aug 18 05:39:31 PM PDT 24
Peak memory 207456 kb
Host smart-bd990d47-bd10-45b5-8b7f-6f725584acad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4135636610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_endpoint_types.4135636610
Directory /workspace/145.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/145.usbdev_tx_rx_disruption.1633997574
Short name T674
Test name
Test status
Simulation time 457672522 ps
CPU time 1.46 seconds
Started Aug 18 05:39:09 PM PDT 24
Finished Aug 18 05:39:11 PM PDT 24
Peak memory 207488 kb
Host smart-3d47f5c5-3ee1-4463-92f1-2945eb29f0fc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633997574 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 145.usbdev_tx_rx_disruption.1633997574
Directory /workspace/145.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/146.usbdev_endpoint_types.1744349905
Short name T3244
Test name
Test status
Simulation time 226616007 ps
CPU time 0.98 seconds
Started Aug 18 05:39:12 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207504 kb
Host smart-1e8e4dad-1659-4e51-9ae4-e0a60853df80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1744349905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_endpoint_types.1744349905
Directory /workspace/146.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/146.usbdev_tx_rx_disruption.589872343
Short name T3294
Test name
Test status
Simulation time 541922912 ps
CPU time 1.7 seconds
Started Aug 18 05:39:28 PM PDT 24
Finished Aug 18 05:39:30 PM PDT 24
Peak memory 207544 kb
Host smart-209988e4-db13-4fef-8659-d4e29b682db9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589872343 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 146.usbdev_tx_rx_disruption.589872343
Directory /workspace/146.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/147.usbdev_endpoint_types.1682997135
Short name T413
Test name
Test status
Simulation time 268422087 ps
CPU time 0.99 seconds
Started Aug 18 05:39:33 PM PDT 24
Finished Aug 18 05:39:34 PM PDT 24
Peak memory 207496 kb
Host smart-0d440003-fea9-4c47-82c7-0e258ba190c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1682997135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_endpoint_types.1682997135
Directory /workspace/147.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/147.usbdev_tx_rx_disruption.2843458866
Short name T1426
Test name
Test status
Simulation time 502319608 ps
CPU time 1.49 seconds
Started Aug 18 05:39:10 PM PDT 24
Finished Aug 18 05:39:12 PM PDT 24
Peak memory 207544 kb
Host smart-6f609fe9-3bf5-4bf6-9779-114f9b042dfe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843458866 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 147.usbdev_tx_rx_disruption.2843458866
Directory /workspace/147.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/148.usbdev_endpoint_types.2101694078
Short name T435
Test name
Test status
Simulation time 442561232 ps
CPU time 1.36 seconds
Started Aug 18 05:39:26 PM PDT 24
Finished Aug 18 05:39:28 PM PDT 24
Peak memory 207568 kb
Host smart-22804c12-53c4-49bc-ba14-97195381d3d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2101694078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_endpoint_types.2101694078
Directory /workspace/148.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/148.usbdev_tx_rx_disruption.3810938171
Short name T869
Test name
Test status
Simulation time 500364579 ps
CPU time 1.59 seconds
Started Aug 18 05:39:23 PM PDT 24
Finished Aug 18 05:39:25 PM PDT 24
Peak memory 207472 kb
Host smart-68bf4b17-c43d-4cfa-af17-d3ee0b9b60fe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810938171 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.usbdev_tx_rx_disruption.3810938171
Directory /workspace/148.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/149.usbdev_endpoint_types.1095730752
Short name T2842
Test name
Test status
Simulation time 220172665 ps
CPU time 0.94 seconds
Started Aug 18 05:39:34 PM PDT 24
Finished Aug 18 05:39:35 PM PDT 24
Peak memory 207456 kb
Host smart-ae5038d4-5c78-4c54-a7e4-af06d0b1e0bc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1095730752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_endpoint_types.1095730752
Directory /workspace/149.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/149.usbdev_tx_rx_disruption.2765044100
Short name T989
Test name
Test status
Simulation time 510904990 ps
CPU time 1.64 seconds
Started Aug 18 05:39:21 PM PDT 24
Finished Aug 18 05:39:23 PM PDT 24
Peak memory 207516 kb
Host smart-9046aeaa-cd7f-4ff2-b002-c8a3755b8d5c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765044100 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.usbdev_tx_rx_disruption.2765044100
Directory /workspace/149.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.130062025
Short name T925
Test name
Test status
Simulation time 93655163 ps
CPU time 0.76 seconds
Started Aug 18 05:34:17 PM PDT 24
Finished Aug 18 05:34:18 PM PDT 24
Peak memory 207452 kb
Host smart-5fa9edeb-b810-4610-9892-180c809fa54f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=130062025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.130062025
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.516776001
Short name T2588
Test name
Test status
Simulation time 10193865897 ps
CPU time 13.66 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:34:19 PM PDT 24
Peak memory 207524 kb
Host smart-8bc416d0-d399-4d23-9d11-c5951165b493
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516776001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_ao
n_wake_disconnect.516776001
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.3961812721
Short name T3446
Test name
Test status
Simulation time 20008978287 ps
CPU time 22.98 seconds
Started Aug 18 05:34:04 PM PDT 24
Finished Aug 18 05:34:27 PM PDT 24
Peak memory 207524 kb
Host smart-4c462d86-655a-4739-9222-e97330c4409b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961812721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.3961812721
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2013886465
Short name T2255
Test name
Test status
Simulation time 23500371135 ps
CPU time 28.12 seconds
Started Aug 18 05:34:04 PM PDT 24
Finished Aug 18 05:34:32 PM PDT 24
Peak memory 215740 kb
Host smart-11987cc6-75aa-48d6-a78c-05d38037253c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013886465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.2013886465
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2949308439
Short name T1672
Test name
Test status
Simulation time 185948973 ps
CPU time 0.85 seconds
Started Aug 18 05:34:01 PM PDT 24
Finished Aug 18 05:34:02 PM PDT 24
Peak memory 207484 kb
Host smart-a20465df-0e3f-424d-8f61-df41fed938e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29493
08439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2949308439
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.1891345452
Short name T1436
Test name
Test status
Simulation time 148505052 ps
CPU time 0.82 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:34:06 PM PDT 24
Peak memory 207568 kb
Host smart-9795a747-0736-4733-882e-9c41af5d0429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18913
45452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.1891345452
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.3984087081
Short name T2247
Test name
Test status
Simulation time 343780910 ps
CPU time 1.32 seconds
Started Aug 18 05:34:06 PM PDT 24
Finished Aug 18 05:34:08 PM PDT 24
Peak memory 207544 kb
Host smart-e2e9adb7-5b73-47e7-8c65-5034895b784e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39840
87081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.3984087081
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2024876826
Short name T2876
Test name
Test status
Simulation time 1013878092 ps
CPU time 2.81 seconds
Started Aug 18 05:34:06 PM PDT 24
Finished Aug 18 05:34:09 PM PDT 24
Peak memory 207628 kb
Host smart-58c12bb0-4480-49c7-9e07-b3f85fe2f66b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2024876826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2024876826
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.2540995857
Short name T222
Test name
Test status
Simulation time 28501137482 ps
CPU time 56.66 seconds
Started Aug 18 05:34:02 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207788 kb
Host smart-2dc7d8f7-7876-4990-9315-f461a7345d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25409
95857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.2540995857
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.51733846
Short name T2121
Test name
Test status
Simulation time 1850662716 ps
CPU time 42.66 seconds
Started Aug 18 05:34:01 PM PDT 24
Finished Aug 18 05:34:44 PM PDT 24
Peak memory 207760 kb
Host smart-3a005052-1a1f-4106-9e41-3c9ab5ef5545
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51733846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.51733846
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.2375468589
Short name T2346
Test name
Test status
Simulation time 900346432 ps
CPU time 2.33 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:34:07 PM PDT 24
Peak memory 207576 kb
Host smart-8d1dd38e-af21-4f56-af1e-9abdd11fe308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23754
68589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.2375468589
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.2618629259
Short name T2401
Test name
Test status
Simulation time 186300672 ps
CPU time 0.92 seconds
Started Aug 18 05:34:01 PM PDT 24
Finished Aug 18 05:34:02 PM PDT 24
Peak memory 207528 kb
Host smart-714ca4d4-5953-427f-b761-1cdf9ef8be3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26186
29259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2618629259
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.757626477
Short name T646
Test name
Test status
Simulation time 41145999 ps
CPU time 0.78 seconds
Started Aug 18 05:34:00 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 207492 kb
Host smart-f52a2985-8067-45cf-831d-d4f93d66c925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75762
6477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.757626477
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.412622457
Short name T1942
Test name
Test status
Simulation time 856075935 ps
CPU time 2.21 seconds
Started Aug 18 05:34:04 PM PDT 24
Finished Aug 18 05:34:06 PM PDT 24
Peak memory 207496 kb
Host smart-57720451-b517-4c0a-b55d-906697207a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41262
2457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.412622457
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2432939192
Short name T1449
Test name
Test status
Simulation time 260742661 ps
CPU time 1.64 seconds
Started Aug 18 05:34:07 PM PDT 24
Finished Aug 18 05:34:09 PM PDT 24
Peak memory 207680 kb
Host smart-f2d04d1e-7add-439b-ad55-da7aa1940d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24329
39192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2432939192
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.371269306
Short name T1796
Test name
Test status
Simulation time 195608911 ps
CPU time 1 seconds
Started Aug 18 05:34:06 PM PDT 24
Finished Aug 18 05:34:07 PM PDT 24
Peak memory 215620 kb
Host smart-8a33d05c-391f-4dd1-bbb8-0d75354dce18
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=371269306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.371269306
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3389975891
Short name T1030
Test name
Test status
Simulation time 194845676 ps
CPU time 0.93 seconds
Started Aug 18 05:34:04 PM PDT 24
Finished Aug 18 05:34:05 PM PDT 24
Peak memory 207404 kb
Host smart-d109ae50-243c-4cab-a836-e7f7d3e980c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33899
75891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3389975891
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.555350577
Short name T781
Test name
Test status
Simulation time 210534244 ps
CPU time 0.94 seconds
Started Aug 18 05:34:08 PM PDT 24
Finished Aug 18 05:34:09 PM PDT 24
Peak memory 207472 kb
Host smart-e8a68589-542e-4bc7-b240-e8d4a4caf2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55535
0577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.555350577
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.1196621655
Short name T2940
Test name
Test status
Simulation time 3813196475 ps
CPU time 30.26 seconds
Started Aug 18 05:34:01 PM PDT 24
Finished Aug 18 05:34:32 PM PDT 24
Peak memory 217912 kb
Host smart-1f07441e-43d0-4452-8763-d447ed584336
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1196621655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.1196621655
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.4294842153
Short name T2294
Test name
Test status
Simulation time 13500721055 ps
CPU time 90.41 seconds
Started Aug 18 05:34:00 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 207768 kb
Host smart-0f6bab40-4044-45bd-8ada-346691cf3349
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4294842153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.4294842153
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3004372764
Short name T1689
Test name
Test status
Simulation time 169854518 ps
CPU time 0.94 seconds
Started Aug 18 05:34:06 PM PDT 24
Finished Aug 18 05:34:07 PM PDT 24
Peak memory 207544 kb
Host smart-47131058-5705-4dcb-af4d-793c6a9e8b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30043
72764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3004372764
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.4218727604
Short name T2739
Test name
Test status
Simulation time 33298225679 ps
CPU time 56.77 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:35:02 PM PDT 24
Peak memory 207708 kb
Host smart-96123e00-649d-46c5-b334-443a7d36bf34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42187
27604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.4218727604
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.1738973863
Short name T956
Test name
Test status
Simulation time 10688922600 ps
CPU time 12.7 seconds
Started Aug 18 05:34:07 PM PDT 24
Finished Aug 18 05:34:20 PM PDT 24
Peak memory 207792 kb
Host smart-0b986a4d-3211-4bb3-af07-dd1520cbc57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17389
73863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.1738973863
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.773787287
Short name T3037
Test name
Test status
Simulation time 3128882810 ps
CPU time 24.27 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:34:30 PM PDT 24
Peak memory 216048 kb
Host smart-6b96af00-45cf-4299-9f13-1aa9a9c06c9c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=773787287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.773787287
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2108230688
Short name T612
Test name
Test status
Simulation time 3863299267 ps
CPU time 30.27 seconds
Started Aug 18 05:34:07 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 215872 kb
Host smart-d0dd7935-7081-4f00-baaf-20e22bb763bd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2108230688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2108230688
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.4077213274
Short name T928
Test name
Test status
Simulation time 234411082 ps
CPU time 0.95 seconds
Started Aug 18 05:34:04 PM PDT 24
Finished Aug 18 05:34:05 PM PDT 24
Peak memory 207480 kb
Host smart-7966dc11-9e4d-4229-a131-f2e72f057599
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4077213274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.4077213274
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3636771030
Short name T1448
Test name
Test status
Simulation time 187985670 ps
CPU time 0.92 seconds
Started Aug 18 05:34:09 PM PDT 24
Finished Aug 18 05:34:10 PM PDT 24
Peak memory 207516 kb
Host smart-78d58210-7bee-4cd4-8878-859af3f23501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36367
71030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3636771030
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_non_iso_usb_traffic.2130530924
Short name T848
Test name
Test status
Simulation time 2620524220 ps
CPU time 19.48 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:34:25 PM PDT 24
Peak memory 217952 kb
Host smart-f54fb136-5049-41fb-a816-0d0727ec2c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21305
30924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_non_iso_usb_traffic.2130530924
Directory /workspace/15.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.2088993433
Short name T1975
Test name
Test status
Simulation time 2597902228 ps
CPU time 24.38 seconds
Started Aug 18 05:34:04 PM PDT 24
Finished Aug 18 05:34:29 PM PDT 24
Peak memory 217776 kb
Host smart-f60b30df-2a01-483c-b164-b5a37a15da3b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2088993433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.2088993433
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1568965178
Short name T2987
Test name
Test status
Simulation time 175766103 ps
CPU time 0.94 seconds
Started Aug 18 05:34:06 PM PDT 24
Finished Aug 18 05:34:07 PM PDT 24
Peak memory 207488 kb
Host smart-2ffa32a9-6d59-43a3-9c65-f4c0e6acd03d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1568965178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1568965178
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.92839093
Short name T1015
Test name
Test status
Simulation time 158220101 ps
CPU time 0.86 seconds
Started Aug 18 05:34:16 PM PDT 24
Finished Aug 18 05:34:17 PM PDT 24
Peak memory 207520 kb
Host smart-3396c4a6-ca5e-4a79-8f11-a101dcf97412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92839
093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.92839093
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2898692995
Short name T2894
Test name
Test status
Simulation time 148944036 ps
CPU time 0.85 seconds
Started Aug 18 05:34:04 PM PDT 24
Finished Aug 18 05:34:05 PM PDT 24
Peak memory 207404 kb
Host smart-511ced53-c471-4de9-ba50-0a869372d76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28986
92995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2898692995
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3244752980
Short name T3501
Test name
Test status
Simulation time 183552261 ps
CPU time 0.9 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:34:06 PM PDT 24
Peak memory 207432 kb
Host smart-3e039614-996e-42f0-97ac-55ec42722f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32447
52980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3244752980
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.204366993
Short name T1921
Test name
Test status
Simulation time 178943167 ps
CPU time 1.01 seconds
Started Aug 18 05:34:01 PM PDT 24
Finished Aug 18 05:34:03 PM PDT 24
Peak memory 207572 kb
Host smart-388e1dfc-940c-459f-b69c-fa693136a83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20436
6993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.204366993
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.125316743
Short name T1374
Test name
Test status
Simulation time 169224391 ps
CPU time 0.89 seconds
Started Aug 18 05:34:02 PM PDT 24
Finished Aug 18 05:34:03 PM PDT 24
Peak memory 207476 kb
Host smart-d38183c9-ff3e-4823-9258-cf42c3bd23cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12531
6743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.125316743
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.4158351441
Short name T3495
Test name
Test status
Simulation time 215700237 ps
CPU time 1.02 seconds
Started Aug 18 05:34:07 PM PDT 24
Finished Aug 18 05:34:08 PM PDT 24
Peak memory 207576 kb
Host smart-9be1201c-022d-482b-9ee0-db2edf44b27e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4158351441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.4158351441
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3221698962
Short name T2174
Test name
Test status
Simulation time 143469490 ps
CPU time 0.83 seconds
Started Aug 18 05:34:09 PM PDT 24
Finished Aug 18 05:34:10 PM PDT 24
Peak memory 207412 kb
Host smart-6c366cfc-7c06-4c51-b36e-3f5f5d92deab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32216
98962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3221698962
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.2431240944
Short name T3022
Test name
Test status
Simulation time 32772819 ps
CPU time 0.71 seconds
Started Aug 18 05:34:10 PM PDT 24
Finished Aug 18 05:34:11 PM PDT 24
Peak memory 207508 kb
Host smart-dbd8350c-73e2-4965-9f4c-2ccd9d52db81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24312
40944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.2431240944
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.4130436196
Short name T3119
Test name
Test status
Simulation time 12016331484 ps
CPU time 32.3 seconds
Started Aug 18 05:34:13 PM PDT 24
Finished Aug 18 05:34:45 PM PDT 24
Peak memory 215996 kb
Host smart-e34e394b-6f94-4d83-a295-982a355dbdaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41304
36196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.4130436196
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2310010150
Short name T1911
Test name
Test status
Simulation time 175148558 ps
CPU time 0.85 seconds
Started Aug 18 05:34:30 PM PDT 24
Finished Aug 18 05:34:30 PM PDT 24
Peak memory 207376 kb
Host smart-09f7af31-be94-4f1d-92d0-b4412ad2740f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23100
10150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2310010150
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1061672052
Short name T1414
Test name
Test status
Simulation time 204593612 ps
CPU time 0.91 seconds
Started Aug 18 05:34:16 PM PDT 24
Finished Aug 18 05:34:17 PM PDT 24
Peak memory 207528 kb
Host smart-540e6d66-0a14-4b55-b5a9-dd3d2ecb72ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10616
72052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1061672052
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.1699381569
Short name T2044
Test name
Test status
Simulation time 158310731 ps
CPU time 0.9 seconds
Started Aug 18 05:34:18 PM PDT 24
Finished Aug 18 05:34:19 PM PDT 24
Peak memory 207476 kb
Host smart-1fed594e-d212-4916-8f69-0f6c996d1b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16993
81569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.1699381569
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2080594557
Short name T1233
Test name
Test status
Simulation time 156408314 ps
CPU time 0.88 seconds
Started Aug 18 05:34:07 PM PDT 24
Finished Aug 18 05:34:08 PM PDT 24
Peak memory 207508 kb
Host smart-c349573d-75f6-4c0a-b255-a2187ff74489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20805
94557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2080594557
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_resume_link_active.4083967922
Short name T3083
Test name
Test status
Simulation time 20163893332 ps
CPU time 23.27 seconds
Started Aug 18 05:34:20 PM PDT 24
Finished Aug 18 05:34:44 PM PDT 24
Peak memory 207620 kb
Host smart-1bb466f5-8f2b-4eb4-9dca-9d4934d21584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40839
67922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_resume_link_active.4083967922
Directory /workspace/15.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2529953829
Short name T1905
Test name
Test status
Simulation time 195128916 ps
CPU time 0.87 seconds
Started Aug 18 05:34:07 PM PDT 24
Finished Aug 18 05:34:08 PM PDT 24
Peak memory 207424 kb
Host smart-bc09d24f-a341-4ee2-890e-5685dc1a32b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25299
53829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2529953829
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_rx_full.187630216
Short name T3122
Test name
Test status
Simulation time 281057921 ps
CPU time 1.22 seconds
Started Aug 18 05:34:13 PM PDT 24
Finished Aug 18 05:34:14 PM PDT 24
Peak memory 207392 kb
Host smart-263c540f-2606-4f3d-b098-cdd5b5c002c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18763
0216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_full.187630216
Directory /workspace/15.usbdev_rx_full/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3756040601
Short name T2226
Test name
Test status
Simulation time 154374678 ps
CPU time 0.86 seconds
Started Aug 18 05:34:04 PM PDT 24
Finished Aug 18 05:34:05 PM PDT 24
Peak memory 207552 kb
Host smart-cc7ae253-fd38-4eb3-9509-d5b9978357a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37560
40601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3756040601
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.3055158131
Short name T1421
Test name
Test status
Simulation time 189251275 ps
CPU time 0.91 seconds
Started Aug 18 05:34:13 PM PDT 24
Finished Aug 18 05:34:14 PM PDT 24
Peak memory 207504 kb
Host smart-0e576710-9d66-4c78-9f57-74003cc5969c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30551
58131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.3055158131
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.181327315
Short name T2971
Test name
Test status
Simulation time 197912473 ps
CPU time 0.92 seconds
Started Aug 18 05:34:13 PM PDT 24
Finished Aug 18 05:34:14 PM PDT 24
Peak memory 207488 kb
Host smart-a120fe7b-392c-47db-8801-74a344c7d2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18132
7315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.181327315
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.2932662173
Short name T2911
Test name
Test status
Simulation time 2729994931 ps
CPU time 20.57 seconds
Started Aug 18 05:34:09 PM PDT 24
Finished Aug 18 05:34:29 PM PDT 24
Peak memory 217928 kb
Host smart-6cd6846c-d589-4902-9415-d482583c2f2d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2932662173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.2932662173
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.159146128
Short name T1663
Test name
Test status
Simulation time 170299618 ps
CPU time 0.9 seconds
Started Aug 18 05:34:14 PM PDT 24
Finished Aug 18 05:34:15 PM PDT 24
Peak memory 207500 kb
Host smart-ddf9413e-90a3-4b92-aad6-4c5b01f28f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15914
6128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.159146128
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.279155708
Short name T1354
Test name
Test status
Simulation time 157390557 ps
CPU time 0.86 seconds
Started Aug 18 05:34:18 PM PDT 24
Finished Aug 18 05:34:19 PM PDT 24
Peak memory 207416 kb
Host smart-1dfd7a52-6834-42ed-9bfc-742542e631c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27915
5708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.279155708
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.1087315029
Short name T3211
Test name
Test status
Simulation time 877355311 ps
CPU time 2.22 seconds
Started Aug 18 05:34:07 PM PDT 24
Finished Aug 18 05:34:09 PM PDT 24
Peak memory 207724 kb
Host smart-96d9d943-f631-4432-a2fb-4ee4f41048ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10873
15029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.1087315029
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.2793438021
Short name T3620
Test name
Test status
Simulation time 1941844300 ps
CPU time 19.19 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:34:24 PM PDT 24
Peak memory 224064 kb
Host smart-802d2b39-7b3c-434a-a838-5638d609e33d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27934
38021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.2793438021
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.3111785519
Short name T2282
Test name
Test status
Simulation time 433473946 ps
CPU time 7.89 seconds
Started Aug 18 05:34:05 PM PDT 24
Finished Aug 18 05:34:12 PM PDT 24
Peak memory 207540 kb
Host smart-8c61686e-bf68-4425-b6b7-9255a44aeaa8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111785519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.3111785519
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/15.usbdev_tx_rx_disruption.1265064422
Short name T2943
Test name
Test status
Simulation time 484910849 ps
CPU time 1.63 seconds
Started Aug 18 05:34:11 PM PDT 24
Finished Aug 18 05:34:13 PM PDT 24
Peak memory 207508 kb
Host smart-88dcfadb-5497-4546-8060-fd6f59215e14
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265064422 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.usbdev_tx_rx_disruption.1265064422
Directory /workspace/15.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/150.usbdev_endpoint_types.2426777844
Short name T391
Test name
Test status
Simulation time 451426383 ps
CPU time 1.42 seconds
Started Aug 18 05:39:19 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207464 kb
Host smart-61db2d52-505f-4215-955e-dad7a867d7dd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2426777844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_endpoint_types.2426777844
Directory /workspace/150.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/150.usbdev_tx_rx_disruption.3488459694
Short name T2673
Test name
Test status
Simulation time 456660081 ps
CPU time 1.37 seconds
Started Aug 18 05:39:26 PM PDT 24
Finished Aug 18 05:39:28 PM PDT 24
Peak memory 207544 kb
Host smart-ce23794c-2a80-41a9-8431-ba8fba7aa370
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488459694 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.usbdev_tx_rx_disruption.3488459694
Directory /workspace/150.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/151.usbdev_endpoint_types.536222531
Short name T1899
Test name
Test status
Simulation time 164527312 ps
CPU time 0.86 seconds
Started Aug 18 05:39:15 PM PDT 24
Finished Aug 18 05:39:16 PM PDT 24
Peak memory 207460 kb
Host smart-dd3c3091-7724-480d-b9f6-d586594e0024
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=536222531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_endpoint_types.536222531
Directory /workspace/151.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/151.usbdev_tx_rx_disruption.2867709748
Short name T205
Test name
Test status
Simulation time 595594958 ps
CPU time 1.67 seconds
Started Aug 18 05:39:27 PM PDT 24
Finished Aug 18 05:39:34 PM PDT 24
Peak memory 207592 kb
Host smart-d1a4e659-40f6-41d6-83b2-e34303bbe193
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867709748 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.usbdev_tx_rx_disruption.2867709748
Directory /workspace/151.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/152.usbdev_endpoint_types.3801560567
Short name T492
Test name
Test status
Simulation time 318905464 ps
CPU time 1.11 seconds
Started Aug 18 05:39:16 PM PDT 24
Finished Aug 18 05:39:17 PM PDT 24
Peak memory 207464 kb
Host smart-1e30722e-554c-45ce-b035-bf79c00c0322
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3801560567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_endpoint_types.3801560567
Directory /workspace/152.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/152.usbdev_tx_rx_disruption.284374234
Short name T2086
Test name
Test status
Simulation time 672599646 ps
CPU time 1.8 seconds
Started Aug 18 05:39:21 PM PDT 24
Finished Aug 18 05:39:23 PM PDT 24
Peak memory 207588 kb
Host smart-cf4a500d-3e1c-434b-8195-724d13b3059d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284374234 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 152.usbdev_tx_rx_disruption.284374234
Directory /workspace/152.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/153.usbdev_endpoint_types.1872826942
Short name T2043
Test name
Test status
Simulation time 175969445 ps
CPU time 0.96 seconds
Started Aug 18 05:39:22 PM PDT 24
Finished Aug 18 05:39:23 PM PDT 24
Peak memory 207548 kb
Host smart-2bb80720-d0a3-4313-b13e-157d95f7e829
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1872826942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_endpoint_types.1872826942
Directory /workspace/153.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/154.usbdev_endpoint_types.2230280133
Short name T1633
Test name
Test status
Simulation time 183442917 ps
CPU time 0.96 seconds
Started Aug 18 05:39:32 PM PDT 24
Finished Aug 18 05:39:33 PM PDT 24
Peak memory 207528 kb
Host smart-833ecf76-fec7-49f5-8a0a-90b2fc3d9200
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2230280133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_endpoint_types.2230280133
Directory /workspace/154.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/154.usbdev_tx_rx_disruption.2452826006
Short name T1087
Test name
Test status
Simulation time 541765946 ps
CPU time 1.58 seconds
Started Aug 18 05:39:15 PM PDT 24
Finished Aug 18 05:39:16 PM PDT 24
Peak memory 207528 kb
Host smart-0d166a87-fc07-4535-ae3a-79d5ed49c9df
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452826006 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.usbdev_tx_rx_disruption.2452826006
Directory /workspace/154.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/155.usbdev_endpoint_types.2729777358
Short name T420
Test name
Test status
Simulation time 396358669 ps
CPU time 1.26 seconds
Started Aug 18 05:39:30 PM PDT 24
Finished Aug 18 05:39:37 PM PDT 24
Peak memory 207428 kb
Host smart-e33a3a19-b1cb-41fe-a5d4-c62a048f48db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2729777358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_endpoint_types.2729777358
Directory /workspace/155.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/155.usbdev_tx_rx_disruption.3248570871
Short name T104
Test name
Test status
Simulation time 471724665 ps
CPU time 1.55 seconds
Started Aug 18 05:39:16 PM PDT 24
Finished Aug 18 05:39:18 PM PDT 24
Peak memory 207580 kb
Host smart-4f89b21c-1d52-43d6-80a9-1504bbc530b9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248570871 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.usbdev_tx_rx_disruption.3248570871
Directory /workspace/155.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/156.usbdev_endpoint_types.1620364078
Short name T473
Test name
Test status
Simulation time 458198792 ps
CPU time 1.39 seconds
Started Aug 18 05:39:39 PM PDT 24
Finished Aug 18 05:39:41 PM PDT 24
Peak memory 207496 kb
Host smart-32aa624f-e015-4935-9fef-3066af4b7cc4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1620364078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_endpoint_types.1620364078
Directory /workspace/156.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/156.usbdev_tx_rx_disruption.369189612
Short name T1008
Test name
Test status
Simulation time 479407624 ps
CPU time 1.4 seconds
Started Aug 18 05:39:18 PM PDT 24
Finished Aug 18 05:39:19 PM PDT 24
Peak memory 207536 kb
Host smart-dc3a80be-f7f9-4f40-8c9c-087395fb64cc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369189612 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 156.usbdev_tx_rx_disruption.369189612
Directory /workspace/156.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/157.usbdev_endpoint_types.648718682
Short name T477
Test name
Test status
Simulation time 183088754 ps
CPU time 0.91 seconds
Started Aug 18 05:39:21 PM PDT 24
Finished Aug 18 05:39:22 PM PDT 24
Peak memory 207496 kb
Host smart-d5c895c0-2181-4eeb-8c8f-d604797bd1cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=648718682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_endpoint_types.648718682
Directory /workspace/157.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/157.usbdev_tx_rx_disruption.1194749345
Short name T2081
Test name
Test status
Simulation time 444558602 ps
CPU time 1.32 seconds
Started Aug 18 05:39:11 PM PDT 24
Finished Aug 18 05:39:12 PM PDT 24
Peak memory 207568 kb
Host smart-22d6548e-5fd6-4900-b500-8f637a7f8662
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194749345 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.usbdev_tx_rx_disruption.1194749345
Directory /workspace/157.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/158.usbdev_tx_rx_disruption.2219261220
Short name T3468
Test name
Test status
Simulation time 636786775 ps
CPU time 1.72 seconds
Started Aug 18 05:39:20 PM PDT 24
Finished Aug 18 05:39:22 PM PDT 24
Peak memory 207472 kb
Host smart-aac50db0-e129-4352-beda-65a76f47f798
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219261220 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 158.usbdev_tx_rx_disruption.2219261220
Directory /workspace/158.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/159.usbdev_endpoint_types.3574726451
Short name T440
Test name
Test status
Simulation time 261730932 ps
CPU time 0.99 seconds
Started Aug 18 05:39:18 PM PDT 24
Finished Aug 18 05:39:19 PM PDT 24
Peak memory 207516 kb
Host smart-9b5d40b6-aedd-421d-8f2e-474c1ceee030
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3574726451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_endpoint_types.3574726451
Directory /workspace/159.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/159.usbdev_tx_rx_disruption.4265515074
Short name T1918
Test name
Test status
Simulation time 491954310 ps
CPU time 1.49 seconds
Started Aug 18 05:39:13 PM PDT 24
Finished Aug 18 05:39:15 PM PDT 24
Peak memory 207568 kb
Host smart-0ca89a6e-535c-491a-9f4b-f00831ec3a1e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265515074 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.usbdev_tx_rx_disruption.4265515074
Directory /workspace/159.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.1788370625
Short name T3589
Test name
Test status
Simulation time 43729915 ps
CPU time 0.66 seconds
Started Aug 18 05:34:28 PM PDT 24
Finished Aug 18 05:34:29 PM PDT 24
Peak memory 207412 kb
Host smart-fb0a70b9-c759-4d80-abe5-a8fca39cfeed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1788370625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.1788370625
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3143853983
Short name T3568
Test name
Test status
Simulation time 10436677669 ps
CPU time 13.82 seconds
Started Aug 18 05:34:17 PM PDT 24
Finished Aug 18 05:34:31 PM PDT 24
Peak memory 207764 kb
Host smart-bd4cfd6a-b663-4565-a3cc-b07f08cd08d7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143853983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_disconnect.3143853983
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.2139084754
Short name T16
Test name
Test status
Simulation time 19879142105 ps
CPU time 25.73 seconds
Started Aug 18 05:34:16 PM PDT 24
Finished Aug 18 05:34:42 PM PDT 24
Peak memory 207840 kb
Host smart-2704ea01-9d44-4ea5-a4d5-cb364e0b4e39
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139084754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2139084754
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.4200289855
Short name T2185
Test name
Test status
Simulation time 25529928955 ps
CPU time 31.96 seconds
Started Aug 18 05:34:29 PM PDT 24
Finished Aug 18 05:35:01 PM PDT 24
Peak memory 215968 kb
Host smart-5a302299-85e6-4b24-ac41-9677c0f5dcbe
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200289855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_resume.4200289855
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2271450005
Short name T630
Test name
Test status
Simulation time 184555945 ps
CPU time 0.89 seconds
Started Aug 18 05:34:11 PM PDT 24
Finished Aug 18 05:34:12 PM PDT 24
Peak memory 207480 kb
Host smart-77a6d6e1-e844-4e6d-92c0-41e3ff57ef27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22714
50005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2271450005
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.1192887742
Short name T1623
Test name
Test status
Simulation time 148428035 ps
CPU time 0.87 seconds
Started Aug 18 05:34:07 PM PDT 24
Finished Aug 18 05:34:08 PM PDT 24
Peak memory 207472 kb
Host smart-368d87ff-57cf-4de9-ab83-19dbe26fc9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11928
87742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.1192887742
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.2632759756
Short name T1512
Test name
Test status
Simulation time 435675078 ps
CPU time 1.49 seconds
Started Aug 18 05:34:07 PM PDT 24
Finished Aug 18 05:34:09 PM PDT 24
Peak memory 207472 kb
Host smart-b1562096-e758-4486-bb28-142040ed14a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26327
59756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.2632759756
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1304468681
Short name T2950
Test name
Test status
Simulation time 995327357 ps
CPU time 2.8 seconds
Started Aug 18 05:34:19 PM PDT 24
Finished Aug 18 05:34:22 PM PDT 24
Peak memory 207680 kb
Host smart-2da81a29-ddd9-4d6c-84b9-2db1fc3576f9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1304468681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1304468681
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3758311996
Short name T2417
Test name
Test status
Simulation time 18692266120 ps
CPU time 34.42 seconds
Started Aug 18 05:34:08 PM PDT 24
Finished Aug 18 05:34:42 PM PDT 24
Peak memory 207716 kb
Host smart-77a7d66e-963b-4bb8-81f1-65ecd7002247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37583
11996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3758311996
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.788253128
Short name T2019
Test name
Test status
Simulation time 2074832064 ps
CPU time 18.21 seconds
Started Aug 18 05:34:09 PM PDT 24
Finished Aug 18 05:34:27 PM PDT 24
Peak memory 207716 kb
Host smart-6cff5263-2740-4c1a-878c-3e66344a46c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788253128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.788253128
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.1236971664
Short name T1319
Test name
Test status
Simulation time 968266796 ps
CPU time 2.3 seconds
Started Aug 18 05:34:10 PM PDT 24
Finished Aug 18 05:34:13 PM PDT 24
Peak memory 207500 kb
Host smart-edc0e557-b39e-4ebc-ab66-254711f2ae60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12369
71664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.1236971664
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.1461796153
Short name T946
Test name
Test status
Simulation time 155992201 ps
CPU time 0.83 seconds
Started Aug 18 05:34:20 PM PDT 24
Finished Aug 18 05:34:21 PM PDT 24
Peak memory 207548 kb
Host smart-895559a2-0fa1-49e6-a5e9-c982ddf8ba0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14617
96153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.1461796153
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1602922894
Short name T2003
Test name
Test status
Simulation time 35107823 ps
CPU time 0.69 seconds
Started Aug 18 05:34:29 PM PDT 24
Finished Aug 18 05:34:30 PM PDT 24
Peak memory 207440 kb
Host smart-7aa24217-0a55-49eb-a467-a57fae0cdc73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16029
22894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1602922894
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.3036695344
Short name T3357
Test name
Test status
Simulation time 676530142 ps
CPU time 1.95 seconds
Started Aug 18 05:34:32 PM PDT 24
Finished Aug 18 05:34:34 PM PDT 24
Peak memory 207684 kb
Host smart-a92330f9-3553-45d7-993c-04c57e534ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30366
95344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.3036695344
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_types.3151413195
Short name T2201
Test name
Test status
Simulation time 391492533 ps
CPU time 1.19 seconds
Started Aug 18 05:34:20 PM PDT 24
Finished Aug 18 05:34:21 PM PDT 24
Peak memory 207536 kb
Host smart-d65fd2a9-7160-4fba-b805-fcd5d75d92b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3151413195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_types.3151413195
Directory /workspace/16.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.1160414870
Short name T2674
Test name
Test status
Simulation time 176305235 ps
CPU time 1.76 seconds
Started Aug 18 05:34:30 PM PDT 24
Finished Aug 18 05:34:31 PM PDT 24
Peak memory 207452 kb
Host smart-eab33bc0-c2f5-4daa-9191-3a223a0a928d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11604
14870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.1160414870
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.2636934408
Short name T554
Test name
Test status
Simulation time 185160745 ps
CPU time 1.03 seconds
Started Aug 18 05:34:28 PM PDT 24
Finished Aug 18 05:34:29 PM PDT 24
Peak memory 215896 kb
Host smart-3c9caf96-eed6-4ee3-89bb-2e81a3440395
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2636934408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.2636934408
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1938212435
Short name T1713
Test name
Test status
Simulation time 142412040 ps
CPU time 0.83 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:36 PM PDT 24
Peak memory 207472 kb
Host smart-aec075c2-7870-4895-b6f9-a8d256b3631d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19382
12435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1938212435
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4247092181
Short name T3549
Test name
Test status
Simulation time 232532676 ps
CPU time 0.97 seconds
Started Aug 18 05:34:20 PM PDT 24
Finished Aug 18 05:34:21 PM PDT 24
Peak memory 207528 kb
Host smart-e994f352-0870-4914-8c2d-57a0109529a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42470
92181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4247092181
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.170903493
Short name T2561
Test name
Test status
Simulation time 4902919768 ps
CPU time 48.34 seconds
Started Aug 18 05:34:23 PM PDT 24
Finished Aug 18 05:35:11 PM PDT 24
Peak memory 217540 kb
Host smart-efafb6d4-16b9-4ec6-bf57-dbb71d5d2246
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=170903493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.170903493
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.1394433618
Short name T692
Test name
Test status
Simulation time 8902121635 ps
CPU time 59.09 seconds
Started Aug 18 05:34:16 PM PDT 24
Finished Aug 18 05:35:15 PM PDT 24
Peak memory 207800 kb
Host smart-dca0c2bd-120e-47de-8494-f82563b88c0b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1394433618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.1394433618
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2428180413
Short name T1592
Test name
Test status
Simulation time 226799761 ps
CPU time 0.98 seconds
Started Aug 18 05:34:33 PM PDT 24
Finished Aug 18 05:34:34 PM PDT 24
Peak memory 207540 kb
Host smart-bd4f461d-4f76-47c6-b7af-f9c6ca7908ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24281
80413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2428180413
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1849469637
Short name T610
Test name
Test status
Simulation time 8511845332 ps
CPU time 10.19 seconds
Started Aug 18 05:34:33 PM PDT 24
Finished Aug 18 05:34:43 PM PDT 24
Peak memory 207792 kb
Host smart-0a60db32-ca20-435b-bbd3-ccfcc73c1da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18494
69637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1849469637
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.347968895
Short name T2746
Test name
Test status
Simulation time 4800147966 ps
CPU time 134.18 seconds
Started Aug 18 05:34:26 PM PDT 24
Finished Aug 18 05:36:40 PM PDT 24
Peak memory 215868 kb
Host smart-2e2d9a74-eca8-405f-9525-9461e3ff848d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=347968895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.347968895
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.742183732
Short name T2744
Test name
Test status
Simulation time 2605220114 ps
CPU time 20.17 seconds
Started Aug 18 05:34:27 PM PDT 24
Finished Aug 18 05:34:47 PM PDT 24
Peak memory 217664 kb
Host smart-869d29fe-e392-415e-99ae-514e493f42c7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=742183732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.742183732
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.2261284422
Short name T3208
Test name
Test status
Simulation time 278424034 ps
CPU time 1.02 seconds
Started Aug 18 05:34:29 PM PDT 24
Finished Aug 18 05:34:30 PM PDT 24
Peak memory 207460 kb
Host smart-b6768230-be49-4404-884b-c7904977ee08
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2261284422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.2261284422
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2765920047
Short name T1998
Test name
Test status
Simulation time 194360183 ps
CPU time 0.95 seconds
Started Aug 18 05:34:30 PM PDT 24
Finished Aug 18 05:34:31 PM PDT 24
Peak memory 207456 kb
Host smart-8f0eb2ef-2779-4324-816e-87c0dcc4e095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27659
20047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2765920047
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_non_iso_usb_traffic.3578296848
Short name T3067
Test name
Test status
Simulation time 3281390053 ps
CPU time 25.96 seconds
Started Aug 18 05:34:23 PM PDT 24
Finished Aug 18 05:34:49 PM PDT 24
Peak memory 224028 kb
Host smart-a2e6bc85-2f50-40db-8943-681bf9081ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35782
96848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_non_iso_usb_traffic.3578296848
Directory /workspace/16.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.3431138080
Short name T533
Test name
Test status
Simulation time 2815416410 ps
CPU time 80.65 seconds
Started Aug 18 05:34:28 PM PDT 24
Finished Aug 18 05:35:49 PM PDT 24
Peak memory 217452 kb
Host smart-2c3e90f6-bf55-46b3-b00d-985dccafaeac
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3431138080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.3431138080
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.2778021058
Short name T2343
Test name
Test status
Simulation time 241236034 ps
CPU time 0.96 seconds
Started Aug 18 05:34:38 PM PDT 24
Finished Aug 18 05:34:39 PM PDT 24
Peak memory 207508 kb
Host smart-39847f5a-8e24-4966-be7a-220ca990b73f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2778021058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.2778021058
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1699810083
Short name T2968
Test name
Test status
Simulation time 147285710 ps
CPU time 0.86 seconds
Started Aug 18 05:34:19 PM PDT 24
Finished Aug 18 05:34:20 PM PDT 24
Peak memory 207496 kb
Host smart-4e9b6f05-45df-4217-92a7-e4c16b6fdf5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16998
10083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1699810083
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.3926193277
Short name T2432
Test name
Test status
Simulation time 171411162 ps
CPU time 0.87 seconds
Started Aug 18 05:34:18 PM PDT 24
Finished Aug 18 05:34:19 PM PDT 24
Peak memory 207460 kb
Host smart-4e508358-cf6c-423b-94c9-59dfc682fde2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39261
93277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.3926193277
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.421646281
Short name T3064
Test name
Test status
Simulation time 156112701 ps
CPU time 0.84 seconds
Started Aug 18 05:34:26 PM PDT 24
Finished Aug 18 05:34:27 PM PDT 24
Peak memory 207468 kb
Host smart-e36aad67-c235-4cbb-b73a-eabe21da8131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42164
6281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.421646281
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2164297669
Short name T1264
Test name
Test status
Simulation time 223294175 ps
CPU time 0.9 seconds
Started Aug 18 05:34:19 PM PDT 24
Finished Aug 18 05:34:20 PM PDT 24
Peak memory 207596 kb
Host smart-23b23777-29a4-42ce-94c7-d6a91456b78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21642
97669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2164297669
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2117807283
Short name T187
Test name
Test status
Simulation time 159861507 ps
CPU time 0.88 seconds
Started Aug 18 05:34:27 PM PDT 24
Finished Aug 18 05:34:28 PM PDT 24
Peak memory 207564 kb
Host smart-527f69b4-3de1-4099-bc3e-86be79058994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21178
07283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2117807283
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.1883725145
Short name T2265
Test name
Test status
Simulation time 266840497 ps
CPU time 1.15 seconds
Started Aug 18 05:34:26 PM PDT 24
Finished Aug 18 05:34:28 PM PDT 24
Peak memory 207588 kb
Host smart-193d46a9-311b-40ca-b75b-434feaec2848
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1883725145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.1883725145
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2632367611
Short name T2027
Test name
Test status
Simulation time 177608102 ps
CPU time 0.85 seconds
Started Aug 18 05:34:32 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 207464 kb
Host smart-2318fab6-cdb8-4e11-86ca-31a2de8cb5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26323
67611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2632367611
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.641248220
Short name T1891
Test name
Test status
Simulation time 109441246 ps
CPU time 0.74 seconds
Started Aug 18 05:34:29 PM PDT 24
Finished Aug 18 05:34:30 PM PDT 24
Peak memory 207444 kb
Host smart-3db78952-21a0-4121-bf6b-18cffc20696d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64124
8220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.641248220
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1858632841
Short name T3278
Test name
Test status
Simulation time 22122804082 ps
CPU time 55.99 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 215912 kb
Host smart-23dbf395-4cc1-4ce3-ac69-36d772d18e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18586
32841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1858632841
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3117307866
Short name T645
Test name
Test status
Simulation time 223141568 ps
CPU time 0.97 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 207456 kb
Host smart-33a2bb4d-e5f5-4ded-8900-03bfe50161b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31173
07866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3117307866
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.3911430672
Short name T2665
Test name
Test status
Simulation time 215855494 ps
CPU time 0.92 seconds
Started Aug 18 05:34:21 PM PDT 24
Finished Aug 18 05:34:22 PM PDT 24
Peak memory 207464 kb
Host smart-026676c0-7fcb-4c67-9087-562b12e2d1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39114
30672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.3911430672
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.4292562931
Short name T2176
Test name
Test status
Simulation time 153423426 ps
CPU time 0.86 seconds
Started Aug 18 05:34:26 PM PDT 24
Finished Aug 18 05:34:27 PM PDT 24
Peak memory 207424 kb
Host smart-4db718d8-23ba-4d1f-878d-2bbedeb1709c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42925
62931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.4292562931
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_resume_link_active.352197824
Short name T1902
Test name
Test status
Simulation time 20166982202 ps
CPU time 22.71 seconds
Started Aug 18 05:34:24 PM PDT 24
Finished Aug 18 05:34:47 PM PDT 24
Peak memory 207516 kb
Host smart-2fc6c9ee-274c-43c9-b169-619668cbdf94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35219
7824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_resume_link_active.352197824
Directory /workspace/16.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.629398796
Short name T3238
Test name
Test status
Simulation time 137493614 ps
CPU time 0.8 seconds
Started Aug 18 05:34:20 PM PDT 24
Finished Aug 18 05:34:21 PM PDT 24
Peak memory 207436 kb
Host smart-1460e388-5bb2-4798-b23f-dccbf4ff955f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62939
8796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.629398796
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_rx_full.1448201985
Short name T2073
Test name
Test status
Simulation time 265367762 ps
CPU time 1.13 seconds
Started Aug 18 05:34:31 PM PDT 24
Finished Aug 18 05:34:32 PM PDT 24
Peak memory 207460 kb
Host smart-0c0b93f8-d459-4dd9-b3ba-e0c76b761f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14482
01985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_full.1448201985
Directory /workspace/16.usbdev_rx_full/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2105398222
Short name T1171
Test name
Test status
Simulation time 144471707 ps
CPU time 0.79 seconds
Started Aug 18 05:34:20 PM PDT 24
Finished Aug 18 05:34:21 PM PDT 24
Peak memory 207552 kb
Host smart-ddbae882-1349-47a8-86b1-4645b8a28ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21053
98222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2105398222
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.476655806
Short name T3080
Test name
Test status
Simulation time 149410649 ps
CPU time 0.84 seconds
Started Aug 18 05:34:32 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 207540 kb
Host smart-27c8061b-67b3-42ab-b5bb-99979a172462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47665
5806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.476655806
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3470440617
Short name T3416
Test name
Test status
Simulation time 267513967 ps
CPU time 1.12 seconds
Started Aug 18 05:34:36 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 207444 kb
Host smart-245ae366-e4b6-45d5-831c-8b3591793806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34704
40617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3470440617
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.2571426874
Short name T3195
Test name
Test status
Simulation time 2521815801 ps
CPU time 70.89 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:35:46 PM PDT 24
Peak memory 224108 kb
Host smart-90cadbf6-911f-438e-8ad9-a59d7f59fffd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2571426874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.2571426874
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.581095580
Short name T992
Test name
Test status
Simulation time 164840965 ps
CPU time 0.95 seconds
Started Aug 18 05:34:30 PM PDT 24
Finished Aug 18 05:34:31 PM PDT 24
Peak memory 207472 kb
Host smart-bc342c7f-65a0-4d71-bc23-df0adbff74cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58109
5580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.581095580
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.4039626697
Short name T2150
Test name
Test status
Simulation time 206721512 ps
CPU time 0.95 seconds
Started Aug 18 05:34:32 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 207492 kb
Host smart-1864adbc-2069-4364-ac4d-7b23f8ac3ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
26697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.4039626697
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2679576338
Short name T1408
Test name
Test status
Simulation time 2685754914 ps
CPU time 75.12 seconds
Started Aug 18 05:34:27 PM PDT 24
Finished Aug 18 05:35:42 PM PDT 24
Peak memory 217424 kb
Host smart-7edb2f51-a733-4585-bbfb-3d9d9f24866f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26795
76338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2679576338
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.1787364147
Short name T2812
Test name
Test status
Simulation time 1537211872 ps
CPU time 9.43 seconds
Started Aug 18 05:34:07 PM PDT 24
Finished Aug 18 05:34:17 PM PDT 24
Peak memory 207392 kb
Host smart-7cc748c2-e260-4371-a201-a0811849d7e9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787364147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_hos
t_handshake.1787364147
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_tx_rx_disruption.3510478585
Short name T595
Test name
Test status
Simulation time 602828333 ps
CPU time 1.7 seconds
Started Aug 18 05:34:23 PM PDT 24
Finished Aug 18 05:34:25 PM PDT 24
Peak memory 207584 kb
Host smart-4b6fb897-fb0c-4306-bfe7-2dff310ca06a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510478585 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.usbdev_tx_rx_disruption.3510478585
Directory /workspace/16.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/160.usbdev_endpoint_types.2245271753
Short name T472
Test name
Test status
Simulation time 298677155 ps
CPU time 1.1 seconds
Started Aug 18 05:39:16 PM PDT 24
Finished Aug 18 05:39:17 PM PDT 24
Peak memory 207540 kb
Host smart-0bcb7957-4e69-4b4b-b2e1-3db17e6539f3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2245271753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_endpoint_types.2245271753
Directory /workspace/160.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/160.usbdev_tx_rx_disruption.2362776481
Short name T640
Test name
Test status
Simulation time 493221203 ps
CPU time 1.51 seconds
Started Aug 18 05:39:19 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207560 kb
Host smart-9c9661a6-63a8-459c-839d-867147bd6bfd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362776481 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 160.usbdev_tx_rx_disruption.2362776481
Directory /workspace/160.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/161.usbdev_tx_rx_disruption.704409409
Short name T3590
Test name
Test status
Simulation time 458513893 ps
CPU time 1.54 seconds
Started Aug 18 05:39:24 PM PDT 24
Finished Aug 18 05:39:26 PM PDT 24
Peak memory 207580 kb
Host smart-d64d6c61-8478-460c-a5aa-a83e0f5ba142
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704409409 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 161.usbdev_tx_rx_disruption.704409409
Directory /workspace/161.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/162.usbdev_tx_rx_disruption.3682840112
Short name T1704
Test name
Test status
Simulation time 646047709 ps
CPU time 1.62 seconds
Started Aug 18 05:39:28 PM PDT 24
Finished Aug 18 05:39:30 PM PDT 24
Peak memory 207444 kb
Host smart-a05265da-0796-4b64-92e1-162b0dd39534
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682840112 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 162.usbdev_tx_rx_disruption.3682840112
Directory /workspace/162.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/163.usbdev_endpoint_types.3616738890
Short name T400
Test name
Test status
Simulation time 590894088 ps
CPU time 1.67 seconds
Started Aug 18 05:39:21 PM PDT 24
Finished Aug 18 05:39:23 PM PDT 24
Peak memory 207504 kb
Host smart-94d613d5-6175-46bf-8ac7-7c850b5e3fd4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3616738890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_endpoint_types.3616738890
Directory /workspace/163.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/163.usbdev_tx_rx_disruption.4210792922
Short name T1375
Test name
Test status
Simulation time 564369105 ps
CPU time 1.58 seconds
Started Aug 18 05:39:15 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207464 kb
Host smart-97823cfa-d6c8-4e4d-b658-0ebce5052228
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210792922 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.usbdev_tx_rx_disruption.4210792922
Directory /workspace/163.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/164.usbdev_endpoint_types.3355005909
Short name T456
Test name
Test status
Simulation time 501207234 ps
CPU time 1.4 seconds
Started Aug 18 05:39:19 PM PDT 24
Finished Aug 18 05:39:20 PM PDT 24
Peak memory 207424 kb
Host smart-6fd21fe0-847d-43a4-8372-30170c989742
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3355005909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_endpoint_types.3355005909
Directory /workspace/164.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/164.usbdev_tx_rx_disruption.4004801483
Short name T727
Test name
Test status
Simulation time 551253380 ps
CPU time 1.6 seconds
Started Aug 18 05:39:53 PM PDT 24
Finished Aug 18 05:39:55 PM PDT 24
Peak memory 207560 kb
Host smart-b9c44cf9-3d62-4975-a8b4-e1c8ceea4532
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004801483 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 164.usbdev_tx_rx_disruption.4004801483
Directory /workspace/164.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/165.usbdev_tx_rx_disruption.1694127429
Short name T2960
Test name
Test status
Simulation time 576018218 ps
CPU time 1.68 seconds
Started Aug 18 05:39:58 PM PDT 24
Finished Aug 18 05:39:59 PM PDT 24
Peak memory 207548 kb
Host smart-757a6b7d-0e22-41af-86ab-72530c1a7608
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694127429 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 165.usbdev_tx_rx_disruption.1694127429
Directory /workspace/165.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/166.usbdev_endpoint_types.1735914357
Short name T2057
Test name
Test status
Simulation time 300938352 ps
CPU time 1.22 seconds
Started Aug 18 05:39:28 PM PDT 24
Finished Aug 18 05:39:29 PM PDT 24
Peak memory 207452 kb
Host smart-ba187e33-c0fa-48f8-8522-d34f757d9418
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1735914357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_endpoint_types.1735914357
Directory /workspace/166.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/167.usbdev_endpoint_types.2261886925
Short name T489
Test name
Test status
Simulation time 209812133 ps
CPU time 1.03 seconds
Started Aug 18 05:39:20 PM PDT 24
Finished Aug 18 05:39:22 PM PDT 24
Peak memory 207504 kb
Host smart-0bb17caa-9011-457b-beac-a4fd29bcd3f7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2261886925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_endpoint_types.2261886925
Directory /workspace/167.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/167.usbdev_tx_rx_disruption.2206936566
Short name T686
Test name
Test status
Simulation time 499701953 ps
CPU time 1.55 seconds
Started Aug 18 05:39:48 PM PDT 24
Finished Aug 18 05:39:50 PM PDT 24
Peak memory 207472 kb
Host smart-ee78c1c6-4498-4cf7-9df0-4f88e53aa8c6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206936566 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 167.usbdev_tx_rx_disruption.2206936566
Directory /workspace/167.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/168.usbdev_tx_rx_disruption.3258499381
Short name T2883
Test name
Test status
Simulation time 493989509 ps
CPU time 1.59 seconds
Started Aug 18 05:39:43 PM PDT 24
Finished Aug 18 05:39:45 PM PDT 24
Peak memory 207588 kb
Host smart-450a484a-a25c-4f7c-afb8-f54293d4b01e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258499381 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.usbdev_tx_rx_disruption.3258499381
Directory /workspace/168.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/169.usbdev_tx_rx_disruption.327035417
Short name T1752
Test name
Test status
Simulation time 535982336 ps
CPU time 1.66 seconds
Started Aug 18 05:39:42 PM PDT 24
Finished Aug 18 05:39:44 PM PDT 24
Peak memory 207508 kb
Host smart-e6d320a3-e76d-4c32-ad0b-29a23e35d6bd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327035417 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 169.usbdev_tx_rx_disruption.327035417
Directory /workspace/169.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.3000566828
Short name T2062
Test name
Test status
Simulation time 47958305 ps
CPU time 0.71 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:34:40 PM PDT 24
Peak memory 207444 kb
Host smart-f333536f-1c70-4d8d-8710-f11526b2afa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3000566828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.3000566828
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1644932840
Short name T273
Test name
Test status
Simulation time 5456766827 ps
CPU time 7.54 seconds
Started Aug 18 05:34:29 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 216008 kb
Host smart-e11e3882-8636-4f37-acdb-ab6592985dc7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644932840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_disconnect.1644932840
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2347306698
Short name T1509
Test name
Test status
Simulation time 14199640694 ps
CPU time 17.06 seconds
Started Aug 18 05:34:31 PM PDT 24
Finished Aug 18 05:34:48 PM PDT 24
Peak memory 215948 kb
Host smart-2dfa73c5-08b4-42c8-a269-e3643a25d5e3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347306698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2347306698
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.96696747
Short name T1693
Test name
Test status
Simulation time 25153900941 ps
CPU time 29.76 seconds
Started Aug 18 05:34:22 PM PDT 24
Finished Aug 18 05:34:52 PM PDT 24
Peak memory 215980 kb
Host smart-2760c6ee-fd55-442d-943f-9c31fc12c40f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96696747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon
_wake_resume.96696747
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3764744975
Short name T1875
Test name
Test status
Simulation time 151057256 ps
CPU time 0.83 seconds
Started Aug 18 05:34:36 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 207468 kb
Host smart-4dd58725-a7e2-4f96-8304-238178b4cc5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37647
44975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3764744975
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.884365839
Short name T2626
Test name
Test status
Simulation time 148503987 ps
CPU time 0.87 seconds
Started Aug 18 05:34:33 PM PDT 24
Finished Aug 18 05:34:34 PM PDT 24
Peak memory 207516 kb
Host smart-11cb7428-12c6-45ee-9a4b-fcffc4f57506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88436
5839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.884365839
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.2047004183
Short name T2280
Test name
Test status
Simulation time 330418520 ps
CPU time 1.27 seconds
Started Aug 18 05:34:33 PM PDT 24
Finished Aug 18 05:34:34 PM PDT 24
Peak memory 207516 kb
Host smart-51ab0e40-9037-49c4-8c7b-06b6c0f201ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20470
04183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2047004183
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1171666013
Short name T108
Test name
Test status
Simulation time 563217549 ps
CPU time 1.67 seconds
Started Aug 18 05:34:31 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 207220 kb
Host smart-f84cf097-fe1a-4792-ace6-080059287b89
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1171666013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1171666013
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.82103355
Short name T1850
Test name
Test status
Simulation time 24266032995 ps
CPU time 37.73 seconds
Started Aug 18 05:34:21 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207836 kb
Host smart-9c3e476f-de3d-4959-8562-ec41fd789ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82103
355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.82103355
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.118624081
Short name T1624
Test name
Test status
Simulation time 1274914604 ps
CPU time 30.21 seconds
Started Aug 18 05:34:30 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 207692 kb
Host smart-2526cfe9-d62b-4ae8-8ed3-624e511eec21
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118624081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.118624081
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.3120102272
Short name T379
Test name
Test status
Simulation time 843535460 ps
CPU time 1.79 seconds
Started Aug 18 05:34:29 PM PDT 24
Finished Aug 18 05:34:31 PM PDT 24
Peak memory 207416 kb
Host smart-fc00b2bd-50fb-4a18-9deb-0d2ba341f703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31201
02272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.3120102272
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2521218426
Short name T1032
Test name
Test status
Simulation time 163626698 ps
CPU time 0.87 seconds
Started Aug 18 05:34:20 PM PDT 24
Finished Aug 18 05:34:21 PM PDT 24
Peak memory 207532 kb
Host smart-35e09b7d-54ba-4ae9-8fe4-fc0f89d88e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25212
18426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2521218426
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.716760010
Short name T666
Test name
Test status
Simulation time 54028214 ps
CPU time 0.71 seconds
Started Aug 18 05:34:19 PM PDT 24
Finished Aug 18 05:34:20 PM PDT 24
Peak memory 207424 kb
Host smart-00619168-cee7-4ddc-b3d5-d9dbbb9c39b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71676
0010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.716760010
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.4044459373
Short name T2488
Test name
Test status
Simulation time 815003786 ps
CPU time 2.14 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:34:40 PM PDT 24
Peak memory 207724 kb
Host smart-1d4dc055-5b2b-461c-a827-f992a34fbcf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40444
59373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.4044459373
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.822586314
Short name T2076
Test name
Test status
Simulation time 171414790 ps
CPU time 2.14 seconds
Started Aug 18 05:34:29 PM PDT 24
Finished Aug 18 05:34:31 PM PDT 24
Peak memory 207604 kb
Host smart-592f197f-6192-49ec-815b-53f1f48b5b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82258
6314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.822586314
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2095585744
Short name T3277
Test name
Test status
Simulation time 236979732 ps
CPU time 1.27 seconds
Started Aug 18 05:34:34 PM PDT 24
Finished Aug 18 05:34:35 PM PDT 24
Peak memory 215880 kb
Host smart-e3216631-a935-40ca-a58d-e00413a5e5d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2095585744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2095585744
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2959482839
Short name T1368
Test name
Test status
Simulation time 156335503 ps
CPU time 0.84 seconds
Started Aug 18 05:34:31 PM PDT 24
Finished Aug 18 05:34:35 PM PDT 24
Peak memory 207456 kb
Host smart-23a62a0f-b09c-47da-95f1-7b3f1c7ba41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29594
82839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2959482839
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1304334445
Short name T2157
Test name
Test status
Simulation time 201689603 ps
CPU time 0.98 seconds
Started Aug 18 05:34:31 PM PDT 24
Finished Aug 18 05:34:32 PM PDT 24
Peak memory 207400 kb
Host smart-b056de64-078e-48c5-a8cb-0c8e3f7a76e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13043
34445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1304334445
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.1821806384
Short name T1097
Test name
Test status
Simulation time 3810896523 ps
CPU time 104.5 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:36:24 PM PDT 24
Peak memory 218412 kb
Host smart-483239ef-3211-4adb-85d6-a857128718bf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1821806384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.1821806384
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.3708905355
Short name T2629
Test name
Test status
Simulation time 14613055312 ps
CPU time 91.27 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:36:06 PM PDT 24
Peak memory 207764 kb
Host smart-a40ae2a3-f1a5-40b2-9e8c-72cd5b04c722
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3708905355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.3708905355
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.4218004468
Short name T691
Test name
Test status
Simulation time 265144974 ps
CPU time 1.08 seconds
Started Aug 18 05:34:36 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 207528 kb
Host smart-a320c770-343d-4ea9-8a2a-150c77e68f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42180
04468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.4218004468
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.4104457054
Short name T2421
Test name
Test status
Simulation time 24042348126 ps
CPU time 41.24 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:35:21 PM PDT 24
Peak memory 216028 kb
Host smart-5267d428-091f-4bf8-96b7-e198f4815d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41044
57054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.4104457054
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2407455649
Short name T1885
Test name
Test status
Simulation time 9955495155 ps
CPU time 13.33 seconds
Started Aug 18 05:34:33 PM PDT 24
Finished Aug 18 05:34:47 PM PDT 24
Peak memory 207704 kb
Host smart-ea0a51fe-8c27-4b9a-ba85-836487ec9fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24074
55649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2407455649
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.3069733756
Short name T3415
Test name
Test status
Simulation time 3922434926 ps
CPU time 106.74 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:36:22 PM PDT 24
Peak memory 224176 kb
Host smart-3afc1092-3aef-47d3-90c0-72d7db577107
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3069733756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.3069733756
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1505534645
Short name T2829
Test name
Test status
Simulation time 1779041395 ps
CPU time 48.72 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:35:27 PM PDT 24
Peak memory 217248 kb
Host smart-6189d2c3-6a44-4186-b3ad-0409365a2fc0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1505534645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1505534645
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.3647975755
Short name T2067
Test name
Test status
Simulation time 259857152 ps
CPU time 1.04 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:36 PM PDT 24
Peak memory 207452 kb
Host smart-82b982ba-2b16-43be-8006-53f84392c776
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3647975755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.3647975755
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.72353781
Short name T1429
Test name
Test status
Simulation time 199084979 ps
CPU time 0.97 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:34:38 PM PDT 24
Peak memory 207440 kb
Host smart-28321519-38f9-47e7-b7c7-6396cbc52ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72353
781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.72353781
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_non_iso_usb_traffic.2553314568
Short name T2591
Test name
Test status
Simulation time 2227488126 ps
CPU time 65.04 seconds
Started Aug 18 05:34:30 PM PDT 24
Finished Aug 18 05:35:35 PM PDT 24
Peak memory 224096 kb
Host smart-96b7f31f-ae9a-444a-9be6-b121ca0ae421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25533
14568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_non_iso_usb_traffic.2553314568
Directory /workspace/17.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2063774054
Short name T3634
Test name
Test status
Simulation time 1987350020 ps
CPU time 54.07 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:35:33 PM PDT 24
Peak memory 215836 kb
Host smart-29d3bcdf-0701-4d2e-82e3-6dffa7cba832
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2063774054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.2063774054
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.3891332449
Short name T3094
Test name
Test status
Simulation time 166027287 ps
CPU time 0.82 seconds
Started Aug 18 05:34:34 PM PDT 24
Finished Aug 18 05:34:35 PM PDT 24
Peak memory 207492 kb
Host smart-83314ae3-4f08-48c7-9082-c0f1a0410441
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3891332449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.3891332449
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2347627285
Short name T1090
Test name
Test status
Simulation time 153531679 ps
CPU time 0.82 seconds
Started Aug 18 05:34:31 PM PDT 24
Finished Aug 18 05:34:35 PM PDT 24
Peak memory 207452 kb
Host smart-17b18dae-2714-4017-8ba8-e9a80520055d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23476
27285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2347627285
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.4125283876
Short name T2462
Test name
Test status
Simulation time 151123574 ps
CPU time 0.86 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:36 PM PDT 24
Peak memory 207412 kb
Host smart-8687da3c-8b9c-42ba-a23d-c428b40dfc48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41252
83876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.4125283876
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.360094531
Short name T1307
Test name
Test status
Simulation time 180864538 ps
CPU time 0.9 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:34:42 PM PDT 24
Peak memory 207496 kb
Host smart-6db8624e-e1db-41b3-95d8-e015c0a45e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36009
4531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.360094531
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3121212888
Short name T561
Test name
Test status
Simulation time 152907282 ps
CPU time 0.84 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:34:38 PM PDT 24
Peak memory 207584 kb
Host smart-6ba87fec-902d-44f9-a63b-004be15f2d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31212
12888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3121212888
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3913100932
Short name T3222
Test name
Test status
Simulation time 187559387 ps
CPU time 0.91 seconds
Started Aug 18 05:34:32 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 207476 kb
Host smart-bcc5ff1a-3483-4ba5-bc1f-5a24d37d57b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39131
00932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3913100932
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.2165088864
Short name T1580
Test name
Test status
Simulation time 199528021 ps
CPU time 1.02 seconds
Started Aug 18 05:34:38 PM PDT 24
Finished Aug 18 05:34:39 PM PDT 24
Peak memory 207544 kb
Host smart-b1b42e4d-6ac0-4095-b9ce-3581eb6af0d5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2165088864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.2165088864
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.568336857
Short name T1973
Test name
Test status
Simulation time 91903178 ps
CPU time 0.77 seconds
Started Aug 18 05:34:32 PM PDT 24
Finished Aug 18 05:34:32 PM PDT 24
Peak memory 207532 kb
Host smart-1985f76c-74ad-4188-87f0-5fd4a85ac7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56833
6857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.568336857
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.4088565842
Short name T3369
Test name
Test status
Simulation time 13149567890 ps
CPU time 32.68 seconds
Started Aug 18 05:34:34 PM PDT 24
Finished Aug 18 05:35:07 PM PDT 24
Peak memory 215964 kb
Host smart-5c8b8b18-f2f9-44e9-916c-2245b34f091a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40885
65842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.4088565842
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2960122071
Short name T792
Test name
Test status
Simulation time 148314330 ps
CPU time 0.91 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:36 PM PDT 24
Peak memory 207476 kb
Host smart-9e9a0ece-13dd-438f-aefb-f338bda8bb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29601
22071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2960122071
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1669569210
Short name T1708
Test name
Test status
Simulation time 184670172 ps
CPU time 0.99 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:36 PM PDT 24
Peak memory 207468 kb
Host smart-286ddb23-9075-4a7e-89f8-f83d332cf82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16695
69210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1669569210
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1389179919
Short name T747
Test name
Test status
Simulation time 304685111 ps
CPU time 1.1 seconds
Started Aug 18 05:34:32 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 207452 kb
Host smart-f3b944ec-e4e5-4c72-beea-ee13f92c3785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13891
79919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1389179919
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.3058142149
Short name T3220
Test name
Test status
Simulation time 221500684 ps
CPU time 0.96 seconds
Started Aug 18 05:34:32 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 207496 kb
Host smart-6e9e0a18-c26a-4502-908f-8b18437af365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30581
42149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.3058142149
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_resume_link_active.739960148
Short name T1495
Test name
Test status
Simulation time 20151267363 ps
CPU time 31.16 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:35:12 PM PDT 24
Peak memory 207596 kb
Host smart-b0ce9743-0ec7-42b9-8e8e-8736cef7925c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73996
0148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_resume_link_active.739960148
Directory /workspace/17.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2093920633
Short name T3506
Test name
Test status
Simulation time 200207101 ps
CPU time 1.02 seconds
Started Aug 18 05:34:38 PM PDT 24
Finished Aug 18 05:34:39 PM PDT 24
Peak memory 207448 kb
Host smart-8b0e49ab-2ffd-4439-82e5-0c13a87e8ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20939
20633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2093920633
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_rx_full.2654312449
Short name T1667
Test name
Test status
Simulation time 250088416 ps
CPU time 1.08 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:34:38 PM PDT 24
Peak memory 207504 kb
Host smart-e0628954-3a8d-40b3-95f8-7f7428de7f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26543
12449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_full.2654312449
Directory /workspace/17.usbdev_rx_full/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3177560686
Short name T571
Test name
Test status
Simulation time 153464132 ps
CPU time 0.87 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:34:39 PM PDT 24
Peak memory 207544 kb
Host smart-708a3989-1369-47a6-8db6-fe82bce05891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31775
60686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3177560686
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3609665260
Short name T2284
Test name
Test status
Simulation time 157752855 ps
CPU time 0.89 seconds
Started Aug 18 05:34:42 PM PDT 24
Finished Aug 18 05:34:43 PM PDT 24
Peak memory 207500 kb
Host smart-ace053d3-c437-463d-9e66-207f1f3aee25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36096
65260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3609665260
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2547386728
Short name T1326
Test name
Test status
Simulation time 278926490 ps
CPU time 1.06 seconds
Started Aug 18 05:34:36 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 207504 kb
Host smart-3603e88a-8fa8-4b42-bed3-4064489702a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25473
86728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2547386728
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2683960582
Short name T1112
Test name
Test status
Simulation time 3303338563 ps
CPU time 33.92 seconds
Started Aug 18 05:34:45 PM PDT 24
Finished Aug 18 05:35:19 PM PDT 24
Peak memory 224000 kb
Host smart-b369d4c4-ea2a-4c9d-ba5d-ea8263dead2c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2683960582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2683960582
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1386061385
Short name T996
Test name
Test status
Simulation time 181029807 ps
CPU time 0.86 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:34:40 PM PDT 24
Peak memory 207508 kb
Host smart-86ee8219-7445-4a37-8ded-bb79428f414d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13860
61385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1386061385
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1295073772
Short name T773
Test name
Test status
Simulation time 168627009 ps
CPU time 0.85 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:34:42 PM PDT 24
Peak memory 207484 kb
Host smart-6b25c9c3-85eb-43b4-b8d8-2f8ae417af21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12950
73772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1295073772
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.2934436158
Short name T81
Test name
Test status
Simulation time 212195953 ps
CPU time 0.99 seconds
Started Aug 18 05:34:44 PM PDT 24
Finished Aug 18 05:34:45 PM PDT 24
Peak memory 207544 kb
Host smart-051e6088-7998-44be-9092-b3d69643b907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29344
36158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.2934436158
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2012226260
Short name T1685
Test name
Test status
Simulation time 2694145519 ps
CPU time 72.16 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:35:51 PM PDT 24
Peak memory 217472 kb
Host smart-32003d68-3366-488c-b44a-a0617ec84175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20122
26260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2012226260
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.1436638622
Short name T2191
Test name
Test status
Simulation time 3001306686 ps
CPU time 26.64 seconds
Started Aug 18 05:34:29 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 207596 kb
Host smart-d94addd2-88e1-4f95-902a-629ffc5b2e75
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436638622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_hos
t_handshake.1436638622
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/17.usbdev_tx_rx_disruption.2480314785
Short name T1634
Test name
Test status
Simulation time 559793183 ps
CPU time 1.77 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:34:39 PM PDT 24
Peak memory 207488 kb
Host smart-dd6ca3ba-d59b-4739-b3ae-7036a098986a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480314785 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.usbdev_tx_rx_disruption.2480314785
Directory /workspace/17.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/170.usbdev_endpoint_types.3342292796
Short name T3478
Test name
Test status
Simulation time 431943794 ps
CPU time 1.23 seconds
Started Aug 18 05:39:22 PM PDT 24
Finished Aug 18 05:39:23 PM PDT 24
Peak memory 207468 kb
Host smart-e6b108c7-5c53-4326-a778-2f3938a2aeab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3342292796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_endpoint_types.3342292796
Directory /workspace/170.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/171.usbdev_tx_rx_disruption.340514216
Short name T179
Test name
Test status
Simulation time 480969658 ps
CPU time 1.56 seconds
Started Aug 18 05:39:37 PM PDT 24
Finished Aug 18 05:39:39 PM PDT 24
Peak memory 207580 kb
Host smart-0efb16ed-1eee-403c-a37b-cfed696cc696
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340514216 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 171.usbdev_tx_rx_disruption.340514216
Directory /workspace/171.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/172.usbdev_endpoint_types.2698313473
Short name T403
Test name
Test status
Simulation time 537580763 ps
CPU time 1.42 seconds
Started Aug 18 05:39:21 PM PDT 24
Finished Aug 18 05:39:33 PM PDT 24
Peak memory 207460 kb
Host smart-583491f3-6274-483d-a971-3748b5216de1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2698313473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_endpoint_types.2698313473
Directory /workspace/172.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/172.usbdev_tx_rx_disruption.1422372470
Short name T1955
Test name
Test status
Simulation time 529539617 ps
CPU time 1.55 seconds
Started Aug 18 05:39:35 PM PDT 24
Finished Aug 18 05:39:37 PM PDT 24
Peak memory 207572 kb
Host smart-b19cb738-ea19-4b3f-923a-f02faef17dbb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422372470 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 172.usbdev_tx_rx_disruption.1422372470
Directory /workspace/172.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/173.usbdev_tx_rx_disruption.1595200968
Short name T3041
Test name
Test status
Simulation time 523340254 ps
CPU time 1.53 seconds
Started Aug 18 05:39:24 PM PDT 24
Finished Aug 18 05:39:26 PM PDT 24
Peak memory 207476 kb
Host smart-5644d05b-9398-4ce1-95ae-df2a0d6e5588
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595200968 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 173.usbdev_tx_rx_disruption.1595200968
Directory /workspace/173.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/174.usbdev_endpoint_types.2144919193
Short name T455
Test name
Test status
Simulation time 363403951 ps
CPU time 1.2 seconds
Started Aug 18 05:39:38 PM PDT 24
Finished Aug 18 05:39:40 PM PDT 24
Peak memory 207532 kb
Host smart-9d1a6f60-8930-431b-8c9e-3e14bc036ed6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2144919193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_endpoint_types.2144919193
Directory /workspace/174.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/174.usbdev_tx_rx_disruption.1308251738
Short name T27
Test name
Test status
Simulation time 447825646 ps
CPU time 1.41 seconds
Started Aug 18 05:39:38 PM PDT 24
Finished Aug 18 05:39:40 PM PDT 24
Peak memory 207552 kb
Host smart-e71aa2fc-0c10-424b-a852-6f1f2bae6edf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308251738 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 174.usbdev_tx_rx_disruption.1308251738
Directory /workspace/174.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/175.usbdev_endpoint_types.3136815370
Short name T1737
Test name
Test status
Simulation time 486756411 ps
CPU time 1.39 seconds
Started Aug 18 05:39:41 PM PDT 24
Finished Aug 18 05:39:43 PM PDT 24
Peak memory 207496 kb
Host smart-4214759d-20d0-4047-aa34-77c58159aeef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3136815370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_endpoint_types.3136815370
Directory /workspace/175.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/175.usbdev_tx_rx_disruption.4018768014
Short name T1931
Test name
Test status
Simulation time 570398138 ps
CPU time 1.61 seconds
Started Aug 18 05:39:51 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207592 kb
Host smart-4558179b-29fa-4ad3-be7a-4f301434b5d1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018768014 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 175.usbdev_tx_rx_disruption.4018768014
Directory /workspace/175.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/176.usbdev_endpoint_types.2566087396
Short name T407
Test name
Test status
Simulation time 440227423 ps
CPU time 1.37 seconds
Started Aug 18 05:39:43 PM PDT 24
Finished Aug 18 05:39:45 PM PDT 24
Peak memory 207544 kb
Host smart-0603597a-0647-4849-84c1-16030bd1a96b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2566087396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_endpoint_types.2566087396
Directory /workspace/176.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/176.usbdev_tx_rx_disruption.780636100
Short name T2279
Test name
Test status
Simulation time 436343281 ps
CPU time 1.39 seconds
Started Aug 18 05:39:22 PM PDT 24
Finished Aug 18 05:39:24 PM PDT 24
Peak memory 207548 kb
Host smart-443e71cc-da5f-4ce7-bd97-da3c2f491046
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780636100 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 176.usbdev_tx_rx_disruption.780636100
Directory /workspace/176.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/177.usbdev_endpoint_types.3087903960
Short name T732
Test name
Test status
Simulation time 158032769 ps
CPU time 0.88 seconds
Started Aug 18 05:39:48 PM PDT 24
Finished Aug 18 05:39:49 PM PDT 24
Peak memory 207528 kb
Host smart-89df05ce-0dcf-4463-8a52-ccb6b3c123db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3087903960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_endpoint_types.3087903960
Directory /workspace/177.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/177.usbdev_tx_rx_disruption.567083404
Short name T2771
Test name
Test status
Simulation time 510748714 ps
CPU time 1.58 seconds
Started Aug 18 05:39:53 PM PDT 24
Finished Aug 18 05:39:55 PM PDT 24
Peak memory 207508 kb
Host smart-45810bef-2503-487a-a4b2-d0adffea525e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567083404 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 177.usbdev_tx_rx_disruption.567083404
Directory /workspace/177.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/178.usbdev_endpoint_types.1590140568
Short name T389
Test name
Test status
Simulation time 247011091 ps
CPU time 0.97 seconds
Started Aug 18 05:39:23 PM PDT 24
Finished Aug 18 05:39:24 PM PDT 24
Peak memory 207524 kb
Host smart-f981cd5e-37a5-4563-ab72-3c1c9bbc3fdb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1590140568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.usbdev_endpoint_types.1590140568
Directory /workspace/178.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/178.usbdev_tx_rx_disruption.3825230786
Short name T3003
Test name
Test status
Simulation time 505064634 ps
CPU time 1.65 seconds
Started Aug 18 05:39:49 PM PDT 24
Finished Aug 18 05:39:51 PM PDT 24
Peak memory 207588 kb
Host smart-84271ac1-486e-47db-9f33-509716edd7cb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825230786 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 178.usbdev_tx_rx_disruption.3825230786
Directory /workspace/178.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/179.usbdev_endpoint_types.2686609865
Short name T368
Test name
Test status
Simulation time 427037589 ps
CPU time 1.26 seconds
Started Aug 18 05:39:41 PM PDT 24
Finished Aug 18 05:39:42 PM PDT 24
Peak memory 207464 kb
Host smart-0129d1b0-7da3-43b0-97e8-632e969a7f5a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2686609865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.usbdev_endpoint_types.2686609865
Directory /workspace/179.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/179.usbdev_tx_rx_disruption.2943968117
Short name T2442
Test name
Test status
Simulation time 453351359 ps
CPU time 1.55 seconds
Started Aug 18 05:39:37 PM PDT 24
Finished Aug 18 05:39:38 PM PDT 24
Peak memory 207472 kb
Host smart-a9e5f8f9-9d86-403d-8623-d4ca544c2c37
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943968117 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 179.usbdev_tx_rx_disruption.2943968117
Directory /workspace/179.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.3440165664
Short name T2530
Test name
Test status
Simulation time 67650904 ps
CPU time 0.69 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:34:42 PM PDT 24
Peak memory 207448 kb
Host smart-8fe46c69-fdad-4010-b42d-92e52e54778e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3440165664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.3440165664
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.1742354846
Short name T2118
Test name
Test status
Simulation time 6372647147 ps
CPU time 8.42 seconds
Started Aug 18 05:34:40 PM PDT 24
Finished Aug 18 05:34:48 PM PDT 24
Peak memory 216020 kb
Host smart-43100d1b-17cb-4b5d-af63-69b1a658ea78
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742354846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_disconnect.1742354846
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1387807240
Short name T1437
Test name
Test status
Simulation time 13717829440 ps
CPU time 16.1 seconds
Started Aug 18 05:34:40 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 215984 kb
Host smart-e72130e9-d9ff-4e6c-9537-53065e1d1d6e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387807240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1387807240
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3723669155
Short name T3386
Test name
Test status
Simulation time 24210613830 ps
CPU time 29.01 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:35:06 PM PDT 24
Peak memory 215952 kb
Host smart-179d58d8-56e2-4724-81a3-15dac175aa9f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723669155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.3723669155
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.352223641
Short name T1935
Test name
Test status
Simulation time 166590038 ps
CPU time 0.89 seconds
Started Aug 18 05:34:36 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 207388 kb
Host smart-0b80afc7-bd40-4be2-9b28-c73a2ce5f4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35222
3641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.352223641
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.2521797234
Short name T1022
Test name
Test status
Simulation time 151808555 ps
CPU time 0.87 seconds
Started Aug 18 05:34:34 PM PDT 24
Finished Aug 18 05:34:35 PM PDT 24
Peak memory 207368 kb
Host smart-bd907b24-3e73-4ab3-b162-9e1a93a90b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25217
97234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.2521797234
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3631358481
Short name T127
Test name
Test status
Simulation time 287896934 ps
CPU time 1.18 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 207528 kb
Host smart-2e73a412-f224-438b-a908-4b98874b4c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36313
58481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3631358481
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3989600773
Short name T3498
Test name
Test status
Simulation time 906946779 ps
CPU time 2.48 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:38 PM PDT 24
Peak memory 207648 kb
Host smart-3e9fbdce-601e-4141-b14b-5ea96d803845
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3989600773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3989600773
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.2769211369
Short name T525
Test name
Test status
Simulation time 35395943778 ps
CPU time 60.47 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:35:39 PM PDT 24
Peak memory 207756 kb
Host smart-78138c2d-1a4a-4d05-93de-2e9f266300fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27692
11369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.2769211369
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.3240681562
Short name T22
Test name
Test status
Simulation time 429282359 ps
CPU time 7.9 seconds
Started Aug 18 05:34:34 PM PDT 24
Finished Aug 18 05:34:42 PM PDT 24
Peak memory 207512 kb
Host smart-aeee19ff-02d3-493f-b7d3-c8f7769793e2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240681562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.3240681562
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.2562167130
Short name T2854
Test name
Test status
Simulation time 869979616 ps
CPU time 2.09 seconds
Started Aug 18 05:34:34 PM PDT 24
Finished Aug 18 05:34:36 PM PDT 24
Peak memory 207552 kb
Host smart-c09b437e-6954-4ed4-b646-630422adb1e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25621
67130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.2562167130
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3275726510
Short name T2240
Test name
Test status
Simulation time 153024276 ps
CPU time 0.87 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:36 PM PDT 24
Peak memory 207536 kb
Host smart-5d26eb67-d8fd-47e3-9f0f-b46a41197086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32757
26510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3275726510
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.3407029048
Short name T2559
Test name
Test status
Simulation time 34005333 ps
CPU time 0.67 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:36 PM PDT 24
Peak memory 207420 kb
Host smart-43410c05-552c-4dea-889e-9f539d671b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34070
29048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3407029048
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.3189935889
Short name T1629
Test name
Test status
Simulation time 834544469 ps
CPU time 2.16 seconds
Started Aug 18 05:34:36 PM PDT 24
Finished Aug 18 05:34:39 PM PDT 24
Peak memory 207724 kb
Host smart-57f7220c-6788-42eb-b1f6-0f7be2931d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31899
35889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.3189935889
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_types.2173936329
Short name T465
Test name
Test status
Simulation time 448863184 ps
CPU time 1.39 seconds
Started Aug 18 05:34:47 PM PDT 24
Finished Aug 18 05:34:49 PM PDT 24
Peak memory 207504 kb
Host smart-d9165f42-eeca-4f2e-b6bb-9a75439b53d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2173936329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_types.2173936329
Directory /workspace/18.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3999244848
Short name T1833
Test name
Test status
Simulation time 253335741 ps
CPU time 2.04 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:38 PM PDT 24
Peak memory 207580 kb
Host smart-2a10a245-2212-43da-805b-8fb736fcc283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39992
44848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3999244848
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2573743377
Short name T2407
Test name
Test status
Simulation time 189100354 ps
CPU time 1.02 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:34:38 PM PDT 24
Peak memory 215880 kb
Host smart-4e4c6adb-464f-4321-b455-638857827541
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2573743377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2573743377
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.99887287
Short name T3193
Test name
Test status
Simulation time 162687162 ps
CPU time 0.8 seconds
Started Aug 18 05:34:34 PM PDT 24
Finished Aug 18 05:34:35 PM PDT 24
Peak memory 207340 kb
Host smart-30bde001-00c9-4ef9-85df-e39f310cd85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99887
287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.99887287
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3319923620
Short name T1415
Test name
Test status
Simulation time 225528189 ps
CPU time 0.97 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:34:42 PM PDT 24
Peak memory 207460 kb
Host smart-1600b161-15c7-4a60-925a-07409953d19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33199
23620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3319923620
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.2220986665
Short name T2600
Test name
Test status
Simulation time 2784904287 ps
CPU time 79.75 seconds
Started Aug 18 05:34:38 PM PDT 24
Finished Aug 18 05:35:58 PM PDT 24
Peak memory 215912 kb
Host smart-188b99e0-e5b2-4a1a-b504-2d0e83e65056
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2220986665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.2220986665
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.679206048
Short name T3531
Test name
Test status
Simulation time 7961120765 ps
CPU time 54.29 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:35:33 PM PDT 24
Peak memory 207784 kb
Host smart-b2cc384c-ddfd-461e-9563-458561a50bbb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=679206048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.679206048
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3950956348
Short name T858
Test name
Test status
Simulation time 186717229 ps
CPU time 0.9 seconds
Started Aug 18 05:34:36 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 207584 kb
Host smart-7ba56837-51ed-4e6a-8a97-e4136703a39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39509
56348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3950956348
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.2854090239
Short name T2834
Test name
Test status
Simulation time 33152425605 ps
CPU time 51.49 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:35:27 PM PDT 24
Peak memory 207840 kb
Host smart-9d8679eb-a429-457f-a65f-2309a2e8a655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28540
90239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.2854090239
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.2752992374
Short name T2584
Test name
Test status
Simulation time 3965032576 ps
CPU time 5.99 seconds
Started Aug 18 05:34:40 PM PDT 24
Finished Aug 18 05:34:46 PM PDT 24
Peak memory 207788 kb
Host smart-420a1672-0558-4054-91a7-46e318499706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27529
92374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2752992374
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.1453829042
Short name T3580
Test name
Test status
Simulation time 4677776691 ps
CPU time 130.24 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:36:47 PM PDT 24
Peak memory 216020 kb
Host smart-d740334a-24be-41fb-be40-680fb7779a6d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1453829042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.1453829042
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.951753741
Short name T597
Test name
Test status
Simulation time 4279277434 ps
CPU time 32.9 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:35:12 PM PDT 24
Peak memory 216036 kb
Host smart-7f24df0c-27ea-4d46-91e5-f60eb33d2840
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=951753741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.951753741
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.2367754073
Short name T2054
Test name
Test status
Simulation time 235820221 ps
CPU time 1.02 seconds
Started Aug 18 05:34:32 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 207416 kb
Host smart-35b6c5fa-6b1c-4967-b902-ec38af293bc6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2367754073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.2367754073
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1349504955
Short name T807
Test name
Test status
Simulation time 215014869 ps
CPU time 0.96 seconds
Started Aug 18 05:34:38 PM PDT 24
Finished Aug 18 05:34:39 PM PDT 24
Peak memory 207388 kb
Host smart-10b4765d-4f0e-4f18-bbb3-099d8ab15c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13495
04955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1349504955
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_non_iso_usb_traffic.1425413484
Short name T3545
Test name
Test status
Simulation time 2913211369 ps
CPU time 84.21 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:36:02 PM PDT 24
Peak memory 217532 kb
Host smart-00974d2d-5073-4c76-852a-600f7f8679f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14254
13484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_non_iso_usb_traffic.1425413484
Directory /workspace/18.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.209291405
Short name T1422
Test name
Test status
Simulation time 3619826454 ps
CPU time 37 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:35:15 PM PDT 24
Peak memory 216004 kb
Host smart-b4ee1d04-8774-41e6-b136-7a4d0a1af7e1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=209291405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.209291405
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.2539334997
Short name T3072
Test name
Test status
Simulation time 163717929 ps
CPU time 0.84 seconds
Started Aug 18 05:34:38 PM PDT 24
Finished Aug 18 05:34:39 PM PDT 24
Peak memory 207488 kb
Host smart-6d815678-3a7a-4478-a0fd-397d4bb0c336
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2539334997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.2539334997
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.899804951
Short name T1280
Test name
Test status
Simulation time 165627097 ps
CPU time 0.86 seconds
Started Aug 18 05:34:32 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 207444 kb
Host smart-0b740f44-717e-465f-bb76-b46d19ea7c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89980
4951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.899804951
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1894425525
Short name T3111
Test name
Test status
Simulation time 239861691 ps
CPU time 0.99 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:34:40 PM PDT 24
Peak memory 207496 kb
Host smart-de82aa2e-64db-4b49-b400-20a04a08b7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18944
25525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1894425525
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2896139373
Short name T3391
Test name
Test status
Simulation time 149213583 ps
CPU time 0.83 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:36 PM PDT 24
Peak memory 207420 kb
Host smart-d12286dc-b569-49d8-99f0-362084b148d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28961
39373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2896139373
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1264913998
Short name T2485
Test name
Test status
Simulation time 162213092 ps
CPU time 0.83 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:35 PM PDT 24
Peak memory 207508 kb
Host smart-6abfa946-30fe-46ca-b6b8-f06fffe178d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12649
13998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1264913998
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3671855009
Short name T1874
Test name
Test status
Simulation time 191550937 ps
CPU time 0.97 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 207556 kb
Host smart-b2515f96-4f8b-47b8-89fe-d68fd6a0c393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36718
55009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3671855009
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3365518978
Short name T194
Test name
Test status
Simulation time 216698195 ps
CPU time 1 seconds
Started Aug 18 05:34:37 PM PDT 24
Finished Aug 18 05:34:38 PM PDT 24
Peak memory 207488 kb
Host smart-6a5d9173-0b1f-475f-a112-4aaa4d267797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33655
18978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3365518978
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.847094438
Short name T2160
Test name
Test status
Simulation time 202657139 ps
CPU time 0.96 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:36 PM PDT 24
Peak memory 207560 kb
Host smart-d00a754c-1ad6-431a-96d7-97dab07a6ae7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=847094438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.847094438
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1724537519
Short name T3335
Test name
Test status
Simulation time 146672574 ps
CPU time 0.85 seconds
Started Aug 18 05:34:42 PM PDT 24
Finished Aug 18 05:34:43 PM PDT 24
Peak memory 207456 kb
Host smart-6764dccc-d8e9-44d2-8848-1cf0df15233b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17245
37519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1724537519
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.4020277932
Short name T2904
Test name
Test status
Simulation time 50512331 ps
CPU time 0.72 seconds
Started Aug 18 05:34:32 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 207440 kb
Host smart-5ee21a52-b9d5-41ab-aa70-3f1e7356b810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40202
77932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.4020277932
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.4075643677
Short name T2594
Test name
Test status
Simulation time 9829579657 ps
CPU time 25.22 seconds
Started Aug 18 05:34:30 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 215976 kb
Host smart-1bc6f455-17ab-4a09-bb70-d039b8d5cbe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40756
43677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.4075643677
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.3374518522
Short name T1221
Test name
Test status
Simulation time 215613536 ps
CPU time 0.95 seconds
Started Aug 18 05:34:34 PM PDT 24
Finished Aug 18 05:34:35 PM PDT 24
Peak memory 207580 kb
Host smart-6159387a-177e-48f9-9b56-3eed3ffbe088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33745
18522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.3374518522
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1832650524
Short name T3088
Test name
Test status
Simulation time 213947032 ps
CPU time 0.96 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:34:42 PM PDT 24
Peak memory 207460 kb
Host smart-68a668e8-df30-41c2-8d9f-dbdb1e0ed475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18326
50524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1832650524
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.1127340116
Short name T3160
Test name
Test status
Simulation time 211160438 ps
CPU time 0.97 seconds
Started Aug 18 05:34:40 PM PDT 24
Finished Aug 18 05:34:41 PM PDT 24
Peak memory 207488 kb
Host smart-c24767d8-09e1-4003-863a-afd0ea3502ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11273
40116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.1127340116
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.3858667270
Short name T2080
Test name
Test status
Simulation time 153488267 ps
CPU time 0.88 seconds
Started Aug 18 05:34:43 PM PDT 24
Finished Aug 18 05:34:44 PM PDT 24
Peak memory 207524 kb
Host smart-0a914e5b-f606-4f40-85f2-5e7d3e30fbfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38586
67270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.3858667270
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_resume_link_active.1921630664
Short name T2127
Test name
Test status
Simulation time 20151351248 ps
CPU time 23.22 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207592 kb
Host smart-83fd864e-7ce9-4ce7-9f87-eaac5cd02714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19216
30664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_resume_link_active.1921630664
Directory /workspace/18.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2603106145
Short name T1914
Test name
Test status
Simulation time 177074897 ps
CPU time 0.91 seconds
Started Aug 18 05:34:36 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 207440 kb
Host smart-900cabb3-63c3-4d79-930c-06f6060f5967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26031
06145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2603106145
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_rx_full.3245215759
Short name T3058
Test name
Test status
Simulation time 245217739 ps
CPU time 1.09 seconds
Started Aug 18 05:34:43 PM PDT 24
Finished Aug 18 05:34:44 PM PDT 24
Peak memory 207472 kb
Host smart-9632fc41-733b-4457-aea8-d25312505b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32452
15759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_full.3245215759
Directory /workspace/18.usbdev_rx_full/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3023429215
Short name T1360
Test name
Test status
Simulation time 155646793 ps
CPU time 0.91 seconds
Started Aug 18 05:34:42 PM PDT 24
Finished Aug 18 05:34:43 PM PDT 24
Peak memory 207544 kb
Host smart-3beb533d-5eb4-4492-889b-57b99da8d860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30234
29215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3023429215
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1229740630
Short name T1674
Test name
Test status
Simulation time 142413080 ps
CPU time 0.86 seconds
Started Aug 18 05:34:34 PM PDT 24
Finished Aug 18 05:34:35 PM PDT 24
Peak memory 207396 kb
Host smart-f61554c7-e452-4ced-b054-a91b2e24a061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12297
40630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1229740630
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.918032355
Short name T2979
Test name
Test status
Simulation time 203222459 ps
CPU time 1.01 seconds
Started Aug 18 05:34:49 PM PDT 24
Finished Aug 18 05:34:50 PM PDT 24
Peak memory 207480 kb
Host smart-80b088f5-8adb-4f22-834d-f0ea2e2f3419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91803
2355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.918032355
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.1381044297
Short name T2730
Test name
Test status
Simulation time 3946763843 ps
CPU time 28.36 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:35:09 PM PDT 24
Peak memory 215884 kb
Host smart-a8385757-709f-4629-8645-975b514174b3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1381044297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.1381044297
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2039926301
Short name T502
Test name
Test status
Simulation time 176087997 ps
CPU time 0.88 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:36 PM PDT 24
Peak memory 207456 kb
Host smart-93ba2366-30cc-4a45-8e98-5e6e4b83a27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20399
26301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2039926301
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.4246293445
Short name T2567
Test name
Test status
Simulation time 177267229 ps
CPU time 0.85 seconds
Started Aug 18 05:34:42 PM PDT 24
Finished Aug 18 05:34:43 PM PDT 24
Peak memory 207540 kb
Host smart-fc93748c-cca8-44bf-9224-2e7ec832031a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42462
93445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.4246293445
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.2923646635
Short name T1114
Test name
Test status
Simulation time 894542889 ps
CPU time 2.28 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:34:44 PM PDT 24
Peak memory 207768 kb
Host smart-8343b3dc-1b69-4631-8330-4581bb5c2264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29236
46635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.2923646635
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2862576972
Short name T1274
Test name
Test status
Simulation time 1840265567 ps
CPU time 50.63 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 215952 kb
Host smart-228a2569-ce21-41b3-93fb-70dfc6573b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28625
76972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2862576972
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.28224599
Short name T2921
Test name
Test status
Simulation time 2498355536 ps
CPU time 22.32 seconds
Started Aug 18 05:34:40 PM PDT 24
Finished Aug 18 05:35:02 PM PDT 24
Peak memory 207684 kb
Host smart-444a7218-a2ed-4cb0-91b8-3da343177370
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28224599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_host_
handshake.28224599
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/18.usbdev_tx_rx_disruption.1842264391
Short name T2669
Test name
Test status
Simulation time 538049384 ps
CPU time 1.6 seconds
Started Aug 18 05:34:51 PM PDT 24
Finished Aug 18 05:34:53 PM PDT 24
Peak memory 207540 kb
Host smart-2ef35739-c794-42eb-869f-59d9010b5617
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842264391 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.usbdev_tx_rx_disruption.1842264391
Directory /workspace/18.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/180.usbdev_endpoint_types.2842585917
Short name T128
Test name
Test status
Simulation time 239298152 ps
CPU time 0.96 seconds
Started Aug 18 05:39:51 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207504 kb
Host smart-01839140-331d-43ce-bc89-01a70d88e5a2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2842585917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_endpoint_types.2842585917
Directory /workspace/180.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/180.usbdev_tx_rx_disruption.1960988560
Short name T1220
Test name
Test status
Simulation time 547965471 ps
CPU time 1.63 seconds
Started Aug 18 05:39:22 PM PDT 24
Finished Aug 18 05:39:23 PM PDT 24
Peak memory 207520 kb
Host smart-59541242-276d-4f36-aed5-03d6c989918f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960988560 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 180.usbdev_tx_rx_disruption.1960988560
Directory /workspace/180.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/181.usbdev_endpoint_types.1129483861
Short name T442
Test name
Test status
Simulation time 397700937 ps
CPU time 1.3 seconds
Started Aug 18 05:39:52 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207556 kb
Host smart-96957ab3-55d6-4aeb-b389-46b019bcf0b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1129483861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_endpoint_types.1129483861
Directory /workspace/181.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/181.usbdev_tx_rx_disruption.60402735
Short name T642
Test name
Test status
Simulation time 511071220 ps
CPU time 1.54 seconds
Started Aug 18 05:39:31 PM PDT 24
Finished Aug 18 05:39:33 PM PDT 24
Peak memory 207540 kb
Host smart-b2b7302c-47e2-4b33-bb9c-ff775c0ba3ba
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60402735 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 181.usbdev_tx_rx_disruption.60402735
Directory /workspace/181.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/182.usbdev_tx_rx_disruption.1188569506
Short name T2091
Test name
Test status
Simulation time 475602598 ps
CPU time 1.57 seconds
Started Aug 18 05:39:45 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207584 kb
Host smart-c070eb4f-4bfa-4ff4-a386-60de61756fed
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188569506 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 182.usbdev_tx_rx_disruption.1188569506
Directory /workspace/182.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/183.usbdev_endpoint_types.704371287
Short name T468
Test name
Test status
Simulation time 263675479 ps
CPU time 1 seconds
Started Aug 18 05:39:49 PM PDT 24
Finished Aug 18 05:39:51 PM PDT 24
Peak memory 207536 kb
Host smart-eff03b83-7710-47d0-9afe-450c92949d8f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=704371287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_endpoint_types.704371287
Directory /workspace/183.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/183.usbdev_tx_rx_disruption.3855997080
Short name T214
Test name
Test status
Simulation time 518782659 ps
CPU time 1.59 seconds
Started Aug 18 05:39:40 PM PDT 24
Finished Aug 18 05:39:42 PM PDT 24
Peak memory 207560 kb
Host smart-439df1cb-d08e-4272-8695-3f6235234503
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855997080 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 183.usbdev_tx_rx_disruption.3855997080
Directory /workspace/183.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/184.usbdev_tx_rx_disruption.2098296221
Short name T1536
Test name
Test status
Simulation time 565864066 ps
CPU time 1.53 seconds
Started Aug 18 05:39:46 PM PDT 24
Finished Aug 18 05:39:48 PM PDT 24
Peak memory 207456 kb
Host smart-e2fe735d-ab5e-445b-9a93-108628bfcbde
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098296221 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.usbdev_tx_rx_disruption.2098296221
Directory /workspace/184.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/185.usbdev_endpoint_types.2005693950
Short name T432
Test name
Test status
Simulation time 370576343 ps
CPU time 1.18 seconds
Started Aug 18 05:39:27 PM PDT 24
Finished Aug 18 05:39:28 PM PDT 24
Peak memory 207460 kb
Host smart-0e853bee-0aea-4bac-8986-790243692256
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2005693950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_endpoint_types.2005693950
Directory /workspace/185.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/185.usbdev_tx_rx_disruption.2694574173
Short name T1162
Test name
Test status
Simulation time 568756666 ps
CPU time 1.67 seconds
Started Aug 18 05:39:46 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207584 kb
Host smart-25676f32-c5f5-484f-bd48-fadfb0994c43
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694574173 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 185.usbdev_tx_rx_disruption.2694574173
Directory /workspace/185.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/186.usbdev_endpoint_types.3540590911
Short name T463
Test name
Test status
Simulation time 698942216 ps
CPU time 1.74 seconds
Started Aug 18 05:39:43 PM PDT 24
Finished Aug 18 05:39:44 PM PDT 24
Peak memory 207540 kb
Host smart-3c07e546-d527-40a0-93b2-e94d750cc966
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3540590911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_endpoint_types.3540590911
Directory /workspace/186.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/186.usbdev_tx_rx_disruption.995667191
Short name T2286
Test name
Test status
Simulation time 566120922 ps
CPU time 1.68 seconds
Started Aug 18 05:39:38 PM PDT 24
Finished Aug 18 05:39:40 PM PDT 24
Peak memory 207552 kb
Host smart-dbf2117c-d39e-4793-9bf2-4d3a13e5739e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995667191 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 186.usbdev_tx_rx_disruption.995667191
Directory /workspace/186.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/187.usbdev_tx_rx_disruption.431298300
Short name T902
Test name
Test status
Simulation time 522401260 ps
CPU time 1.52 seconds
Started Aug 18 05:39:43 PM PDT 24
Finished Aug 18 05:39:50 PM PDT 24
Peak memory 207584 kb
Host smart-9ab35d6a-a632-4e4f-ade9-dd115a3d6839
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431298300 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 187.usbdev_tx_rx_disruption.431298300
Directory /workspace/187.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/188.usbdev_endpoint_types.3127432997
Short name T416
Test name
Test status
Simulation time 555168932 ps
CPU time 1.43 seconds
Started Aug 18 05:39:53 PM PDT 24
Finished Aug 18 05:39:55 PM PDT 24
Peak memory 207448 kb
Host smart-9c9cb28c-294d-410c-a0ac-b218f6a353b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3127432997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.usbdev_endpoint_types.3127432997
Directory /workspace/188.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/188.usbdev_tx_rx_disruption.355922655
Short name T2410
Test name
Test status
Simulation time 490789894 ps
CPU time 1.7 seconds
Started Aug 18 05:39:21 PM PDT 24
Finished Aug 18 05:39:23 PM PDT 24
Peak memory 207572 kb
Host smart-b0bac014-db8f-451b-82a0-6e52035e79cb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355922655 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 188.usbdev_tx_rx_disruption.355922655
Directory /workspace/188.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/189.usbdev_endpoint_types.3329845930
Short name T374
Test name
Test status
Simulation time 352201903 ps
CPU time 1.18 seconds
Started Aug 18 05:39:20 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 207472 kb
Host smart-7b8d54a4-dfbc-44b5-92d0-c0251997a1f8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3329845930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.usbdev_endpoint_types.3329845930
Directory /workspace/189.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/189.usbdev_tx_rx_disruption.2370169548
Short name T3499
Test name
Test status
Simulation time 460056801 ps
CPU time 1.47 seconds
Started Aug 18 05:39:43 PM PDT 24
Finished Aug 18 05:39:44 PM PDT 24
Peak memory 207540 kb
Host smart-635f1a69-a37d-410f-82dc-81e70eb5223c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370169548 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 189.usbdev_tx_rx_disruption.2370169548
Directory /workspace/189.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.2454665895
Short name T2901
Test name
Test status
Simulation time 36273607 ps
CPU time 0.65 seconds
Started Aug 18 05:34:53 PM PDT 24
Finished Aug 18 05:34:54 PM PDT 24
Peak memory 207456 kb
Host smart-0bb8a566-0a54-4a8b-bb93-5754c057374b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2454665895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.2454665895
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1628453172
Short name T3633
Test name
Test status
Simulation time 5291421279 ps
CPU time 7.55 seconds
Started Aug 18 05:34:52 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 215984 kb
Host smart-1d4c3e27-cd76-4cec-b6c8-ddaf56a18e00
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628453172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_disconnect.1628453172
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.2815858062
Short name T3607
Test name
Test status
Simulation time 14638031890 ps
CPU time 17.63 seconds
Started Aug 18 05:34:42 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 215864 kb
Host smart-94e5a302-2274-4c77-85f8-5973d0f347c1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815858062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.2815858062
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2853855946
Short name T1943
Test name
Test status
Simulation time 159116426 ps
CPU time 0.81 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:34:41 PM PDT 24
Peak memory 207520 kb
Host smart-c8b473c4-b56b-419c-99fc-a5ea88eab2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28538
55946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2853855946
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.4016425465
Short name T1336
Test name
Test status
Simulation time 144398195 ps
CPU time 0.81 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:34:42 PM PDT 24
Peak memory 207512 kb
Host smart-eba25ae1-c719-43da-b693-2f34005cd063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40164
25465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.4016425465
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.696022215
Short name T2642
Test name
Test status
Simulation time 327065311 ps
CPU time 1.27 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:34:40 PM PDT 24
Peak memory 207560 kb
Host smart-020e141a-44ec-4236-a7e6-1c08249a3e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69602
2215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.696022215
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.4073586499
Short name T347
Test name
Test status
Simulation time 592455690 ps
CPU time 1.64 seconds
Started Aug 18 05:34:54 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 207480 kb
Host smart-0eb12e5a-e8d4-4db4-b754-6b6630d59697
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4073586499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.4073586499
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.1698060836
Short name T3543
Test name
Test status
Simulation time 37325810909 ps
CPU time 62.2 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:35:37 PM PDT 24
Peak memory 207828 kb
Host smart-118134cf-9d23-4e86-836f-e3954ece697f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16980
60836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.1698060836
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.3516147479
Short name T1239
Test name
Test status
Simulation time 2028475177 ps
CPU time 17.02 seconds
Started Aug 18 05:34:42 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207732 kb
Host smart-3424c199-2714-4a7f-9e00-40eb766d8482
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516147479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.3516147479
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3610695307
Short name T1351
Test name
Test status
Simulation time 1065623614 ps
CPU time 2.31 seconds
Started Aug 18 05:34:36 PM PDT 24
Finished Aug 18 05:34:38 PM PDT 24
Peak memory 207516 kb
Host smart-ab98c21d-ea05-414b-8452-d54bd432a86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36106
95307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3610695307
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.8619293
Short name T2275
Test name
Test status
Simulation time 133755373 ps
CPU time 0.9 seconds
Started Aug 18 05:34:43 PM PDT 24
Finished Aug 18 05:34:45 PM PDT 24
Peak memory 207468 kb
Host smart-0db09eaa-7ee4-40b6-b38f-0eff0147bbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86192
93 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.8619293
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.3794333340
Short name T1605
Test name
Test status
Simulation time 47700403 ps
CPU time 0.7 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:34:39 PM PDT 24
Peak memory 207416 kb
Host smart-fe2a4acb-cc96-488e-94b9-514fcc37ec3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37943
33340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3794333340
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.2234890757
Short name T1997
Test name
Test status
Simulation time 775642466 ps
CPU time 2.25 seconds
Started Aug 18 05:34:38 PM PDT 24
Finished Aug 18 05:34:41 PM PDT 24
Peak memory 207752 kb
Host smart-791fa7d5-9825-4855-ba72-bb7730016cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22348
90757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.2234890757
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_types.841241447
Short name T2490
Test name
Test status
Simulation time 308854265 ps
CPU time 1.12 seconds
Started Aug 18 05:34:51 PM PDT 24
Finished Aug 18 05:34:53 PM PDT 24
Peak memory 207460 kb
Host smart-e7cc88c8-be6b-4b85-ba55-08cf738a2765
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=841241447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_types.841241447
Directory /workspace/19.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.4238111201
Short name T659
Test name
Test status
Simulation time 294094641 ps
CPU time 2.03 seconds
Started Aug 18 05:34:42 PM PDT 24
Finished Aug 18 05:34:44 PM PDT 24
Peak memory 207660 kb
Host smart-730e9c48-abdd-4ddb-bded-4af5e9cc83fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42381
11201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.4238111201
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2129799596
Short name T2959
Test name
Test status
Simulation time 293745819 ps
CPU time 1.28 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:34:42 PM PDT 24
Peak memory 223920 kb
Host smart-8636f6e2-e444-4334-be6f-8d1f18bb1b78
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2129799596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2129799596
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1618522161
Short name T1166
Test name
Test status
Simulation time 148499188 ps
CPU time 0.84 seconds
Started Aug 18 05:34:43 PM PDT 24
Finished Aug 18 05:34:44 PM PDT 24
Peak memory 207464 kb
Host smart-f805eef7-4939-4892-b54d-83e2aaaa5750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16185
22161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1618522161
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1296351454
Short name T1135
Test name
Test status
Simulation time 198585853 ps
CPU time 0.91 seconds
Started Aug 18 05:34:48 PM PDT 24
Finished Aug 18 05:34:49 PM PDT 24
Peak memory 207448 kb
Host smart-ca1e3528-7ad6-4001-9d0c-9bea9073b256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12963
51454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1296351454
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.3784511731
Short name T1122
Test name
Test status
Simulation time 5021170606 ps
CPU time 147.25 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:37:07 PM PDT 24
Peak memory 224076 kb
Host smart-8bc0719f-93ac-4321-a856-93416f2424a2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3784511731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.3784511731
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.748951075
Short name T3085
Test name
Test status
Simulation time 11455245953 ps
CPU time 79.3 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:36:01 PM PDT 24
Peak memory 207820 kb
Host smart-c306b81f-36a6-463c-a9e1-1b489d18d985
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=748951075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.748951075
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.601945028
Short name T800
Test name
Test status
Simulation time 200178019 ps
CPU time 0.93 seconds
Started Aug 18 05:34:42 PM PDT 24
Finished Aug 18 05:34:43 PM PDT 24
Peak memory 207512 kb
Host smart-0e975900-6e8e-4ce3-8460-6c2cfacadf20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60194
5028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.601945028
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3132399882
Short name T1411
Test name
Test status
Simulation time 6651647284 ps
CPU time 10.09 seconds
Started Aug 18 05:34:50 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 216688 kb
Host smart-0e756826-49a2-488a-a73b-50ed1aaf2e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31323
99882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3132399882
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2257710645
Short name T1359
Test name
Test status
Simulation time 10478940086 ps
CPU time 13.53 seconds
Started Aug 18 05:34:45 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207820 kb
Host smart-29613bb6-c1c0-4832-9e77-de9c7b5c8d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22577
10645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2257710645
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.4244557878
Short name T3052
Test name
Test status
Simulation time 2231174914 ps
CPU time 17.91 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:34:57 PM PDT 24
Peak memory 224120 kb
Host smart-4c64e1a2-b3de-468f-8bb8-7282e552013e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4244557878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.4244557878
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.103003199
Short name T276
Test name
Test status
Simulation time 2278495483 ps
CPU time 23.07 seconds
Started Aug 18 05:34:52 PM PDT 24
Finished Aug 18 05:35:15 PM PDT 24
Peak memory 215976 kb
Host smart-454e1c46-31a4-4724-970d-2515e1d73347
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=103003199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.103003199
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3558008959
Short name T543
Test name
Test status
Simulation time 243919701 ps
CPU time 0.99 seconds
Started Aug 18 05:34:42 PM PDT 24
Finished Aug 18 05:34:43 PM PDT 24
Peak memory 207456 kb
Host smart-8925f19b-ffb8-42af-9204-1bf082f9aff0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3558008959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3558008959
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2858316495
Short name T1761
Test name
Test status
Simulation time 197512957 ps
CPU time 1.01 seconds
Started Aug 18 05:34:44 PM PDT 24
Finished Aug 18 05:34:45 PM PDT 24
Peak memory 207464 kb
Host smart-3829f6cb-2f5f-424e-9236-10395cd2025a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28583
16495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2858316495
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_non_iso_usb_traffic.2359528481
Short name T2099
Test name
Test status
Simulation time 3021102889 ps
CPU time 22.08 seconds
Started Aug 18 05:34:42 PM PDT 24
Finished Aug 18 05:35:04 PM PDT 24
Peak memory 207716 kb
Host smart-4bc6c872-dd35-4ae4-87dc-a1d02e9d4cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23595
28481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_non_iso_usb_traffic.2359528481
Directory /workspace/19.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.2079932890
Short name T2710
Test name
Test status
Simulation time 1756941202 ps
CPU time 16.78 seconds
Started Aug 18 05:34:47 PM PDT 24
Finished Aug 18 05:35:04 PM PDT 24
Peak memory 223984 kb
Host smart-029c740a-8c9a-406f-b84b-53ff531e0bcf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2079932890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2079932890
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.154211713
Short name T2132
Test name
Test status
Simulation time 149911458 ps
CPU time 0.88 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:34:40 PM PDT 24
Peak memory 207472 kb
Host smart-d6e4e527-bf26-485a-8c67-6340af91f5f4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=154211713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.154211713
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1489459218
Short name T574
Test name
Test status
Simulation time 197151492 ps
CPU time 0.87 seconds
Started Aug 18 05:34:49 PM PDT 24
Finished Aug 18 05:34:50 PM PDT 24
Peak memory 207464 kb
Host smart-87d50f50-91da-4715-be9c-9bd3a4562a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14894
59218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1489459218
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3057990072
Short name T147
Test name
Test status
Simulation time 199334961 ps
CPU time 0.97 seconds
Started Aug 18 05:34:41 PM PDT 24
Finished Aug 18 05:34:42 PM PDT 24
Peak memory 207488 kb
Host smart-4781780e-2a74-48ba-8c7b-9f66ecc8dd11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30579
90072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3057990072
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2379259878
Short name T2310
Test name
Test status
Simulation time 188822296 ps
CPU time 0.95 seconds
Started Aug 18 05:34:42 PM PDT 24
Finished Aug 18 05:34:43 PM PDT 24
Peak memory 207488 kb
Host smart-13ec7aae-dce3-499c-941f-06b00aa6f6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23792
59878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2379259878
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1853842207
Short name T852
Test name
Test status
Simulation time 150064794 ps
CPU time 0.89 seconds
Started Aug 18 05:34:44 PM PDT 24
Finished Aug 18 05:34:45 PM PDT 24
Peak memory 207460 kb
Host smart-ab51d468-7352-42e7-aefc-c7e8f1f6b335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18538
42207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1853842207
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.31347919
Short name T142
Test name
Test status
Simulation time 182515620 ps
CPU time 0.84 seconds
Started Aug 18 05:34:32 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 207576 kb
Host smart-a6439dad-5c02-4a46-bc5c-4c993b33111a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31347
919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.31347919
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3479948807
Short name T1505
Test name
Test status
Simulation time 151593461 ps
CPU time 0.84 seconds
Started Aug 18 05:34:39 PM PDT 24
Finished Aug 18 05:34:40 PM PDT 24
Peak memory 207560 kb
Host smart-df2ae9b3-6923-40cf-ac9e-7e38e51b2029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34799
48807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3479948807
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.1084772357
Short name T3185
Test name
Test status
Simulation time 220570482 ps
CPU time 0.98 seconds
Started Aug 18 05:34:35 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 207560 kb
Host smart-e94e0f1b-acdb-4182-af83-25e8827fce40
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1084772357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.1084772357
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1333452568
Short name T968
Test name
Test status
Simulation time 151971831 ps
CPU time 0.85 seconds
Started Aug 18 05:34:44 PM PDT 24
Finished Aug 18 05:34:45 PM PDT 24
Peak memory 207424 kb
Host smart-ef8b3b7f-1ebd-4c61-818f-56cc31a144e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13334
52568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1333452568
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2317340460
Short name T25
Test name
Test status
Simulation time 48624722 ps
CPU time 0.65 seconds
Started Aug 18 05:34:55 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 207504 kb
Host smart-e15903b2-1a62-4160-bdba-793400763196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23173
40460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2317340460
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2946671246
Short name T1454
Test name
Test status
Simulation time 16806807017 ps
CPU time 50.49 seconds
Started Aug 18 05:35:03 PM PDT 24
Finished Aug 18 05:35:53 PM PDT 24
Peak memory 215824 kb
Host smart-3b808ce9-bd8e-464e-8bd1-180f8a520e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29466
71246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2946671246
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3254842106
Short name T2268
Test name
Test status
Simulation time 219259391 ps
CPU time 1.03 seconds
Started Aug 18 05:34:55 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 207524 kb
Host smart-3b9e3aba-9cf0-4664-aca6-972bce8e6a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32548
42106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3254842106
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.212126603
Short name T1494
Test name
Test status
Simulation time 193055927 ps
CPU time 0.9 seconds
Started Aug 18 05:34:54 PM PDT 24
Finished Aug 18 05:34:55 PM PDT 24
Peak memory 207436 kb
Host smart-917b7307-8f21-490c-945a-986e0d83f3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21212
6603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.212126603
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.1783116055
Short name T752
Test name
Test status
Simulation time 186459511 ps
CPU time 0.87 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:34:58 PM PDT 24
Peak memory 207508 kb
Host smart-00cbcbca-fa31-4457-aaf8-2f760ed24601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17831
16055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.1783116055
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.3907920438
Short name T558
Test name
Test status
Simulation time 202313276 ps
CPU time 0.99 seconds
Started Aug 18 05:34:58 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207412 kb
Host smart-07c530b6-bd84-474d-9053-f7fab160d1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39079
20438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.3907920438
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_resume_link_active.444998473
Short name T2612
Test name
Test status
Simulation time 20182717284 ps
CPU time 24.4 seconds
Started Aug 18 05:34:51 PM PDT 24
Finished Aug 18 05:35:15 PM PDT 24
Peak memory 207604 kb
Host smart-6f846931-5c88-48e4-91bb-65eb1a872b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44499
8473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_resume_link_active.444998473
Directory /workspace/19.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.744554499
Short name T1660
Test name
Test status
Simulation time 137459180 ps
CPU time 0.79 seconds
Started Aug 18 05:34:54 PM PDT 24
Finished Aug 18 05:34:55 PM PDT 24
Peak memory 207440 kb
Host smart-94324cc0-91f1-4a54-a72e-373a04052d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74455
4499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.744554499
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_rx_full.1401871344
Short name T924
Test name
Test status
Simulation time 372261432 ps
CPU time 1.31 seconds
Started Aug 18 05:34:53 PM PDT 24
Finished Aug 18 05:34:54 PM PDT 24
Peak memory 207448 kb
Host smart-ef2cad9e-0152-474d-84fa-025137586525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14018
71344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_full.1401871344
Directory /workspace/19.usbdev_rx_full/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.4100173784
Short name T619
Test name
Test status
Simulation time 149366253 ps
CPU time 0.85 seconds
Started Aug 18 05:35:02 PM PDT 24
Finished Aug 18 05:35:04 PM PDT 24
Peak memory 207524 kb
Host smart-c0f73c00-048a-47ef-a7ac-37d26320a759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41001
73784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.4100173784
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1374597784
Short name T608
Test name
Test status
Simulation time 194749447 ps
CPU time 0.91 seconds
Started Aug 18 05:35:00 PM PDT 24
Finished Aug 18 05:35:01 PM PDT 24
Peak memory 207472 kb
Host smart-8152f401-361d-4f0b-b6c7-051395fa6ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13745
97784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1374597784
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.52629486
Short name T3600
Test name
Test status
Simulation time 214406807 ps
CPU time 1.02 seconds
Started Aug 18 05:35:01 PM PDT 24
Finished Aug 18 05:35:03 PM PDT 24
Peak memory 207484 kb
Host smart-8f6edb96-b762-487d-b751-7bffa7bc28a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52629
486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.52629486
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2742286565
Short name T2819
Test name
Test status
Simulation time 1781745394 ps
CPU time 18.04 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:35:21 PM PDT 24
Peak memory 216552 kb
Host smart-105e0902-2948-43ff-90ea-2b495de63ecf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2742286565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2742286565
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.434402395
Short name T1254
Test name
Test status
Simulation time 157624701 ps
CPU time 0.88 seconds
Started Aug 18 05:34:58 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 207384 kb
Host smart-41aeb0f9-2422-4f33-81cd-c35110bda076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43440
2395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.434402395
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3287972384
Short name T3297
Test name
Test status
Simulation time 158995280 ps
CPU time 0.83 seconds
Started Aug 18 05:34:52 PM PDT 24
Finished Aug 18 05:34:53 PM PDT 24
Peak memory 207504 kb
Host smart-d699379f-09f6-47f4-b507-517976de2a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32879
72384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3287972384
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.2355908337
Short name T1412
Test name
Test status
Simulation time 460648167 ps
CPU time 1.4 seconds
Started Aug 18 05:34:53 PM PDT 24
Finished Aug 18 05:34:55 PM PDT 24
Peak memory 207508 kb
Host smart-4aa2543b-ee91-4f71-af1b-fa046ede771d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23559
08337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.2355908337
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.4132900607
Short name T2822
Test name
Test status
Simulation time 4213086658 ps
CPU time 121.64 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:37:31 PM PDT 24
Peak memory 216012 kb
Host smart-24e48a34-08c4-4b25-b28f-f99941c292dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41329
00607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.4132900607
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.1395187671
Short name T2974
Test name
Test status
Simulation time 149198399 ps
CPU time 0.89 seconds
Started Aug 18 05:34:42 PM PDT 24
Finished Aug 18 05:34:43 PM PDT 24
Peak memory 207364 kb
Host smart-1998d057-3398-492e-b181-d12276fa67b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395187671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.1395187671
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/19.usbdev_tx_rx_disruption.743150249
Short name T2339
Test name
Test status
Simulation time 494972065 ps
CPU time 1.54 seconds
Started Aug 18 05:34:55 PM PDT 24
Finished Aug 18 05:34:57 PM PDT 24
Peak memory 207492 kb
Host smart-b652eace-b920-4f51-93e8-bed54f70a4ab
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743150249 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.usbdev_tx_rx_disruption.743150249
Directory /workspace/19.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/190.usbdev_endpoint_types.2023004734
Short name T364
Test name
Test status
Simulation time 369529926 ps
CPU time 1.21 seconds
Started Aug 18 05:39:46 PM PDT 24
Finished Aug 18 05:39:48 PM PDT 24
Peak memory 207516 kb
Host smart-9e046831-e938-4366-897a-3454cc13d3b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2023004734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.usbdev_endpoint_types.2023004734
Directory /workspace/190.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/190.usbdev_tx_rx_disruption.3136473108
Short name T266
Test name
Test status
Simulation time 428158700 ps
CPU time 1.35 seconds
Started Aug 18 05:39:42 PM PDT 24
Finished Aug 18 05:39:43 PM PDT 24
Peak memory 207592 kb
Host smart-f133cc75-d517-40bb-b43f-87803e4ddfcb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136473108 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 190.usbdev_tx_rx_disruption.3136473108
Directory /workspace/190.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/191.usbdev_endpoint_types.3622336683
Short name T2090
Test name
Test status
Simulation time 387343946 ps
CPU time 1.24 seconds
Started Aug 18 05:39:49 PM PDT 24
Finished Aug 18 05:39:50 PM PDT 24
Peak memory 207540 kb
Host smart-c19be33b-0846-4b10-b7a5-0db1e5a16c7e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3622336683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.usbdev_endpoint_types.3622336683
Directory /workspace/191.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/191.usbdev_tx_rx_disruption.885089079
Short name T17
Test name
Test status
Simulation time 653951752 ps
CPU time 1.73 seconds
Started Aug 18 05:39:42 PM PDT 24
Finished Aug 18 05:39:44 PM PDT 24
Peak memory 207456 kb
Host smart-f3269093-e3e0-4d0d-a41a-5c1d40bff74d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885089079 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 191.usbdev_tx_rx_disruption.885089079
Directory /workspace/191.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/192.usbdev_endpoint_types.569894170
Short name T2047
Test name
Test status
Simulation time 376438229 ps
CPU time 1.24 seconds
Started Aug 18 05:39:45 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207552 kb
Host smart-b5d508a6-2f38-4963-9391-1678e48565f1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=569894170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_endpoint_types.569894170
Directory /workspace/192.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/192.usbdev_tx_rx_disruption.3817133952
Short name T123
Test name
Test status
Simulation time 694413721 ps
CPU time 1.79 seconds
Started Aug 18 05:39:40 PM PDT 24
Finished Aug 18 05:39:42 PM PDT 24
Peak memory 207584 kb
Host smart-c297413c-aea7-482f-a603-017542c64e29
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817133952 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.usbdev_tx_rx_disruption.3817133952
Directory /workspace/192.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/193.usbdev_tx_rx_disruption.977230545
Short name T200
Test name
Test status
Simulation time 631055897 ps
CPU time 1.7 seconds
Started Aug 18 05:39:48 PM PDT 24
Finished Aug 18 05:39:50 PM PDT 24
Peak memory 207504 kb
Host smart-e83df1c9-d3c6-4837-8e4b-c333f184bdac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977230545 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 193.usbdev_tx_rx_disruption.977230545
Directory /workspace/193.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/194.usbdev_endpoint_types.1353966597
Short name T437
Test name
Test status
Simulation time 683400682 ps
CPU time 1.85 seconds
Started Aug 18 05:39:44 PM PDT 24
Finished Aug 18 05:39:46 PM PDT 24
Peak memory 207408 kb
Host smart-a3f5fdc9-912a-49cc-a460-757696d6f084
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1353966597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_endpoint_types.1353966597
Directory /workspace/194.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/194.usbdev_tx_rx_disruption.633297148
Short name T2418
Test name
Test status
Simulation time 588915167 ps
CPU time 1.54 seconds
Started Aug 18 05:39:45 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207492 kb
Host smart-feb51465-e4c6-4247-8b97-2dc1684f93a0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633297148 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 194.usbdev_tx_rx_disruption.633297148
Directory /workspace/194.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/195.usbdev_endpoint_types.3123935117
Short name T429
Test name
Test status
Simulation time 352391040 ps
CPU time 1.18 seconds
Started Aug 18 05:39:42 PM PDT 24
Finished Aug 18 05:39:44 PM PDT 24
Peak memory 207460 kb
Host smart-6d6d1176-ec13-4df9-b950-6fbb036de871
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3123935117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_endpoint_types.3123935117
Directory /workspace/195.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/195.usbdev_tx_rx_disruption.3755935444
Short name T184
Test name
Test status
Simulation time 578522984 ps
CPU time 1.62 seconds
Started Aug 18 05:39:45 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207580 kb
Host smart-3f952677-5207-440d-a94b-2325788a66c9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755935444 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.usbdev_tx_rx_disruption.3755935444
Directory /workspace/195.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/196.usbdev_endpoint_types.2446151143
Short name T428
Test name
Test status
Simulation time 625545272 ps
CPU time 1.62 seconds
Started Aug 18 05:39:46 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207456 kb
Host smart-b2a55f23-bf91-43c6-a3ab-fd33144bb1ec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2446151143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_endpoint_types.2446151143
Directory /workspace/196.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/196.usbdev_tx_rx_disruption.551647066
Short name T3467
Test name
Test status
Simulation time 704513879 ps
CPU time 1.72 seconds
Started Aug 18 05:39:46 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207540 kb
Host smart-b44803a9-ac23-4673-807f-30305ed3d9f5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551647066 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 196.usbdev_tx_rx_disruption.551647066
Directory /workspace/196.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/197.usbdev_endpoint_types.382846289
Short name T2899
Test name
Test status
Simulation time 148303157 ps
CPU time 0.88 seconds
Started Aug 18 05:39:27 PM PDT 24
Finished Aug 18 05:39:28 PM PDT 24
Peak memory 207448 kb
Host smart-f5bb4207-307b-4e7a-a8eb-a32f149efbb2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=382846289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_endpoint_types.382846289
Directory /workspace/197.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/197.usbdev_tx_rx_disruption.1395083550
Short name T1534
Test name
Test status
Simulation time 659457021 ps
CPU time 1.78 seconds
Started Aug 18 05:39:23 PM PDT 24
Finished Aug 18 05:39:25 PM PDT 24
Peak memory 207540 kb
Host smart-989ec4e2-b62f-4514-aa89-2c07058cb52f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395083550 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.usbdev_tx_rx_disruption.1395083550
Directory /workspace/197.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/198.usbdev_endpoint_types.2379043352
Short name T439
Test name
Test status
Simulation time 356211183 ps
CPU time 1.2 seconds
Started Aug 18 05:39:27 PM PDT 24
Finished Aug 18 05:39:28 PM PDT 24
Peak memory 207504 kb
Host smart-da251e0d-b6d0-4e79-8310-ad6d75473d7b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2379043352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_endpoint_types.2379043352
Directory /workspace/198.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/198.usbdev_tx_rx_disruption.1915006359
Short name T2887
Test name
Test status
Simulation time 497560320 ps
CPU time 1.48 seconds
Started Aug 18 05:39:46 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207584 kb
Host smart-77719e71-29e8-49e0-985c-24352d0458d4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915006359 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 198.usbdev_tx_rx_disruption.1915006359
Directory /workspace/198.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/199.usbdev_endpoint_types.2512745456
Short name T1061
Test name
Test status
Simulation time 192730748 ps
CPU time 0.91 seconds
Started Aug 18 05:39:38 PM PDT 24
Finished Aug 18 05:39:39 PM PDT 24
Peak memory 207524 kb
Host smart-a4cb6551-8522-4e47-97f6-359d4daf6a60
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2512745456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.usbdev_endpoint_types.2512745456
Directory /workspace/199.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/199.usbdev_tx_rx_disruption.162569305
Short name T2857
Test name
Test status
Simulation time 533033422 ps
CPU time 1.57 seconds
Started Aug 18 05:39:26 PM PDT 24
Finished Aug 18 05:39:28 PM PDT 24
Peak memory 207584 kb
Host smart-bf7f5b06-2a7e-48c6-9d1d-2ec07396044f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162569305 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 199.usbdev_tx_rx_disruption.162569305
Directory /workspace/199.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3391585701
Short name T2423
Test name
Test status
Simulation time 36224588 ps
CPU time 0.67 seconds
Started Aug 18 05:32:07 PM PDT 24
Finished Aug 18 05:32:08 PM PDT 24
Peak memory 207416 kb
Host smart-db60ce09-f369-4e8d-b8ec-c2510bbeac6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3391585701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3391585701
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.3986632718
Short name T2808
Test name
Test status
Simulation time 5246631024 ps
CPU time 7.54 seconds
Started Aug 18 05:31:53 PM PDT 24
Finished Aug 18 05:32:01 PM PDT 24
Peak memory 215972 kb
Host smart-9481914b-f955-4cc4-9483-6f7a9c9830be
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986632718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.3986632718
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.367691125
Short name T274
Test name
Test status
Simulation time 19953609514 ps
CPU time 24.11 seconds
Started Aug 18 05:31:56 PM PDT 24
Finished Aug 18 05:32:20 PM PDT 24
Peak memory 207724 kb
Host smart-c1f6f96a-bb10-4f67-a518-8e47713406c5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=367691125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.367691125
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.3123689154
Short name T2272
Test name
Test status
Simulation time 25451704704 ps
CPU time 33.39 seconds
Started Aug 18 05:32:02 PM PDT 24
Finished Aug 18 05:32:36 PM PDT 24
Peak memory 215916 kb
Host smart-94bf52b9-13da-4103-9b50-6d6cc676bf78
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123689154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.3123689154
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3188579836
Short name T3023
Test name
Test status
Simulation time 158325803 ps
CPU time 0.88 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:31:55 PM PDT 24
Peak memory 207488 kb
Host smart-812d2f7f-b236-4e10-98d9-385fc986f00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31885
79836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3188579836
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.923061022
Short name T47
Test name
Test status
Simulation time 164273170 ps
CPU time 0.92 seconds
Started Aug 18 05:32:04 PM PDT 24
Finished Aug 18 05:32:05 PM PDT 24
Peak memory 207440 kb
Host smart-4639266c-0a7e-4a46-bad9-1dcceb33271c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92306
1022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.923061022
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.1716123677
Short name T53
Test name
Test status
Simulation time 137405683 ps
CPU time 0.87 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:31:59 PM PDT 24
Peak memory 207420 kb
Host smart-5318fc0a-6aeb-42cd-b2f1-c910e7ffe391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17161
23677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.1716123677
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2548111730
Short name T757
Test name
Test status
Simulation time 164637944 ps
CPU time 0.88 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:31:59 PM PDT 24
Peak memory 207548 kb
Host smart-7bf26d52-2072-443e-bd07-c76a49ecb8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25481
11730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2548111730
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.1390112516
Short name T1563
Test name
Test status
Simulation time 269568541 ps
CPU time 1.08 seconds
Started Aug 18 05:32:14 PM PDT 24
Finished Aug 18 05:32:15 PM PDT 24
Peak memory 207524 kb
Host smart-6cea6625-4adb-449f-b0c5-45d0010e343c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13901
12516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.1390112516
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.60903888
Short name T355
Test name
Test status
Simulation time 1188087084 ps
CPU time 2.96 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:32:01 PM PDT 24
Peak memory 207776 kb
Host smart-002a9662-25cf-42e5-8f95-607fc1ed1341
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=60903888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.60903888
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.2202536109
Short name T212
Test name
Test status
Simulation time 16280503825 ps
CPU time 27.73 seconds
Started Aug 18 05:31:51 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 207752 kb
Host smart-7470c23a-ac3a-49f5-87d9-2b2ddcfbc2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22025
36109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.2202536109
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.3393389059
Short name T2038
Test name
Test status
Simulation time 3386179899 ps
CPU time 29.87 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:32:27 PM PDT 24
Peak memory 207760 kb
Host smart-a8fd4e78-4386-49c8-b11b-b1670e0db3e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393389059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.3393389059
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.2571030835
Short name T2117
Test name
Test status
Simulation time 814879425 ps
CPU time 2.06 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:31:56 PM PDT 24
Peak memory 207496 kb
Host smart-337a9b7f-abd3-4503-9a01-cbbdc84f1a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25710
30835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.2571030835
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.1849750742
Short name T3604
Test name
Test status
Simulation time 175336412 ps
CPU time 0.87 seconds
Started Aug 18 05:31:55 PM PDT 24
Finished Aug 18 05:31:56 PM PDT 24
Peak memory 207512 kb
Host smart-61ca1a5d-ab61-4daf-a086-dc1ae0bb126a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18497
50742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.1849750742
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.3296604585
Short name T1617
Test name
Test status
Simulation time 42377818 ps
CPU time 0.68 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:31:59 PM PDT 24
Peak memory 207412 kb
Host smart-4d6ec1af-98e4-4b9f-ae1c-e392aa634d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32966
04585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3296604585
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.2606259343
Short name T1178
Test name
Test status
Simulation time 853490264 ps
CPU time 2.4 seconds
Started Aug 18 05:31:53 PM PDT 24
Finished Aug 18 05:31:56 PM PDT 24
Peak memory 207756 kb
Host smart-2d188a88-fec5-46a7-b4f0-61af1f891c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26062
59343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.2606259343
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_types.393240721
Short name T385
Test name
Test status
Simulation time 527668391 ps
CPU time 1.54 seconds
Started Aug 18 05:32:02 PM PDT 24
Finished Aug 18 05:32:03 PM PDT 24
Peak memory 207496 kb
Host smart-7a9b548d-d3ca-4aff-b085-f8d240976cce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=393240721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_types.393240721
Directory /workspace/2.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1488507013
Short name T1940
Test name
Test status
Simulation time 311605769 ps
CPU time 2.7 seconds
Started Aug 18 05:32:02 PM PDT 24
Finished Aug 18 05:32:05 PM PDT 24
Peak memory 207644 kb
Host smart-b17464d2-8473-4c65-80f2-9eb5170216da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14885
07013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1488507013
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.3514507673
Short name T2527
Test name
Test status
Simulation time 94199061687 ps
CPU time 158.76 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:34:37 PM PDT 24
Peak memory 207668 kb
Host smart-ff988f87-60ce-44d6-ac7a-c4242d316508
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3514507673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.3514507673
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.2481440818
Short name T1320
Test name
Test status
Simulation time 97168409399 ps
CPU time 153.54 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:34:31 PM PDT 24
Peak memory 207868 kb
Host smart-8f66b398-7d4a-4d1f-892c-8192a075da8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481440818 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.2481440818
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.2695452176
Short name T539
Test name
Test status
Simulation time 89106778601 ps
CPU time 150.21 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:34:27 PM PDT 24
Peak memory 207752 kb
Host smart-8f6eb66c-efa6-475c-86b6-4484d61b8122
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2695452176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.2695452176
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.79357536
Short name T840
Test name
Test status
Simulation time 101001413822 ps
CPU time 157.28 seconds
Started Aug 18 05:31:56 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 207800 kb
Host smart-edabf434-2154-4e2f-83c6-8e4624a66089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79357536 -assert nop
ostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.79357536
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.389287674
Short name T540
Test name
Test status
Simulation time 88177034669 ps
CPU time 136.3 seconds
Started Aug 18 05:32:01 PM PDT 24
Finished Aug 18 05:34:17 PM PDT 24
Peak memory 207720 kb
Host smart-e427af20-ebc4-4b5c-875a-b4bafcde55bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38928
7674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.389287674
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.126958254
Short name T1969
Test name
Test status
Simulation time 213715330 ps
CPU time 1.19 seconds
Started Aug 18 05:31:56 PM PDT 24
Finished Aug 18 05:31:57 PM PDT 24
Peak memory 215848 kb
Host smart-fed1801c-8c63-478d-8833-0cacede117ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=126958254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.126958254
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2491136290
Short name T2609
Test name
Test status
Simulation time 193607677 ps
CPU time 0.89 seconds
Started Aug 18 05:31:56 PM PDT 24
Finished Aug 18 05:31:57 PM PDT 24
Peak memory 207408 kb
Host smart-8b9e81f3-1e6f-4279-87d0-8d3dab602fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24911
36290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2491136290
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2760618799
Short name T2480
Test name
Test status
Simulation time 220022435 ps
CPU time 0.97 seconds
Started Aug 18 05:31:56 PM PDT 24
Finished Aug 18 05:31:57 PM PDT 24
Peak memory 207416 kb
Host smart-0b479768-2e89-449c-ae1a-7ec220caaaa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27606
18799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2760618799
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.3450648106
Short name T1139
Test name
Test status
Simulation time 3582643978 ps
CPU time 34.79 seconds
Started Aug 18 05:31:59 PM PDT 24
Finished Aug 18 05:32:35 PM PDT 24
Peak memory 224200 kb
Host smart-8d0dac10-ab96-4e5f-9dbe-5cac6b476c9f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3450648106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.3450648106
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.154583080
Short name T1716
Test name
Test status
Simulation time 11862108785 ps
CPU time 79.99 seconds
Started Aug 18 05:32:14 PM PDT 24
Finished Aug 18 05:33:34 PM PDT 24
Peak memory 207784 kb
Host smart-08884b9c-34eb-4d61-b253-acf541e8d688
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=154583080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.154583080
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.2072693164
Short name T764
Test name
Test status
Simulation time 186573354 ps
CPU time 0.97 seconds
Started Aug 18 05:31:55 PM PDT 24
Finished Aug 18 05:31:56 PM PDT 24
Peak memory 207500 kb
Host smart-6af4e41e-33f0-4f0d-ac3f-9c44e9d4fe3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20726
93164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2072693164
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.320528483
Short name T2760
Test name
Test status
Simulation time 29203907766 ps
CPU time 51.77 seconds
Started Aug 18 05:32:00 PM PDT 24
Finished Aug 18 05:32:52 PM PDT 24
Peak memory 207748 kb
Host smart-3fe6a3a3-bdcd-4f17-ae77-95056edcea3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32052
8483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.320528483
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.376397441
Short name T1496
Test name
Test status
Simulation time 10268439751 ps
CPU time 14.61 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:32:13 PM PDT 24
Peak memory 207764 kb
Host smart-f66a84aa-85b8-4759-b81b-6959beef863e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37639
7441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.376397441
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2778717900
Short name T818
Test name
Test status
Simulation time 3857752480 ps
CPU time 108.77 seconds
Started Aug 18 05:32:04 PM PDT 24
Finished Aug 18 05:33:53 PM PDT 24
Peak memory 216028 kb
Host smart-131a77f0-2a58-40b2-a038-96920fd313c1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2778717900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2778717900
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3841280603
Short name T2130
Test name
Test status
Simulation time 3641287636 ps
CPU time 27.82 seconds
Started Aug 18 05:31:57 PM PDT 24
Finished Aug 18 05:32:25 PM PDT 24
Peak memory 217652 kb
Host smart-4d275423-c94d-4e25-89ac-e1ce72cbf35c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3841280603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3841280603
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.1872822347
Short name T2337
Test name
Test status
Simulation time 252632349 ps
CPU time 1.09 seconds
Started Aug 18 05:32:01 PM PDT 24
Finished Aug 18 05:32:03 PM PDT 24
Peak memory 207504 kb
Host smart-37c4fb80-1dfa-44bf-806c-328b1db5be37
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1872822347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.1872822347
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2357510537
Short name T3134
Test name
Test status
Simulation time 192933108 ps
CPU time 0.97 seconds
Started Aug 18 05:31:59 PM PDT 24
Finished Aug 18 05:32:05 PM PDT 24
Peak memory 207448 kb
Host smart-3e02a6ed-8141-46fd-a93d-cf89814cd323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23575
10537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2357510537
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_non_iso_usb_traffic.1176452604
Short name T2036
Test name
Test status
Simulation time 3369115271 ps
CPU time 35.69 seconds
Started Aug 18 05:31:55 PM PDT 24
Finished Aug 18 05:32:33 PM PDT 24
Peak memory 217972 kb
Host smart-42aaf265-374f-498f-843e-026e70b18f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11764
52604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_non_iso_usb_traffic.1176452604
Directory /workspace/2.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.2320960158
Short name T2555
Test name
Test status
Simulation time 2259349614 ps
CPU time 65.2 seconds
Started Aug 18 05:32:07 PM PDT 24
Finished Aug 18 05:33:13 PM PDT 24
Peak memory 217528 kb
Host smart-ac822288-22c8-44bc-b59b-cc3ea70e095d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2320960158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.2320960158
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1750827060
Short name T2229
Test name
Test status
Simulation time 2796192131 ps
CPU time 28.14 seconds
Started Aug 18 05:32:07 PM PDT 24
Finished Aug 18 05:32:36 PM PDT 24
Peak memory 217580 kb
Host smart-619bab16-0004-4195-a3d7-afb666406cd5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1750827060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1750827060
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.2304227648
Short name T965
Test name
Test status
Simulation time 149258631 ps
CPU time 0.85 seconds
Started Aug 18 05:32:07 PM PDT 24
Finished Aug 18 05:32:08 PM PDT 24
Peak memory 207476 kb
Host smart-34a17a6d-d89c-419a-a73b-1c95ea92a2de
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2304227648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.2304227648
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3975726905
Short name T1743
Test name
Test status
Simulation time 140583962 ps
CPU time 0.82 seconds
Started Aug 18 05:32:04 PM PDT 24
Finished Aug 18 05:32:05 PM PDT 24
Peak memory 207500 kb
Host smart-2c01c219-8e15-41b7-ac85-a4ee5809be8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39757
26905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3975726905
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.3257510173
Short name T1499
Test name
Test status
Simulation time 228561900 ps
CPU time 0.97 seconds
Started Aug 18 05:32:15 PM PDT 24
Finished Aug 18 05:32:16 PM PDT 24
Peak memory 207432 kb
Host smart-175d1a01-f081-49b7-b0bf-95eba8a428b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32575
10173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.3257510173
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.144782306
Short name T3047
Test name
Test status
Simulation time 150759916 ps
CPU time 0.88 seconds
Started Aug 18 05:32:18 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 207480 kb
Host smart-be772335-607b-4ffe-b6b2-76616c0b0b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14478
2306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.144782306
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1890321960
Short name T570
Test name
Test status
Simulation time 200816098 ps
CPU time 0.94 seconds
Started Aug 18 05:32:13 PM PDT 24
Finished Aug 18 05:32:14 PM PDT 24
Peak memory 207568 kb
Host smart-bfdf8b6f-ca19-495b-a0da-8c7a08ae2357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18903
21960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1890321960
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3619399433
Short name T2759
Test name
Test status
Simulation time 181383766 ps
CPU time 0.87 seconds
Started Aug 18 05:32:16 PM PDT 24
Finished Aug 18 05:32:17 PM PDT 24
Peak memory 207596 kb
Host smart-052937dd-3f94-4055-8371-b28c6be76639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36193
99433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3619399433
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.3458924072
Short name T1332
Test name
Test status
Simulation time 202545184 ps
CPU time 1.02 seconds
Started Aug 18 05:32:32 PM PDT 24
Finished Aug 18 05:32:33 PM PDT 24
Peak memory 207564 kb
Host smart-8539a441-1011-4480-8081-d9f71f0a6733
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3458924072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.3458924072
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1952355205
Short name T581
Test name
Test status
Simulation time 233297368 ps
CPU time 1.06 seconds
Started Aug 18 05:32:00 PM PDT 24
Finished Aug 18 05:32:01 PM PDT 24
Peak memory 207360 kb
Host smart-ab5abab1-1308-47a5-8c55-17ac417f5dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19523
55205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1952355205
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3973752898
Short name T1390
Test name
Test status
Simulation time 137213328 ps
CPU time 0.79 seconds
Started Aug 18 05:32:16 PM PDT 24
Finished Aug 18 05:32:17 PM PDT 24
Peak memory 207476 kb
Host smart-d22da591-708d-4449-b00c-3a08f9be7232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39737
52898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3973752898
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2442256493
Short name T2982
Test name
Test status
Simulation time 29719797 ps
CPU time 0.68 seconds
Started Aug 18 05:32:00 PM PDT 24
Finished Aug 18 05:32:01 PM PDT 24
Peak memory 207524 kb
Host smart-19f4c222-ce29-44ea-9000-77660ed5bff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24422
56493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2442256493
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2243637175
Short name T2880
Test name
Test status
Simulation time 21391647356 ps
CPU time 54.32 seconds
Started Aug 18 05:32:14 PM PDT 24
Finished Aug 18 05:33:08 PM PDT 24
Peak memory 220380 kb
Host smart-1ff7edcc-c109-4f4d-9513-5ac41f533d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22436
37175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2243637175
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3914550823
Short name T3075
Test name
Test status
Simulation time 207390318 ps
CPU time 0.99 seconds
Started Aug 18 05:32:01 PM PDT 24
Finished Aug 18 05:32:02 PM PDT 24
Peak memory 207500 kb
Host smart-4a5a67f9-f05c-4e9e-babc-149c61415e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39145
50823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3914550823
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1361430955
Short name T552
Test name
Test status
Simulation time 193898475 ps
CPU time 0.88 seconds
Started Aug 18 05:32:17 PM PDT 24
Finished Aug 18 05:32:18 PM PDT 24
Peak memory 207436 kb
Host smart-022b2308-22f1-4db6-8886-b8a242302719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13614
30955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1361430955
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.578519860
Short name T1321
Test name
Test status
Simulation time 7835905349 ps
CPU time 72.79 seconds
Started Aug 18 05:32:06 PM PDT 24
Finished Aug 18 05:33:19 PM PDT 24
Peak memory 218576 kb
Host smart-f9eef5d1-ee78-4621-a48a-52e082c02170
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=578519860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.578519860
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.2851975297
Short name T3354
Test name
Test status
Simulation time 3268059738 ps
CPU time 31.84 seconds
Started Aug 18 05:32:12 PM PDT 24
Finished Aug 18 05:32:44 PM PDT 24
Peak memory 224172 kb
Host smart-c0af1d2e-8d14-46ad-ac37-4b506689553d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2851975297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.2851975297
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3918437814
Short name T2670
Test name
Test status
Simulation time 6538326008 ps
CPU time 25.84 seconds
Started Aug 18 05:32:16 PM PDT 24
Finished Aug 18 05:32:44 PM PDT 24
Peak memory 224100 kb
Host smart-07c0443e-ce1f-4b9d-80bc-b3752de45533
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918437814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3918437814
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.2114245474
Short name T2129
Test name
Test status
Simulation time 207128252 ps
CPU time 0.92 seconds
Started Aug 18 05:32:10 PM PDT 24
Finished Aug 18 05:32:11 PM PDT 24
Peak memory 207508 kb
Host smart-593b1ecf-9e5c-487a-9750-20acf6356c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21142
45474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.2114245474
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.834486947
Short name T1908
Test name
Test status
Simulation time 190443788 ps
CPU time 0.94 seconds
Started Aug 18 05:32:08 PM PDT 24
Finished Aug 18 05:32:09 PM PDT 24
Peak memory 207396 kb
Host smart-ccf26547-badf-4f01-b090-3746ab3f7fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83448
6947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.834486947
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_resume_link_active.2930149852
Short name T98
Test name
Test status
Simulation time 20168504514 ps
CPU time 25.47 seconds
Started Aug 18 05:32:08 PM PDT 24
Finished Aug 18 05:32:34 PM PDT 24
Peak memory 207604 kb
Host smart-88c6c0fc-e2e3-4755-b850-01dabac202d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29301
49852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_resume_link_active.2930149852
Directory /workspace/2.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.559657136
Short name T2936
Test name
Test status
Simulation time 229496789 ps
CPU time 0.97 seconds
Started Aug 18 05:32:08 PM PDT 24
Finished Aug 18 05:32:09 PM PDT 24
Peak memory 207496 kb
Host smart-4193e922-0cd0-45d5-b6e7-f82b00d05d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55965
7136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.559657136
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_full.118219626
Short name T1562
Test name
Test status
Simulation time 315787889 ps
CPU time 1.11 seconds
Started Aug 18 05:31:58 PM PDT 24
Finished Aug 18 05:32:00 PM PDT 24
Peak memory 207504 kb
Host smart-eaada129-f46c-4b75-b3da-726266393362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11821
9626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_full.118219626
Directory /workspace/2.usbdev_rx_full/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.206624425
Short name T72
Test name
Test status
Simulation time 159684198 ps
CPU time 0.88 seconds
Started Aug 18 05:32:07 PM PDT 24
Finished Aug 18 05:32:08 PM PDT 24
Peak memory 207504 kb
Host smart-6f06436f-6e9c-48d3-8787-14bcddc5b5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20662
4425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.206624425
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.70812370
Short name T253
Test name
Test status
Simulation time 553700725 ps
CPU time 1.41 seconds
Started Aug 18 05:32:15 PM PDT 24
Finished Aug 18 05:32:17 PM PDT 24
Peak memory 223464 kb
Host smart-1e0f9834-9e79-44b5-98de-26b872c7d944
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=70812370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.70812370
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.4033472587
Short name T45
Test name
Test status
Simulation time 394950006 ps
CPU time 1.37 seconds
Started Aug 18 05:32:06 PM PDT 24
Finished Aug 18 05:32:08 PM PDT 24
Peak memory 207568 kb
Host smart-8944b79c-1314-4625-b5d1-aa5e3affd9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40334
72587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.4033472587
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.4192924610
Short name T1696
Test name
Test status
Simulation time 363164700 ps
CPU time 1.2 seconds
Started Aug 18 05:32:12 PM PDT 24
Finished Aug 18 05:32:14 PM PDT 24
Peak memory 207636 kb
Host smart-5d5ce930-1899-4fa4-9459-6c8a4e24792d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41929
24610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.4192924610
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1133618503
Short name T681
Test name
Test status
Simulation time 160926925 ps
CPU time 0.88 seconds
Started Aug 18 05:32:15 PM PDT 24
Finished Aug 18 05:32:16 PM PDT 24
Peak memory 207424 kb
Host smart-09b519ba-d798-44b6-99c3-3b239ca9af1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11336
18503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1133618503
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2297008709
Short name T914
Test name
Test status
Simulation time 170264978 ps
CPU time 0.88 seconds
Started Aug 18 05:32:11 PM PDT 24
Finished Aug 18 05:32:12 PM PDT 24
Peak memory 207580 kb
Host smart-29c4f208-b276-4f65-8776-14f786658259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22970
08709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2297008709
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2289560530
Short name T1010
Test name
Test status
Simulation time 208507897 ps
CPU time 0.98 seconds
Started Aug 18 05:32:11 PM PDT 24
Finished Aug 18 05:32:13 PM PDT 24
Peak memory 207516 kb
Host smart-31c89501-e80c-4451-94db-12e3aa07b845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22895
60530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2289560530
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1023527284
Short name T1082
Test name
Test status
Simulation time 1901046168 ps
CPU time 55.28 seconds
Started Aug 18 05:32:07 PM PDT 24
Finished Aug 18 05:33:03 PM PDT 24
Peak memory 215908 kb
Host smart-f3c9ad7b-a42c-4c07-a7d5-7916b2477de6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1023527284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1023527284
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.568439189
Short name T1923
Test name
Test status
Simulation time 157818408 ps
CPU time 0.86 seconds
Started Aug 18 05:32:15 PM PDT 24
Finished Aug 18 05:32:16 PM PDT 24
Peak memory 207496 kb
Host smart-d05653a5-95ee-4cab-9465-ecbfdffedf6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56843
9189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.568439189
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1591958580
Short name T1313
Test name
Test status
Simulation time 167590636 ps
CPU time 0.91 seconds
Started Aug 18 05:32:23 PM PDT 24
Finished Aug 18 05:32:24 PM PDT 24
Peak memory 207480 kb
Host smart-511750ea-c4da-4fbd-9723-83cc18b9a9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15919
58580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1591958580
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.2384361954
Short name T3216
Test name
Test status
Simulation time 1208658790 ps
CPU time 3 seconds
Started Aug 18 05:32:07 PM PDT 24
Finished Aug 18 05:32:10 PM PDT 24
Peak memory 207784 kb
Host smart-cfe57bd9-a243-4b0f-85e1-6251fdbce103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23843
61954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.2384361954
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2684936417
Short name T819
Test name
Test status
Simulation time 2601719853 ps
CPU time 27 seconds
Started Aug 18 05:32:06 PM PDT 24
Finished Aug 18 05:32:33 PM PDT 24
Peak memory 217732 kb
Host smart-2395535f-9966-43e0-b012-ced11c6639b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26849
36417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2684936417
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.563258779
Short name T326
Test name
Test status
Simulation time 3396581778 ps
CPU time 26.64 seconds
Started Aug 18 05:32:11 PM PDT 24
Finished Aug 18 05:32:38 PM PDT 24
Peak memory 217468 kb
Host smart-2a2f09b8-0f8c-4fe5-9fb9-87703526e1ca
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563258779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.563258779
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.509542088
Short name T749
Test name
Test status
Simulation time 2077217193 ps
CPU time 17.3 seconds
Started Aug 18 05:32:04 PM PDT 24
Finished Aug 18 05:32:21 PM PDT 24
Peak memory 207712 kb
Host smart-138ea0a7-f63e-4208-acd1-680f6d100e6b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509542088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host_
handshake.509542088
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/2.usbdev_tx_rx_disruption.3469112039
Short name T2063
Test name
Test status
Simulation time 536293124 ps
CPU time 1.51 seconds
Started Aug 18 05:32:12 PM PDT 24
Finished Aug 18 05:32:14 PM PDT 24
Peak memory 207576 kb
Host smart-b1641f02-fa61-4744-b2d9-862ab51eb863
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469112039 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.usbdev_tx_rx_disruption.3469112039
Directory /workspace/2.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.2459821250
Short name T1583
Test name
Test status
Simulation time 46501885 ps
CPU time 0.7 seconds
Started Aug 18 05:35:15 PM PDT 24
Finished Aug 18 05:35:15 PM PDT 24
Peak memory 207360 kb
Host smart-860d307c-aabb-45cd-a30c-ea95d87ec6c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2459821250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.2459821250
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2210520387
Short name T1853
Test name
Test status
Simulation time 9850139395 ps
CPU time 11.91 seconds
Started Aug 18 05:34:56 PM PDT 24
Finished Aug 18 05:35:08 PM PDT 24
Peak memory 207796 kb
Host smart-a439e9ef-03b2-41b5-bfcf-9a4f5c69d111
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210520387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_disconnect.2210520387
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.372477235
Short name T236
Test name
Test status
Simulation time 16412316310 ps
CPU time 21.61 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:35:19 PM PDT 24
Peak memory 215824 kb
Host smart-39815e98-ef87-4efc-a916-2cde0b96c538
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=372477235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.372477235
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.3557378959
Short name T1934
Test name
Test status
Simulation time 30924418886 ps
CPU time 36.98 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:35:34 PM PDT 24
Peak memory 207856 kb
Host smart-69abbaaa-191c-4c03-a5a9-5d7e524e31e4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557378959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.3557378959
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2662150234
Short name T3313
Test name
Test status
Simulation time 244152103 ps
CPU time 0.94 seconds
Started Aug 18 05:34:59 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 207456 kb
Host smart-3ec5d3af-def8-4c1c-96de-49dee2f51acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26621
50234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2662150234
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1197237366
Short name T3219
Test name
Test status
Simulation time 151829465 ps
CPU time 0.89 seconds
Started Aug 18 05:34:59 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 207428 kb
Host smart-1ba693a9-2e60-49bf-9175-2a135ba6ffca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11972
37366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1197237366
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.1968717082
Short name T1585
Test name
Test status
Simulation time 341356744 ps
CPU time 1.36 seconds
Started Aug 18 05:34:55 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 207584 kb
Host smart-77e3612d-b614-4770-8f3d-14030060e71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19687
17082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.1968717082
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1158581430
Short name T350
Test name
Test status
Simulation time 1414239777 ps
CPU time 3.64 seconds
Started Aug 18 05:34:56 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 207720 kb
Host smart-556aae69-096b-4c03-b182-fb22fa5ee016
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1158581430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1158581430
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.527144706
Short name T3121
Test name
Test status
Simulation time 39225499723 ps
CPU time 61.31 seconds
Started Aug 18 05:34:59 PM PDT 24
Finished Aug 18 05:36:01 PM PDT 24
Peak memory 207748 kb
Host smart-1d35dee7-5522-4b74-b231-fdeb957fafc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52714
4706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.527144706
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.744036200
Short name T1219
Test name
Test status
Simulation time 878173695 ps
CPU time 5.2 seconds
Started Aug 18 05:34:45 PM PDT 24
Finished Aug 18 05:34:51 PM PDT 24
Peak memory 207724 kb
Host smart-796933a5-6766-47ab-bf76-ecd5da07df0f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744036200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.744036200
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.23552381
Short name T1101
Test name
Test status
Simulation time 718970315 ps
CPU time 1.82 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207544 kb
Host smart-09bc656f-4c4b-4373-9ab1-ed367eafc1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23552
381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.23552381
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.3145798334
Short name T2571
Test name
Test status
Simulation time 144384049 ps
CPU time 0.84 seconds
Started Aug 18 05:34:58 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 207548 kb
Host smart-452c43c5-1f2d-4f9b-8d90-0effd8fb3f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31457
98334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.3145798334
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1051703585
Short name T999
Test name
Test status
Simulation time 87152819 ps
CPU time 0.75 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:34:58 PM PDT 24
Peak memory 207448 kb
Host smart-ef33fd47-5780-488a-a7da-84c56f3facac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10517
03585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1051703585
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.2791819235
Short name T3389
Test name
Test status
Simulation time 980513546 ps
CPU time 2.56 seconds
Started Aug 18 05:34:56 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207760 kb
Host smart-206ec524-ec62-486e-935b-278b6bf8b230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27918
19235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2791819235
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_types.2757100824
Short name T496
Test name
Test status
Simulation time 402636725 ps
CPU time 1.23 seconds
Started Aug 18 05:34:52 PM PDT 24
Finished Aug 18 05:34:53 PM PDT 24
Peak memory 207512 kb
Host smart-1360d661-122c-4ffe-8bab-ea94f63b51aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2757100824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_types.2757100824
Directory /workspace/20.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3562401339
Short name T2139
Test name
Test status
Simulation time 160000962 ps
CPU time 1.38 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207648 kb
Host smart-d94d713e-f4e5-4a76-b3d0-2f071b5f2965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35624
01339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3562401339
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1480295965
Short name T1822
Test name
Test status
Simulation time 229607953 ps
CPU time 1.31 seconds
Started Aug 18 05:34:58 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 215840 kb
Host smart-f81004cd-a4d8-4d6f-87a7-b08a413b7fb2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1480295965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1480295965
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.655787548
Short name T1518
Test name
Test status
Simulation time 182607508 ps
CPU time 0.9 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207464 kb
Host smart-a4b84182-2969-41d3-98df-3aed732a5ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65578
7548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.655787548
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2188968390
Short name T2171
Test name
Test status
Simulation time 200991179 ps
CPU time 0.92 seconds
Started Aug 18 05:34:56 PM PDT 24
Finished Aug 18 05:34:57 PM PDT 24
Peak memory 207488 kb
Host smart-6c18c410-3411-4a83-85f2-86ebabca427c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21889
68390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2188968390
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.3108663110
Short name T1883
Test name
Test status
Simulation time 3970765311 ps
CPU time 31.01 seconds
Started Aug 18 05:35:12 PM PDT 24
Finished Aug 18 05:35:43 PM PDT 24
Peak memory 224152 kb
Host smart-0326c3ec-bdc5-4322-b79b-4fc68bacb785
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3108663110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.3108663110
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.3710684623
Short name T1754
Test name
Test status
Simulation time 4672684690 ps
CPU time 33.74 seconds
Started Aug 18 05:34:59 PM PDT 24
Finished Aug 18 05:35:33 PM PDT 24
Peak memory 207708 kb
Host smart-84802b18-43a6-414c-b40f-b12620fbed3c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3710684623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.3710684623
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.856468342
Short name T1888
Test name
Test status
Simulation time 195509244 ps
CPU time 1.01 seconds
Started Aug 18 05:34:54 PM PDT 24
Finished Aug 18 05:34:55 PM PDT 24
Peak memory 207508 kb
Host smart-d9662ca9-0973-4baa-adf4-a7886b8ad7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85646
8342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.856468342
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.1624877496
Short name T35
Test name
Test status
Simulation time 32094701862 ps
CPU time 53.72 seconds
Started Aug 18 05:34:54 PM PDT 24
Finished Aug 18 05:35:48 PM PDT 24
Peak memory 207840 kb
Host smart-49c3434a-1761-4915-9873-713bfe517a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16248
77496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.1624877496
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.1759132524
Short name T1571
Test name
Test status
Simulation time 4957424198 ps
CPU time 7.74 seconds
Started Aug 18 05:34:59 PM PDT 24
Finished Aug 18 05:35:07 PM PDT 24
Peak memory 207768 kb
Host smart-bbfd1e06-f8f7-4a10-9787-122b28cef5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17591
32524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.1759132524
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.3717797333
Short name T2541
Test name
Test status
Simulation time 2960941069 ps
CPU time 23.31 seconds
Started Aug 18 05:34:55 PM PDT 24
Finished Aug 18 05:35:18 PM PDT 24
Peak memory 224124 kb
Host smart-753f54f8-d350-48fc-96a1-58ba5c210886
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3717797333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.3717797333
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.843662635
Short name T577
Test name
Test status
Simulation time 2391498841 ps
CPU time 67.74 seconds
Started Aug 18 05:34:59 PM PDT 24
Finished Aug 18 05:36:07 PM PDT 24
Peak memory 217668 kb
Host smart-1f9cd46d-d19e-4ec1-8182-748fc86c1738
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=843662635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.843662635
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.1165027307
Short name T1018
Test name
Test status
Simulation time 263058135 ps
CPU time 1.02 seconds
Started Aug 18 05:34:53 PM PDT 24
Finished Aug 18 05:34:54 PM PDT 24
Peak memory 207488 kb
Host smart-9e40f345-68b0-444b-94ae-b47e4c38cce9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1165027307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.1165027307
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.718681390
Short name T3309
Test name
Test status
Simulation time 212668050 ps
CPU time 1.02 seconds
Started Aug 18 05:35:06 PM PDT 24
Finished Aug 18 05:35:07 PM PDT 24
Peak memory 207480 kb
Host smart-5ead76b4-6881-4631-973b-94e82523adc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71868
1390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.718681390
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_non_iso_usb_traffic.2218762785
Short name T2828
Test name
Test status
Simulation time 1953911776 ps
CPU time 15.09 seconds
Started Aug 18 05:35:16 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 217780 kb
Host smart-572a2c62-553e-4117-adb5-c5c776dc8cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22187
62785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_non_iso_usb_traffic.2218762785
Directory /workspace/20.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.1049936195
Short name T1836
Test name
Test status
Simulation time 2242745962 ps
CPU time 62.33 seconds
Started Aug 18 05:34:55 PM PDT 24
Finished Aug 18 05:35:58 PM PDT 24
Peak memory 215864 kb
Host smart-e1aee770-3536-4190-8016-f3a28784be6c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1049936195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.1049936195
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1646871804
Short name T2708
Test name
Test status
Simulation time 155298023 ps
CPU time 0.89 seconds
Started Aug 18 05:34:55 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 207488 kb
Host smart-6b19494c-bfc5-40a7-b2e4-d5ea2769751c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1646871804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1646871804
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1454636155
Short name T1222
Test name
Test status
Simulation time 153015221 ps
CPU time 0.89 seconds
Started Aug 18 05:34:51 PM PDT 24
Finished Aug 18 05:34:53 PM PDT 24
Peak memory 207468 kb
Host smart-40d7cd8b-1334-436b-a187-9226bcced200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14546
36155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1454636155
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1586996085
Short name T163
Test name
Test status
Simulation time 218338150 ps
CPU time 1.07 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:35:03 PM PDT 24
Peak memory 207448 kb
Host smart-83d8e448-13fe-48f3-9cc7-b5562093707f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15869
96085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1586996085
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2777548046
Short name T1364
Test name
Test status
Simulation time 194401764 ps
CPU time 0.89 seconds
Started Aug 18 05:34:58 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207424 kb
Host smart-4c96729d-5d4b-44b4-a775-dd82538cfc26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27775
48046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2777548046
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3890619832
Short name T1842
Test name
Test status
Simulation time 195310174 ps
CPU time 1.03 seconds
Started Aug 18 05:34:49 PM PDT 24
Finished Aug 18 05:34:50 PM PDT 24
Peak memory 207504 kb
Host smart-92d8b4c1-6cc0-43bf-b730-d62f2e1b0747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38906
19832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3890619832
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3585021191
Short name T141
Test name
Test status
Simulation time 189253033 ps
CPU time 0.9 seconds
Started Aug 18 05:34:54 PM PDT 24
Finished Aug 18 05:34:55 PM PDT 24
Peak memory 207464 kb
Host smart-41f810b9-a0c2-4f6f-81d8-50acfaf59869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35850
21191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3585021191
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2208217527
Short name T226
Test name
Test status
Simulation time 158039245 ps
CPU time 0.91 seconds
Started Aug 18 05:34:54 PM PDT 24
Finished Aug 18 05:34:55 PM PDT 24
Peak memory 207488 kb
Host smart-4c817b7b-b4e5-44f7-a20d-eef1fcdce703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22082
17527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2208217527
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.3839447691
Short name T2424
Test name
Test status
Simulation time 229749188 ps
CPU time 1.02 seconds
Started Aug 18 05:34:46 PM PDT 24
Finished Aug 18 05:34:47 PM PDT 24
Peak memory 207492 kb
Host smart-a003ffd5-7e57-4aa1-82c4-b33c2e9d69e5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3839447691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.3839447691
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.4180222686
Short name T1431
Test name
Test status
Simulation time 141187484 ps
CPU time 0.85 seconds
Started Aug 18 05:34:59 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 207252 kb
Host smart-a3e0787f-1b66-4be6-aade-47287fa6ab68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41802
22686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.4180222686
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2907761641
Short name T2729
Test name
Test status
Simulation time 45277765 ps
CPU time 0.7 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:34:58 PM PDT 24
Peak memory 207520 kb
Host smart-34cc9859-c511-4285-92c4-f7b4557c2d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29077
61641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2907761641
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1171937197
Short name T2589
Test name
Test status
Simulation time 18849340605 ps
CPU time 49.08 seconds
Started Aug 18 05:34:54 PM PDT 24
Finished Aug 18 05:35:44 PM PDT 24
Peak memory 215944 kb
Host smart-c0d62e39-a27a-4b06-bf9c-51a82bac3c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11719
37197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1171937197
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2491660121
Short name T1384
Test name
Test status
Simulation time 168145810 ps
CPU time 0.88 seconds
Started Aug 18 05:35:00 PM PDT 24
Finished Aug 18 05:35:01 PM PDT 24
Peak memory 207472 kb
Host smart-cc114c53-89f5-4b0c-b099-3a0923b5db26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24916
60121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2491660121
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.4095096608
Short name T1485
Test name
Test status
Simulation time 212727416 ps
CPU time 0.95 seconds
Started Aug 18 05:34:55 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 207464 kb
Host smart-697261a9-d249-409d-84ab-5f90c65801a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40950
96608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.4095096608
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.1691553360
Short name T755
Test name
Test status
Simulation time 220068563 ps
CPU time 0.94 seconds
Started Aug 18 05:34:54 PM PDT 24
Finished Aug 18 05:34:55 PM PDT 24
Peak memory 207468 kb
Host smart-00afed59-923f-465d-a987-cc7075b0ba48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16915
53360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.1691553360
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.2738503417
Short name T777
Test name
Test status
Simulation time 168008254 ps
CPU time 0.93 seconds
Started Aug 18 05:34:53 PM PDT 24
Finished Aug 18 05:34:54 PM PDT 24
Peak memory 207484 kb
Host smart-c7a542ba-54ec-4517-8b1d-63a9bd776d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27385
03417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.2738503417
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.342207283
Short name T772
Test name
Test status
Simulation time 196207940 ps
CPU time 0.88 seconds
Started Aug 18 05:34:55 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 207424 kb
Host smart-2296dd5e-2ddf-4be8-b464-0c8a4bc91ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34220
7283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.342207283
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_rx_full.1957779040
Short name T3320
Test name
Test status
Simulation time 375573975 ps
CPU time 1.28 seconds
Started Aug 18 05:34:54 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 207504 kb
Host smart-8519ea90-9311-4573-af7a-a305837789e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19577
79040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_full.1957779040
Directory /workspace/20.usbdev_rx_full/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2862556879
Short name T1214
Test name
Test status
Simulation time 151564160 ps
CPU time 0.86 seconds
Started Aug 18 05:34:55 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 207548 kb
Host smart-5e65d58f-3e33-4724-9b1c-81bfb0da9a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28625
56879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2862556879
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2264250232
Short name T943
Test name
Test status
Simulation time 148501922 ps
CPU time 0.93 seconds
Started Aug 18 05:35:16 PM PDT 24
Finished Aug 18 05:35:17 PM PDT 24
Peak memory 207396 kb
Host smart-d2f93594-3673-476e-86bc-26d8cce53fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22642
50232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2264250232
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.452552446
Short name T3038
Test name
Test status
Simulation time 204617862 ps
CPU time 0.97 seconds
Started Aug 18 05:35:04 PM PDT 24
Finished Aug 18 05:35:05 PM PDT 24
Peak memory 207488 kb
Host smart-8f59d57f-902f-4518-b5fd-c42c98f9487f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45255
2446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.452552446
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.2835107454
Short name T1576
Test name
Test status
Simulation time 2902061305 ps
CPU time 21.69 seconds
Started Aug 18 05:34:55 PM PDT 24
Finished Aug 18 05:35:17 PM PDT 24
Peak memory 217928 kb
Host smart-19cd7dd7-20ba-479d-83f9-99b9ded813dc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2835107454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.2835107454
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1774569917
Short name T854
Test name
Test status
Simulation time 176573470 ps
CPU time 0.98 seconds
Started Aug 18 05:34:53 PM PDT 24
Finished Aug 18 05:34:54 PM PDT 24
Peak memory 207488 kb
Host smart-4b93ccac-df77-4d80-b129-aea18423efd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17745
69917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1774569917
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.881691483
Short name T2034
Test name
Test status
Simulation time 142305158 ps
CPU time 0.8 seconds
Started Aug 18 05:34:54 PM PDT 24
Finished Aug 18 05:34:55 PM PDT 24
Peak memory 207508 kb
Host smart-bac4a87b-d66f-45da-99e6-4722cdc97d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88169
1483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.881691483
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.2915859365
Short name T592
Test name
Test status
Simulation time 1140447224 ps
CPU time 2.64 seconds
Started Aug 18 05:34:53 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 207680 kb
Host smart-8dbc03ac-f85f-4d1f-a497-35375c4dbcd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29158
59365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.2915859365
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.4108399047
Short name T2632
Test name
Test status
Simulation time 3904997993 ps
CPU time 113.39 seconds
Started Aug 18 05:34:59 PM PDT 24
Finished Aug 18 05:36:52 PM PDT 24
Peak memory 216004 kb
Host smart-56b29699-0a6e-446d-b3d0-085bbc65a775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41083
99047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.4108399047
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.1447463470
Short name T779
Test name
Test status
Simulation time 2497718544 ps
CPU time 21.88 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:35:19 PM PDT 24
Peak memory 207564 kb
Host smart-24b69641-d924-4c3d-adbd-a6bc732e3dc4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447463470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.1447463470
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_tx_rx_disruption.2944746926
Short name T1352
Test name
Test status
Simulation time 525783575 ps
CPU time 1.74 seconds
Started Aug 18 05:34:59 PM PDT 24
Finished Aug 18 05:35:01 PM PDT 24
Peak memory 207580 kb
Host smart-bc94d656-55c2-456b-987e-ee9766f7a2d7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944746926 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.usbdev_tx_rx_disruption.2944746926
Directory /workspace/20.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/200.usbdev_tx_rx_disruption.4218706196
Short name T3370
Test name
Test status
Simulation time 475910534 ps
CPU time 1.44 seconds
Started Aug 18 05:39:40 PM PDT 24
Finished Aug 18 05:39:41 PM PDT 24
Peak memory 207564 kb
Host smart-b79ce652-4fb1-4d40-b479-2fb7736d02f3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218706196 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.usbdev_tx_rx_disruption.4218706196
Directory /workspace/200.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/201.usbdev_tx_rx_disruption.2248321661
Short name T1210
Test name
Test status
Simulation time 620905340 ps
CPU time 1.79 seconds
Started Aug 18 05:39:25 PM PDT 24
Finished Aug 18 05:39:27 PM PDT 24
Peak memory 207548 kb
Host smart-2fb646e5-dd71-414d-866a-330430bae030
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248321661 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.usbdev_tx_rx_disruption.2248321661
Directory /workspace/201.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/202.usbdev_tx_rx_disruption.2267325440
Short name T2148
Test name
Test status
Simulation time 526978910 ps
CPU time 1.66 seconds
Started Aug 18 05:39:36 PM PDT 24
Finished Aug 18 05:39:38 PM PDT 24
Peak memory 207496 kb
Host smart-2279b94e-edaa-4d7f-a68a-bacf70e1c682
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267325440 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.usbdev_tx_rx_disruption.2267325440
Directory /workspace/202.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/203.usbdev_tx_rx_disruption.2674927055
Short name T583
Test name
Test status
Simulation time 663920507 ps
CPU time 1.77 seconds
Started Aug 18 05:39:47 PM PDT 24
Finished Aug 18 05:39:49 PM PDT 24
Peak memory 207604 kb
Host smart-21110626-fc14-4a9e-92b9-5a97cdb4ecae
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674927055 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 203.usbdev_tx_rx_disruption.2674927055
Directory /workspace/203.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/204.usbdev_tx_rx_disruption.1518369771
Short name T2613
Test name
Test status
Simulation time 487413477 ps
CPU time 1.44 seconds
Started Aug 18 05:39:33 PM PDT 24
Finished Aug 18 05:39:34 PM PDT 24
Peak memory 207572 kb
Host smart-f68be15f-26bc-40bd-be74-3126ecd9891f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518369771 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 204.usbdev_tx_rx_disruption.1518369771
Directory /workspace/204.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/205.usbdev_tx_rx_disruption.3085987615
Short name T2532
Test name
Test status
Simulation time 658343791 ps
CPU time 1.77 seconds
Started Aug 18 05:39:51 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207456 kb
Host smart-f21e38d3-6fd9-4031-9318-705370319c20
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085987615 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.usbdev_tx_rx_disruption.3085987615
Directory /workspace/205.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/206.usbdev_tx_rx_disruption.1937228355
Short name T3325
Test name
Test status
Simulation time 608569610 ps
CPU time 1.64 seconds
Started Aug 18 05:39:42 PM PDT 24
Finished Aug 18 05:39:43 PM PDT 24
Peak memory 207564 kb
Host smart-a60aa04c-f2bc-4b5f-a0d8-9807d54130e6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937228355 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 206.usbdev_tx_rx_disruption.1937228355
Directory /workspace/206.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/207.usbdev_tx_rx_disruption.2780800329
Short name T180
Test name
Test status
Simulation time 620316857 ps
CPU time 1.72 seconds
Started Aug 18 05:39:31 PM PDT 24
Finished Aug 18 05:39:33 PM PDT 24
Peak memory 207480 kb
Host smart-ebf30990-32d6-47f3-8d4b-46b3be018a01
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780800329 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.usbdev_tx_rx_disruption.2780800329
Directory /workspace/207.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/208.usbdev_tx_rx_disruption.4072523570
Short name T652
Test name
Test status
Simulation time 445950873 ps
CPU time 1.42 seconds
Started Aug 18 05:39:54 PM PDT 24
Finished Aug 18 05:39:55 PM PDT 24
Peak memory 207588 kb
Host smart-0a670516-4f88-41a1-ac69-a008e4342b2f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072523570 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 208.usbdev_tx_rx_disruption.4072523570
Directory /workspace/208.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/209.usbdev_tx_rx_disruption.1276925942
Short name T220
Test name
Test status
Simulation time 579773151 ps
CPU time 1.56 seconds
Started Aug 18 05:39:44 PM PDT 24
Finished Aug 18 05:39:46 PM PDT 24
Peak memory 207544 kb
Host smart-8a6fabe0-1be0-4471-901b-530081fe1860
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276925942 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 209.usbdev_tx_rx_disruption.1276925942
Directory /workspace/209.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.270837170
Short name T1225
Test name
Test status
Simulation time 43959649 ps
CPU time 0.69 seconds
Started Aug 18 05:35:00 PM PDT 24
Finished Aug 18 05:35:01 PM PDT 24
Peak memory 207468 kb
Host smart-4420a34b-326c-42f8-829b-af160c7e5255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=270837170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.270837170
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3144283070
Short name T2824
Test name
Test status
Simulation time 6204995977 ps
CPU time 9.44 seconds
Started Aug 18 05:34:59 PM PDT 24
Finished Aug 18 05:35:09 PM PDT 24
Peak memory 216004 kb
Host smart-f9655679-ca67-4a24-98cf-39544ec0f076
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144283070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_disconnect.3144283070
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.2197733803
Short name T1782
Test name
Test status
Simulation time 13913057565 ps
CPU time 18.78 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:35:16 PM PDT 24
Peak memory 215916 kb
Host smart-6386263c-f00d-477f-a1a1-b4b6dbb39e87
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197733803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2197733803
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.167731680
Short name T2154
Test name
Test status
Simulation time 23442413999 ps
CPU time 26.49 seconds
Started Aug 18 05:35:10 PM PDT 24
Finished Aug 18 05:35:37 PM PDT 24
Peak memory 215912 kb
Host smart-c051dc43-86fe-47bd-acfe-e6058d118912
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167731680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_ao
n_wake_resume.167731680
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3992922853
Short name T1869
Test name
Test status
Simulation time 150869805 ps
CPU time 0.87 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:34:58 PM PDT 24
Peak memory 207528 kb
Host smart-565b693e-0805-4a8d-a4fc-9cad1b121b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39929
22853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3992922853
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.1326503436
Short name T77
Test name
Test status
Simulation time 147844463 ps
CPU time 0.93 seconds
Started Aug 18 05:35:18 PM PDT 24
Finished Aug 18 05:35:19 PM PDT 24
Peak memory 207268 kb
Host smart-ac42973f-f9fd-4b61-8e88-776654ce61f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13265
03436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.1326503436
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.3829948234
Short name T1020
Test name
Test status
Simulation time 421713943 ps
CPU time 1.45 seconds
Started Aug 18 05:35:14 PM PDT 24
Finished Aug 18 05:35:16 PM PDT 24
Peak memory 207572 kb
Host smart-83a5cc05-3af3-4ec4-a028-5c11cfa7fddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38299
48234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.3829948234
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3376629631
Short name T1910
Test name
Test status
Simulation time 1050941058 ps
CPU time 2.67 seconds
Started Aug 18 05:35:06 PM PDT 24
Finished Aug 18 05:35:09 PM PDT 24
Peak memory 207684 kb
Host smart-3d7c607b-ec1e-4456-8657-3e983e42f913
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3376629631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3376629631
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.2795506631
Short name T137
Test name
Test status
Simulation time 50058822994 ps
CPU time 85.05 seconds
Started Aug 18 05:34:56 PM PDT 24
Finished Aug 18 05:36:22 PM PDT 24
Peak memory 207716 kb
Host smart-10712589-b4a2-443b-a9e7-638ab8783658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27955
06631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.2795506631
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.2910500425
Short name T3114
Test name
Test status
Simulation time 4931239690 ps
CPU time 36.23 seconds
Started Aug 18 05:34:59 PM PDT 24
Finished Aug 18 05:35:36 PM PDT 24
Peak memory 207764 kb
Host smart-87c0736b-e294-4a37-a6d1-fbab52e4bda5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910500425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.2910500425
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.96055423
Short name T2778
Test name
Test status
Simulation time 634538828 ps
CPU time 1.53 seconds
Started Aug 18 05:34:59 PM PDT 24
Finished Aug 18 05:35:01 PM PDT 24
Peak memory 207528 kb
Host smart-b16d9942-8f7d-4658-9edf-7bf3c8d907bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96055
423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.96055423
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3560699000
Short name T1312
Test name
Test status
Simulation time 138224049 ps
CPU time 0.82 seconds
Started Aug 18 05:35:17 PM PDT 24
Finished Aug 18 05:35:18 PM PDT 24
Peak memory 207540 kb
Host smart-b4126dd4-2f1a-417d-9016-d4f22f591577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35606
99000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3560699000
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1480795447
Short name T1809
Test name
Test status
Simulation time 50178912 ps
CPU time 0.7 seconds
Started Aug 18 05:35:12 PM PDT 24
Finished Aug 18 05:35:13 PM PDT 24
Peak memory 207432 kb
Host smart-ff8a2f59-5840-47c7-92c9-d8ad380cd8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14807
95447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1480795447
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1103354667
Short name T2206
Test name
Test status
Simulation time 887239425 ps
CPU time 2.32 seconds
Started Aug 18 05:35:07 PM PDT 24
Finished Aug 18 05:35:09 PM PDT 24
Peak memory 207740 kb
Host smart-8a81e706-2aed-4cf3-bcdc-8df4472b6755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11033
54667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1103354667
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_types.34706499
Short name T3460
Test name
Test status
Simulation time 162553619 ps
CPU time 0.88 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:34:58 PM PDT 24
Peak memory 207504 kb
Host smart-b2d6a9e8-d36b-4ac7-8aec-9d3a3ec9a402
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=34706499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_types.34706499
Directory /workspace/21.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3192932209
Short name T3512
Test name
Test status
Simulation time 183035625 ps
CPU time 1.4 seconds
Started Aug 18 05:35:09 PM PDT 24
Finished Aug 18 05:35:11 PM PDT 24
Peak memory 207644 kb
Host smart-a9b3945a-367b-46c4-99f9-5bc9afcd49e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31929
32209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3192932209
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.531247410
Short name T2313
Test name
Test status
Simulation time 210287863 ps
CPU time 0.99 seconds
Started Aug 18 05:35:04 PM PDT 24
Finished Aug 18 05:35:05 PM PDT 24
Peak memory 215880 kb
Host smart-acbaf331-16c6-44ab-ae03-3b87fe29a0ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=531247410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.531247410
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.4026434253
Short name T2354
Test name
Test status
Simulation time 138217820 ps
CPU time 0.81 seconds
Started Aug 18 05:34:54 PM PDT 24
Finished Aug 18 05:34:55 PM PDT 24
Peak memory 207472 kb
Host smart-84a521ff-070d-4b9d-bc11-51bf44d651ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40264
34253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.4026434253
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1016263186
Short name T2593
Test name
Test status
Simulation time 178350717 ps
CPU time 0.85 seconds
Started Aug 18 05:35:02 PM PDT 24
Finished Aug 18 05:35:03 PM PDT 24
Peak memory 207492 kb
Host smart-5a6fa9db-bbb2-4253-9c72-16335c175ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10162
63186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1016263186
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.2707077322
Short name T961
Test name
Test status
Simulation time 4866498643 ps
CPU time 47.43 seconds
Started Aug 18 05:34:56 PM PDT 24
Finished Aug 18 05:35:43 PM PDT 24
Peak memory 218404 kb
Host smart-817fb802-860b-4a9b-8564-9b0f7c11b394
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2707077322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.2707077322
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.944573606
Short name T1537
Test name
Test status
Simulation time 13088014679 ps
CPU time 86.34 seconds
Started Aug 18 05:35:18 PM PDT 24
Finished Aug 18 05:36:44 PM PDT 24
Peak memory 207696 kb
Host smart-04753456-0ddc-484b-9c21-779f23f407c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=944573606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.944573606
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.2698237485
Short name T1635
Test name
Test status
Simulation time 265787286 ps
CPU time 1.03 seconds
Started Aug 18 05:34:55 PM PDT 24
Finished Aug 18 05:34:56 PM PDT 24
Peak memory 207504 kb
Host smart-9973fc56-e7ed-4567-8d68-8ebe98260241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26982
37485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.2698237485
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.1112960368
Short name T3132
Test name
Test status
Simulation time 26124812225 ps
CPU time 31.73 seconds
Started Aug 18 05:34:58 PM PDT 24
Finished Aug 18 05:35:30 PM PDT 24
Peak memory 215912 kb
Host smart-0c997dcb-20fa-44ec-af14-d6ab51030e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11129
60368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.1112960368
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3842318541
Short name T1217
Test name
Test status
Simulation time 9195616708 ps
CPU time 14.64 seconds
Started Aug 18 05:35:07 PM PDT 24
Finished Aug 18 05:35:22 PM PDT 24
Peak memory 207860 kb
Host smart-7565a5e9-ce3e-46d5-8d2e-38a66047381a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38423
18541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3842318541
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1454402340
Short name T2325
Test name
Test status
Simulation time 5359154718 ps
CPU time 163.67 seconds
Started Aug 18 05:34:56 PM PDT 24
Finished Aug 18 05:37:40 PM PDT 24
Peak memory 223960 kb
Host smart-edf4cc80-8831-4e2a-87c8-e608b42d67a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1454402340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1454402340
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.3081863338
Short name T1739
Test name
Test status
Simulation time 4129229462 ps
CPU time 32.26 seconds
Started Aug 18 05:35:00 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 217596 kb
Host smart-4f937ae4-d7e2-4e01-8c68-183a17b04003
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3081863338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.3081863338
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.1465972848
Short name T596
Test name
Test status
Simulation time 292511991 ps
CPU time 1.14 seconds
Started Aug 18 05:35:05 PM PDT 24
Finished Aug 18 05:35:06 PM PDT 24
Peak memory 207512 kb
Host smart-3b97caee-5379-4149-9eeb-a0e50a4724ca
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1465972848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.1465972848
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1009144304
Short name T1048
Test name
Test status
Simulation time 185827546 ps
CPU time 0.97 seconds
Started Aug 18 05:34:58 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207516 kb
Host smart-b2bc97ae-bb65-4574-9393-3df96fb77e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10091
44304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1009144304
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_non_iso_usb_traffic.1323528455
Short name T532
Test name
Test status
Simulation time 3116559154 ps
CPU time 85.79 seconds
Started Aug 18 05:35:06 PM PDT 24
Finished Aug 18 05:36:32 PM PDT 24
Peak memory 217672 kb
Host smart-60ab331c-5dcd-4350-aebc-0b68e3f70816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13235
28455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_non_iso_usb_traffic.1323528455
Directory /workspace/21.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.3022593386
Short name T3249
Test name
Test status
Simulation time 1970690830 ps
CPU time 16.03 seconds
Started Aug 18 05:34:52 PM PDT 24
Finished Aug 18 05:35:09 PM PDT 24
Peak memory 215824 kb
Host smart-2c60692d-e720-47c2-a057-9cc9b05e93fe
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3022593386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.3022593386
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.3560411634
Short name T2947
Test name
Test status
Simulation time 148702510 ps
CPU time 0.83 seconds
Started Aug 18 05:35:14 PM PDT 24
Finished Aug 18 05:35:15 PM PDT 24
Peak memory 207504 kb
Host smart-e0142511-e7f3-433d-b6ce-e1dd218060da
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3560411634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.3560411634
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1019162139
Short name T1182
Test name
Test status
Simulation time 137639198 ps
CPU time 0.9 seconds
Started Aug 18 05:35:16 PM PDT 24
Finished Aug 18 05:35:17 PM PDT 24
Peak memory 207636 kb
Host smart-15b32ca2-b9f6-4ca8-9b9e-0ab31bdb0627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10191
62139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1019162139
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2627286399
Short name T154
Test name
Test status
Simulation time 208525996 ps
CPU time 1 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:34:58 PM PDT 24
Peak memory 207416 kb
Host smart-2cf0172c-2bec-4e8b-8d89-69594f7f3fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26272
86399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2627286399
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2134944186
Short name T930
Test name
Test status
Simulation time 194758347 ps
CPU time 0.98 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:34:58 PM PDT 24
Peak memory 207464 kb
Host smart-51b8a315-e169-4bca-969f-0b957146f396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21349
44186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2134944186
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.983524162
Short name T1486
Test name
Test status
Simulation time 205539955 ps
CPU time 0.95 seconds
Started Aug 18 05:35:12 PM PDT 24
Finished Aug 18 05:35:13 PM PDT 24
Peak memory 207220 kb
Host smart-132507a8-97ce-434f-9769-400738c5cd0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98352
4162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.983524162
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3770965982
Short name T2497
Test name
Test status
Simulation time 168332584 ps
CPU time 0.87 seconds
Started Aug 18 05:35:13 PM PDT 24
Finished Aug 18 05:35:14 PM PDT 24
Peak memory 207564 kb
Host smart-babbb668-df27-4d60-ae92-f95ade246d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37709
65982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3770965982
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3667829800
Short name T3435
Test name
Test status
Simulation time 162172701 ps
CPU time 0.9 seconds
Started Aug 18 05:34:58 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207584 kb
Host smart-dbe5c411-b13f-4202-9449-2b81a939cde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36678
29800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3667829800
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3003468821
Short name T2766
Test name
Test status
Simulation time 184259543 ps
CPU time 0.93 seconds
Started Aug 18 05:34:59 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 207560 kb
Host smart-6ad7784e-70e6-4613-a9e1-67d5bf5f9f11
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3003468821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3003468821
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.300257105
Short name T1556
Test name
Test status
Simulation time 142141090 ps
CPU time 0.84 seconds
Started Aug 18 05:35:02 PM PDT 24
Finished Aug 18 05:35:03 PM PDT 24
Peak memory 207376 kb
Host smart-25cda561-44d9-4746-92be-402a2fe85a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30025
7105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.300257105
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.710735478
Short name T2701
Test name
Test status
Simulation time 29806412 ps
CPU time 0.66 seconds
Started Aug 18 05:35:19 PM PDT 24
Finished Aug 18 05:35:20 PM PDT 24
Peak memory 207436 kb
Host smart-60e366a6-a3c0-421e-b97d-561c526775fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71073
5478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.710735478
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.4281814861
Short name T3408
Test name
Test status
Simulation time 16981317064 ps
CPU time 43.77 seconds
Started Aug 18 05:35:05 PM PDT 24
Finished Aug 18 05:35:49 PM PDT 24
Peak memory 215980 kb
Host smart-6f64d9a9-7390-4eaf-b3b2-a9f5c2000fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42818
14861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.4281814861
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2638673055
Short name T1619
Test name
Test status
Simulation time 206556622 ps
CPU time 0.93 seconds
Started Aug 18 05:35:03 PM PDT 24
Finished Aug 18 05:35:04 PM PDT 24
Peak memory 207596 kb
Host smart-90f29907-c1e2-43ba-978d-3f378c656f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26386
73055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2638673055
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.701345524
Short name T3069
Test name
Test status
Simulation time 182878048 ps
CPU time 0.98 seconds
Started Aug 18 05:35:17 PM PDT 24
Finished Aug 18 05:35:18 PM PDT 24
Peak memory 207492 kb
Host smart-5eb50aa9-a32d-447c-b6b9-10c4d6a4b6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70134
5524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.701345524
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.712646953
Short name T3448
Test name
Test status
Simulation time 182216176 ps
CPU time 0.9 seconds
Started Aug 18 05:35:17 PM PDT 24
Finished Aug 18 05:35:18 PM PDT 24
Peak memory 207228 kb
Host smart-5f312834-0650-4a4d-9772-04d542555465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71264
6953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.712646953
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3136911282
Short name T1540
Test name
Test status
Simulation time 183765423 ps
CPU time 1 seconds
Started Aug 18 05:34:57 PM PDT 24
Finished Aug 18 05:34:58 PM PDT 24
Peak memory 207512 kb
Host smart-126403bc-7572-497c-a7be-af94342801c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31369
11282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3136911282
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3636613958
Short name T2893
Test name
Test status
Simulation time 145797992 ps
CPU time 0.83 seconds
Started Aug 18 05:35:21 PM PDT 24
Finished Aug 18 05:35:22 PM PDT 24
Peak memory 207396 kb
Host smart-222de12f-16a8-4869-b622-2a0e0c459a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36366
13958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3636613958
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_rx_full.1115527627
Short name T669
Test name
Test status
Simulation time 402898949 ps
CPU time 1.35 seconds
Started Aug 18 05:34:54 PM PDT 24
Finished Aug 18 05:34:55 PM PDT 24
Peak memory 207508 kb
Host smart-957b03ed-a95d-487e-8e32-cbed053779ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11155
27627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_full.1115527627
Directory /workspace/21.usbdev_rx_full/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.761292620
Short name T3624
Test name
Test status
Simulation time 198825071 ps
CPU time 0.87 seconds
Started Aug 18 05:34:58 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 207468 kb
Host smart-1418501d-8b31-4c07-b5a4-fc2cf4432b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76129
2620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.761292620
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1167729011
Short name T1346
Test name
Test status
Simulation time 157996862 ps
CPU time 0.83 seconds
Started Aug 18 05:35:00 PM PDT 24
Finished Aug 18 05:35:01 PM PDT 24
Peak memory 207228 kb
Host smart-f3cdd66c-e10a-4cc9-b581-0a7ef1478856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11677
29011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1167729011
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.963785127
Short name T725
Test name
Test status
Simulation time 220290886 ps
CPU time 1.03 seconds
Started Aug 18 05:35:12 PM PDT 24
Finished Aug 18 05:35:13 PM PDT 24
Peak memory 207520 kb
Host smart-a001b5a0-5d03-4ec2-9b64-295005c76e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96378
5127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.963785127
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.566254837
Short name T1110
Test name
Test status
Simulation time 3331431991 ps
CPU time 34.54 seconds
Started Aug 18 05:35:30 PM PDT 24
Finished Aug 18 05:36:05 PM PDT 24
Peak memory 217540 kb
Host smart-4da6b783-6ede-4d4b-8968-a376f3089404
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=566254837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.566254837
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.3254930445
Short name T632
Test name
Test status
Simulation time 189849074 ps
CPU time 0.89 seconds
Started Aug 18 05:35:01 PM PDT 24
Finished Aug 18 05:35:03 PM PDT 24
Peak memory 207504 kb
Host smart-2482feb7-f63e-4293-ad9f-778bba1ad0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32549
30445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.3254930445
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.1421904150
Short name T2215
Test name
Test status
Simulation time 171596284 ps
CPU time 0.94 seconds
Started Aug 18 05:35:10 PM PDT 24
Finished Aug 18 05:35:11 PM PDT 24
Peak memory 207708 kb
Host smart-1cf4bc0b-7b4e-42d6-86b6-265d0f7973f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14219
04150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1421904150
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.983820168
Short name T846
Test name
Test status
Simulation time 1028058519 ps
CPU time 2.58 seconds
Started Aug 18 05:35:19 PM PDT 24
Finished Aug 18 05:35:21 PM PDT 24
Peak memory 207464 kb
Host smart-38ef785d-6945-49e8-bb69-28604f45a85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98382
0168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.983820168
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.3909062717
Short name T1767
Test name
Test status
Simulation time 4131356847 ps
CPU time 33.14 seconds
Started Aug 18 05:34:58 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 217860 kb
Host smart-21897a1b-b917-45af-9fe2-d5ef28d205a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39090
62717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.3909062717
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.2048180354
Short name T2188
Test name
Test status
Simulation time 6730678818 ps
CPU time 47.61 seconds
Started Aug 18 05:35:05 PM PDT 24
Finished Aug 18 05:35:52 PM PDT 24
Peak memory 207792 kb
Host smart-03b9e2a1-3c96-4f94-9962-5e6020109d68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048180354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.2048180354
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_tx_rx_disruption.2780458000
Short name T2587
Test name
Test status
Simulation time 588851586 ps
CPU time 1.83 seconds
Started Aug 18 05:35:00 PM PDT 24
Finished Aug 18 05:35:02 PM PDT 24
Peak memory 207608 kb
Host smart-8f4f81aa-6599-43e9-8b26-7979cc16c9dd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780458000 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.usbdev_tx_rx_disruption.2780458000
Directory /workspace/21.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/210.usbdev_tx_rx_disruption.2338155400
Short name T3133
Test name
Test status
Simulation time 530837501 ps
CPU time 1.5 seconds
Started Aug 18 05:39:28 PM PDT 24
Finished Aug 18 05:39:30 PM PDT 24
Peak memory 207544 kb
Host smart-f243c6a4-6c6b-48bf-814a-ac14e447a83f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338155400 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 210.usbdev_tx_rx_disruption.2338155400
Directory /workspace/210.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/211.usbdev_tx_rx_disruption.1785501496
Short name T2184
Test name
Test status
Simulation time 595227136 ps
CPU time 1.53 seconds
Started Aug 18 05:39:20 PM PDT 24
Finished Aug 18 05:39:22 PM PDT 24
Peak memory 207480 kb
Host smart-e483a359-a997-41ba-b253-31079199a859
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785501496 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 211.usbdev_tx_rx_disruption.1785501496
Directory /workspace/211.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/212.usbdev_tx_rx_disruption.2004552160
Short name T2831
Test name
Test status
Simulation time 570710980 ps
CPU time 1.66 seconds
Started Aug 18 05:39:22 PM PDT 24
Finished Aug 18 05:39:24 PM PDT 24
Peak memory 207568 kb
Host smart-2706113a-ecf2-449d-b29d-134cd84ba3bf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004552160 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 212.usbdev_tx_rx_disruption.2004552160
Directory /workspace/212.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/213.usbdev_tx_rx_disruption.1998985599
Short name T2352
Test name
Test status
Simulation time 569098240 ps
CPU time 1.57 seconds
Started Aug 18 05:39:21 PM PDT 24
Finished Aug 18 05:39:22 PM PDT 24
Peak memory 207444 kb
Host smart-6df36c6c-972e-4ccc-b1bf-27964259de58
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998985599 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.usbdev_tx_rx_disruption.1998985599
Directory /workspace/213.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/214.usbdev_tx_rx_disruption.2413664378
Short name T3350
Test name
Test status
Simulation time 609425286 ps
CPU time 1.7 seconds
Started Aug 18 05:39:36 PM PDT 24
Finished Aug 18 05:39:38 PM PDT 24
Peak memory 207584 kb
Host smart-77935ebd-5bba-4360-96d9-c56d1295c636
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413664378 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 214.usbdev_tx_rx_disruption.2413664378
Directory /workspace/214.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/215.usbdev_tx_rx_disruption.1625504994
Short name T196
Test name
Test status
Simulation time 475585570 ps
CPU time 1.45 seconds
Started Aug 18 05:39:38 PM PDT 24
Finished Aug 18 05:39:39 PM PDT 24
Peak memory 207580 kb
Host smart-9298d3ce-6210-4e10-9c91-3fc78e78a228
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625504994 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 215.usbdev_tx_rx_disruption.1625504994
Directory /workspace/215.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/216.usbdev_tx_rx_disruption.705368946
Short name T1641
Test name
Test status
Simulation time 652566970 ps
CPU time 1.64 seconds
Started Aug 18 05:39:46 PM PDT 24
Finished Aug 18 05:39:48 PM PDT 24
Peak memory 207572 kb
Host smart-6380992d-8b2b-4445-a4b2-5c25355bce01
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705368946 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 216.usbdev_tx_rx_disruption.705368946
Directory /workspace/216.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/217.usbdev_tx_rx_disruption.4003273385
Short name T267
Test name
Test status
Simulation time 610710930 ps
CPU time 1.62 seconds
Started Aug 18 05:39:41 PM PDT 24
Finished Aug 18 05:39:43 PM PDT 24
Peak memory 207544 kb
Host smart-8e2e0af1-eb02-41eb-8c8f-39410d43f995
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003273385 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.usbdev_tx_rx_disruption.4003273385
Directory /workspace/217.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/218.usbdev_tx_rx_disruption.2221371030
Short name T3332
Test name
Test status
Simulation time 517172957 ps
CPU time 1.69 seconds
Started Aug 18 05:39:39 PM PDT 24
Finished Aug 18 05:39:41 PM PDT 24
Peak memory 207480 kb
Host smart-9c10038b-f90e-4c10-8619-5637656835ab
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221371030 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 218.usbdev_tx_rx_disruption.2221371030
Directory /workspace/218.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/219.usbdev_tx_rx_disruption.1585185813
Short name T724
Test name
Test status
Simulation time 471983030 ps
CPU time 1.51 seconds
Started Aug 18 05:39:42 PM PDT 24
Finished Aug 18 05:39:43 PM PDT 24
Peak memory 207544 kb
Host smart-71d6475d-017e-45a1-a359-881899a01248
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585185813 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.usbdev_tx_rx_disruption.1585185813
Directory /workspace/219.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.1175804980
Short name T1236
Test name
Test status
Simulation time 34843995 ps
CPU time 0.63 seconds
Started Aug 18 05:35:27 PM PDT 24
Finished Aug 18 05:35:28 PM PDT 24
Peak memory 207464 kb
Host smart-e6e1b082-de4a-43cf-97df-347fb10d4384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1175804980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.1175804980
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.1128951565
Short name T1231
Test name
Test status
Simulation time 11226866287 ps
CPU time 15.51 seconds
Started Aug 18 05:35:12 PM PDT 24
Finished Aug 18 05:35:28 PM PDT 24
Peak memory 207544 kb
Host smart-473d2283-8240-4ab7-bafe-4e7748ce9115
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128951565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.1128951565
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3444612289
Short name T1315
Test name
Test status
Simulation time 19524259537 ps
CPU time 22.56 seconds
Started Aug 18 05:35:14 PM PDT 24
Finished Aug 18 05:35:36 PM PDT 24
Peak memory 207940 kb
Host smart-b0ada1b1-8512-4e95-beeb-606b8ca1aaab
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444612289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3444612289
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.837561490
Short name T1723
Test name
Test status
Simulation time 30224458201 ps
CPU time 35.69 seconds
Started Aug 18 05:35:01 PM PDT 24
Finished Aug 18 05:35:37 PM PDT 24
Peak memory 207808 kb
Host smart-444bf11f-f25e-4168-90c6-7b0d96144e4e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837561490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_ao
n_wake_resume.837561490
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.4009173312
Short name T3267
Test name
Test status
Simulation time 185732024 ps
CPU time 0.86 seconds
Started Aug 18 05:35:15 PM PDT 24
Finished Aug 18 05:35:16 PM PDT 24
Peak memory 207636 kb
Host smart-9bb87284-a241-4a10-8f52-187e2b3b1a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40091
73312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.4009173312
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2039440239
Short name T3509
Test name
Test status
Simulation time 148797256 ps
CPU time 0.85 seconds
Started Aug 18 05:35:00 PM PDT 24
Finished Aug 18 05:35:01 PM PDT 24
Peak memory 207676 kb
Host smart-d35041c5-70bc-4658-bfd0-8cc9bb101b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20394
40239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2039440239
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.2689966123
Short name T2873
Test name
Test status
Simulation time 419069812 ps
CPU time 1.5 seconds
Started Aug 18 05:35:08 PM PDT 24
Finished Aug 18 05:35:09 PM PDT 24
Peak memory 207604 kb
Host smart-80291d88-5d30-45cf-b457-0171c679be0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26899
66123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.2689966123
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3908197963
Short name T2723
Test name
Test status
Simulation time 1371090809 ps
CPU time 3.35 seconds
Started Aug 18 05:34:56 PM PDT 24
Finished Aug 18 05:35:00 PM PDT 24
Peak memory 207696 kb
Host smart-783e3d2c-b79d-49fe-a9b2-8fd8cf62e32c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3908197963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3908197963
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.3546399659
Short name T523
Test name
Test status
Simulation time 36376458049 ps
CPU time 64.43 seconds
Started Aug 18 05:35:08 PM PDT 24
Finished Aug 18 05:36:12 PM PDT 24
Peak memory 207740 kb
Host smart-82a85188-d7de-412b-9cc3-ab24ff2bf5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35463
99659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.3546399659
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.3822968778
Short name T1528
Test name
Test status
Simulation time 3600804409 ps
CPU time 23.81 seconds
Started Aug 18 05:35:22 PM PDT 24
Finished Aug 18 05:35:46 PM PDT 24
Peak memory 207752 kb
Host smart-3dcf61fc-643d-405a-a0b7-cdb3f5aee263
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822968778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.3822968778
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.3796592896
Short name T2028
Test name
Test status
Simulation time 556246916 ps
CPU time 1.66 seconds
Started Aug 18 05:35:10 PM PDT 24
Finished Aug 18 05:35:12 PM PDT 24
Peak memory 207548 kb
Host smart-e28e6b55-e924-4ebf-a232-0505af0f804c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37965
92896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.3796592896
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.315480813
Short name T2550
Test name
Test status
Simulation time 152377086 ps
CPU time 0.83 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:35:30 PM PDT 24
Peak memory 207548 kb
Host smart-993720e9-7e94-45ff-a00f-016b81f37ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31548
0813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.315480813
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.3257466944
Short name T2283
Test name
Test status
Simulation time 65195793 ps
CPU time 0.76 seconds
Started Aug 18 05:36:08 PM PDT 24
Finished Aug 18 05:36:10 PM PDT 24
Peak memory 206464 kb
Host smart-de557eeb-f088-471a-9782-ee4803c5de78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32574
66944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3257466944
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3854004449
Short name T3055
Test name
Test status
Simulation time 840280910 ps
CPU time 2.23 seconds
Started Aug 18 05:35:18 PM PDT 24
Finished Aug 18 05:35:20 PM PDT 24
Peak memory 207680 kb
Host smart-1d7f2830-97bf-4f9d-b77f-35918acecf0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38540
04449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3854004449
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_types.2638003868
Short name T484
Test name
Test status
Simulation time 526674058 ps
CPU time 1.46 seconds
Started Aug 18 05:35:07 PM PDT 24
Finished Aug 18 05:35:09 PM PDT 24
Peak memory 207536 kb
Host smart-4f8dd270-75b1-469a-9228-0cd2f3a160ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2638003868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_types.2638003868
Directory /workspace/22.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.2641194577
Short name T230
Test name
Test status
Simulation time 207598567 ps
CPU time 1.63 seconds
Started Aug 18 05:35:02 PM PDT 24
Finished Aug 18 05:35:04 PM PDT 24
Peak memory 207620 kb
Host smart-54a297e2-e956-4d5e-bb43-376026014ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26411
94577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.2641194577
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1972457279
Short name T1410
Test name
Test status
Simulation time 208814798 ps
CPU time 1.16 seconds
Started Aug 18 05:35:11 PM PDT 24
Finished Aug 18 05:35:12 PM PDT 24
Peak memory 215808 kb
Host smart-701be40f-4b87-49c8-aa79-79bff1f764f8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1972457279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1972457279
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2827099680
Short name T3184
Test name
Test status
Simulation time 148494113 ps
CPU time 0.83 seconds
Started Aug 18 05:35:05 PM PDT 24
Finished Aug 18 05:35:06 PM PDT 24
Peak memory 207476 kb
Host smart-45f9905b-b530-4589-895a-e1f9a6bc4160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28270
99680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2827099680
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1049464176
Short name T2713
Test name
Test status
Simulation time 191059834 ps
CPU time 0.92 seconds
Started Aug 18 05:35:26 PM PDT 24
Finished Aug 18 05:35:27 PM PDT 24
Peak memory 207484 kb
Host smart-fba75052-dd74-4b46-b06b-7f125248b84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10494
64176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1049464176
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.2795359980
Short name T1146
Test name
Test status
Simulation time 2851971968 ps
CPU time 21.98 seconds
Started Aug 18 05:35:20 PM PDT 24
Finished Aug 18 05:35:42 PM PDT 24
Peak memory 224188 kb
Host smart-f9e73754-7ba3-4eb3-9798-7c6935938f75
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2795359980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.2795359980
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.1122884623
Short name T88
Test name
Test status
Simulation time 13034656559 ps
CPU time 89.61 seconds
Started Aug 18 05:35:25 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207792 kb
Host smart-53efbcb5-0730-4164-a6d4-212783d3c997
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1122884623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.1122884623
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2281318167
Short name T705
Test name
Test status
Simulation time 181247962 ps
CPU time 0.93 seconds
Started Aug 18 05:35:11 PM PDT 24
Finished Aug 18 05:35:12 PM PDT 24
Peak memory 207580 kb
Host smart-f81981e0-c97e-4c23-aef0-852606f9c35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22813
18167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2281318167
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.1082350096
Short name T3087
Test name
Test status
Simulation time 26421339788 ps
CPU time 40.91 seconds
Started Aug 18 05:35:20 PM PDT 24
Finished Aug 18 05:36:01 PM PDT 24
Peak memory 207816 kb
Host smart-fc9ec310-9d34-468b-92d1-7ccf2c781df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10823
50096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1082350096
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2882839096
Short name T103
Test name
Test status
Simulation time 3996490006 ps
CPU time 5.72 seconds
Started Aug 18 05:35:20 PM PDT 24
Finished Aug 18 05:35:26 PM PDT 24
Peak memory 207932 kb
Host smart-eea3b13b-bb61-4f0b-8de4-329ad34ffe50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28828
39096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2882839096
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.1677405701
Short name T1645
Test name
Test status
Simulation time 3017335444 ps
CPU time 32.21 seconds
Started Aug 18 05:35:37 PM PDT 24
Finished Aug 18 05:36:09 PM PDT 24
Peak memory 218348 kb
Host smart-4d45260a-6f5d-43f2-a20f-319494c4f1c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1677405701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.1677405701
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.3406693038
Short name T2562
Test name
Test status
Simulation time 2049063201 ps
CPU time 20.28 seconds
Started Aug 18 05:35:19 PM PDT 24
Finished Aug 18 05:35:39 PM PDT 24
Peak memory 215856 kb
Host smart-0f8bafed-d458-4ad2-a77e-ee9cb079468e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3406693038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.3406693038
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3699028960
Short name T3081
Test name
Test status
Simulation time 256024150 ps
CPU time 1.01 seconds
Started Aug 18 05:35:24 PM PDT 24
Finished Aug 18 05:35:25 PM PDT 24
Peak memory 207452 kb
Host smart-57ce7e83-9880-4e36-832b-8dd531e91aa7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3699028960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3699028960
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3215528350
Short name T2753
Test name
Test status
Simulation time 191017447 ps
CPU time 0.99 seconds
Started Aug 18 05:35:24 PM PDT 24
Finished Aug 18 05:35:25 PM PDT 24
Peak memory 207500 kb
Host smart-03f75070-db50-4fde-967d-ea7625efe160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32155
28350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3215528350
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_non_iso_usb_traffic.1823378037
Short name T1396
Test name
Test status
Simulation time 2838769082 ps
CPU time 84.9 seconds
Started Aug 18 05:35:14 PM PDT 24
Finished Aug 18 05:36:39 PM PDT 24
Peak memory 217696 kb
Host smart-b43697b4-4f5e-432b-9f14-13872117f301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18233
78037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_non_iso_usb_traffic.1823378037
Directory /workspace/22.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.3230455806
Short name T2897
Test name
Test status
Simulation time 3461305512 ps
CPU time 35.22 seconds
Started Aug 18 05:35:03 PM PDT 24
Finished Aug 18 05:35:38 PM PDT 24
Peak memory 217672 kb
Host smart-261a861e-c009-449b-b149-453ee4054f37
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3230455806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.3230455806
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.134361005
Short name T1404
Test name
Test status
Simulation time 163741979 ps
CPU time 0.9 seconds
Started Aug 18 05:35:07 PM PDT 24
Finished Aug 18 05:35:08 PM PDT 24
Peak memory 207460 kb
Host smart-5fdf7ced-1517-44be-8f4d-d4cbf39e25a2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=134361005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.134361005
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3445601612
Short name T1033
Test name
Test status
Simulation time 146037487 ps
CPU time 0.88 seconds
Started Aug 18 05:35:13 PM PDT 24
Finished Aug 18 05:35:14 PM PDT 24
Peak memory 207440 kb
Host smart-f7ba6c75-1f92-4664-83e6-f5152585c4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34456
01612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3445601612
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1882371943
Short name T170
Test name
Test status
Simulation time 241150543 ps
CPU time 0.98 seconds
Started Aug 18 05:35:25 PM PDT 24
Finished Aug 18 05:35:26 PM PDT 24
Peak memory 207480 kb
Host smart-08c21754-2adc-403b-837f-37d0fcf21916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18823
71943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1882371943
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.204410871
Short name T1702
Test name
Test status
Simulation time 181682561 ps
CPU time 0.94 seconds
Started Aug 18 05:35:13 PM PDT 24
Finished Aug 18 05:35:14 PM PDT 24
Peak memory 207496 kb
Host smart-97d4ca16-4743-4379-8c08-0a7042cea39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20441
0871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.204410871
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.4040409155
Short name T3153
Test name
Test status
Simulation time 181640822 ps
CPU time 0.96 seconds
Started Aug 18 05:35:15 PM PDT 24
Finished Aug 18 05:35:16 PM PDT 24
Peak memory 207396 kb
Host smart-01f7ffa2-8fb0-4b68-93ae-3f2110faf9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40404
09155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.4040409155
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.444985319
Short name T893
Test name
Test status
Simulation time 186581352 ps
CPU time 0.91 seconds
Started Aug 18 05:35:08 PM PDT 24
Finished Aug 18 05:35:09 PM PDT 24
Peak memory 207536 kb
Host smart-f153fd58-7740-4479-bb10-3ef26c8f8900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44498
5319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.444985319
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3247227195
Short name T3254
Test name
Test status
Simulation time 164879990 ps
CPU time 0.81 seconds
Started Aug 18 05:35:08 PM PDT 24
Finished Aug 18 05:35:09 PM PDT 24
Peak memory 207564 kb
Host smart-b485621e-0b3f-49ec-aa42-94cb3b4c4c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32472
27195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3247227195
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.2837061582
Short name T3190
Test name
Test status
Simulation time 240757805 ps
CPU time 1.08 seconds
Started Aug 18 05:35:12 PM PDT 24
Finished Aug 18 05:35:13 PM PDT 24
Peak memory 207548 kb
Host smart-f02ac62b-580c-4400-83b3-7211ed02de9a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2837061582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.2837061582
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.117302203
Short name T2254
Test name
Test status
Simulation time 193084319 ps
CPU time 0.87 seconds
Started Aug 18 05:35:22 PM PDT 24
Finished Aug 18 05:35:23 PM PDT 24
Peak memory 207452 kb
Host smart-a0b51c34-9d1e-4c27-be10-302c5e4b4ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11730
2203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.117302203
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2827557655
Short name T2637
Test name
Test status
Simulation time 29526587 ps
CPU time 0.67 seconds
Started Aug 18 05:35:30 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 207676 kb
Host smart-55dc01d2-1c75-4cfa-b89e-7df71362f806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28275
57655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2827557655
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.271046266
Short name T324
Test name
Test status
Simulation time 20675448773 ps
CPU time 52.94 seconds
Started Aug 18 05:35:12 PM PDT 24
Finished Aug 18 05:36:05 PM PDT 24
Peak memory 216012 kb
Host smart-64c5d9ad-db7e-4a67-910a-7f427459eab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27104
6266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.271046266
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1737047217
Short name T2698
Test name
Test status
Simulation time 160835941 ps
CPU time 0.85 seconds
Started Aug 18 05:35:20 PM PDT 24
Finished Aug 18 05:35:21 PM PDT 24
Peak memory 207552 kb
Host smart-ad589b29-5bbf-4f72-a083-db48b794fa47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17370
47217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1737047217
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1457853109
Short name T2110
Test name
Test status
Simulation time 237160584 ps
CPU time 0.95 seconds
Started Aug 18 05:35:33 PM PDT 24
Finished Aug 18 05:35:34 PM PDT 24
Peak memory 207456 kb
Host smart-fb1e84ff-79c3-4461-a473-a39803c57b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14578
53109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1457853109
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2230246547
Short name T801
Test name
Test status
Simulation time 212323933 ps
CPU time 0.99 seconds
Started Aug 18 05:35:07 PM PDT 24
Finished Aug 18 05:35:08 PM PDT 24
Peak memory 207484 kb
Host smart-1c54ada7-ef25-4012-93bd-e4c9319f8aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22302
46547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2230246547
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.3284397570
Short name T706
Test name
Test status
Simulation time 194403729 ps
CPU time 0.97 seconds
Started Aug 18 05:35:25 PM PDT 24
Finished Aug 18 05:35:26 PM PDT 24
Peak memory 207496 kb
Host smart-23200fe0-1431-4fa1-a761-e35d3aeb988b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32843
97570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.3284397570
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.2666278344
Short name T892
Test name
Test status
Simulation time 179179669 ps
CPU time 0.95 seconds
Started Aug 18 05:35:08 PM PDT 24
Finished Aug 18 05:35:09 PM PDT 24
Peak memory 207504 kb
Host smart-88283e8b-2cd0-47e4-828b-79d40ec7ac8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26662
78344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.2666278344
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_rx_full.441948144
Short name T3299
Test name
Test status
Simulation time 385380588 ps
CPU time 1.38 seconds
Started Aug 18 05:35:10 PM PDT 24
Finished Aug 18 05:35:12 PM PDT 24
Peak memory 207456 kb
Host smart-b0c3e550-3f71-4582-82dc-39ce786394f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44194
8144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_full.441948144
Directory /workspace/22.usbdev_rx_full/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2738066521
Short name T687
Test name
Test status
Simulation time 147316082 ps
CPU time 0.86 seconds
Started Aug 18 05:35:06 PM PDT 24
Finished Aug 18 05:35:07 PM PDT 24
Peak memory 207516 kb
Host smart-0a67b3ba-8874-4f26-bdd7-d026adc4d915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27380
66521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2738066521
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3633041020
Short name T2999
Test name
Test status
Simulation time 158958319 ps
CPU time 0.84 seconds
Started Aug 18 05:36:26 PM PDT 24
Finished Aug 18 05:36:27 PM PDT 24
Peak memory 207280 kb
Host smart-d4b272fb-991c-41e3-91de-bc2afa0c9527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36330
41020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3633041020
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1350282010
Short name T2391
Test name
Test status
Simulation time 215422935 ps
CPU time 1 seconds
Started Aug 18 05:35:14 PM PDT 24
Finished Aug 18 05:35:15 PM PDT 24
Peak memory 207484 kb
Host smart-abe05bc3-79a8-480c-a4fb-c5e8a24f87fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13502
82010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1350282010
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.4021164983
Short name T1720
Test name
Test status
Simulation time 2657198244 ps
CPU time 27.48 seconds
Started Aug 18 05:35:13 PM PDT 24
Finished Aug 18 05:35:40 PM PDT 24
Peak memory 217932 kb
Host smart-7700a526-41e3-4d85-807c-fd67dbf3a4ac
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4021164983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.4021164983
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3187223059
Short name T3015
Test name
Test status
Simulation time 221299220 ps
CPU time 0.95 seconds
Started Aug 18 05:35:07 PM PDT 24
Finished Aug 18 05:35:08 PM PDT 24
Peak memory 207520 kb
Host smart-3c642b29-17b1-4cf3-8ad6-4c4c4a0e9ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31872
23059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3187223059
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.4154631662
Short name T803
Test name
Test status
Simulation time 235763261 ps
CPU time 0.97 seconds
Started Aug 18 05:35:23 PM PDT 24
Finished Aug 18 05:35:24 PM PDT 24
Peak memory 207584 kb
Host smart-c450906c-f7ee-40f0-b7a9-af5b217333ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41546
31662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.4154631662
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.3704678200
Short name T1524
Test name
Test status
Simulation time 874147397 ps
CPU time 2.2 seconds
Started Aug 18 05:35:28 PM PDT 24
Finished Aug 18 05:35:30 PM PDT 24
Peak memory 207756 kb
Host smart-7c312f54-dc23-42a9-8bb7-1d0d737421c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37046
78200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.3704678200
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.319044836
Short name T2243
Test name
Test status
Simulation time 2107524600 ps
CPU time 21.02 seconds
Started Aug 18 05:35:14 PM PDT 24
Finished Aug 18 05:35:35 PM PDT 24
Peak memory 217360 kb
Host smart-585bac4b-4376-467e-bc61-922b93423bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31904
4836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.319044836
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.929520863
Short name T3303
Test name
Test status
Simulation time 2102608690 ps
CPU time 17.62 seconds
Started Aug 18 05:35:15 PM PDT 24
Finished Aug 18 05:35:33 PM PDT 24
Peak memory 207704 kb
Host smart-69fe734a-7126-44a2-b6b0-8ccb1780ab24
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929520863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_host
_handshake.929520863
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_tx_rx_disruption.1242751301
Short name T2693
Test name
Test status
Simulation time 499202986 ps
CPU time 1.58 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 207584 kb
Host smart-3c5a2dd2-ec4e-40bd-8608-f7d5caecd3ee
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242751301 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.usbdev_tx_rx_disruption.1242751301
Directory /workspace/22.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/220.usbdev_tx_rx_disruption.2593900475
Short name T19
Test name
Test status
Simulation time 412836491 ps
CPU time 1.39 seconds
Started Aug 18 05:39:39 PM PDT 24
Finished Aug 18 05:39:41 PM PDT 24
Peak memory 207444 kb
Host smart-eb94527f-5d8b-4dab-8442-d37d764c83bd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593900475 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 220.usbdev_tx_rx_disruption.2593900475
Directory /workspace/220.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/221.usbdev_tx_rx_disruption.77269638
Short name T916
Test name
Test status
Simulation time 496967676 ps
CPU time 1.51 seconds
Started Aug 18 05:39:51 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207592 kb
Host smart-e22655ca-9371-47a8-93b1-7d229df9ee78
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77269638 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 221.usbdev_tx_rx_disruption.77269638
Directory /workspace/221.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/222.usbdev_tx_rx_disruption.1112343858
Short name T1535
Test name
Test status
Simulation time 519611645 ps
CPU time 1.4 seconds
Started Aug 18 05:39:45 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207572 kb
Host smart-9981121b-fe28-4b76-b97b-4928788a7cff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112343858 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 222.usbdev_tx_rx_disruption.1112343858
Directory /workspace/222.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/223.usbdev_tx_rx_disruption.1541854010
Short name T3334
Test name
Test status
Simulation time 660923904 ps
CPU time 1.68 seconds
Started Aug 18 05:39:34 PM PDT 24
Finished Aug 18 05:39:36 PM PDT 24
Peak memory 207492 kb
Host smart-00134e5f-cf59-4c90-acf5-b99a72fbb93a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541854010 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.usbdev_tx_rx_disruption.1541854010
Directory /workspace/223.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/224.usbdev_tx_rx_disruption.933919163
Short name T2187
Test name
Test status
Simulation time 578498781 ps
CPU time 1.54 seconds
Started Aug 18 05:39:45 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207588 kb
Host smart-c90f5e4e-ba97-428c-8bb4-ed43a3d8dfe9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933919163 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 224.usbdev_tx_rx_disruption.933919163
Directory /workspace/224.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/225.usbdev_tx_rx_disruption.2362206146
Short name T3445
Test name
Test status
Simulation time 484880149 ps
CPU time 1.46 seconds
Started Aug 18 05:39:31 PM PDT 24
Finished Aug 18 05:39:32 PM PDT 24
Peak memory 207524 kb
Host smart-f17b9419-1815-416c-baf2-6866dadf426c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362206146 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.usbdev_tx_rx_disruption.2362206146
Directory /workspace/225.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/226.usbdev_tx_rx_disruption.1986110912
Short name T575
Test name
Test status
Simulation time 592672426 ps
CPU time 1.65 seconds
Started Aug 18 05:39:50 PM PDT 24
Finished Aug 18 05:39:52 PM PDT 24
Peak memory 207524 kb
Host smart-cd902e25-6553-4e51-9798-4a4deab6865c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986110912 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 226.usbdev_tx_rx_disruption.1986110912
Directory /workspace/226.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/227.usbdev_tx_rx_disruption.1668096696
Short name T1251
Test name
Test status
Simulation time 651201141 ps
CPU time 1.65 seconds
Started Aug 18 05:39:58 PM PDT 24
Finished Aug 18 05:40:00 PM PDT 24
Peak memory 207588 kb
Host smart-51d5fd8b-098f-4b80-9e26-01e24e0ed365
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668096696 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 227.usbdev_tx_rx_disruption.1668096696
Directory /workspace/227.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/228.usbdev_tx_rx_disruption.533010063
Short name T2685
Test name
Test status
Simulation time 608104629 ps
CPU time 1.73 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207456 kb
Host smart-84b5f0b0-c320-41b8-9904-1c9145391412
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533010063 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 228.usbdev_tx_rx_disruption.533010063
Directory /workspace/228.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/229.usbdev_tx_rx_disruption.3551511402
Short name T1732
Test name
Test status
Simulation time 555399351 ps
CPU time 1.65 seconds
Started Aug 18 05:39:46 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207376 kb
Host smart-06836840-a2fe-45ba-80ce-30e312569175
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551511402 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.usbdev_tx_rx_disruption.3551511402
Directory /workspace/229.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.2458285102
Short name T3011
Test name
Test status
Simulation time 44215620 ps
CPU time 0.69 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 207456 kb
Host smart-ac50aefd-82ea-4c94-b75e-d5cc68e62418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2458285102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.2458285102
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3150928694
Short name T1682
Test name
Test status
Simulation time 5099790259 ps
CPU time 7.89 seconds
Started Aug 18 05:35:17 PM PDT 24
Finished Aug 18 05:35:25 PM PDT 24
Peak memory 216008 kb
Host smart-b2f55949-6b67-489b-bef4-f5b4c3657f20
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150928694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.3150928694
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.4112384092
Short name T3302
Test name
Test status
Simulation time 18431894821 ps
CPU time 21.68 seconds
Started Aug 18 05:35:23 PM PDT 24
Finished Aug 18 05:35:45 PM PDT 24
Peak memory 207832 kb
Host smart-e7ee093e-1740-4f81-af52-ed3471d071df
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112384092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.4112384092
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.1993320601
Short name T2928
Test name
Test status
Simulation time 28809803852 ps
CPU time 36.04 seconds
Started Aug 18 05:35:34 PM PDT 24
Finished Aug 18 05:36:10 PM PDT 24
Peak memory 207688 kb
Host smart-c217e137-b092-4fd0-8c16-4ad80202f92b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993320601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.1993320601
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.258714259
Short name T1793
Test name
Test status
Simulation time 161822858 ps
CPU time 0.9 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:35:30 PM PDT 24
Peak memory 207496 kb
Host smart-ce63cc9c-1494-4a82-b528-85c1e8461679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25871
4259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.258714259
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.739641094
Short name T1893
Test name
Test status
Simulation time 200563651 ps
CPU time 0.96 seconds
Started Aug 18 05:35:34 PM PDT 24
Finished Aug 18 05:35:35 PM PDT 24
Peak memory 207460 kb
Host smart-cc7b5b7b-5b4c-4dac-b490-2df9c7d01c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73964
1094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.739641094
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.4213249197
Short name T1108
Test name
Test status
Simulation time 449029059 ps
CPU time 1.57 seconds
Started Aug 18 05:35:24 PM PDT 24
Finished Aug 18 05:35:26 PM PDT 24
Peak memory 207556 kb
Host smart-40e3388d-3223-4c2d-80ef-7af12576b091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42132
49197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.4213249197
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1443989607
Short name T1452
Test name
Test status
Simulation time 911944936 ps
CPU time 2.46 seconds
Started Aug 18 05:35:13 PM PDT 24
Finished Aug 18 05:35:16 PM PDT 24
Peak memory 207732 kb
Host smart-f5e3a6d4-eaeb-48be-ab43-6895ff417bab
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1443989607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1443989607
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.4164670402
Short name T2151
Test name
Test status
Simulation time 13284165602 ps
CPU time 21.47 seconds
Started Aug 18 05:35:23 PM PDT 24
Finished Aug 18 05:35:44 PM PDT 24
Peak memory 207716 kb
Host smart-eb491ebf-09cc-47b0-9313-ee25f3b42d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41646
70402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.4164670402
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.2593263168
Short name T620
Test name
Test status
Simulation time 851237371 ps
CPU time 5.91 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:35:35 PM PDT 24
Peak memory 207680 kb
Host smart-c4eb84b3-2551-494f-968a-4bd9f848b7f3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593263168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.2593263168
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.3598698113
Short name T3628
Test name
Test status
Simulation time 798190277 ps
CPU time 1.87 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 207480 kb
Host smart-f6f2ed9b-e74a-4ea8-ad7f-bbaa7cf48b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35986
98113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.3598698113
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2048243149
Short name T1173
Test name
Test status
Simulation time 158837958 ps
CPU time 0.86 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 207528 kb
Host smart-59b32189-5eaf-48f0-81fa-e672aa8af8c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20482
43149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2048243149
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.259749687
Short name T673
Test name
Test status
Simulation time 29688594 ps
CPU time 0.73 seconds
Started Aug 18 05:35:26 PM PDT 24
Finished Aug 18 05:35:27 PM PDT 24
Peak memory 207420 kb
Host smart-7a2ed37d-a924-4721-ae87-fca712fd5ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25974
9687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.259749687
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.2309104798
Short name T1054
Test name
Test status
Simulation time 916459374 ps
CPU time 2.48 seconds
Started Aug 18 05:35:13 PM PDT 24
Finished Aug 18 05:35:15 PM PDT 24
Peak memory 207692 kb
Host smart-9de780d9-5926-404e-a53b-250954f4781a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23091
04798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.2309104798
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_types.3190068887
Short name T443
Test name
Test status
Simulation time 591789128 ps
CPU time 1.5 seconds
Started Aug 18 05:35:17 PM PDT 24
Finished Aug 18 05:35:19 PM PDT 24
Peak memory 207532 kb
Host smart-67d79259-9c87-4172-a125-ed55a8cbf0cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3190068887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_types.3190068887
Directory /workspace/23.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2370742493
Short name T872
Test name
Test status
Simulation time 157684949 ps
CPU time 1.26 seconds
Started Aug 18 05:35:14 PM PDT 24
Finished Aug 18 05:35:15 PM PDT 24
Peak memory 207684 kb
Host smart-3d4f897d-ed57-4f32-8adc-80660fb97e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23707
42493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2370742493
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.597686758
Short name T2529
Test name
Test status
Simulation time 194357877 ps
CPU time 1.04 seconds
Started Aug 18 05:35:22 PM PDT 24
Finished Aug 18 05:35:23 PM PDT 24
Peak memory 215844 kb
Host smart-49037c5d-004f-42b8-832a-2185241b41ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=597686758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.597686758
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3972041876
Short name T2357
Test name
Test status
Simulation time 173617888 ps
CPU time 0.9 seconds
Started Aug 18 05:35:20 PM PDT 24
Finished Aug 18 05:35:21 PM PDT 24
Peak memory 207448 kb
Host smart-eb663ca7-6fe7-49c4-8174-5cc2f31c296a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39720
41876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3972041876
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.4251319896
Short name T2733
Test name
Test status
Simulation time 178234587 ps
CPU time 0.94 seconds
Started Aug 18 05:35:21 PM PDT 24
Finished Aug 18 05:35:22 PM PDT 24
Peak memory 207424 kb
Host smart-1d9edde5-48c5-4411-8a60-33ff8b30f4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42513
19896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.4251319896
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.3565982235
Short name T1401
Test name
Test status
Simulation time 3803385974 ps
CPU time 36.26 seconds
Started Aug 18 05:35:16 PM PDT 24
Finished Aug 18 05:35:52 PM PDT 24
Peak memory 224140 kb
Host smart-ec49c180-f694-4446-852e-c598252b5d85
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3565982235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3565982235
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.2308068936
Short name T1133
Test name
Test status
Simulation time 7075878089 ps
CPU time 49.43 seconds
Started Aug 18 05:35:17 PM PDT 24
Finished Aug 18 05:36:06 PM PDT 24
Peak memory 207800 kb
Host smart-905d8903-fa6a-45e5-8650-73f900a3bcff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2308068936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.2308068936
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1478632314
Short name T1882
Test name
Test status
Simulation time 201683455 ps
CPU time 0.91 seconds
Started Aug 18 05:35:26 PM PDT 24
Finished Aug 18 05:35:27 PM PDT 24
Peak memory 207576 kb
Host smart-2b2f28e3-ac90-45ca-9c4b-9341ee593308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14786
32314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1478632314
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.111001279
Short name T1188
Test name
Test status
Simulation time 12445040392 ps
CPU time 19.14 seconds
Started Aug 18 05:35:39 PM PDT 24
Finished Aug 18 05:35:58 PM PDT 24
Peak memory 207712 kb
Host smart-e23e821f-65bc-4d3a-b8a4-1ab8dcc677d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11100
1279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.111001279
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.1652880239
Short name T1622
Test name
Test status
Simulation time 9769594488 ps
CPU time 12.66 seconds
Started Aug 18 05:35:26 PM PDT 24
Finished Aug 18 05:35:39 PM PDT 24
Peak memory 207788 kb
Host smart-7e110b91-0137-47f9-9bf6-77fe2a5a4e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16528
80239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1652880239
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.3505801394
Short name T3312
Test name
Test status
Simulation time 3160331982 ps
CPU time 89.86 seconds
Started Aug 18 05:35:15 PM PDT 24
Finished Aug 18 05:36:45 PM PDT 24
Peak memory 218464 kb
Host smart-9e5cface-1eed-462a-bc77-eef2e5cee3d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3505801394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3505801394
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1197622246
Short name T1179
Test name
Test status
Simulation time 3075049371 ps
CPU time 90.52 seconds
Started Aug 18 05:35:15 PM PDT 24
Finished Aug 18 05:36:45 PM PDT 24
Peak memory 215948 kb
Host smart-2b4e7016-2923-4b7e-9b71-64be1a1120b2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1197622246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1197622246
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.2300077778
Short name T1184
Test name
Test status
Simulation time 263715791 ps
CPU time 1.04 seconds
Started Aug 18 05:35:28 PM PDT 24
Finished Aug 18 05:35:29 PM PDT 24
Peak memory 207412 kb
Host smart-f31ffa0b-039f-4afb-a29f-a22559234f32
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2300077778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.2300077778
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1118501645
Short name T2664
Test name
Test status
Simulation time 220673038 ps
CPU time 1 seconds
Started Aug 18 05:35:33 PM PDT 24
Finished Aug 18 05:35:34 PM PDT 24
Peak memory 207516 kb
Host smart-da835290-ab22-4e4b-9be1-d9d568c181cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11185
01645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1118501645
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_non_iso_usb_traffic.1180489542
Short name T3096
Test name
Test status
Simulation time 2376509017 ps
CPU time 69.91 seconds
Started Aug 18 05:35:24 PM PDT 24
Finished Aug 18 05:36:34 PM PDT 24
Peak memory 217644 kb
Host smart-d769308d-b382-495e-847d-87217562a36f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11804
89542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_non_iso_usb_traffic.1180489542
Directory /workspace/23.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.4264975936
Short name T1819
Test name
Test status
Simulation time 2660002606 ps
CPU time 25.72 seconds
Started Aug 18 05:35:24 PM PDT 24
Finished Aug 18 05:35:50 PM PDT 24
Peak memory 217628 kb
Host smart-ccc93084-a6c2-4518-bd1c-8f72aeb61495
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4264975936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.4264975936
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.1030030504
Short name T1978
Test name
Test status
Simulation time 180013066 ps
CPU time 0.93 seconds
Started Aug 18 05:35:24 PM PDT 24
Finished Aug 18 05:35:25 PM PDT 24
Peak memory 207496 kb
Host smart-3bebb99f-c8e8-4985-9a77-bdabaaebd692
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1030030504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.1030030504
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2662506644
Short name T1371
Test name
Test status
Simulation time 196108547 ps
CPU time 1 seconds
Started Aug 18 05:35:36 PM PDT 24
Finished Aug 18 05:35:37 PM PDT 24
Peak memory 207452 kb
Host smart-9ff06a6d-5b07-463a-8117-82bdd7393fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26625
06644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2662506644
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.4016260890
Short name T148
Test name
Test status
Simulation time 258643198 ps
CPU time 1.1 seconds
Started Aug 18 05:35:28 PM PDT 24
Finished Aug 18 05:35:29 PM PDT 24
Peak memory 207468 kb
Host smart-26395761-e32f-4d36-945f-08c874a30c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40162
60890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.4016260890
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3565955602
Short name T3470
Test name
Test status
Simulation time 162772670 ps
CPU time 0.88 seconds
Started Aug 18 05:35:25 PM PDT 24
Finished Aug 18 05:35:26 PM PDT 24
Peak memory 207404 kb
Host smart-306bcaca-8ce3-4c5a-aa09-12d4d991dec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35659
55602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3565955602
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.342914637
Short name T1157
Test name
Test status
Simulation time 157241395 ps
CPU time 0.83 seconds
Started Aug 18 05:35:14 PM PDT 24
Finished Aug 18 05:35:15 PM PDT 24
Peak memory 207508 kb
Host smart-ac6f8744-1e10-4a29-a137-4c6eb870d0f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34291
4637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.342914637
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3589830192
Short name T1293
Test name
Test status
Simulation time 235285314 ps
CPU time 0.94 seconds
Started Aug 18 05:35:27 PM PDT 24
Finished Aug 18 05:35:28 PM PDT 24
Peak memory 207568 kb
Host smart-529d1d13-c93a-4e76-98a1-23b13f84b311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35898
30192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3589830192
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.275770572
Short name T2966
Test name
Test status
Simulation time 159218649 ps
CPU time 0.85 seconds
Started Aug 18 05:35:19 PM PDT 24
Finished Aug 18 05:35:20 PM PDT 24
Peak memory 207576 kb
Host smart-399899b7-5c29-4502-8218-f25d0dd5702e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27577
0572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.275770572
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.758573094
Short name T3021
Test name
Test status
Simulation time 255341774 ps
CPU time 1.05 seconds
Started Aug 18 05:35:30 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 207572 kb
Host smart-018c3678-f514-4dcf-9bcd-3fceaf88b4ba
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=758573094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.758573094
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.600100391
Short name T1529
Test name
Test status
Simulation time 138425287 ps
CPU time 0.86 seconds
Started Aug 18 05:35:25 PM PDT 24
Finished Aug 18 05:35:25 PM PDT 24
Peak memory 207456 kb
Host smart-0c349628-a469-40bf-bc0f-67fe7aa06d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60010
0391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.600100391
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1758127017
Short name T2513
Test name
Test status
Simulation time 74204940 ps
CPU time 0.73 seconds
Started Aug 18 05:35:39 PM PDT 24
Finished Aug 18 05:35:45 PM PDT 24
Peak memory 207440 kb
Host smart-b50aaae7-b864-491c-a82f-3c081497a7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17581
27017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1758127017
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.562931737
Short name T325
Test name
Test status
Simulation time 14371357395 ps
CPU time 33.54 seconds
Started Aug 18 05:35:26 PM PDT 24
Finished Aug 18 05:36:00 PM PDT 24
Peak memory 216000 kb
Host smart-c10afcf3-9079-4793-adfc-3366519b7206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56293
1737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.562931737
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.556225717
Short name T2535
Test name
Test status
Simulation time 172636124 ps
CPU time 0.89 seconds
Started Aug 18 05:35:44 PM PDT 24
Finished Aug 18 05:35:45 PM PDT 24
Peak memory 207560 kb
Host smart-101aa148-508a-42ad-9486-d7562066cba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55622
5717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.556225717
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2910330413
Short name T672
Test name
Test status
Simulation time 168828081 ps
CPU time 0.95 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 207496 kb
Host smart-b9450288-1d4d-40b3-acae-befb3033f398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29103
30413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2910330413
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.681926868
Short name T3464
Test name
Test status
Simulation time 198329442 ps
CPU time 0.93 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 207512 kb
Host smart-8e8fb330-adfd-449d-b626-75c2d523f7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68192
6868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.681926868
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.43629980
Short name T1961
Test name
Test status
Simulation time 213503728 ps
CPU time 1.03 seconds
Started Aug 18 05:35:37 PM PDT 24
Finished Aug 18 05:35:38 PM PDT 24
Peak memory 207480 kb
Host smart-c86f0537-d01d-4cd5-a09a-ae5aad79b344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43629
980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.43629980
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.3935644564
Short name T1726
Test name
Test status
Simulation time 199276996 ps
CPU time 0.85 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:35:30 PM PDT 24
Peak memory 207428 kb
Host smart-58f4afbf-06da-4366-b516-5b49aa5c5551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39356
44564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.3935644564
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_rx_full.4179258686
Short name T1299
Test name
Test status
Simulation time 367968325 ps
CPU time 1.25 seconds
Started Aug 18 05:35:27 PM PDT 24
Finished Aug 18 05:35:33 PM PDT 24
Peak memory 207460 kb
Host smart-0a5cc12c-3b37-456f-88a4-57147c16c40a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41792
58686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_full.4179258686
Directory /workspace/23.usbdev_rx_full/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2582637973
Short name T2358
Test name
Test status
Simulation time 172838622 ps
CPU time 0.85 seconds
Started Aug 18 05:35:41 PM PDT 24
Finished Aug 18 05:35:42 PM PDT 24
Peak memory 207552 kb
Host smart-5d23eb32-b1d9-40c7-b6f4-57d9ae3d0e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25826
37973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2582637973
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.577984703
Short name T899
Test name
Test status
Simulation time 157638015 ps
CPU time 0.87 seconds
Started Aug 18 05:35:25 PM PDT 24
Finished Aug 18 05:35:26 PM PDT 24
Peak memory 207556 kb
Host smart-a8a21808-f79b-47bd-bd2b-e66a78d623b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57798
4703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.577984703
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.4053897836
Short name T2443
Test name
Test status
Simulation time 176550675 ps
CPU time 0.97 seconds
Started Aug 18 05:35:19 PM PDT 24
Finished Aug 18 05:35:20 PM PDT 24
Peak memory 207444 kb
Host smart-8fd01e7b-ab77-4c0a-8791-a1aca25b4a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40538
97836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.4053897836
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.457448959
Short name T2422
Test name
Test status
Simulation time 3009292300 ps
CPU time 82.05 seconds
Started Aug 18 05:35:19 PM PDT 24
Finished Aug 18 05:36:41 PM PDT 24
Peak memory 215928 kb
Host smart-4c29f0ac-0883-4d1c-9766-cf1860a1085f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=457448959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.457448959
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3141560164
Short name T917
Test name
Test status
Simulation time 262726978 ps
CPU time 0.99 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 207504 kb
Host smart-08bddbd4-c54c-48e5-914f-775447595a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31415
60164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3141560164
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1906993880
Short name T618
Test name
Test status
Simulation time 211185142 ps
CPU time 0.95 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:35:30 PM PDT 24
Peak memory 207576 kb
Host smart-b9a30302-839a-4acd-a6d6-55210cc5967f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19069
93880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1906993880
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.180458931
Short name T3242
Test name
Test status
Simulation time 1282849212 ps
CPU time 3.24 seconds
Started Aug 18 05:35:33 PM PDT 24
Finished Aug 18 05:35:36 PM PDT 24
Peak memory 207700 kb
Host smart-3daadb2f-c14c-4900-9e5d-b241db5e7d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18045
8931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.180458931
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.312765865
Short name T2679
Test name
Test status
Simulation time 3217049823 ps
CPU time 32.35 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:36:04 PM PDT 24
Peak memory 217592 kb
Host smart-9be97fb6-526a-4428-8150-15931b4e0f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31276
5865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.312765865
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.956017912
Short name T607
Test name
Test status
Simulation time 4303996391 ps
CPU time 29.99 seconds
Started Aug 18 05:35:26 PM PDT 24
Finished Aug 18 05:35:57 PM PDT 24
Peak memory 207628 kb
Host smart-2ffa699d-1ab6-47e5-8c91-2186b93d31f9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956017912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_host
_handshake.956017912
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_tx_rx_disruption.3531941125
Short name T1069
Test name
Test status
Simulation time 496811875 ps
CPU time 1.47 seconds
Started Aug 18 05:35:44 PM PDT 24
Finished Aug 18 05:35:51 PM PDT 24
Peak memory 207532 kb
Host smart-5e2a8d68-e881-46a8-87ec-cd260fc02087
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531941125 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.usbdev_tx_rx_disruption.3531941125
Directory /workspace/23.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/230.usbdev_tx_rx_disruption.3087923578
Short name T1071
Test name
Test status
Simulation time 552514411 ps
CPU time 1.74 seconds
Started Aug 18 05:39:22 PM PDT 24
Finished Aug 18 05:39:24 PM PDT 24
Peak memory 207552 kb
Host smart-7457d0b7-17ef-4e16-bdc5-1de2a42b74fa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087923578 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.usbdev_tx_rx_disruption.3087923578
Directory /workspace/230.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/231.usbdev_tx_rx_disruption.3045148496
Short name T1557
Test name
Test status
Simulation time 643728915 ps
CPU time 1.77 seconds
Started Aug 18 05:39:50 PM PDT 24
Finished Aug 18 05:39:52 PM PDT 24
Peak memory 207524 kb
Host smart-5ceff291-29b0-4e1f-ae7f-488156e3737a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045148496 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.usbdev_tx_rx_disruption.3045148496
Directory /workspace/231.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/232.usbdev_tx_rx_disruption.1582917844
Short name T763
Test name
Test status
Simulation time 424112244 ps
CPU time 1.32 seconds
Started Aug 18 05:39:48 PM PDT 24
Finished Aug 18 05:39:49 PM PDT 24
Peak memory 207504 kb
Host smart-ea6120de-4071-4d00-a248-d0da91d36f30
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582917844 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 232.usbdev_tx_rx_disruption.1582917844
Directory /workspace/232.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/233.usbdev_tx_rx_disruption.561644218
Short name T938
Test name
Test status
Simulation time 497214227 ps
CPU time 1.52 seconds
Started Aug 18 05:39:38 PM PDT 24
Finished Aug 18 05:39:39 PM PDT 24
Peak memory 207560 kb
Host smart-203d98f9-03ae-4363-97f2-941dc1cf0431
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561644218 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 233.usbdev_tx_rx_disruption.561644218
Directory /workspace/233.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/234.usbdev_tx_rx_disruption.1061308226
Short name T2690
Test name
Test status
Simulation time 515952375 ps
CPU time 1.58 seconds
Started Aug 18 05:39:35 PM PDT 24
Finished Aug 18 05:39:37 PM PDT 24
Peak memory 207376 kb
Host smart-e287a861-a4ef-4a3c-afd0-3cfe858a234f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061308226 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 234.usbdev_tx_rx_disruption.1061308226
Directory /workspace/234.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/235.usbdev_tx_rx_disruption.2224740996
Short name T2520
Test name
Test status
Simulation time 454577936 ps
CPU time 1.58 seconds
Started Aug 18 05:39:55 PM PDT 24
Finished Aug 18 05:39:56 PM PDT 24
Peak memory 207560 kb
Host smart-62df19c9-b37a-4820-bfd9-7c02b7a2bfb8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224740996 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 235.usbdev_tx_rx_disruption.2224740996
Directory /workspace/235.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/236.usbdev_tx_rx_disruption.2601777472
Short name T3419
Test name
Test status
Simulation time 471998493 ps
CPU time 1.49 seconds
Started Aug 18 05:39:52 PM PDT 24
Finished Aug 18 05:39:54 PM PDT 24
Peak memory 207572 kb
Host smart-f331f42c-458e-42a9-8230-233049a361c5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601777472 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 236.usbdev_tx_rx_disruption.2601777472
Directory /workspace/236.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/237.usbdev_tx_rx_disruption.1294284575
Short name T912
Test name
Test status
Simulation time 550332299 ps
CPU time 1.57 seconds
Started Aug 18 05:39:50 PM PDT 24
Finished Aug 18 05:39:51 PM PDT 24
Peak memory 207540 kb
Host smart-a96f9cdd-eed6-4bc8-8f88-d551a1436180
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294284575 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.usbdev_tx_rx_disruption.1294284575
Directory /workspace/237.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/238.usbdev_tx_rx_disruption.431518224
Short name T3306
Test name
Test status
Simulation time 514609394 ps
CPU time 1.54 seconds
Started Aug 18 05:39:33 PM PDT 24
Finished Aug 18 05:39:35 PM PDT 24
Peak memory 207560 kb
Host smart-34d87eb6-4016-495a-bed3-23fbcb90d6e0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431518224 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 238.usbdev_tx_rx_disruption.431518224
Directory /workspace/238.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/239.usbdev_tx_rx_disruption.3492618041
Short name T2502
Test name
Test status
Simulation time 644646282 ps
CPU time 1.71 seconds
Started Aug 18 05:39:42 PM PDT 24
Finished Aug 18 05:39:43 PM PDT 24
Peak memory 207560 kb
Host smart-44ebd846-4137-4ab2-a02c-7727e17c5c76
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492618041 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.usbdev_tx_rx_disruption.3492618041
Directory /workspace/239.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.3824008605
Short name T2691
Test name
Test status
Simulation time 38882091 ps
CPU time 0.73 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:35:30 PM PDT 24
Peak memory 207432 kb
Host smart-6a81e619-9ac2-4c0d-9366-5329cec40912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3824008605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.3824008605
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.2875905380
Short name T3614
Test name
Test status
Simulation time 12094299999 ps
CPU time 17.39 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:53 PM PDT 24
Peak memory 207752 kb
Host smart-b373d13c-3e4d-449d-8ae3-29dad6d8b5ef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875905380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_disconnect.2875905380
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.605637591
Short name T3575
Test name
Test status
Simulation time 20062028866 ps
CPU time 23.28 seconds
Started Aug 18 05:35:24 PM PDT 24
Finished Aug 18 05:35:48 PM PDT 24
Peak memory 207776 kb
Host smart-cbf2c634-acf8-4057-9602-6157b04b9a84
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=605637591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.605637591
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.4269325830
Short name T2547
Test name
Test status
Simulation time 30575236154 ps
CPU time 38.08 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:36:07 PM PDT 24
Peak memory 207820 kb
Host smart-770f4d65-6b44-4ef1-94c8-4a70e5bf2f0d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269325830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.4269325830
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.381620436
Short name T3235
Test name
Test status
Simulation time 173648563 ps
CPU time 0.87 seconds
Started Aug 18 05:35:30 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 207472 kb
Host smart-c7540707-57a3-436c-90f6-cf53a2d4ed62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38162
0436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.381620436
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.3449510164
Short name T3107
Test name
Test status
Simulation time 153558638 ps
CPU time 0.82 seconds
Started Aug 18 05:35:46 PM PDT 24
Finished Aug 18 05:35:47 PM PDT 24
Peak memory 207560 kb
Host smart-32d5b3ef-17e0-4aee-89d7-16da98b10935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34495
10164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3449510164
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.3580922050
Short name T1140
Test name
Test status
Simulation time 408934174 ps
CPU time 1.46 seconds
Started Aug 18 05:35:33 PM PDT 24
Finished Aug 18 05:35:34 PM PDT 24
Peak memory 207596 kb
Host smart-85a26cee-cb29-4652-a9f7-cfd7a9f9ed23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35809
22050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.3580922050
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1510667374
Short name T351
Test name
Test status
Simulation time 874062006 ps
CPU time 2.14 seconds
Started Aug 18 05:35:39 PM PDT 24
Finished Aug 18 05:35:41 PM PDT 24
Peak memory 207720 kb
Host smart-5ee68dde-d71a-4522-b822-e7302fa1b8a7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1510667374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1510667374
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.2898048269
Short name T2825
Test name
Test status
Simulation time 41517672493 ps
CPU time 64.53 seconds
Started Aug 18 05:35:46 PM PDT 24
Finished Aug 18 05:36:51 PM PDT 24
Peak memory 207796 kb
Host smart-43332878-b19c-4edf-9668-106067f93f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28980
48269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2898048269
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.3747893674
Short name T3150
Test name
Test status
Simulation time 4338246506 ps
CPU time 37.5 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:36:09 PM PDT 24
Peak memory 207740 kb
Host smart-d6bfc2bc-9af3-4c15-8aa2-695adce66ccb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747893674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.3747893674
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.2655419021
Short name T2732
Test name
Test status
Simulation time 862269674 ps
CPU time 1.84 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 207524 kb
Host smart-dfa1018e-0941-42ad-b5fd-cb931ab62b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26554
19021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.2655419021
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.2520768812
Short name T2165
Test name
Test status
Simulation time 171655084 ps
CPU time 0.85 seconds
Started Aug 18 05:35:32 PM PDT 24
Finished Aug 18 05:35:33 PM PDT 24
Peak memory 207440 kb
Host smart-8b9e41ef-d4c3-43ec-96de-6f346f52b77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25207
68812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.2520768812
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2493041128
Short name T2425
Test name
Test status
Simulation time 42094216 ps
CPU time 0.7 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:35:30 PM PDT 24
Peak memory 207408 kb
Host smart-36523ec8-9c14-4fd3-bcc4-6c26115b32ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24930
41128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2493041128
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1013958019
Short name T3112
Test name
Test status
Simulation time 835102509 ps
CPU time 2.24 seconds
Started Aug 18 05:35:37 PM PDT 24
Finished Aug 18 05:35:40 PM PDT 24
Peak memory 207736 kb
Host smart-b15a1e51-4e94-4de9-8c35-dcf86cd75416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10139
58019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1013958019
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2175955950
Short name T2796
Test name
Test status
Simulation time 192179612 ps
CPU time 2.13 seconds
Started Aug 18 05:35:43 PM PDT 24
Finished Aug 18 05:35:45 PM PDT 24
Peak memory 207588 kb
Host smart-54870d22-e0cf-4bcf-966e-3c271f819072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21759
55950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2175955950
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3962334559
Short name T586
Test name
Test status
Simulation time 218888725 ps
CPU time 1.16 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 215888 kb
Host smart-8f30735f-ad66-4548-ba17-e1304baff36e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3962334559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3962334559
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1640636310
Short name T1927
Test name
Test status
Simulation time 147082236 ps
CPU time 0.82 seconds
Started Aug 18 05:35:45 PM PDT 24
Finished Aug 18 05:35:46 PM PDT 24
Peak memory 207452 kb
Host smart-9a513b4d-2003-41f9-ba46-a46859ee026c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16406
36310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1640636310
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.534062887
Short name T557
Test name
Test status
Simulation time 271991145 ps
CPU time 1.04 seconds
Started Aug 18 05:35:44 PM PDT 24
Finished Aug 18 05:35:45 PM PDT 24
Peak memory 207472 kb
Host smart-b9ceab2f-5fcd-4368-b763-82c96f1f8ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53406
2887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.534062887
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.3542659838
Short name T3516
Test name
Test status
Simulation time 2663389347 ps
CPU time 25.6 seconds
Started Aug 18 05:35:30 PM PDT 24
Finished Aug 18 05:35:56 PM PDT 24
Peak memory 224168 kb
Host smart-decf4760-1e35-469f-86ea-79f6c08d580c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3542659838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.3542659838
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.2026316988
Short name T113
Test name
Test status
Simulation time 5856313167 ps
CPU time 40.82 seconds
Started Aug 18 05:35:38 PM PDT 24
Finished Aug 18 05:36:19 PM PDT 24
Peak memory 207760 kb
Host smart-6c660b26-180b-47a4-b10a-4cdd5b55c68d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2026316988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.2026316988
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.332151148
Short name T2285
Test name
Test status
Simulation time 216523523 ps
CPU time 1.01 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:35:30 PM PDT 24
Peak memory 207508 kb
Host smart-11de97b7-cc8c-4998-a4ef-ae215b852218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33215
1148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.332151148
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.2355889451
Short name T3454
Test name
Test status
Simulation time 29545964577 ps
CPU time 45.29 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:36:17 PM PDT 24
Peak memory 207824 kb
Host smart-e76bf99d-fcc4-4f30-95cb-38f0bf1a0d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23558
89451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.2355889451
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2547902017
Short name T102
Test name
Test status
Simulation time 8540238786 ps
CPU time 10.76 seconds
Started Aug 18 05:35:32 PM PDT 24
Finished Aug 18 05:35:43 PM PDT 24
Peak memory 207832 kb
Host smart-26b0b676-5ef9-44be-b0b0-728faaef5e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25479
02017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2547902017
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.4119595273
Short name T1977
Test name
Test status
Simulation time 3440502877 ps
CPU time 35.74 seconds
Started Aug 18 05:35:28 PM PDT 24
Finished Aug 18 05:36:04 PM PDT 24
Peak memory 224184 kb
Host smart-a7775d87-0900-404e-a2d7-965d5f1e6f48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4119595273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.4119595273
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.585164709
Short name T3316
Test name
Test status
Simulation time 3111123827 ps
CPU time 22.67 seconds
Started Aug 18 05:35:32 PM PDT 24
Finished Aug 18 05:35:55 PM PDT 24
Peak memory 215988 kb
Host smart-d3ab80e6-3fcf-4b52-82cb-d8752863ac03
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=585164709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.585164709
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.1166114775
Short name T3247
Test name
Test status
Simulation time 247313028 ps
CPU time 0.95 seconds
Started Aug 18 05:35:43 PM PDT 24
Finished Aug 18 05:35:45 PM PDT 24
Peak memory 207504 kb
Host smart-324c1367-12f1-4990-95fa-642078e32c84
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1166114775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1166114775
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.329205654
Short name T1130
Test name
Test status
Simulation time 226057774 ps
CPU time 1.01 seconds
Started Aug 18 05:35:37 PM PDT 24
Finished Aug 18 05:35:38 PM PDT 24
Peak memory 207488 kb
Host smart-6485b84b-7091-41ad-974e-ba7dfb669d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32920
5654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.329205654
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_non_iso_usb_traffic.4082073977
Short name T2909
Test name
Test status
Simulation time 2622722216 ps
CPU time 24.97 seconds
Started Aug 18 05:35:28 PM PDT 24
Finished Aug 18 05:35:53 PM PDT 24
Peak memory 215864 kb
Host smart-be2b4781-d3bc-4bd1-beb9-d159a1f168e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40820
73977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_non_iso_usb_traffic.4082073977
Directory /workspace/24.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.2412077765
Short name T3561
Test name
Test status
Simulation time 2806537377 ps
CPU time 79.55 seconds
Started Aug 18 05:35:36 PM PDT 24
Finished Aug 18 05:36:56 PM PDT 24
Peak memory 215916 kb
Host smart-13ab1597-2f04-4a56-b29e-34da1169b1da
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2412077765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.2412077765
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.234500784
Short name T3282
Test name
Test status
Simulation time 152115753 ps
CPU time 0.89 seconds
Started Aug 18 05:35:38 PM PDT 24
Finished Aug 18 05:35:39 PM PDT 24
Peak memory 207488 kb
Host smart-c7891fe6-5f7f-443c-b31d-72ecce36a9c8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=234500784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.234500784
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.518608003
Short name T794
Test name
Test status
Simulation time 157223759 ps
CPU time 0.86 seconds
Started Aug 18 05:35:35 PM PDT 24
Finished Aug 18 05:35:36 PM PDT 24
Peak memory 207460 kb
Host smart-2cab4ebb-408b-4bbb-b27d-0e1226f5b584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51860
8003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.518608003
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2612202820
Short name T2912
Test name
Test status
Simulation time 191048092 ps
CPU time 0.91 seconds
Started Aug 18 05:35:41 PM PDT 24
Finished Aug 18 05:35:42 PM PDT 24
Peak memory 207440 kb
Host smart-911e1343-f2c8-463b-a290-14caf5483082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26122
02820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2612202820
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2313826281
Short name T3118
Test name
Test status
Simulation time 183227036 ps
CPU time 0.9 seconds
Started Aug 18 05:35:32 PM PDT 24
Finished Aug 18 05:35:33 PM PDT 24
Peak memory 207488 kb
Host smart-3297466f-2c6e-4ff3-a81e-215ee36bee5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23138
26281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2313826281
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3239898269
Short name T841
Test name
Test status
Simulation time 181394763 ps
CPU time 0.87 seconds
Started Aug 18 05:35:40 PM PDT 24
Finished Aug 18 05:35:41 PM PDT 24
Peak memory 207396 kb
Host smart-47a10168-d8e9-4b94-81da-d273ef41816a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32398
98269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3239898269
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.4196066474
Short name T1972
Test name
Test status
Simulation time 227562130 ps
CPU time 0.98 seconds
Started Aug 18 05:35:37 PM PDT 24
Finished Aug 18 05:35:38 PM PDT 24
Peak memory 207524 kb
Host smart-8e64a571-32a9-4493-8618-25481b3398a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41960
66474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.4196066474
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3817663039
Short name T193
Test name
Test status
Simulation time 163063449 ps
CPU time 0.86 seconds
Started Aug 18 05:35:43 PM PDT 24
Finished Aug 18 05:35:49 PM PDT 24
Peak memory 207532 kb
Host smart-3263ec4e-ed5f-476b-a2f4-f0cfa7f0e4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38176
63039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3817663039
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3626325431
Short name T3060
Test name
Test status
Simulation time 223866499 ps
CPU time 1.08 seconds
Started Aug 18 05:35:30 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 207556 kb
Host smart-0abeb962-f7be-40da-80e5-428b8220cb71
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3626325431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3626325431
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.71248257
Short name T1665
Test name
Test status
Simulation time 144216479 ps
CPU time 0.78 seconds
Started Aug 18 05:35:38 PM PDT 24
Finished Aug 18 05:35:39 PM PDT 24
Peak memory 207452 kb
Host smart-a0f7f89f-e1d2-4a94-acf3-3567549aa1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71248
257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.71248257
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.3087355362
Short name T3364
Test name
Test status
Simulation time 47247836 ps
CPU time 0.7 seconds
Started Aug 18 05:35:37 PM PDT 24
Finished Aug 18 05:35:38 PM PDT 24
Peak memory 207504 kb
Host smart-4761a516-5d97-4d4b-962a-eb3a52932392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30873
55362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3087355362
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1337804250
Short name T297
Test name
Test status
Simulation time 16032218497 ps
CPU time 39.8 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:36:09 PM PDT 24
Peak memory 224072 kb
Host smart-c36865a1-53b9-4705-8758-99e7edec28e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13378
04250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1337804250
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.952294370
Short name T3581
Test name
Test status
Simulation time 182931771 ps
CPU time 0.94 seconds
Started Aug 18 05:35:39 PM PDT 24
Finished Aug 18 05:35:40 PM PDT 24
Peak memory 207576 kb
Host smart-f67e66be-d197-4fdc-9ea7-ec6cc306cb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95229
4370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.952294370
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.395153137
Short name T1626
Test name
Test status
Simulation time 225279403 ps
CPU time 0.98 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 207204 kb
Host smart-bb35a07d-6c1f-4f34-9176-e336e3f1055e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39515
3137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.395153137
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.669034471
Short name T1759
Test name
Test status
Simulation time 238029965 ps
CPU time 0.97 seconds
Started Aug 18 05:35:33 PM PDT 24
Finished Aug 18 05:35:34 PM PDT 24
Peak memory 207460 kb
Host smart-c96223e7-ef0b-424a-9b89-b4745acd232d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66903
4471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.669034471
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.190415995
Short name T1866
Test name
Test status
Simulation time 180822145 ps
CPU time 0.93 seconds
Started Aug 18 05:35:40 PM PDT 24
Finished Aug 18 05:35:41 PM PDT 24
Peak memory 207504 kb
Host smart-1133a5a0-447a-4802-90b2-d35b498627e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19041
5995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.190415995
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.969678420
Short name T2000
Test name
Test status
Simulation time 169374441 ps
CPU time 0.83 seconds
Started Aug 18 05:35:46 PM PDT 24
Finished Aug 18 05:35:46 PM PDT 24
Peak memory 207188 kb
Host smart-a2ef76fe-ab5d-4512-880f-845b13c18bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96967
8420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.969678420
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_rx_full.2950184936
Short name T2409
Test name
Test status
Simulation time 258114278 ps
CPU time 1.13 seconds
Started Aug 18 05:35:34 PM PDT 24
Finished Aug 18 05:35:35 PM PDT 24
Peak memory 207392 kb
Host smart-ba4e6fa6-537f-4b73-b2f7-28d92e157622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29501
84936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_full.2950184936
Directory /workspace/24.usbdev_rx_full/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.4248691096
Short name T1742
Test name
Test status
Simulation time 144725638 ps
CPU time 0.81 seconds
Started Aug 18 05:35:26 PM PDT 24
Finished Aug 18 05:35:27 PM PDT 24
Peak memory 207532 kb
Host smart-37bb5048-cd9b-48d6-b3de-25459cd14900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42486
91096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.4248691096
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2449001771
Short name T3537
Test name
Test status
Simulation time 182358092 ps
CPU time 0.93 seconds
Started Aug 18 05:35:37 PM PDT 24
Finished Aug 18 05:35:38 PM PDT 24
Peak memory 207484 kb
Host smart-8c92013e-4523-4418-b7bd-6f65c5e5a973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24490
01771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2449001771
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.162097269
Short name T2373
Test name
Test status
Simulation time 192464180 ps
CPU time 1.05 seconds
Started Aug 18 05:35:36 PM PDT 24
Finished Aug 18 05:35:37 PM PDT 24
Peak memory 207400 kb
Host smart-f7e00a6a-c965-47ee-9f6a-e77a5f6500a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16209
7269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.162097269
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.2870246840
Short name T2320
Test name
Test status
Simulation time 3817065669 ps
CPU time 38.77 seconds
Started Aug 18 05:35:34 PM PDT 24
Finished Aug 18 05:36:13 PM PDT 24
Peak memory 224064 kb
Host smart-c76f8320-81c5-4629-bdab-c235f071d03c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2870246840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.2870246840
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.716978689
Short name T501
Test name
Test status
Simulation time 197740406 ps
CPU time 0.95 seconds
Started Aug 18 05:35:39 PM PDT 24
Finished Aug 18 05:35:40 PM PDT 24
Peak memory 207468 kb
Host smart-a558e1b5-53ae-42cc-91ca-591ef7f486bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71697
8689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.716978689
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.824925451
Short name T3339
Test name
Test status
Simulation time 152567538 ps
CPU time 0.85 seconds
Started Aug 18 05:35:28 PM PDT 24
Finished Aug 18 05:35:29 PM PDT 24
Peak memory 207504 kb
Host smart-1bf8efef-8753-4f1f-8935-7dc0e85b8da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82492
5451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.824925451
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.3052579891
Short name T1117
Test name
Test status
Simulation time 666874889 ps
CPU time 1.8 seconds
Started Aug 18 05:35:40 PM PDT 24
Finished Aug 18 05:35:42 PM PDT 24
Peak memory 207488 kb
Host smart-98263df3-a6f7-48ed-82ed-32ce98f8cf27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30525
79891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.3052579891
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.3487444725
Short name T1950
Test name
Test status
Simulation time 2330253999 ps
CPU time 22.87 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:55 PM PDT 24
Peak memory 217820 kb
Host smart-da3eee63-fbcd-4880-b88e-cb79595289a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34874
44725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3487444725
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.3468452359
Short name T1594
Test name
Test status
Simulation time 6347204729 ps
CPU time 39.81 seconds
Started Aug 18 05:35:37 PM PDT 24
Finished Aug 18 05:36:17 PM PDT 24
Peak memory 207716 kb
Host smart-e1322c38-556a-4585-8b16-d355ca3d2020
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468452359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_hos
t_handshake.3468452359
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_tx_rx_disruption.606018114
Short name T264
Test name
Test status
Simulation time 505718877 ps
CPU time 1.47 seconds
Started Aug 18 05:35:33 PM PDT 24
Finished Aug 18 05:35:35 PM PDT 24
Peak memory 207576 kb
Host smart-9ea0e683-6342-467d-949f-09e1f0257396
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606018114 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.usbdev_tx_rx_disruption.606018114
Directory /workspace/24.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/240.usbdev_tx_rx_disruption.3383491989
Short name T1806
Test name
Test status
Simulation time 456316078 ps
CPU time 1.36 seconds
Started Aug 18 05:39:44 PM PDT 24
Finished Aug 18 05:39:45 PM PDT 24
Peak memory 207584 kb
Host smart-22f923c4-80ed-43a0-b183-72a56e6e9a7d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383491989 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 240.usbdev_tx_rx_disruption.3383491989
Directory /workspace/240.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/241.usbdev_tx_rx_disruption.1943511955
Short name T2370
Test name
Test status
Simulation time 546740894 ps
CPU time 1.82 seconds
Started Aug 18 05:39:34 PM PDT 24
Finished Aug 18 05:39:36 PM PDT 24
Peak memory 207564 kb
Host smart-886562fe-66a1-41ec-b58a-80fbc640375c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943511955 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 241.usbdev_tx_rx_disruption.1943511955
Directory /workspace/241.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/242.usbdev_tx_rx_disruption.835405571
Short name T1769
Test name
Test status
Simulation time 481956823 ps
CPU time 1.41 seconds
Started Aug 18 05:39:48 PM PDT 24
Finished Aug 18 05:39:50 PM PDT 24
Peak memory 207592 kb
Host smart-4ac694cc-dea3-4e91-988a-8d2866c89ce9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835405571 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 242.usbdev_tx_rx_disruption.835405571
Directory /workspace/242.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/243.usbdev_tx_rx_disruption.766956336
Short name T3447
Test name
Test status
Simulation time 497111184 ps
CPU time 1.52 seconds
Started Aug 18 05:39:51 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207584 kb
Host smart-f2525d7e-177f-4cc6-97d0-ab19ae1790aa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766956336 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 243.usbdev_tx_rx_disruption.766956336
Directory /workspace/243.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/244.usbdev_tx_rx_disruption.1600966766
Short name T1938
Test name
Test status
Simulation time 477452256 ps
CPU time 1.57 seconds
Started Aug 18 05:39:49 PM PDT 24
Finished Aug 18 05:39:51 PM PDT 24
Peak memory 207588 kb
Host smart-1d3c733f-98ee-41de-aeb1-7a25ac5d962b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600966766 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.usbdev_tx_rx_disruption.1600966766
Directory /workspace/244.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/245.usbdev_tx_rx_disruption.1137020355
Short name T3546
Test name
Test status
Simulation time 610877058 ps
CPU time 1.66 seconds
Started Aug 18 05:39:54 PM PDT 24
Finished Aug 18 05:39:56 PM PDT 24
Peak memory 207376 kb
Host smart-893e8c10-bff9-49ca-8ab1-610d878b0ad7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137020355 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 245.usbdev_tx_rx_disruption.1137020355
Directory /workspace/245.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/246.usbdev_tx_rx_disruption.2642218013
Short name T3418
Test name
Test status
Simulation time 464015639 ps
CPU time 1.64 seconds
Started Aug 18 05:39:51 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207576 kb
Host smart-693fff09-d7bc-4e61-a6c0-e16b1979c0a0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642218013 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.usbdev_tx_rx_disruption.2642218013
Directory /workspace/246.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/247.usbdev_tx_rx_disruption.959204670
Short name T2379
Test name
Test status
Simulation time 442762905 ps
CPU time 1.49 seconds
Started Aug 18 05:39:42 PM PDT 24
Finished Aug 18 05:39:43 PM PDT 24
Peak memory 207380 kb
Host smart-c1983f51-cf8d-44b7-9107-5d5ba3b092c5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959204670 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 247.usbdev_tx_rx_disruption.959204670
Directory /workspace/247.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/248.usbdev_tx_rx_disruption.612014848
Short name T2628
Test name
Test status
Simulation time 599545558 ps
CPU time 1.63 seconds
Started Aug 18 05:39:42 PM PDT 24
Finished Aug 18 05:39:44 PM PDT 24
Peak memory 207532 kb
Host smart-cd522f3b-80f6-407a-b47b-13e2be581b9c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612014848 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 248.usbdev_tx_rx_disruption.612014848
Directory /workspace/248.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/249.usbdev_tx_rx_disruption.506350045
Short name T2031
Test name
Test status
Simulation time 602436863 ps
CPU time 1.66 seconds
Started Aug 18 05:39:37 PM PDT 24
Finished Aug 18 05:39:38 PM PDT 24
Peak memory 207536 kb
Host smart-e2106337-a923-4724-9878-cce227443863
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506350045 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 249.usbdev_tx_rx_disruption.506350045
Directory /workspace/249.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.4046973779
Short name T2801
Test name
Test status
Simulation time 43247814 ps
CPU time 0.67 seconds
Started Aug 18 05:35:48 PM PDT 24
Finished Aug 18 05:35:49 PM PDT 24
Peak memory 207404 kb
Host smart-cd958161-55a0-4d14-ab54-b39be3895d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4046973779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.4046973779
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1127735666
Short name T3170
Test name
Test status
Simulation time 14707114294 ps
CPU time 17.41 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:35:47 PM PDT 24
Peak memory 215980 kb
Host smart-b8134187-ad69-41d3-a621-12578317d2be
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127735666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1127735666
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.735232393
Short name T2168
Test name
Test status
Simulation time 26433479775 ps
CPU time 35.79 seconds
Started Aug 18 05:35:33 PM PDT 24
Finished Aug 18 05:36:09 PM PDT 24
Peak memory 216020 kb
Host smart-22333c1d-3922-4394-93d1-1233855c7d55
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735232393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_ao
n_wake_resume.735232393
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.376251132
Short name T3007
Test name
Test status
Simulation time 178723344 ps
CPU time 0.88 seconds
Started Aug 18 05:35:43 PM PDT 24
Finished Aug 18 05:35:44 PM PDT 24
Peak memory 207464 kb
Host smart-ccc65943-44d2-4d30-bb70-771826750ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37625
1132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.376251132
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.4144334905
Short name T2678
Test name
Test status
Simulation time 151258141 ps
CPU time 0.87 seconds
Started Aug 18 05:35:37 PM PDT 24
Finished Aug 18 05:35:38 PM PDT 24
Peak memory 207532 kb
Host smart-4e2995e0-6556-408c-b45d-527ad8319451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41443
34905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.4144334905
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.2758743166
Short name T2473
Test name
Test status
Simulation time 457187561 ps
CPU time 1.55 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:33 PM PDT 24
Peak memory 207536 kb
Host smart-efa16231-e761-43a0-802a-58180fc8a0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27587
43166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.2758743166
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1145878374
Short name T1403
Test name
Test status
Simulation time 1101404628 ps
CPU time 3.02 seconds
Started Aug 18 05:35:34 PM PDT 24
Finished Aug 18 05:35:42 PM PDT 24
Peak memory 207652 kb
Host smart-fabe1595-5f2d-4c84-a195-6521516ef14b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1145878374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1145878374
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.573571456
Short name T1808
Test name
Test status
Simulation time 31960275340 ps
CPU time 55.55 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:36:26 PM PDT 24
Peak memory 207800 kb
Host smart-ce752392-a30c-4bf8-bcb6-5373aa657cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57357
1456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.573571456
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.2540339454
Short name T2525
Test name
Test status
Simulation time 217549356 ps
CPU time 1.02 seconds
Started Aug 18 05:35:29 PM PDT 24
Finished Aug 18 05:35:30 PM PDT 24
Peak memory 207560 kb
Host smart-aaf7666b-c521-4a65-b412-20a7db57d609
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540339454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.2540339454
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.2087209938
Short name T3013
Test name
Test status
Simulation time 500462039 ps
CPU time 1.48 seconds
Started Aug 18 05:35:30 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 207544 kb
Host smart-04e2f45b-7057-46cc-95db-ebd4cb6f8298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20872
09938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.2087209938
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.183567422
Short name T966
Test name
Test status
Simulation time 146426002 ps
CPU time 0.81 seconds
Started Aug 18 05:35:28 PM PDT 24
Finished Aug 18 05:35:29 PM PDT 24
Peak memory 207492 kb
Host smart-ba930bd5-fb7e-4e41-850a-b63a871f82d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18356
7422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.183567422
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1323877049
Short name T915
Test name
Test status
Simulation time 48975847 ps
CPU time 0.73 seconds
Started Aug 18 05:35:37 PM PDT 24
Finished Aug 18 05:35:38 PM PDT 24
Peak memory 207404 kb
Host smart-fde4eb51-94d2-4573-a43c-1be3548f438d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13238
77049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1323877049
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.772201198
Short name T3024
Test name
Test status
Simulation time 922832616 ps
CPU time 2.57 seconds
Started Aug 18 05:35:26 PM PDT 24
Finished Aug 18 05:35:29 PM PDT 24
Peak memory 207800 kb
Host smart-33145115-722f-410f-890b-6dc13a371f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77220
1198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.772201198
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_types.102097976
Short name T448
Test name
Test status
Simulation time 240552092 ps
CPU time 1.15 seconds
Started Aug 18 05:35:43 PM PDT 24
Finished Aug 18 05:35:44 PM PDT 24
Peak memory 207280 kb
Host smart-81d4c717-ed13-41b5-bc2a-038dc8e740a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=102097976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_types.102097976
Directory /workspace/25.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2502302523
Short name T838
Test name
Test status
Simulation time 302083158 ps
CPU time 2.09 seconds
Started Aug 18 05:35:35 PM PDT 24
Finished Aug 18 05:35:37 PM PDT 24
Peak memory 207676 kb
Host smart-560a844e-0ed9-4d41-a527-6c1c47afea72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25023
02523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2502302523
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.31930361
Short name T2991
Test name
Test status
Simulation time 168336432 ps
CPU time 0.98 seconds
Started Aug 18 05:35:37 PM PDT 24
Finished Aug 18 05:35:38 PM PDT 24
Peak memory 207516 kb
Host smart-a9c51e52-2640-4769-b512-98632b59a664
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=31930361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.31930361
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.96732288
Short name T1789
Test name
Test status
Simulation time 142418438 ps
CPU time 0.86 seconds
Started Aug 18 05:35:42 PM PDT 24
Finished Aug 18 05:35:43 PM PDT 24
Peak memory 207436 kb
Host smart-7e45f625-fc2a-4558-a4bc-a96a3867001b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96732
288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.96732288
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.763759661
Short name T2408
Test name
Test status
Simulation time 296223481 ps
CPU time 1.1 seconds
Started Aug 18 05:35:30 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 207500 kb
Host smart-1da7f6e2-b526-4e0c-9ced-94d886b7bd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76375
9661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.763759661
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.2522167322
Short name T1398
Test name
Test status
Simulation time 3176254811 ps
CPU time 31.82 seconds
Started Aug 18 05:35:36 PM PDT 24
Finished Aug 18 05:36:07 PM PDT 24
Peak memory 218432 kb
Host smart-27603499-f6bf-446d-abb6-d2849816f1d3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2522167322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.2522167322
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.529501494
Short name T3166
Test name
Test status
Simulation time 6995805356 ps
CPU time 82.48 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:36:54 PM PDT 24
Peak memory 207712 kb
Host smart-caac36d3-0bb1-436a-861d-cc83eebefc15
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=529501494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.529501494
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.2904493208
Short name T2020
Test name
Test status
Simulation time 249313401 ps
CPU time 0.99 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 207492 kb
Host smart-629a0523-86f4-4767-88a3-50cfd9794157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29044
93208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2904493208
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.1248471162
Short name T1852
Test name
Test status
Simulation time 28477284333 ps
CPU time 47.58 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:36:18 PM PDT 24
Peak memory 215988 kb
Host smart-7e79b30f-7d6c-4ec1-9362-141d70c5557a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12484
71162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.1248471162
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.2690014618
Short name T1238
Test name
Test status
Simulation time 11107062044 ps
CPU time 13.16 seconds
Started Aug 18 05:35:40 PM PDT 24
Finished Aug 18 05:35:53 PM PDT 24
Peak memory 207788 kb
Host smart-81a0dd27-9963-417d-8b32-c01df18131af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26900
14618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.2690014618
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.673096139
Short name T1481
Test name
Test status
Simulation time 4693321415 ps
CPU time 37.23 seconds
Started Aug 18 05:35:42 PM PDT 24
Finished Aug 18 05:36:20 PM PDT 24
Peak memory 215944 kb
Host smart-e03166b3-0eeb-4ae4-9c23-1c01a4a8af1c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=673096139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.673096139
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.2896715186
Short name T603
Test name
Test status
Simulation time 3153857170 ps
CPU time 23.19 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:54 PM PDT 24
Peak memory 217568 kb
Host smart-03d76092-92b4-4a32-8ba6-172473ef01aa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2896715186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.2896715186
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.2882854216
Short name T711
Test name
Test status
Simulation time 238683874 ps
CPU time 1.02 seconds
Started Aug 18 05:35:43 PM PDT 24
Finished Aug 18 05:35:44 PM PDT 24
Peak memory 207388 kb
Host smart-92e99c3f-84d1-4463-948f-24aa6cb40cf8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2882854216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2882854216
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2365763297
Short name T1837
Test name
Test status
Simulation time 196385543 ps
CPU time 0.96 seconds
Started Aug 18 05:35:37 PM PDT 24
Finished Aug 18 05:35:38 PM PDT 24
Peak memory 207504 kb
Host smart-27c6d60e-dd3d-4d74-9151-41ecfbd42678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23657
63297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2365763297
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.4174071769
Short name T758
Test name
Test status
Simulation time 4220111908 ps
CPU time 31.7 seconds
Started Aug 18 05:35:28 PM PDT 24
Finished Aug 18 05:36:00 PM PDT 24
Peak memory 217536 kb
Host smart-0f4961f2-6b17-4982-816c-c34d8972d63b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4174071769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.4174071769
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.1874023107
Short name T948
Test name
Test status
Simulation time 155079375 ps
CPU time 0.9 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 207408 kb
Host smart-556f3ca3-e052-4977-87a1-276d10754d29
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1874023107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.1874023107
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.605741340
Short name T547
Test name
Test status
Simulation time 142375291 ps
CPU time 0.88 seconds
Started Aug 18 05:35:30 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 207388 kb
Host smart-7945c5b0-4e48-42ef-b1de-3beb6939eb6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60574
1340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.605741340
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3406479320
Short name T151
Test name
Test status
Simulation time 220405421 ps
CPU time 0.97 seconds
Started Aug 18 05:35:37 PM PDT 24
Finished Aug 18 05:35:38 PM PDT 24
Peak memory 207508 kb
Host smart-efaa80e8-8e25-4f31-a971-45e56aca559a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34064
79320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3406479320
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.2432025185
Short name T856
Test name
Test status
Simulation time 227439361 ps
CPU time 0.99 seconds
Started Aug 18 05:35:32 PM PDT 24
Finished Aug 18 05:35:33 PM PDT 24
Peak memory 207508 kb
Host smart-46f7dd89-f13e-429a-bbad-31b5aea98883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24320
25185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.2432025185
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1785379655
Short name T3322
Test name
Test status
Simulation time 239063384 ps
CPU time 0.98 seconds
Started Aug 18 05:35:40 PM PDT 24
Finished Aug 18 05:35:41 PM PDT 24
Peak memory 207444 kb
Host smart-ded801a7-8085-4527-9cd0-7c2303e652d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17853
79655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1785379655
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.4039676651
Short name T2774
Test name
Test status
Simulation time 167241430 ps
CPU time 0.85 seconds
Started Aug 18 05:35:32 PM PDT 24
Finished Aug 18 05:35:33 PM PDT 24
Peak memory 207584 kb
Host smart-4ec13db0-edbb-4a2a-aa2f-4370f165d638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
76651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.4039676651
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2577438727
Short name T1290
Test name
Test status
Simulation time 150771171 ps
CPU time 0.86 seconds
Started Aug 18 05:35:46 PM PDT 24
Finished Aug 18 05:35:47 PM PDT 24
Peak memory 207580 kb
Host smart-b14d630c-01ff-4df0-9f30-cfc398992fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25774
38727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2577438727
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.1656449212
Short name T617
Test name
Test status
Simulation time 243472021 ps
CPU time 1.05 seconds
Started Aug 18 05:35:28 PM PDT 24
Finished Aug 18 05:35:29 PM PDT 24
Peak memory 207572 kb
Host smart-65bfe35f-5632-469a-a662-073b5e5adcc4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1656449212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.1656449212
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.210094653
Short name T2553
Test name
Test status
Simulation time 146891905 ps
CPU time 0.81 seconds
Started Aug 18 05:35:34 PM PDT 24
Finished Aug 18 05:35:35 PM PDT 24
Peak memory 207420 kb
Host smart-e592ffc7-16ce-48b0-a732-b7f84d50c270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21009
4653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.210094653
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.3044893622
Short name T2331
Test name
Test status
Simulation time 37790673 ps
CPU time 0.69 seconds
Started Aug 18 05:35:34 PM PDT 24
Finished Aug 18 05:35:35 PM PDT 24
Peak memory 207536 kb
Host smart-cb154852-375f-4b27-b222-51afe466d084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30448
93622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.3044893622
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2057739694
Short name T1497
Test name
Test status
Simulation time 14323319771 ps
CPU time 36.08 seconds
Started Aug 18 05:35:30 PM PDT 24
Finished Aug 18 05:36:06 PM PDT 24
Peak memory 215952 kb
Host smart-70ce56c7-d2ce-4f86-993f-2b4b169d9eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20577
39694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2057739694
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.889808858
Short name T751
Test name
Test status
Simulation time 195308964 ps
CPU time 0.96 seconds
Started Aug 18 05:35:30 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 207548 kb
Host smart-b2d1ccb2-483f-4e3f-9d4d-fad1c42adedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88980
8858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.889808858
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2096783163
Short name T1455
Test name
Test status
Simulation time 264841024 ps
CPU time 0.97 seconds
Started Aug 18 05:35:38 PM PDT 24
Finished Aug 18 05:35:40 PM PDT 24
Peak memory 207484 kb
Host smart-36918c50-d32d-46f5-a609-21f90806702a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20967
83163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2096783163
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.4000272720
Short name T1347
Test name
Test status
Simulation time 245145745 ps
CPU time 1.05 seconds
Started Aug 18 05:35:44 PM PDT 24
Finished Aug 18 05:35:46 PM PDT 24
Peak memory 207488 kb
Host smart-2f766c1c-5414-4341-a4fc-03237ff08714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40002
72720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.4000272720
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.1768373469
Short name T786
Test name
Test status
Simulation time 184654943 ps
CPU time 0.89 seconds
Started Aug 18 05:35:40 PM PDT 24
Finished Aug 18 05:35:41 PM PDT 24
Peak memory 207232 kb
Host smart-c76649d8-1e45-4c78-9f9c-68341e9209d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17683
73469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.1768373469
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.950849903
Short name T2457
Test name
Test status
Simulation time 131973226 ps
CPU time 0.87 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 207468 kb
Host smart-3ae816e5-c5b5-435e-8d03-170c9eea050b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95084
9903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.950849903
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_rx_full.1670621802
Short name T3151
Test name
Test status
Simulation time 248368134 ps
CPU time 1.06 seconds
Started Aug 18 05:35:36 PM PDT 24
Finished Aug 18 05:35:37 PM PDT 24
Peak memory 207424 kb
Host smart-a4443371-4ea4-4d79-8653-e9b89ca9470e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16706
21802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_full.1670621802
Directory /workspace/25.usbdev_rx_full/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.361259300
Short name T3596
Test name
Test status
Simulation time 154262055 ps
CPU time 0.87 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 207476 kb
Host smart-aa6ce069-331a-4dbc-8086-d1c7cc445c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36125
9300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.361259300
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3758878618
Short name T3457
Test name
Test status
Simulation time 150722484 ps
CPU time 0.92 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 207500 kb
Host smart-95bd9978-5cf6-419f-98de-a24f19896fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37588
78618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3758878618
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1976937144
Short name T3471
Test name
Test status
Simulation time 256685382 ps
CPU time 1.12 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:35:32 PM PDT 24
Peak memory 207496 kb
Host smart-fc3d9e8c-7a78-4a4b-b7e9-326a5323c362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19769
37144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1976937144
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.3010640798
Short name T3482
Test name
Test status
Simulation time 2282134084 ps
CPU time 23.44 seconds
Started Aug 18 05:35:44 PM PDT 24
Finished Aug 18 05:36:08 PM PDT 24
Peak memory 217548 kb
Host smart-1328180f-e8e1-48fe-9081-389e167d813f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3010640798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.3010640798
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3566390415
Short name T1838
Test name
Test status
Simulation time 200032349 ps
CPU time 0.91 seconds
Started Aug 18 05:35:43 PM PDT 24
Finished Aug 18 05:35:44 PM PDT 24
Peak memory 207468 kb
Host smart-019d0854-466e-40c9-b14f-6d4198d6b938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35663
90415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3566390415
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3704627264
Short name T3403
Test name
Test status
Simulation time 161434107 ps
CPU time 0.86 seconds
Started Aug 18 05:35:42 PM PDT 24
Finished Aug 18 05:35:43 PM PDT 24
Peak memory 207568 kb
Host smart-19fa0983-589f-4df9-bc01-9aa8ee086056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37046
27264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3704627264
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.4217701125
Short name T1367
Test name
Test status
Simulation time 1301018718 ps
CPU time 3.13 seconds
Started Aug 18 05:35:47 PM PDT 24
Finished Aug 18 05:35:50 PM PDT 24
Peak memory 207672 kb
Host smart-429402e0-e103-4221-98f7-97fd34bec61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42177
01125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.4217701125
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.285839186
Short name T2705
Test name
Test status
Simulation time 1903317913 ps
CPU time 14.1 seconds
Started Aug 18 05:35:38 PM PDT 24
Finished Aug 18 05:35:52 PM PDT 24
Peak memory 207724 kb
Host smart-00ad9506-c338-48c3-a80a-437b42b7eb06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28583
9186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.285839186
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.1686676039
Short name T2799
Test name
Test status
Simulation time 8393119723 ps
CPU time 54.77 seconds
Started Aug 18 05:35:31 PM PDT 24
Finished Aug 18 05:36:26 PM PDT 24
Peak memory 207732 kb
Host smart-1e0dc608-fdef-46fc-a939-7f18ce6e90bc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686676039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos
t_handshake.1686676039
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_tx_rx_disruption.2553218597
Short name T2675
Test name
Test status
Simulation time 526977756 ps
CPU time 1.64 seconds
Started Aug 18 05:35:45 PM PDT 24
Finished Aug 18 05:35:46 PM PDT 24
Peak memory 207584 kb
Host smart-b65f29dc-390a-457a-ae9d-5dcbc174e09b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553218597 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.usbdev_tx_rx_disruption.2553218597
Directory /workspace/25.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/250.usbdev_tx_rx_disruption.4058638299
Short name T1459
Test name
Test status
Simulation time 619422225 ps
CPU time 1.62 seconds
Started Aug 18 05:39:43 PM PDT 24
Finished Aug 18 05:39:45 PM PDT 24
Peak memory 207564 kb
Host smart-e3ba220e-ac0f-4f97-9faf-b66a37219b4f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058638299 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.usbdev_tx_rx_disruption.4058638299
Directory /workspace/250.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/251.usbdev_tx_rx_disruption.2927914231
Short name T600
Test name
Test status
Simulation time 588219993 ps
CPU time 1.78 seconds
Started Aug 18 05:39:53 PM PDT 24
Finished Aug 18 05:39:55 PM PDT 24
Peak memory 207732 kb
Host smart-552e891c-adbb-49a3-b61c-61b589c71ba5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927914231 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.usbdev_tx_rx_disruption.2927914231
Directory /workspace/251.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/252.usbdev_tx_rx_disruption.2851741957
Short name T1864
Test name
Test status
Simulation time 606455516 ps
CPU time 1.6 seconds
Started Aug 18 05:39:54 PM PDT 24
Finished Aug 18 05:39:56 PM PDT 24
Peak memory 207488 kb
Host smart-156ee163-b93b-4a27-8e33-49601b87969b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851741957 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 252.usbdev_tx_rx_disruption.2851741957
Directory /workspace/252.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/253.usbdev_tx_rx_disruption.176942265
Short name T2237
Test name
Test status
Simulation time 444304377 ps
CPU time 1.37 seconds
Started Aug 18 05:39:38 PM PDT 24
Finished Aug 18 05:39:40 PM PDT 24
Peak memory 207584 kb
Host smart-1cfc5216-41d7-4af1-b5c3-cf56a353d9d5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176942265 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 253.usbdev_tx_rx_disruption.176942265
Directory /workspace/253.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/254.usbdev_tx_rx_disruption.1676668247
Short name T2314
Test name
Test status
Simulation time 464991525 ps
CPU time 1.38 seconds
Started Aug 18 05:39:53 PM PDT 24
Finished Aug 18 05:39:54 PM PDT 24
Peak memory 207376 kb
Host smart-6ce0e497-747e-4b09-a4ea-4858d4ff58b0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676668247 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 254.usbdev_tx_rx_disruption.1676668247
Directory /workspace/254.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/255.usbdev_tx_rx_disruption.4002141230
Short name T1604
Test name
Test status
Simulation time 444464366 ps
CPU time 1.4 seconds
Started Aug 18 05:39:50 PM PDT 24
Finished Aug 18 05:39:52 PM PDT 24
Peak memory 207564 kb
Host smart-7a82945a-d828-4270-9f46-3fa16b24b1e0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002141230 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.usbdev_tx_rx_disruption.4002141230
Directory /workspace/255.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/256.usbdev_tx_rx_disruption.2588115393
Short name T2072
Test name
Test status
Simulation time 616098974 ps
CPU time 1.73 seconds
Started Aug 18 05:39:55 PM PDT 24
Finished Aug 18 05:39:57 PM PDT 24
Peak memory 207576 kb
Host smart-aeb23ab4-9adb-43d7-8773-29d1e3a54583
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588115393 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.usbdev_tx_rx_disruption.2588115393
Directory /workspace/256.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/257.usbdev_tx_rx_disruption.961822443
Short name T895
Test name
Test status
Simulation time 523132335 ps
CPU time 1.65 seconds
Started Aug 18 05:39:52 PM PDT 24
Finished Aug 18 05:39:54 PM PDT 24
Peak memory 207592 kb
Host smart-6f53c197-f1bb-47b2-b007-950eac24ad22
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961822443 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 257.usbdev_tx_rx_disruption.961822443
Directory /workspace/257.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/258.usbdev_tx_rx_disruption.758092315
Short name T2186
Test name
Test status
Simulation time 511796846 ps
CPU time 1.51 seconds
Started Aug 18 05:39:35 PM PDT 24
Finished Aug 18 05:39:37 PM PDT 24
Peak memory 207584 kb
Host smart-f38a4926-e938-4b98-89fc-7c8ed19977a1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758092315 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 258.usbdev_tx_rx_disruption.758092315
Directory /workspace/258.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/259.usbdev_tx_rx_disruption.979113446
Short name T1247
Test name
Test status
Simulation time 599778940 ps
CPU time 1.71 seconds
Started Aug 18 05:39:48 PM PDT 24
Finished Aug 18 05:39:50 PM PDT 24
Peak memory 207536 kb
Host smart-9bf97edf-59da-4799-bd5f-3aae3b30ee2f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979113446 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 259.usbdev_tx_rx_disruption.979113446
Directory /workspace/259.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.2706231803
Short name T2837
Test name
Test status
Simulation time 81675599 ps
CPU time 0.72 seconds
Started Aug 18 05:35:43 PM PDT 24
Finished Aug 18 05:35:44 PM PDT 24
Peak memory 207448 kb
Host smart-27b19ecf-82c9-4a7a-a9f9-4065184569f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2706231803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.2706231803
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.28319318
Short name T1863
Test name
Test status
Simulation time 10071966565 ps
CPU time 13.55 seconds
Started Aug 18 05:35:52 PM PDT 24
Finished Aug 18 05:36:05 PM PDT 24
Peak memory 207784 kb
Host smart-86990edb-e2a3-43b9-b451-2e2bae0e93e7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28319318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon
_wake_disconnect.28319318
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.562687729
Short name T2980
Test name
Test status
Simulation time 13882775224 ps
CPU time 18.08 seconds
Started Aug 18 05:35:41 PM PDT 24
Finished Aug 18 05:35:59 PM PDT 24
Peak memory 215996 kb
Host smart-420012e2-b324-4211-82fe-4850a5294bf0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=562687729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.562687729
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1072771550
Short name T2450
Test name
Test status
Simulation time 151602510 ps
CPU time 0.85 seconds
Started Aug 18 05:35:50 PM PDT 24
Finished Aug 18 05:35:51 PM PDT 24
Peak memory 207440 kb
Host smart-15fd15d6-405e-4a55-ab10-8045880f2df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10727
71550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1072771550
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1485327652
Short name T1197
Test name
Test status
Simulation time 162721429 ps
CPU time 0.85 seconds
Started Aug 18 05:35:54 PM PDT 24
Finished Aug 18 05:35:55 PM PDT 24
Peak memory 207488 kb
Host smart-a53e3895-b03b-497e-814e-13d590c07471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14853
27652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1485327652
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.822326910
Short name T745
Test name
Test status
Simulation time 177668614 ps
CPU time 0.89 seconds
Started Aug 18 05:35:51 PM PDT 24
Finished Aug 18 05:35:52 PM PDT 24
Peak memory 207516 kb
Host smart-906e6343-71bf-4d5c-8cb2-d4ac057bb2cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82232
6910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.822326910
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.4184283808
Short name T1666
Test name
Test status
Simulation time 478024075 ps
CPU time 1.41 seconds
Started Aug 18 05:35:52 PM PDT 24
Finished Aug 18 05:35:54 PM PDT 24
Peak memory 207516 kb
Host smart-b5ed86da-5b69-46b0-9919-790c16dd7074
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4184283808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.4184283808
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.1208851905
Short name T3500
Test name
Test status
Simulation time 37667397879 ps
CPU time 56.71 seconds
Started Aug 18 05:35:47 PM PDT 24
Finished Aug 18 05:36:44 PM PDT 24
Peak memory 207796 kb
Host smart-5d4ba1c9-613f-4c3c-b492-71e7588e6916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12088
51905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.1208851905
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.421517247
Short name T661
Test name
Test status
Simulation time 2884078226 ps
CPU time 19.21 seconds
Started Aug 18 05:35:55 PM PDT 24
Finished Aug 18 05:36:14 PM PDT 24
Peak memory 207824 kb
Host smart-111b0bde-35ab-4476-882f-22f0bc15b24e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421517247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.421517247
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3787545008
Short name T957
Test name
Test status
Simulation time 669089486 ps
CPU time 1.86 seconds
Started Aug 18 05:35:43 PM PDT 24
Finished Aug 18 05:35:45 PM PDT 24
Peak memory 207496 kb
Host smart-3f480bf9-bcfd-44d5-a402-95c471b583c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37875
45008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3787545008
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2937220069
Short name T1136
Test name
Test status
Simulation time 139861438 ps
CPU time 0.81 seconds
Started Aug 18 05:35:38 PM PDT 24
Finished Aug 18 05:35:39 PM PDT 24
Peak memory 207508 kb
Host smart-b6924302-d18f-4cc3-8d46-aed67f1fb6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29372
20069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2937220069
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.3949270697
Short name T653
Test name
Test status
Simulation time 46706946 ps
CPU time 0.68 seconds
Started Aug 18 05:35:50 PM PDT 24
Finished Aug 18 05:35:51 PM PDT 24
Peak memory 207440 kb
Host smart-41f4fa15-5d32-470b-bba8-58547f5d92ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39492
70697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3949270697
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.815239439
Short name T2248
Test name
Test status
Simulation time 816857006 ps
CPU time 2.34 seconds
Started Aug 18 05:35:45 PM PDT 24
Finished Aug 18 05:35:48 PM PDT 24
Peak memory 207724 kb
Host smart-986a49fd-e18b-45b4-81f8-d390e1ffb368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81523
9439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.815239439
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_types.3475323793
Short name T3368
Test name
Test status
Simulation time 497225640 ps
CPU time 1.32 seconds
Started Aug 18 05:35:53 PM PDT 24
Finished Aug 18 05:35:54 PM PDT 24
Peak memory 207480 kb
Host smart-933d4ff9-5b74-49b0-8bad-43169a0d441c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3475323793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_types.3475323793
Directory /workspace/26.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3399269550
Short name T2222
Test name
Test status
Simulation time 244831726 ps
CPU time 1.4 seconds
Started Aug 18 05:35:36 PM PDT 24
Finished Aug 18 05:35:38 PM PDT 24
Peak memory 207656 kb
Host smart-c70c82d3-25dd-41ae-b530-97956abdc6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33992
69550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3399269550
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1426483486
Short name T1541
Test name
Test status
Simulation time 165310932 ps
CPU time 0.97 seconds
Started Aug 18 05:36:05 PM PDT 24
Finished Aug 18 05:36:06 PM PDT 24
Peak memory 207504 kb
Host smart-b0effdbc-6fd3-4de5-a23f-21ef8b6ddac6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1426483486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1426483486
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2494661170
Short name T2368
Test name
Test status
Simulation time 142179107 ps
CPU time 0.82 seconds
Started Aug 18 05:35:46 PM PDT 24
Finished Aug 18 05:35:47 PM PDT 24
Peak memory 207416 kb
Host smart-f22f01cc-28b7-4144-8b90-3691b73f358c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24946
61170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2494661170
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2526533541
Short name T1992
Test name
Test status
Simulation time 171715987 ps
CPU time 0.86 seconds
Started Aug 18 05:35:51 PM PDT 24
Finished Aug 18 05:35:52 PM PDT 24
Peak memory 207508 kb
Host smart-d14ebda5-f7cd-46a1-afa0-beada12ee447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25265
33541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2526533541
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.3342563995
Short name T718
Test name
Test status
Simulation time 3648084389 ps
CPU time 27.09 seconds
Started Aug 18 05:35:42 PM PDT 24
Finished Aug 18 05:36:09 PM PDT 24
Peak memory 218440 kb
Host smart-53383070-f297-4d48-b3de-452f69896335
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3342563995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.3342563995
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.2318599937
Short name T1447
Test name
Test status
Simulation time 7835882746 ps
CPU time 52.54 seconds
Started Aug 18 05:35:42 PM PDT 24
Finished Aug 18 05:36:35 PM PDT 24
Peak memory 207764 kb
Host smart-76a68a3c-192c-40dc-b968-5a0043bc9cbe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2318599937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.2318599937
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1083377949
Short name T1277
Test name
Test status
Simulation time 213053883 ps
CPU time 0.94 seconds
Started Aug 18 05:35:48 PM PDT 24
Finished Aug 18 05:35:49 PM PDT 24
Peak memory 207584 kb
Host smart-b1c00ed0-3c72-48e7-a4b3-cd7cf270e4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10833
77949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1083377949
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.28722495
Short name T1435
Test name
Test status
Simulation time 27279916025 ps
CPU time 41.85 seconds
Started Aug 18 05:35:40 PM PDT 24
Finished Aug 18 05:36:21 PM PDT 24
Peak memory 207768 kb
Host smart-0bd92bee-2093-4570-9bbe-d735b5cf8bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28722
495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.28722495
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.638147074
Short name T3230
Test name
Test status
Simulation time 4270947271 ps
CPU time 6.31 seconds
Started Aug 18 05:35:44 PM PDT 24
Finished Aug 18 05:35:51 PM PDT 24
Peak memory 215956 kb
Host smart-26684996-924a-46d1-9b0c-52f7a1abe8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63814
7074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.638147074
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.3391421470
Short name T2633
Test name
Test status
Simulation time 4791223159 ps
CPU time 137.59 seconds
Started Aug 18 05:35:40 PM PDT 24
Finished Aug 18 05:37:57 PM PDT 24
Peak memory 218352 kb
Host smart-e40d5d86-6ac9-401c-9873-51fd3f5cf57c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3391421470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.3391421470
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.463979862
Short name T3404
Test name
Test status
Simulation time 1775565438 ps
CPU time 48.61 seconds
Started Aug 18 05:35:48 PM PDT 24
Finished Aug 18 05:36:36 PM PDT 24
Peak memory 215828 kb
Host smart-0def8059-7d1c-49a4-9c80-c995064f09b6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=463979862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.463979862
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.1853320790
Short name T2581
Test name
Test status
Simulation time 245651559 ps
CPU time 1 seconds
Started Aug 18 05:35:46 PM PDT 24
Finished Aug 18 05:35:47 PM PDT 24
Peak memory 207508 kb
Host smart-ca6b161d-a782-47e6-85b0-58156cc6620e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1853320790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.1853320790
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.4064618468
Short name T2111
Test name
Test status
Simulation time 202004431 ps
CPU time 0.92 seconds
Started Aug 18 05:36:03 PM PDT 24
Finished Aug 18 05:36:04 PM PDT 24
Peak memory 207436 kb
Host smart-6ff08327-43cc-4731-8ca5-439403da267f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40646
18468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.4064618468
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.361637667
Short name T2033
Test name
Test status
Simulation time 2375385516 ps
CPU time 22.35 seconds
Started Aug 18 05:35:41 PM PDT 24
Finished Aug 18 05:36:04 PM PDT 24
Peak memory 217772 kb
Host smart-ac35f052-d08c-42c0-ba97-2807ccc4a7c5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=361637667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.361637667
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.2316779895
Short name T739
Test name
Test status
Simulation time 152451919 ps
CPU time 0.86 seconds
Started Aug 18 05:35:48 PM PDT 24
Finished Aug 18 05:35:49 PM PDT 24
Peak memory 207460 kb
Host smart-86f882ec-ec20-43ef-add2-82a6cdd6fc37
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2316779895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.2316779895
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1329948342
Short name T2209
Test name
Test status
Simulation time 175157655 ps
CPU time 0.89 seconds
Started Aug 18 05:35:47 PM PDT 24
Finished Aug 18 05:35:48 PM PDT 24
Peak memory 207420 kb
Host smart-12aa6ee8-298c-4583-91a2-0353a8c5a728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13299
48342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1329948342
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.4279977264
Short name T3233
Test name
Test status
Simulation time 210539121 ps
CPU time 0.97 seconds
Started Aug 18 05:35:53 PM PDT 24
Finished Aug 18 05:35:54 PM PDT 24
Peak memory 207484 kb
Host smart-97b1c9a3-b2a3-4fc8-b590-31d666c90ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42799
77264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.4279977264
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.959656378
Short name T1423
Test name
Test status
Simulation time 165909585 ps
CPU time 0.87 seconds
Started Aug 18 05:35:49 PM PDT 24
Finished Aug 18 05:35:50 PM PDT 24
Peak memory 207504 kb
Host smart-386d3fbd-9394-42b0-83b3-6cf720212b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95965
6378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.959656378
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.119923217
Short name T1343
Test name
Test status
Simulation time 247417117 ps
CPU time 1.06 seconds
Started Aug 18 05:35:44 PM PDT 24
Finished Aug 18 05:35:45 PM PDT 24
Peak memory 207508 kb
Host smart-5b1e4c6c-e35d-4d26-8d1c-97d142b97b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11992
3217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.119923217
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.619647635
Short name T2329
Test name
Test status
Simulation time 197153585 ps
CPU time 0.88 seconds
Started Aug 18 05:35:46 PM PDT 24
Finished Aug 18 05:35:47 PM PDT 24
Peak memory 207568 kb
Host smart-f826d9a8-5fe9-47d3-b3c1-9e85e218ae42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61964
7635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.619647635
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.246242213
Short name T2143
Test name
Test status
Simulation time 169379797 ps
CPU time 0.85 seconds
Started Aug 18 05:35:38 PM PDT 24
Finished Aug 18 05:35:38 PM PDT 24
Peak memory 207488 kb
Host smart-f0dfa4ae-9a86-49f8-8a38-4e28321de956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24624
2213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.246242213
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.2881192469
Short name T3618
Test name
Test status
Simulation time 276638098 ps
CPU time 1.1 seconds
Started Aug 18 05:35:52 PM PDT 24
Finished Aug 18 05:35:53 PM PDT 24
Peak memory 207548 kb
Host smart-45cce146-5dfe-4485-896b-9799d5d482e3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2881192469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.2881192469
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.824857559
Short name T2839
Test name
Test status
Simulation time 149460062 ps
CPU time 0.83 seconds
Started Aug 18 05:35:38 PM PDT 24
Finished Aug 18 05:35:39 PM PDT 24
Peak memory 207464 kb
Host smart-8cd7d38e-c3b2-4f04-ada7-73125ec957c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82485
7559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.824857559
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.551568410
Short name T1092
Test name
Test status
Simulation time 57825965 ps
CPU time 0.77 seconds
Started Aug 18 05:35:43 PM PDT 24
Finished Aug 18 05:35:44 PM PDT 24
Peak memory 207480 kb
Host smart-7687762e-c8cb-4f4b-b099-d726ceda9282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55156
8410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.551568410
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.395728576
Short name T296
Test name
Test status
Simulation time 15894462072 ps
CPU time 41.44 seconds
Started Aug 18 05:35:45 PM PDT 24
Finished Aug 18 05:36:26 PM PDT 24
Peak memory 215960 kb
Host smart-068844cf-cba0-462e-bac8-008f2c322975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39572
8576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.395728576
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.139499335
Short name T2109
Test name
Test status
Simulation time 187982429 ps
CPU time 0.94 seconds
Started Aug 18 05:36:01 PM PDT 24
Finished Aug 18 05:36:02 PM PDT 24
Peak memory 207488 kb
Host smart-01d37ca0-10a7-421e-a276-4c75d37525c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13949
9335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.139499335
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.184433981
Short name T1017
Test name
Test status
Simulation time 228092662 ps
CPU time 0.98 seconds
Started Aug 18 05:35:42 PM PDT 24
Finished Aug 18 05:35:43 PM PDT 24
Peak memory 207464 kb
Host smart-e129d07f-f730-4379-a8cc-fa2ad12c4a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18443
3981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.184433981
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.3971890552
Short name T932
Test name
Test status
Simulation time 177503867 ps
CPU time 0.88 seconds
Started Aug 18 05:35:46 PM PDT 24
Finished Aug 18 05:35:47 PM PDT 24
Peak memory 207496 kb
Host smart-58655722-c4b7-44de-bd95-2c74c1176e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39718
90552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.3971890552
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.2982222635
Short name T1325
Test name
Test status
Simulation time 184209348 ps
CPU time 0.89 seconds
Started Aug 18 05:35:41 PM PDT 24
Finished Aug 18 05:35:42 PM PDT 24
Peak memory 207508 kb
Host smart-5b010251-2842-4581-a09c-69a9a84806db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29822
22635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.2982222635
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.4017760968
Short name T3076
Test name
Test status
Simulation time 204279196 ps
CPU time 0.92 seconds
Started Aug 18 05:35:45 PM PDT 24
Finished Aug 18 05:35:46 PM PDT 24
Peak memory 207492 kb
Host smart-871732ff-2da8-482a-8f19-dacb4d5147b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40177
60968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.4017760968
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_rx_full.949038744
Short name T3091
Test name
Test status
Simulation time 305817419 ps
CPU time 1.26 seconds
Started Aug 18 05:36:04 PM PDT 24
Finished Aug 18 05:36:06 PM PDT 24
Peak memory 207512 kb
Host smart-f86a6f3b-eeca-4fc2-97dc-96a32e575e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94903
8744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_full.949038744
Directory /workspace/26.usbdev_rx_full/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.218358952
Short name T683
Test name
Test status
Simulation time 154474897 ps
CPU time 0.86 seconds
Started Aug 18 05:35:52 PM PDT 24
Finished Aug 18 05:35:53 PM PDT 24
Peak memory 207472 kb
Host smart-49f5a295-d068-4561-8c08-6ef33b1bb784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21835
8952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.218358952
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1398957304
Short name T3372
Test name
Test status
Simulation time 148040319 ps
CPU time 0.85 seconds
Started Aug 18 05:35:49 PM PDT 24
Finished Aug 18 05:35:50 PM PDT 24
Peak memory 207408 kb
Host smart-f79c20ae-2f66-47b6-882b-9f363bd4959a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13989
57304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1398957304
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.185782637
Short name T1480
Test name
Test status
Simulation time 217490074 ps
CPU time 1 seconds
Started Aug 18 05:35:52 PM PDT 24
Finished Aug 18 05:35:53 PM PDT 24
Peak memory 207480 kb
Host smart-862a2315-4091-4d4f-b041-ad16add288b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18578
2637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.185782637
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.3109946817
Short name T628
Test name
Test status
Simulation time 2922628943 ps
CPU time 85.61 seconds
Started Aug 18 05:36:04 PM PDT 24
Finished Aug 18 05:37:29 PM PDT 24
Peak memory 215852 kb
Host smart-1bde9895-a0e1-4559-bb8f-486ce1dd0c02
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3109946817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.3109946817
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.527712340
Short name T2223
Test name
Test status
Simulation time 230421537 ps
CPU time 0.93 seconds
Started Aug 18 05:35:59 PM PDT 24
Finished Aug 18 05:36:00 PM PDT 24
Peak memory 207524 kb
Host smart-7365b7d1-ca22-4b65-99c2-bd6db59ad14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52771
2340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.527712340
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2505921119
Short name T3139
Test name
Test status
Simulation time 214326655 ps
CPU time 0.9 seconds
Started Aug 18 05:35:53 PM PDT 24
Finished Aug 18 05:35:54 PM PDT 24
Peak memory 207564 kb
Host smart-b3a84c7f-73cf-4b05-9c12-a10b22b6ae71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25059
21119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2505921119
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.986637147
Short name T3203
Test name
Test status
Simulation time 1204770704 ps
CPU time 2.8 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:36:27 PM PDT 24
Peak memory 207724 kb
Host smart-da787f1b-2f36-4c16-86f9-4f857aeb7115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98663
7147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.986637147
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.1446092072
Short name T3353
Test name
Test status
Simulation time 2846587689 ps
CPU time 22.32 seconds
Started Aug 18 05:36:02 PM PDT 24
Finished Aug 18 05:36:25 PM PDT 24
Peak memory 217708 kb
Host smart-c42c044b-7e91-49a9-80ab-7de1a75f52d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14460
92072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.1446092072
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.2445678836
Short name T2908
Test name
Test status
Simulation time 160679039 ps
CPU time 0.86 seconds
Started Aug 18 05:35:47 PM PDT 24
Finished Aug 18 05:35:48 PM PDT 24
Peak memory 207372 kb
Host smart-7f730fa9-cacf-46dd-8e5b-75ab8cb34f54
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445678836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.2445678836
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_tx_rx_disruption.196658729
Short name T1194
Test name
Test status
Simulation time 530367084 ps
CPU time 1.53 seconds
Started Aug 18 05:35:53 PM PDT 24
Finished Aug 18 05:35:55 PM PDT 24
Peak memory 207496 kb
Host smart-b41603a6-1b0d-4c1f-9e2d-e5ba5a20a45d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196658729 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.usbdev_tx_rx_disruption.196658729
Directory /workspace/26.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/260.usbdev_tx_rx_disruption.4238617742
Short name T1443
Test name
Test status
Simulation time 710897893 ps
CPU time 1.99 seconds
Started Aug 18 05:39:52 PM PDT 24
Finished Aug 18 05:39:54 PM PDT 24
Peak memory 207536 kb
Host smart-4c044fef-8ea9-456b-9886-f90a64be3be5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238617742 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 260.usbdev_tx_rx_disruption.4238617742
Directory /workspace/260.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/261.usbdev_tx_rx_disruption.3936285397
Short name T2703
Test name
Test status
Simulation time 465946023 ps
CPU time 1.49 seconds
Started Aug 18 05:40:01 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207456 kb
Host smart-5e056e7f-ace4-4f5e-b0e9-dca452b97de2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936285397 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.usbdev_tx_rx_disruption.3936285397
Directory /workspace/261.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/262.usbdev_tx_rx_disruption.2531299943
Short name T832
Test name
Test status
Simulation time 495367810 ps
CPU time 1.6 seconds
Started Aug 18 05:39:51 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207576 kb
Host smart-02db52e0-c551-4281-90aa-843bd92dd5a0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531299943 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.usbdev_tx_rx_disruption.2531299943
Directory /workspace/262.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/263.usbdev_tx_rx_disruption.3961934105
Short name T1226
Test name
Test status
Simulation time 644898646 ps
CPU time 1.65 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207536 kb
Host smart-ea6df665-3570-44a1-b678-d78033bac597
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961934105 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 263.usbdev_tx_rx_disruption.3961934105
Directory /workspace/263.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/264.usbdev_tx_rx_disruption.3102299049
Short name T1209
Test name
Test status
Simulation time 520961776 ps
CPU time 1.71 seconds
Started Aug 18 05:39:43 PM PDT 24
Finished Aug 18 05:39:45 PM PDT 24
Peak memory 207564 kb
Host smart-6b79505c-defa-4a0c-9387-8f2a79051c64
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102299049 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 264.usbdev_tx_rx_disruption.3102299049
Directory /workspace/264.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/265.usbdev_tx_rx_disruption.507867474
Short name T2748
Test name
Test status
Simulation time 529755855 ps
CPU time 1.44 seconds
Started Aug 18 05:39:50 PM PDT 24
Finished Aug 18 05:39:52 PM PDT 24
Peak memory 207508 kb
Host smart-3d310a9d-2e49-4fd6-89ce-78f132cc6293
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507867474 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 265.usbdev_tx_rx_disruption.507867474
Directory /workspace/265.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/266.usbdev_tx_rx_disruption.2118510223
Short name T1877
Test name
Test status
Simulation time 615485290 ps
CPU time 1.69 seconds
Started Aug 18 05:39:46 PM PDT 24
Finished Aug 18 05:39:48 PM PDT 24
Peak memory 207588 kb
Host smart-779ac011-57a9-4579-9498-3f814229e30d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118510223 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 266.usbdev_tx_rx_disruption.2118510223
Directory /workspace/266.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/267.usbdev_tx_rx_disruption.3604292904
Short name T2290
Test name
Test status
Simulation time 529351362 ps
CPU time 1.52 seconds
Started Aug 18 05:39:50 PM PDT 24
Finished Aug 18 05:39:52 PM PDT 24
Peak memory 207488 kb
Host smart-48db85dc-fd74-481c-a2a2-db11a28cacf9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604292904 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 267.usbdev_tx_rx_disruption.3604292904
Directory /workspace/267.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/268.usbdev_tx_rx_disruption.2418725128
Short name T1286
Test name
Test status
Simulation time 573950473 ps
CPU time 1.45 seconds
Started Aug 18 05:39:47 PM PDT 24
Finished Aug 18 05:39:49 PM PDT 24
Peak memory 207472 kb
Host smart-ab7a4c79-2544-4508-8956-6d662f341166
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418725128 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 268.usbdev_tx_rx_disruption.2418725128
Directory /workspace/268.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/269.usbdev_tx_rx_disruption.497249136
Short name T62
Test name
Test status
Simulation time 578111915 ps
CPU time 1.59 seconds
Started Aug 18 05:39:53 PM PDT 24
Finished Aug 18 05:39:55 PM PDT 24
Peak memory 207440 kb
Host smart-ee065e34-d714-437f-998c-fc1f1604e4d4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497249136 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 269.usbdev_tx_rx_disruption.497249136
Directory /workspace/269.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.542258859
Short name T1181
Test name
Test status
Simulation time 41949455 ps
CPU time 0.67 seconds
Started Aug 18 05:36:11 PM PDT 24
Finished Aug 18 05:36:12 PM PDT 24
Peak memory 207452 kb
Host smart-25ec8aa4-65e9-4439-b49c-228befc43ed2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=542258859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.542258859
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1944406983
Short name T851
Test name
Test status
Simulation time 10527637426 ps
CPU time 15.22 seconds
Started Aug 18 05:35:52 PM PDT 24
Finished Aug 18 05:36:12 PM PDT 24
Peak memory 207768 kb
Host smart-bec829cc-1dfa-4c73-87d9-43d06a632104
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944406983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.1944406983
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2577535027
Short name T15
Test name
Test status
Simulation time 14552452073 ps
CPU time 20.03 seconds
Started Aug 18 05:35:56 PM PDT 24
Finished Aug 18 05:36:16 PM PDT 24
Peak memory 215920 kb
Host smart-7e96d000-81fb-4b80-8dd6-c59c23521eba
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577535027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2577535027
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.577653013
Short name T2926
Test name
Test status
Simulation time 25577500651 ps
CPU time 32.06 seconds
Started Aug 18 05:35:58 PM PDT 24
Finished Aug 18 05:36:30 PM PDT 24
Peak memory 216004 kb
Host smart-a1ca876b-b518-4419-b6a5-074e97ee5884
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577653013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_ao
n_wake_resume.577653013
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2771548985
Short name T2256
Test name
Test status
Simulation time 162285630 ps
CPU time 0.92 seconds
Started Aug 18 05:36:05 PM PDT 24
Finished Aug 18 05:36:06 PM PDT 24
Peak memory 207388 kb
Host smart-71ca14b4-8a74-46ef-89a0-9f86a8116f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27715
48985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2771548985
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.376553
Short name T1243
Test name
Test status
Simulation time 169819655 ps
CPU time 0.84 seconds
Started Aug 18 05:35:52 PM PDT 24
Finished Aug 18 05:35:53 PM PDT 24
Peak memory 207496 kb
Host smart-4f23e3ce-c90e-496a-86b4-de336256e5ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37655
3 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.376553
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.1965378833
Short name T2059
Test name
Test status
Simulation time 337876432 ps
CPU time 1.38 seconds
Started Aug 18 05:35:47 PM PDT 24
Finished Aug 18 05:35:48 PM PDT 24
Peak memory 207560 kb
Host smart-71f67aba-bf80-42ea-bbe3-4119ed8c01dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19653
78833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.1965378833
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.557922449
Short name T3554
Test name
Test status
Simulation time 319731397 ps
CPU time 1.13 seconds
Started Aug 18 05:35:52 PM PDT 24
Finished Aug 18 05:35:58 PM PDT 24
Peak memory 207536 kb
Host smart-b447299e-770f-42e7-9521-86362f9f83ea
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=557922449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.557922449
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.1458194177
Short name T3400
Test name
Test status
Simulation time 1301374089 ps
CPU time 30.59 seconds
Started Aug 18 05:35:47 PM PDT 24
Finished Aug 18 05:36:18 PM PDT 24
Peak memory 207644 kb
Host smart-8f8c7e94-8b3a-4d67-b9fe-52c0bf50e663
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458194177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.1458194177
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.3085325763
Short name T3043
Test name
Test status
Simulation time 1098085015 ps
CPU time 2.23 seconds
Started Aug 18 05:36:01 PM PDT 24
Finished Aug 18 05:36:04 PM PDT 24
Peak memory 207460 kb
Host smart-dc733bef-d879-4d1d-99c1-63605649fc78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30853
25763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3085325763
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.818360907
Short name T2724
Test name
Test status
Simulation time 158227458 ps
CPU time 0.86 seconds
Started Aug 18 05:35:44 PM PDT 24
Finished Aug 18 05:35:45 PM PDT 24
Peak memory 207548 kb
Host smart-784fe441-bdd2-42bd-99e8-956f5fd5b407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81836
0907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.818360907
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2801240941
Short name T2903
Test name
Test status
Simulation time 91153151 ps
CPU time 0.76 seconds
Started Aug 18 05:36:02 PM PDT 24
Finished Aug 18 05:36:03 PM PDT 24
Peak memory 207464 kb
Host smart-7608c972-39a7-4117-95c4-25523db74d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28012
40941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2801240941
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3094801644
Short name T1387
Test name
Test status
Simulation time 794919519 ps
CPU time 2.23 seconds
Started Aug 18 05:35:50 PM PDT 24
Finished Aug 18 05:35:52 PM PDT 24
Peak memory 207500 kb
Host smart-3aa0bce6-4f54-44fb-89ea-67d105f1234f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30948
01644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3094801644
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_types.3596223460
Short name T381
Test name
Test status
Simulation time 550197134 ps
CPU time 1.49 seconds
Started Aug 18 05:35:49 PM PDT 24
Finished Aug 18 05:35:50 PM PDT 24
Peak memory 207456 kb
Host smart-6c0835b0-2609-4e82-b221-b609525a7326
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3596223460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_types.3596223460
Directory /workspace/27.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.700332653
Short name T229
Test name
Test status
Simulation time 309766203 ps
CPU time 2.5 seconds
Started Aug 18 05:35:48 PM PDT 24
Finished Aug 18 05:35:51 PM PDT 24
Peak memory 207668 kb
Host smart-0a228e1e-7fb2-432a-9f01-c65a55da4cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70033
2653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.700332653
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.368517294
Short name T1694
Test name
Test status
Simulation time 165914238 ps
CPU time 0.94 seconds
Started Aug 18 05:36:00 PM PDT 24
Finished Aug 18 05:36:01 PM PDT 24
Peak memory 207468 kb
Host smart-58c87063-b12e-45f3-86f1-8e3687f29086
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=368517294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.368517294
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2614789476
Short name T1205
Test name
Test status
Simulation time 175608641 ps
CPU time 0.86 seconds
Started Aug 18 05:36:14 PM PDT 24
Finished Aug 18 05:36:15 PM PDT 24
Peak memory 207408 kb
Host smart-e567ac60-bbc0-47c1-ad5f-b827200d53cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26147
89476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2614789476
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3869656898
Short name T2586
Test name
Test status
Simulation time 256147085 ps
CPU time 1.02 seconds
Started Aug 18 05:35:50 PM PDT 24
Finished Aug 18 05:35:51 PM PDT 24
Peak memory 207508 kb
Host smart-99fd2650-b7c5-421d-af8f-f4777c5a7b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38696
56898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3869656898
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.4277345434
Short name T3181
Test name
Test status
Simulation time 2669948189 ps
CPU time 74.08 seconds
Started Aug 18 05:35:55 PM PDT 24
Finished Aug 18 05:37:09 PM PDT 24
Peak memory 215956 kb
Host smart-860addba-269c-4748-a3f9-46dfc4361870
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4277345434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.4277345434
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.293576418
Short name T1802
Test name
Test status
Simulation time 5972689485 ps
CPU time 72.41 seconds
Started Aug 18 05:35:52 PM PDT 24
Finished Aug 18 05:37:04 PM PDT 24
Peak memory 207716 kb
Host smart-eb686fd3-3ff5-4943-82f7-2d9e30ae6d37
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=293576418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.293576418
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.4048469361
Short name T611
Test name
Test status
Simulation time 184550362 ps
CPU time 0.96 seconds
Started Aug 18 05:36:02 PM PDT 24
Finished Aug 18 05:36:03 PM PDT 24
Peak memory 207548 kb
Host smart-e9598968-5590-4980-b7e4-a81089579070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40484
69361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.4048469361
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.745879642
Short name T1620
Test name
Test status
Simulation time 23776443531 ps
CPU time 29.58 seconds
Started Aug 18 05:35:46 PM PDT 24
Finished Aug 18 05:36:16 PM PDT 24
Peak memory 215872 kb
Host smart-3838e879-de8c-48f5-9f47-5370dd88a955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74587
9642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.745879642
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.3375945980
Short name T1418
Test name
Test status
Simulation time 6133873766 ps
CPU time 8.28 seconds
Started Aug 18 05:36:18 PM PDT 24
Finished Aug 18 05:36:27 PM PDT 24
Peak memory 216036 kb
Host smart-afaaf8a0-bbfe-4ab2-91f6-7987a7217d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33759
45980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.3375945980
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.3688830755
Short name T135
Test name
Test status
Simulation time 4924478348 ps
CPU time 49.34 seconds
Started Aug 18 05:35:46 PM PDT 24
Finished Aug 18 05:36:36 PM PDT 24
Peak memory 219140 kb
Host smart-0ce1958d-1b7e-440a-ab91-ed00d0b4f6df
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3688830755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3688830755
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.4081803703
Short name T1029
Test name
Test status
Simulation time 3227671065 ps
CPU time 93.65 seconds
Started Aug 18 05:35:44 PM PDT 24
Finished Aug 18 05:37:18 PM PDT 24
Peak memory 217416 kb
Host smart-08fd458e-d6a3-4761-88d2-e534500e602e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4081803703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.4081803703
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1865932667
Short name T2905
Test name
Test status
Simulation time 250447369 ps
CPU time 0.97 seconds
Started Aug 18 05:35:48 PM PDT 24
Finished Aug 18 05:35:49 PM PDT 24
Peak memory 207424 kb
Host smart-f041d46d-be55-4708-bc2b-c55a8d0abbda
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1865932667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1865932667
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2396398667
Short name T1300
Test name
Test status
Simulation time 204252989 ps
CPU time 1 seconds
Started Aug 18 05:35:48 PM PDT 24
Finished Aug 18 05:35:49 PM PDT 24
Peak memory 207440 kb
Host smart-8bd76b53-9e66-45e0-96b4-a1d8daca3883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23963
98667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2396398667
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.402427839
Short name T3450
Test name
Test status
Simulation time 3914469989 ps
CPU time 109.88 seconds
Started Aug 18 05:35:50 PM PDT 24
Finished Aug 18 05:37:40 PM PDT 24
Peak memory 215908 kb
Host smart-1800d5fb-ad93-4d8a-93c0-b3c5e461b632
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=402427839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.402427839
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.694375349
Short name T2144
Test name
Test status
Simulation time 160101160 ps
CPU time 0.82 seconds
Started Aug 18 05:35:47 PM PDT 24
Finished Aug 18 05:35:48 PM PDT 24
Peak memory 207464 kb
Host smart-5393b5e9-95fe-4e71-8b46-928ed4262527
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=694375349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.694375349
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.419749042
Short name T2487
Test name
Test status
Simulation time 148705038 ps
CPU time 0.84 seconds
Started Aug 18 05:35:50 PM PDT 24
Finished Aug 18 05:35:51 PM PDT 24
Peak memory 207488 kb
Host smart-5e7f7f26-1179-4301-8d92-b1fb814907a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41974
9042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.419749042
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3441667448
Short name T159
Test name
Test status
Simulation time 229421386 ps
CPU time 1.05 seconds
Started Aug 18 05:35:55 PM PDT 24
Finished Aug 18 05:35:56 PM PDT 24
Peak memory 207528 kb
Host smart-5f72c9fd-8285-474a-80be-46f657907d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34416
67448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3441667448
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.886859965
Short name T589
Test name
Test status
Simulation time 169115832 ps
CPU time 0.9 seconds
Started Aug 18 05:35:51 PM PDT 24
Finished Aug 18 05:35:52 PM PDT 24
Peak memory 207468 kb
Host smart-a7350c71-7a75-4ec1-904b-279714671b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88685
9965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.886859965
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3991391341
Short name T2384
Test name
Test status
Simulation time 211936647 ps
CPU time 0.92 seconds
Started Aug 18 05:35:48 PM PDT 24
Finished Aug 18 05:35:49 PM PDT 24
Peak memory 207500 kb
Host smart-11954669-9662-4f03-baab-523226b68a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39913
91341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3991391341
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2550355020
Short name T3167
Test name
Test status
Simulation time 158507258 ps
CPU time 0.83 seconds
Started Aug 18 05:35:47 PM PDT 24
Finished Aug 18 05:35:48 PM PDT 24
Peak memory 207560 kb
Host smart-2e57d603-56b7-42ef-a248-64426961051b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25503
55020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2550355020
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3796390810
Short name T3287
Test name
Test status
Simulation time 151438701 ps
CPU time 0.83 seconds
Started Aug 18 05:35:46 PM PDT 24
Finished Aug 18 05:35:47 PM PDT 24
Peak memory 207552 kb
Host smart-6690e1d1-d8c7-4db9-b71a-b9e9d4c32781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37963
90810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3796390810
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.1528910003
Short name T2079
Test name
Test status
Simulation time 190706748 ps
CPU time 0.9 seconds
Started Aug 18 05:35:50 PM PDT 24
Finished Aug 18 05:35:51 PM PDT 24
Peak memory 207488 kb
Host smart-99b4a79a-9353-4a09-ac40-9d55e317d630
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1528910003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.1528910003
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1076034120
Short name T3298
Test name
Test status
Simulation time 143495298 ps
CPU time 0.83 seconds
Started Aug 18 05:35:56 PM PDT 24
Finished Aug 18 05:35:57 PM PDT 24
Peak memory 207448 kb
Host smart-3f37570b-464b-467c-81bd-014595099943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10760
34120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1076034120
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3937486831
Short name T2852
Test name
Test status
Simulation time 76806221 ps
CPU time 0.75 seconds
Started Aug 18 05:35:53 PM PDT 24
Finished Aug 18 05:35:54 PM PDT 24
Peak memory 207544 kb
Host smart-317a1e59-cbe0-4ff8-9c9e-732a7c09dd06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39374
86831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3937486831
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3230640033
Short name T2569
Test name
Test status
Simulation time 9475616235 ps
CPU time 24.22 seconds
Started Aug 18 05:35:59 PM PDT 24
Finished Aug 18 05:36:24 PM PDT 24
Peak memory 224136 kb
Host smart-018f31e2-4d2e-4507-a20e-3056bb505748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32306
40033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3230640033
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1960320820
Short name T2159
Test name
Test status
Simulation time 184092827 ps
CPU time 0.91 seconds
Started Aug 18 05:35:46 PM PDT 24
Finished Aug 18 05:35:47 PM PDT 24
Peak memory 207596 kb
Host smart-72a6c94d-c183-42ce-81b6-f235cbdc7e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19603
20820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1960320820
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3457324786
Short name T836
Test name
Test status
Simulation time 185818631 ps
CPU time 0.96 seconds
Started Aug 18 05:36:03 PM PDT 24
Finished Aug 18 05:36:04 PM PDT 24
Peak memory 207468 kb
Host smart-f6cee6a5-5912-452f-9f25-5d3e18fea5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34573
24786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3457324786
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.369557476
Short name T2249
Test name
Test status
Simulation time 194552759 ps
CPU time 0.93 seconds
Started Aug 18 05:35:54 PM PDT 24
Finished Aug 18 05:35:55 PM PDT 24
Peak memory 207468 kb
Host smart-15ee3ec6-9db6-47fe-9b92-530652845080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36955
7476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.369557476
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.2823698805
Short name T963
Test name
Test status
Simulation time 280324776 ps
CPU time 1.06 seconds
Started Aug 18 05:35:49 PM PDT 24
Finished Aug 18 05:35:50 PM PDT 24
Peak memory 207504 kb
Host smart-37b169ea-b22f-41c8-9669-41c8114fc8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28236
98805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.2823698805
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.2481406393
Short name T2955
Test name
Test status
Simulation time 155101815 ps
CPU time 0.79 seconds
Started Aug 18 05:35:59 PM PDT 24
Finished Aug 18 05:36:00 PM PDT 24
Peak memory 207432 kb
Host smart-34ed3e28-a296-470a-a423-c7358e1ec4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24814
06393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.2481406393
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_rx_full.3485801357
Short name T1593
Test name
Test status
Simulation time 349063783 ps
CPU time 1.26 seconds
Started Aug 18 05:35:56 PM PDT 24
Finished Aug 18 05:36:03 PM PDT 24
Peak memory 207480 kb
Host smart-11ec0f52-8d5c-4ad3-b52d-4c8c81e4ffbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34858
01357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_full.3485801357
Directory /workspace/27.usbdev_rx_full/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3839068537
Short name T3140
Test name
Test status
Simulation time 155925552 ps
CPU time 0.89 seconds
Started Aug 18 05:35:55 PM PDT 24
Finished Aug 18 05:35:56 PM PDT 24
Peak memory 207572 kb
Host smart-435cc45c-31e7-4116-899a-ca12452a5007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38390
68537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3839068537
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.546694043
Short name T133
Test name
Test status
Simulation time 180027321 ps
CPU time 0.94 seconds
Started Aug 18 05:36:18 PM PDT 24
Finished Aug 18 05:36:20 PM PDT 24
Peak memory 207712 kb
Host smart-a11dc0ac-ba5b-4784-a032-799cdc85d69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54669
4043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.546694043
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2769013139
Short name T1643
Test name
Test status
Simulation time 201900862 ps
CPU time 1.08 seconds
Started Aug 18 05:36:00 PM PDT 24
Finished Aug 18 05:36:01 PM PDT 24
Peak memory 207444 kb
Host smart-d5493c0e-b7d2-413a-a5c3-7ae74e9dbf9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27690
13139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2769013139
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.844856620
Short name T2238
Test name
Test status
Simulation time 2831359872 ps
CPU time 22.55 seconds
Started Aug 18 05:36:13 PM PDT 24
Finished Aug 18 05:36:36 PM PDT 24
Peak memory 217952 kb
Host smart-cd616c6b-1941-4744-af9f-08b45b5acc7a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=844856620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.844856620
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3806210501
Short name T2855
Test name
Test status
Simulation time 193350721 ps
CPU time 0.94 seconds
Started Aug 18 05:35:57 PM PDT 24
Finished Aug 18 05:35:58 PM PDT 24
Peak memory 207500 kb
Host smart-8d11c045-433c-4594-8a76-a3a08e8b4a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38062
10501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3806210501
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1330009236
Short name T2317
Test name
Test status
Simulation time 170615229 ps
CPU time 0.88 seconds
Started Aug 18 05:35:59 PM PDT 24
Finished Aug 18 05:36:00 PM PDT 24
Peak memory 207556 kb
Host smart-9fa2701a-8c74-4278-9f18-d28f0523b418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13300
09236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1330009236
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.3582620358
Short name T633
Test name
Test status
Simulation time 815115584 ps
CPU time 2.1 seconds
Started Aug 18 05:36:14 PM PDT 24
Finished Aug 18 05:36:16 PM PDT 24
Peak memory 207732 kb
Host smart-03a18615-a731-489c-b0c9-808231a5d5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35826
20358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.3582620358
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.4251393388
Short name T1811
Test name
Test status
Simulation time 2218405011 ps
CPU time 63.38 seconds
Started Aug 18 05:35:46 PM PDT 24
Finished Aug 18 05:36:50 PM PDT 24
Peak memory 217500 kb
Host smart-7cdadbc7-2d08-4ed2-9bef-4fde499a85e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42513
93388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.4251393388
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.3076777426
Short name T1762
Test name
Test status
Simulation time 1563733928 ps
CPU time 13.97 seconds
Started Aug 18 05:35:48 PM PDT 24
Finished Aug 18 05:36:02 PM PDT 24
Peak memory 207564 kb
Host smart-bc7c5d4b-8017-4dc9-8947-69d96aeb61c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076777426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.3076777426
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_tx_rx_disruption.2406685068
Short name T21
Test name
Test status
Simulation time 532724073 ps
CPU time 1.57 seconds
Started Aug 18 05:35:55 PM PDT 24
Finished Aug 18 05:35:56 PM PDT 24
Peak memory 207608 kb
Host smart-33f16ded-a521-44b6-84b8-616977484781
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406685068 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.usbdev_tx_rx_disruption.2406685068
Directory /workspace/27.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/270.usbdev_tx_rx_disruption.4138292841
Short name T3252
Test name
Test status
Simulation time 550858350 ps
CPU time 1.74 seconds
Started Aug 18 05:40:06 PM PDT 24
Finished Aug 18 05:40:13 PM PDT 24
Peak memory 207564 kb
Host smart-34a4039f-3e12-4c8a-8c55-f7d4bfed87a3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138292841 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 270.usbdev_tx_rx_disruption.4138292841
Directory /workspace/270.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/271.usbdev_tx_rx_disruption.2825309699
Short name T2757
Test name
Test status
Simulation time 564969822 ps
CPU time 1.7 seconds
Started Aug 18 05:40:05 PM PDT 24
Finished Aug 18 05:40:07 PM PDT 24
Peak memory 207552 kb
Host smart-e0e1f3a4-80a4-4814-94e7-96c5eeccb79e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825309699 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.usbdev_tx_rx_disruption.2825309699
Directory /workspace/271.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/272.usbdev_tx_rx_disruption.1221448933
Short name T2198
Test name
Test status
Simulation time 598755995 ps
CPU time 1.76 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207576 kb
Host smart-d4d5e2e4-c226-4dab-bdf4-2f92b7e38917
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221448933 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.usbdev_tx_rx_disruption.1221448933
Directory /workspace/272.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/273.usbdev_tx_rx_disruption.1913024029
Short name T1543
Test name
Test status
Simulation time 633669995 ps
CPU time 1.58 seconds
Started Aug 18 05:39:59 PM PDT 24
Finished Aug 18 05:40:01 PM PDT 24
Peak memory 207576 kb
Host smart-4ca5d38e-1291-4a34-976b-7970715ff4e7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913024029 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.usbdev_tx_rx_disruption.1913024029
Directory /workspace/273.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/274.usbdev_tx_rx_disruption.2025914175
Short name T1204
Test name
Test status
Simulation time 420438505 ps
CPU time 1.33 seconds
Started Aug 18 05:40:06 PM PDT 24
Finished Aug 18 05:40:08 PM PDT 24
Peak memory 207588 kb
Host smart-32977667-640c-4d4f-ad30-4ed7fbfc09ec
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025914175 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.usbdev_tx_rx_disruption.2025914175
Directory /workspace/274.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/275.usbdev_tx_rx_disruption.3540647987
Short name T1568
Test name
Test status
Simulation time 524239688 ps
CPU time 1.65 seconds
Started Aug 18 05:39:48 PM PDT 24
Finished Aug 18 05:39:50 PM PDT 24
Peak memory 207548 kb
Host smart-36dff625-4a34-4c8a-9325-50a1a086e085
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540647987 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 275.usbdev_tx_rx_disruption.3540647987
Directory /workspace/275.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/276.usbdev_tx_rx_disruption.394688439
Short name T3225
Test name
Test status
Simulation time 571287694 ps
CPU time 1.58 seconds
Started Aug 18 05:39:48 PM PDT 24
Finished Aug 18 05:39:49 PM PDT 24
Peak memory 207584 kb
Host smart-d127208f-66fa-4064-ac93-6ed85a4da016
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394688439 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 276.usbdev_tx_rx_disruption.394688439
Directory /workspace/276.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/277.usbdev_tx_rx_disruption.535015559
Short name T2179
Test name
Test status
Simulation time 519024408 ps
CPU time 1.72 seconds
Started Aug 18 05:39:48 PM PDT 24
Finished Aug 18 05:39:50 PM PDT 24
Peak memory 207496 kb
Host smart-51d7b9e5-d485-40af-b86b-737ee870db2e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535015559 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 277.usbdev_tx_rx_disruption.535015559
Directory /workspace/277.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/278.usbdev_tx_rx_disruption.69413686
Short name T584
Test name
Test status
Simulation time 481974847 ps
CPU time 1.54 seconds
Started Aug 18 05:39:59 PM PDT 24
Finished Aug 18 05:40:00 PM PDT 24
Peak memory 207532 kb
Host smart-e1de2a33-43e5-477c-8fcb-39da7e7c26d7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69413686 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 278.usbdev_tx_rx_disruption.69413686
Directory /workspace/278.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/279.usbdev_tx_rx_disruption.2315258149
Short name T565
Test name
Test status
Simulation time 537750909 ps
CPU time 1.64 seconds
Started Aug 18 05:39:51 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207512 kb
Host smart-a62bae50-9681-4f89-8fe9-96b4d3e2832d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315258149 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.usbdev_tx_rx_disruption.2315258149
Directory /workspace/279.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.344175471
Short name T2467
Test name
Test status
Simulation time 43077682 ps
CPU time 0.68 seconds
Started Aug 18 05:36:00 PM PDT 24
Finished Aug 18 05:36:01 PM PDT 24
Peak memory 207464 kb
Host smart-fd7ce5c4-77c3-42fa-ba6f-7d42055a7981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=344175471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.344175471
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.447846496
Short name T859
Test name
Test status
Simulation time 11414099807 ps
CPU time 14.31 seconds
Started Aug 18 05:36:07 PM PDT 24
Finished Aug 18 05:36:22 PM PDT 24
Peak memory 207740 kb
Host smart-24587651-5ff5-41b6-a81a-fcfa92213097
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447846496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_ao
n_wake_disconnect.447846496
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.773032259
Short name T3476
Test name
Test status
Simulation time 21363172312 ps
CPU time 24.55 seconds
Started Aug 18 05:35:54 PM PDT 24
Finished Aug 18 05:36:19 PM PDT 24
Peak memory 207804 kb
Host smart-0b635f53-e488-4e9e-98c0-19f7a671ba6b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=773032259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.773032259
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.914852752
Short name T3092
Test name
Test status
Simulation time 24909821043 ps
CPU time 30.92 seconds
Started Aug 18 05:36:01 PM PDT 24
Finished Aug 18 05:36:32 PM PDT 24
Peak memory 215980 kb
Host smart-bfdfbfd8-20a8-430d-a589-a37d51120e06
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914852752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_ao
n_wake_resume.914852752
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1308346548
Short name T1506
Test name
Test status
Simulation time 164243470 ps
CPU time 0.93 seconds
Started Aug 18 05:36:12 PM PDT 24
Finished Aug 18 05:36:14 PM PDT 24
Peak memory 207488 kb
Host smart-6f2802bc-bfd3-4a6f-8ebe-c9f8e47e9826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13083
46548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1308346548
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3460934866
Short name T3387
Test name
Test status
Simulation time 147630029 ps
CPU time 0.86 seconds
Started Aug 18 05:36:06 PM PDT 24
Finished Aug 18 05:36:07 PM PDT 24
Peak memory 207496 kb
Host smart-91d92f67-ae3c-420d-968a-800ff2374827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34609
34866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3460934866
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.984210406
Short name T3505
Test name
Test status
Simulation time 474617712 ps
CPU time 1.69 seconds
Started Aug 18 05:36:09 PM PDT 24
Finished Aug 18 05:36:11 PM PDT 24
Peak memory 207556 kb
Host smart-82e1e277-7365-4231-9c0c-0c534cdd9cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98421
0406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.984210406
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2350749253
Short name T3246
Test name
Test status
Simulation time 610815847 ps
CPU time 1.65 seconds
Started Aug 18 05:35:55 PM PDT 24
Finished Aug 18 05:35:57 PM PDT 24
Peak memory 207484 kb
Host smart-4c41a0fa-2a45-4c57-9cd5-506aa641a8d2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2350749253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2350749253
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.3694470057
Short name T1551
Test name
Test status
Simulation time 458774869 ps
CPU time 8 seconds
Started Aug 18 05:36:07 PM PDT 24
Finished Aug 18 05:36:15 PM PDT 24
Peak memory 207756 kb
Host smart-d7fe0109-10e0-44c1-8a60-3b155da24f9b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694470057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.3694470057
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.2974075354
Short name T3017
Test name
Test status
Simulation time 803321591 ps
CPU time 1.87 seconds
Started Aug 18 05:36:09 PM PDT 24
Finished Aug 18 05:36:11 PM PDT 24
Peak memory 207536 kb
Host smart-07440947-ff9a-4513-995b-6b66e20ed22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29740
75354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.2974075354
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.1388136357
Short name T2986
Test name
Test status
Simulation time 147185745 ps
CPU time 0.89 seconds
Started Aug 18 05:36:17 PM PDT 24
Finished Aug 18 05:36:18 PM PDT 24
Peak memory 207512 kb
Host smart-c13598d9-a2d7-4652-b0af-6c252b140e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13881
36357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1388136357
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.43537661
Short name T998
Test name
Test status
Simulation time 29473371 ps
CPU time 0.7 seconds
Started Aug 18 05:36:04 PM PDT 24
Finished Aug 18 05:36:05 PM PDT 24
Peak memory 207468 kb
Host smart-37c28b6b-3639-4250-a9fc-36d480e3f109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43537
661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.43537661
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.369440838
Short name T2444
Test name
Test status
Simulation time 849026327 ps
CPU time 2.15 seconds
Started Aug 18 05:36:15 PM PDT 24
Finished Aug 18 05:36:17 PM PDT 24
Peak memory 207752 kb
Host smart-d29089c5-e24e-43da-97e0-566b2dc9389e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36944
0838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.369440838
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_types.4277115512
Short name T426
Test name
Test status
Simulation time 351371098 ps
CPU time 1.19 seconds
Started Aug 18 05:36:15 PM PDT 24
Finished Aug 18 05:36:16 PM PDT 24
Peak memory 207540 kb
Host smart-5ee77d6b-6678-4f70-a45f-8e9b6b39bb27
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4277115512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_types.4277115512
Directory /workspace/28.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.604336559
Short name T637
Test name
Test status
Simulation time 459328389 ps
CPU time 2.98 seconds
Started Aug 18 05:36:18 PM PDT 24
Finished Aug 18 05:36:21 PM PDT 24
Peak memory 207664 kb
Host smart-b3dc06b9-c876-44e9-8c5f-82eef9b858e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60433
6559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.604336559
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.547398795
Short name T641
Test name
Test status
Simulation time 265766595 ps
CPU time 1.27 seconds
Started Aug 18 05:35:47 PM PDT 24
Finished Aug 18 05:35:48 PM PDT 24
Peak memory 215884 kb
Host smart-3245355d-4e0c-4963-9088-ef8e0901f736
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=547398795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.547398795
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.4077321555
Short name T1729
Test name
Test status
Simulation time 152212586 ps
CPU time 0.87 seconds
Started Aug 18 05:35:58 PM PDT 24
Finished Aug 18 05:35:59 PM PDT 24
Peak memory 207380 kb
Host smart-eb5979fd-7d03-43fb-813b-70fdc10dc022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40773
21555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.4077321555
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3587530517
Short name T1538
Test name
Test status
Simulation time 188169915 ps
CPU time 0.93 seconds
Started Aug 18 05:36:02 PM PDT 24
Finished Aug 18 05:36:03 PM PDT 24
Peak memory 207492 kb
Host smart-7171d9ba-6adb-4ba3-9dc8-720f52a88f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35875
30517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3587530517
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.3582946797
Short name T2366
Test name
Test status
Simulation time 2802782168 ps
CPU time 27.31 seconds
Started Aug 18 05:36:04 PM PDT 24
Finished Aug 18 05:36:32 PM PDT 24
Peak memory 217396 kb
Host smart-a22fa7a0-59d1-417e-b5cb-99c7c808eca0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3582946797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.3582946797
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.4018993569
Short name T1011
Test name
Test status
Simulation time 7210166809 ps
CPU time 91.16 seconds
Started Aug 18 05:36:04 PM PDT 24
Finished Aug 18 05:37:36 PM PDT 24
Peak memory 207776 kb
Host smart-43b37cc2-2372-4500-be99-91a6529d96ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4018993569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.4018993569
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.4045836808
Short name T2245
Test name
Test status
Simulation time 179590591 ps
CPU time 0.88 seconds
Started Aug 18 05:36:15 PM PDT 24
Finished Aug 18 05:36:16 PM PDT 24
Peak memory 207552 kb
Host smart-5577c191-7aee-40fd-9a43-6d9c89f8b971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40458
36808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.4045836808
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.2043381297
Short name T3453
Test name
Test status
Simulation time 10463692258 ps
CPU time 14.77 seconds
Started Aug 18 05:36:07 PM PDT 24
Finished Aug 18 05:36:21 PM PDT 24
Peak memory 207804 kb
Host smart-e4fb8f48-c8eb-4778-aac4-145e88cf53bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20433
81297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.2043381297
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.4164955919
Short name T1753
Test name
Test status
Simulation time 5351553579 ps
CPU time 6.76 seconds
Started Aug 18 05:36:07 PM PDT 24
Finished Aug 18 05:36:14 PM PDT 24
Peak memory 216836 kb
Host smart-2ce1c028-e3c0-4554-a830-a6000940d3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41649
55919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.4164955919
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.967167213
Short name T876
Test name
Test status
Simulation time 5709175778 ps
CPU time 158.12 seconds
Started Aug 18 05:36:12 PM PDT 24
Finished Aug 18 05:38:50 PM PDT 24
Peak memory 218492 kb
Host smart-8ef03980-2f00-4d3f-95e9-823bc3496113
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=967167213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.967167213
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3472977113
Short name T1003
Test name
Test status
Simulation time 2368447010 ps
CPU time 63.85 seconds
Started Aug 18 05:35:56 PM PDT 24
Finished Aug 18 05:37:00 PM PDT 24
Peak memory 215828 kb
Host smart-e3cfd2da-886b-4137-8502-fb6c08f8133b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3472977113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3472977113
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.757141016
Short name T1880
Test name
Test status
Simulation time 247925435 ps
CPU time 1.02 seconds
Started Aug 18 05:36:14 PM PDT 24
Finished Aug 18 05:36:15 PM PDT 24
Peak memory 207484 kb
Host smart-178b4d0a-c8f2-4456-857a-fc9dd1dac5ab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=757141016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.757141016
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.59377761
Short name T3056
Test name
Test status
Simulation time 199309632 ps
CPU time 0.98 seconds
Started Aug 18 05:35:57 PM PDT 24
Finished Aug 18 05:35:58 PM PDT 24
Peak memory 207460 kb
Host smart-98fc1639-6b00-4f1f-8cc0-7c51bb7da5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59377
761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.59377761
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.2507892045
Short name T977
Test name
Test status
Simulation time 3112597972 ps
CPU time 85.57 seconds
Started Aug 18 05:36:14 PM PDT 24
Finished Aug 18 05:37:39 PM PDT 24
Peak memory 217444 kb
Host smart-e33f5b51-3a15-4a8a-b691-ad71d3c131b0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2507892045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.2507892045
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.3072655566
Short name T3503
Test name
Test status
Simulation time 173093353 ps
CPU time 0.89 seconds
Started Aug 18 05:36:14 PM PDT 24
Finished Aug 18 05:36:15 PM PDT 24
Peak memory 207504 kb
Host smart-848182a2-ae90-4143-8e24-acf4def609de
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3072655566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.3072655566
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3815155727
Short name T1430
Test name
Test status
Simulation time 208617182 ps
CPU time 0.91 seconds
Started Aug 18 05:36:21 PM PDT 24
Finished Aug 18 05:36:23 PM PDT 24
Peak memory 207488 kb
Host smart-7ba42162-943c-4e30-bfd7-6e94fcc3903b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38151
55727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3815155727
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.4249206961
Short name T1168
Test name
Test status
Simulation time 176584853 ps
CPU time 0.91 seconds
Started Aug 18 05:36:12 PM PDT 24
Finished Aug 18 05:36:13 PM PDT 24
Peak memory 207500 kb
Host smart-91bf7aef-0e5b-4850-99e0-8ccdf5129393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42492
06961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.4249206961
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3600416343
Short name T730
Test name
Test status
Simulation time 167965521 ps
CPU time 0.85 seconds
Started Aug 18 05:36:01 PM PDT 24
Finished Aug 18 05:36:02 PM PDT 24
Peak memory 207448 kb
Host smart-aa6aa16e-1386-497b-b89b-8de2b57718be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36004
16343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3600416343
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.730341707
Short name T1027
Test name
Test status
Simulation time 205275501 ps
CPU time 0.9 seconds
Started Aug 18 05:36:03 PM PDT 24
Finished Aug 18 05:36:04 PM PDT 24
Peak memory 207564 kb
Host smart-8de4868a-562c-4309-94b2-059264bd06e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73034
1707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.730341707
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1741722125
Short name T203
Test name
Test status
Simulation time 142298413 ps
CPU time 0.82 seconds
Started Aug 18 05:36:15 PM PDT 24
Finished Aug 18 05:36:16 PM PDT 24
Peak memory 207536 kb
Host smart-c1fd7869-b68f-4bf9-9e5a-cf298d049825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17417
22125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1741722125
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3352102364
Short name T3073
Test name
Test status
Simulation time 252243735 ps
CPU time 1.06 seconds
Started Aug 18 05:35:50 PM PDT 24
Finished Aug 18 05:35:51 PM PDT 24
Peak memory 207488 kb
Host smart-7b7696de-5b0a-4dfa-828f-179668f6d855
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3352102364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3352102364
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2968070325
Short name T2917
Test name
Test status
Simulation time 140951889 ps
CPU time 0.86 seconds
Started Aug 18 05:36:07 PM PDT 24
Finished Aug 18 05:36:08 PM PDT 24
Peak memory 207448 kb
Host smart-4e90f999-5230-4f2b-8c4f-926937bf5648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29680
70325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2968070325
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2326405473
Short name T2969
Test name
Test status
Simulation time 60814125 ps
CPU time 0.74 seconds
Started Aug 18 05:36:16 PM PDT 24
Finished Aug 18 05:36:17 PM PDT 24
Peak memory 207524 kb
Host smart-fc10a97d-1b97-42b5-8db1-5adb94ebe6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23264
05473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2326405473
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3014957231
Short name T3629
Test name
Test status
Simulation time 11033862586 ps
CPU time 29.26 seconds
Started Aug 18 05:36:08 PM PDT 24
Finished Aug 18 05:36:37 PM PDT 24
Peak memory 215992 kb
Host smart-fea4f2d7-08f3-4458-9869-6adc7cfaa463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30149
57231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3014957231
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2834655748
Short name T2636
Test name
Test status
Simulation time 168154324 ps
CPU time 0.95 seconds
Started Aug 18 05:36:17 PM PDT 24
Finished Aug 18 05:36:18 PM PDT 24
Peak memory 207444 kb
Host smart-860389bd-d062-49ae-b996-8f19da2635b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28346
55748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2834655748
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3850150184
Short name T2334
Test name
Test status
Simulation time 204587898 ps
CPU time 0.95 seconds
Started Aug 18 05:35:51 PM PDT 24
Finished Aug 18 05:36:03 PM PDT 24
Peak memory 207424 kb
Host smart-99fdc406-5a1d-48a4-b157-b7ab5a5ec21b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38501
50184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3850150184
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.3492435351
Short name T2170
Test name
Test status
Simulation time 220989950 ps
CPU time 0.99 seconds
Started Aug 18 05:36:17 PM PDT 24
Finished Aug 18 05:36:18 PM PDT 24
Peak memory 207480 kb
Host smart-b98895d4-78a3-473b-8f9d-ebd7d9cf7f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34924
35351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.3492435351
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3594200046
Short name T784
Test name
Test status
Simulation time 232457322 ps
CPU time 0.93 seconds
Started Aug 18 05:36:12 PM PDT 24
Finished Aug 18 05:36:13 PM PDT 24
Peak memory 207492 kb
Host smart-42448548-60cd-4144-ae90-ce96863a531c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35942
00046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3594200046
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3521684396
Short name T68
Test name
Test status
Simulation time 162228419 ps
CPU time 0.82 seconds
Started Aug 18 05:36:02 PM PDT 24
Finished Aug 18 05:36:03 PM PDT 24
Peak memory 207500 kb
Host smart-0884abab-7a07-4570-b765-f5b58712eea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35216
84396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3521684396
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_rx_full.3611927496
Short name T1363
Test name
Test status
Simulation time 275384724 ps
CPU time 1.11 seconds
Started Aug 18 05:36:13 PM PDT 24
Finished Aug 18 05:36:14 PM PDT 24
Peak memory 207484 kb
Host smart-fce406f6-3185-4617-b23c-fd7a42bc943a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36119
27496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_full.3611927496
Directory /workspace/28.usbdev_rx_full/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1457811750
Short name T889
Test name
Test status
Simulation time 150322101 ps
CPU time 0.85 seconds
Started Aug 18 05:36:16 PM PDT 24
Finished Aug 18 05:36:17 PM PDT 24
Peak memory 207524 kb
Host smart-acdf784f-3435-4a9d-a41f-97f92b3315e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14578
11750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1457811750
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3035748123
Short name T3207
Test name
Test status
Simulation time 161165091 ps
CPU time 0.88 seconds
Started Aug 18 05:36:05 PM PDT 24
Finished Aug 18 05:36:06 PM PDT 24
Peak memory 207488 kb
Host smart-7a0cf74f-6573-4005-bb6e-b6557b760561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30357
48123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3035748123
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2538151341
Short name T1788
Test name
Test status
Simulation time 199070117 ps
CPU time 0.97 seconds
Started Aug 18 05:36:10 PM PDT 24
Finished Aug 18 05:36:11 PM PDT 24
Peak memory 207488 kb
Host smart-9c11f22a-4946-4794-aef6-a58858393dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25381
51341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2538151341
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.249633078
Short name T2528
Test name
Test status
Simulation time 1678177833 ps
CPU time 46.88 seconds
Started Aug 18 05:36:07 PM PDT 24
Finished Aug 18 05:36:54 PM PDT 24
Peak memory 224008 kb
Host smart-b370f05b-77fc-4c8f-a67f-112a4844bb18
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=249633078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.249633078
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2608002923
Short name T735
Test name
Test status
Simulation time 191391585 ps
CPU time 0.95 seconds
Started Aug 18 05:36:04 PM PDT 24
Finished Aug 18 05:36:05 PM PDT 24
Peak memory 207500 kb
Host smart-8ce37174-3021-4db0-87f8-09b01c439b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26080
02923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2608002923
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.668671808
Short name T3179
Test name
Test status
Simulation time 158614923 ps
CPU time 0.87 seconds
Started Aug 18 05:35:49 PM PDT 24
Finished Aug 18 05:35:50 PM PDT 24
Peak memory 207476 kb
Host smart-4df1ca40-6760-4d6f-befe-0abcae26457e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66867
1808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.668671808
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.4127443450
Short name T1473
Test name
Test status
Simulation time 569638657 ps
CPU time 1.75 seconds
Started Aug 18 05:36:17 PM PDT 24
Finished Aug 18 05:36:19 PM PDT 24
Peak memory 207536 kb
Host smart-50bae7f9-b532-4c65-8bea-fc32c62798a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41274
43450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.4127443450
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.1899784062
Short name T1361
Test name
Test status
Simulation time 1678187411 ps
CPU time 46.34 seconds
Started Aug 18 05:36:08 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 215928 kb
Host smart-1426e52c-3355-4714-9a84-c49866d32520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18997
84062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.1899784062
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.2952384240
Short name T3178
Test name
Test status
Simulation time 497838813 ps
CPU time 8.45 seconds
Started Aug 18 05:35:54 PM PDT 24
Finished Aug 18 05:36:03 PM PDT 24
Peak memory 207664 kb
Host smart-937a950f-015e-426e-ada9-e68830db2597
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952384240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.2952384240
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_tx_rx_disruption.3994639252
Short name T2493
Test name
Test status
Simulation time 495429837 ps
CPU time 1.53 seconds
Started Aug 18 05:36:11 PM PDT 24
Finished Aug 18 05:36:13 PM PDT 24
Peak memory 207564 kb
Host smart-eaec1805-d9db-4984-a026-4b2e6cb9e11f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994639252 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.usbdev_tx_rx_disruption.3994639252
Directory /workspace/28.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/280.usbdev_tx_rx_disruption.3614885065
Short name T1958
Test name
Test status
Simulation time 492215885 ps
CPU time 1.64 seconds
Started Aug 18 05:39:57 PM PDT 24
Finished Aug 18 05:39:59 PM PDT 24
Peak memory 207516 kb
Host smart-eb820d40-d186-4d2d-85c2-9a3da322afdc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614885065 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 280.usbdev_tx_rx_disruption.3614885065
Directory /workspace/280.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/281.usbdev_tx_rx_disruption.3332288446
Short name T2580
Test name
Test status
Simulation time 477664756 ps
CPU time 1.44 seconds
Started Aug 18 05:40:03 PM PDT 24
Finished Aug 18 05:40:05 PM PDT 24
Peak memory 207508 kb
Host smart-45cf7f9b-e2ce-4fa9-a640-bcf67b61011f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332288446 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 281.usbdev_tx_rx_disruption.3332288446
Directory /workspace/281.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/282.usbdev_tx_rx_disruption.3986725978
Short name T2726
Test name
Test status
Simulation time 398893467 ps
CPU time 1.33 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:01 PM PDT 24
Peak memory 207532 kb
Host smart-7b15437d-c3ee-4a5b-9b4f-9e4282f72aef
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986725978 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 282.usbdev_tx_rx_disruption.3986725978
Directory /workspace/282.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/283.usbdev_tx_rx_disruption.1350732483
Short name T888
Test name
Test status
Simulation time 464933854 ps
CPU time 1.45 seconds
Started Aug 18 05:39:53 PM PDT 24
Finished Aug 18 05:39:55 PM PDT 24
Peak memory 207568 kb
Host smart-9c615c25-22ca-4c3f-a649-81f71509cf4d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350732483 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 283.usbdev_tx_rx_disruption.1350732483
Directory /workspace/283.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/284.usbdev_tx_rx_disruption.2014820100
Short name T626
Test name
Test status
Simulation time 519413318 ps
CPU time 1.65 seconds
Started Aug 18 05:39:51 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207732 kb
Host smart-424e26ea-3a48-4fb2-ac30-f7169440fbdc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014820100 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 284.usbdev_tx_rx_disruption.2014820100
Directory /workspace/284.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/285.usbdev_tx_rx_disruption.585774664
Short name T2180
Test name
Test status
Simulation time 480905015 ps
CPU time 1.48 seconds
Started Aug 18 05:40:02 PM PDT 24
Finished Aug 18 05:40:03 PM PDT 24
Peak memory 207532 kb
Host smart-5a3da999-53dd-43e9-a8bd-2532a2ba5ba5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585774664 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 285.usbdev_tx_rx_disruption.585774664
Directory /workspace/285.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/286.usbdev_tx_rx_disruption.2334379434
Short name T3256
Test name
Test status
Simulation time 448378078 ps
CPU time 1.41 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207584 kb
Host smart-28cb9da6-5c6a-425f-a6c2-4f45bef5e6b9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334379434 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 286.usbdev_tx_rx_disruption.2334379434
Directory /workspace/286.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/287.usbdev_tx_rx_disruption.1163599992
Short name T1333
Test name
Test status
Simulation time 644197237 ps
CPU time 1.72 seconds
Started Aug 18 05:39:57 PM PDT 24
Finished Aug 18 05:39:58 PM PDT 24
Peak memory 207508 kb
Host smart-dfedcd40-4eb6-441c-8448-f29ef6e82961
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163599992 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.usbdev_tx_rx_disruption.1163599992
Directory /workspace/287.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/288.usbdev_tx_rx_disruption.3466276421
Short name T697
Test name
Test status
Simulation time 499622382 ps
CPU time 1.56 seconds
Started Aug 18 05:39:52 PM PDT 24
Finished Aug 18 05:39:54 PM PDT 24
Peak memory 207480 kb
Host smart-7cc9ce77-7f7c-496c-a90d-aca38b8b45ac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466276421 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 288.usbdev_tx_rx_disruption.3466276421
Directory /workspace/288.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/289.usbdev_tx_rx_disruption.575528138
Short name T2929
Test name
Test status
Simulation time 475440924 ps
CPU time 1.58 seconds
Started Aug 18 05:40:02 PM PDT 24
Finished Aug 18 05:40:03 PM PDT 24
Peak memory 207552 kb
Host smart-559652d7-0f04-443c-b3c0-6610b0d4bd1d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575528138 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 289.usbdev_tx_rx_disruption.575528138
Directory /workspace/289.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.2896296934
Short name T3542
Test name
Test status
Simulation time 88565578 ps
CPU time 0.69 seconds
Started Aug 18 05:36:18 PM PDT 24
Finished Aug 18 05:36:19 PM PDT 24
Peak memory 207400 kb
Host smart-c24aa16e-9891-4601-a60f-6cdd188511eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2896296934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.2896296934
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.3679160523
Short name T2861
Test name
Test status
Simulation time 9516193827 ps
CPU time 15.15 seconds
Started Aug 18 05:36:10 PM PDT 24
Finished Aug 18 05:36:25 PM PDT 24
Peak memory 207824 kb
Host smart-a8cb3836-803a-4835-8711-051c3c3dd72c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679160523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_disconnect.3679160523
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.759463767
Short name T12
Test name
Test status
Simulation time 13837076704 ps
CPU time 15.02 seconds
Started Aug 18 05:36:07 PM PDT 24
Finished Aug 18 05:36:22 PM PDT 24
Peak memory 215896 kb
Host smart-7dce19a6-f58a-4abf-95ed-ba0fea3e6c66
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=759463767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.759463767
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.1415921147
Short name T2652
Test name
Test status
Simulation time 25285869701 ps
CPU time 28.57 seconds
Started Aug 18 05:36:10 PM PDT 24
Finished Aug 18 05:36:38 PM PDT 24
Peak memory 215884 kb
Host smart-8a3b3dd0-cc0a-40d5-83e5-2cd26478366b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415921147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_resume.1415921147
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3422352503
Short name T650
Test name
Test status
Simulation time 151687775 ps
CPU time 0.84 seconds
Started Aug 18 05:36:04 PM PDT 24
Finished Aug 18 05:36:05 PM PDT 24
Peak memory 207476 kb
Host smart-5701fb60-1c99-4e24-baad-bccce5e3165d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34223
52503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3422352503
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.1861363135
Short name T768
Test name
Test status
Simulation time 165724842 ps
CPU time 0.89 seconds
Started Aug 18 05:36:05 PM PDT 24
Finished Aug 18 05:36:06 PM PDT 24
Peak memory 207444 kb
Host smart-d39b254f-c6e1-4566-9837-474c98ea8ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18613
63135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1861363135
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.1383376466
Short name T3228
Test name
Test status
Simulation time 387581773 ps
CPU time 1.46 seconds
Started Aug 18 05:36:01 PM PDT 24
Finished Aug 18 05:36:03 PM PDT 24
Peak memory 207568 kb
Host smart-101c4b41-2faf-47b3-8f88-e51cc6d9ebb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13833
76466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.1383376466
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2417178950
Short name T1504
Test name
Test status
Simulation time 445053424 ps
CPU time 1.38 seconds
Started Aug 18 05:36:18 PM PDT 24
Finished Aug 18 05:36:19 PM PDT 24
Peak memory 207464 kb
Host smart-bb7c4531-6025-4aaa-bbbb-272f6be92a43
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2417178950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2417178950
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.2780093256
Short name T3564
Test name
Test status
Simulation time 17649200710 ps
CPU time 29.54 seconds
Started Aug 18 05:36:08 PM PDT 24
Finished Aug 18 05:36:38 PM PDT 24
Peak memory 207804 kb
Host smart-41ba72c2-b2fa-46ac-a299-32c4b7e3721d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27800
93256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.2780093256
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.15570760
Short name T2655
Test name
Test status
Simulation time 1324131678 ps
CPU time 29.14 seconds
Started Aug 18 05:36:15 PM PDT 24
Finished Aug 18 05:36:44 PM PDT 24
Peak memory 207760 kb
Host smart-1b4e8be7-9529-4c34-ba36-1f794af4cf86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15570760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.15570760
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.3283559054
Short name T2850
Test name
Test status
Simulation time 771978522 ps
CPU time 1.79 seconds
Started Aug 18 05:36:15 PM PDT 24
Finished Aug 18 05:36:17 PM PDT 24
Peak memory 207528 kb
Host smart-66a4cf57-0d94-4490-8bb3-b4e92bd3d22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32835
59054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.3283559054
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.2884739638
Short name T1840
Test name
Test status
Simulation time 144933028 ps
CPU time 0.82 seconds
Started Aug 18 05:36:14 PM PDT 24
Finished Aug 18 05:36:15 PM PDT 24
Peak memory 207480 kb
Host smart-8d1d65a5-f82e-46e4-8bd2-28868fc8c0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28847
39638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2884739638
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.2719637635
Short name T602
Test name
Test status
Simulation time 43689063 ps
CPU time 0.72 seconds
Started Aug 18 05:36:20 PM PDT 24
Finished Aug 18 05:36:21 PM PDT 24
Peak memory 207388 kb
Host smart-26ffa7fb-59b3-4c56-bcb7-f5178d3f8950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27196
37635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2719637635
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.1089597811
Short name T281
Test name
Test status
Simulation time 1006417224 ps
CPU time 2.29 seconds
Started Aug 18 05:36:16 PM PDT 24
Finished Aug 18 05:36:18 PM PDT 24
Peak memory 207768 kb
Host smart-66d40574-a635-462e-a470-b4fbba0f259d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10895
97811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.1089597811
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_types.284756666
Short name T469
Test name
Test status
Simulation time 202722096 ps
CPU time 0.95 seconds
Started Aug 18 05:36:17 PM PDT 24
Finished Aug 18 05:36:18 PM PDT 24
Peak memory 207504 kb
Host smart-04f1b74c-1980-4ea6-92ee-d8cefdbdb01b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=284756666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_types.284756666
Directory /workspace/29.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.746353147
Short name T1153
Test name
Test status
Simulation time 251946012 ps
CPU time 1.72 seconds
Started Aug 18 05:36:16 PM PDT 24
Finished Aug 18 05:36:28 PM PDT 24
Peak memory 207608 kb
Host smart-fa6e97fc-876a-4f32-be75-4aad80df4eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74635
3147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.746353147
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3547173372
Short name T984
Test name
Test status
Simulation time 210280172 ps
CPU time 1.19 seconds
Started Aug 18 05:36:16 PM PDT 24
Finished Aug 18 05:36:17 PM PDT 24
Peak memory 215912 kb
Host smart-7a1b74a1-c64c-4c99-a4c3-6be56c4999b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3547173372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3547173372
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3829137079
Short name T1832
Test name
Test status
Simulation time 165230573 ps
CPU time 0.89 seconds
Started Aug 18 05:36:20 PM PDT 24
Finished Aug 18 05:36:21 PM PDT 24
Peak memory 207472 kb
Host smart-22f9039f-256d-42ad-a863-ba93d8d7409a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38291
37079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3829137079
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.693450423
Short name T3586
Test name
Test status
Simulation time 235984397 ps
CPU time 1.05 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:36:25 PM PDT 24
Peak memory 207468 kb
Host smart-10185318-5cfd-4681-b7df-64ef42ac1419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69345
0423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.693450423
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.3946247385
Short name T2234
Test name
Test status
Simulation time 3914425197 ps
CPU time 39.44 seconds
Started Aug 18 05:36:19 PM PDT 24
Finished Aug 18 05:36:58 PM PDT 24
Peak memory 218056 kb
Host smart-4f3dfae9-b816-421a-9b19-d0d1f9c7ed47
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3946247385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.3946247385
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.32970025
Short name T1564
Test name
Test status
Simulation time 12941862647 ps
CPU time 93.65 seconds
Started Aug 18 05:36:18 PM PDT 24
Finished Aug 18 05:37:52 PM PDT 24
Peak memory 207804 kb
Host smart-0355fc76-382d-4776-b898-7a57cd383edb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=32970025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.32970025
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.3370936812
Short name T1050
Test name
Test status
Simulation time 184581269 ps
CPU time 0.91 seconds
Started Aug 18 05:36:15 PM PDT 24
Finished Aug 18 05:36:16 PM PDT 24
Peak memory 207532 kb
Host smart-3fc24959-2bad-40e3-ad8c-5885fae681ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33709
36812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.3370936812
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.864583783
Short name T2296
Test name
Test status
Simulation time 5184631222 ps
CPU time 8.16 seconds
Started Aug 18 05:36:07 PM PDT 24
Finished Aug 18 05:36:16 PM PDT 24
Peak memory 215840 kb
Host smart-6ede491f-836f-4c30-aad5-6e23b89f4117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86458
3783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.864583783
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.2825929269
Short name T2332
Test name
Test status
Simulation time 4907143337 ps
CPU time 6.7 seconds
Started Aug 18 05:36:17 PM PDT 24
Finished Aug 18 05:36:24 PM PDT 24
Peak memory 216824 kb
Host smart-3fc0ef0d-36ef-4c9f-8a82-c21b3fd7e73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28259
29269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.2825929269
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.780617570
Short name T2189
Test name
Test status
Simulation time 4283088515 ps
CPU time 45.74 seconds
Started Aug 18 05:36:11 PM PDT 24
Finished Aug 18 05:36:57 PM PDT 24
Peak memory 219528 kb
Host smart-a0b1b773-3329-4687-94b6-edc9b902c0bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=780617570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.780617570
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.202010549
Short name T1042
Test name
Test status
Simulation time 3400162235 ps
CPU time 23.95 seconds
Started Aug 18 05:36:19 PM PDT 24
Finished Aug 18 05:36:43 PM PDT 24
Peak memory 216000 kb
Host smart-3ea65da6-7a19-4ae3-8780-9150063929ec
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=202010549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.202010549
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.3187007734
Short name T972
Test name
Test status
Simulation time 251119617 ps
CPU time 1.06 seconds
Started Aug 18 05:36:16 PM PDT 24
Finished Aug 18 05:36:18 PM PDT 24
Peak memory 207488 kb
Host smart-c1c763ee-5107-4602-b069-95c0b99bb733
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3187007734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.3187007734
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1069148461
Short name T1800
Test name
Test status
Simulation time 189510974 ps
CPU time 1.02 seconds
Started Aug 18 05:36:14 PM PDT 24
Finished Aug 18 05:36:16 PM PDT 24
Peak memory 207524 kb
Host smart-7cab638e-83c7-43b5-a8f6-e230010babcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10691
48461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1069148461
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.2791737528
Short name T3065
Test name
Test status
Simulation time 2341387429 ps
CPU time 64.74 seconds
Started Aug 18 05:36:10 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 215840 kb
Host smart-d479de47-3f40-4edd-8f7c-325e988e7fe9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2791737528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.2791737528
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.439513910
Short name T2557
Test name
Test status
Simulation time 225883288 ps
CPU time 0.95 seconds
Started Aug 18 05:36:19 PM PDT 24
Finished Aug 18 05:36:20 PM PDT 24
Peak memory 207488 kb
Host smart-b2578537-6d93-455d-9c31-cdfc153bdf7c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=439513910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.439513910
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2752879392
Short name T3330
Test name
Test status
Simulation time 172847260 ps
CPU time 0.92 seconds
Started Aug 18 05:36:09 PM PDT 24
Finished Aug 18 05:36:10 PM PDT 24
Peak memory 207472 kb
Host smart-226cc421-3b9c-4ee0-bba1-1e01f7666579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27528
79392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2752879392
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3317358184
Short name T165
Test name
Test status
Simulation time 164385348 ps
CPU time 0.92 seconds
Started Aug 18 05:36:03 PM PDT 24
Finished Aug 18 05:36:04 PM PDT 24
Peak memory 207508 kb
Host smart-34a48543-4c99-4ab1-b9ec-7ba9acd81841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33173
58184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3317358184
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.3190438413
Short name T136
Test name
Test status
Simulation time 164778615 ps
CPU time 0.89 seconds
Started Aug 18 05:36:10 PM PDT 24
Finished Aug 18 05:36:11 PM PDT 24
Peak memory 207504 kb
Host smart-729cb1fb-a73a-4938-b93a-68cb4aaf8614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31904
38413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.3190438413
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2030885714
Short name T881
Test name
Test status
Simulation time 225918940 ps
CPU time 0.89 seconds
Started Aug 18 05:36:27 PM PDT 24
Finished Aug 18 05:36:28 PM PDT 24
Peak memory 207384 kb
Host smart-43105bcb-6869-483d-b0b3-d4f9bad3ee76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20308
85714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2030885714
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1587595678
Short name T3044
Test name
Test status
Simulation time 158363459 ps
CPU time 0.94 seconds
Started Aug 18 05:36:21 PM PDT 24
Finished Aug 18 05:36:22 PM PDT 24
Peak memory 207584 kb
Host smart-9c807289-1233-40eb-bba5-fe52ca39481f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15875
95678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1587595678
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1663267357
Short name T3599
Test name
Test status
Simulation time 187036329 ps
CPU time 0.89 seconds
Started Aug 18 05:36:14 PM PDT 24
Finished Aug 18 05:36:15 PM PDT 24
Peak memory 207552 kb
Host smart-2e3495b2-f418-4c63-a81b-73511e8aa2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16632
67357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1663267357
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1461137206
Short name T1999
Test name
Test status
Simulation time 218412398 ps
CPU time 0.95 seconds
Started Aug 18 05:36:13 PM PDT 24
Finished Aug 18 05:36:14 PM PDT 24
Peak memory 207492 kb
Host smart-5456c0d9-66fe-402e-bd60-433bbd9da1a8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1461137206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1461137206
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2604991255
Short name T3527
Test name
Test status
Simulation time 205446439 ps
CPU time 0.93 seconds
Started Aug 18 05:36:27 PM PDT 24
Finished Aug 18 05:36:28 PM PDT 24
Peak memory 207360 kb
Host smart-b10782cd-3e01-40be-9313-05ceb4b80148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26049
91255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2604991255
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2993071778
Short name T710
Test name
Test status
Simulation time 37984380 ps
CPU time 0.68 seconds
Started Aug 18 05:36:20 PM PDT 24
Finished Aug 18 05:36:21 PM PDT 24
Peak memory 207516 kb
Host smart-8f8e6058-77ca-442b-a385-17b9809d6afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29930
71778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2993071778
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.16978447
Short name T1701
Test name
Test status
Simulation time 19198014741 ps
CPU time 53.58 seconds
Started Aug 18 05:36:11 PM PDT 24
Finished Aug 18 05:37:05 PM PDT 24
Peak memory 215860 kb
Host smart-53f3e92b-1afc-4614-bdc5-813576f7ee5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16978
447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.16978447
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1417713222
Short name T2653
Test name
Test status
Simulation time 153166102 ps
CPU time 1.02 seconds
Started Aug 18 05:36:12 PM PDT 24
Finished Aug 18 05:36:13 PM PDT 24
Peak memory 207580 kb
Host smart-9c04644f-2579-4d00-9477-d84791d89305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14177
13222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1417713222
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3971817357
Short name T2514
Test name
Test status
Simulation time 253939502 ps
CPU time 1.07 seconds
Started Aug 18 05:36:21 PM PDT 24
Finished Aug 18 05:36:23 PM PDT 24
Peak memory 207492 kb
Host smart-dd2cdd33-9ab9-4802-80ee-595290a3a323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39718
17357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3971817357
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2329260276
Short name T662
Test name
Test status
Simulation time 215010514 ps
CPU time 0.98 seconds
Started Aug 18 05:36:12 PM PDT 24
Finished Aug 18 05:36:13 PM PDT 24
Peak memory 207496 kb
Host smart-d6c9548d-fadf-4360-8a27-5bb4a46621b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23292
60276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2329260276
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1366707854
Short name T2436
Test name
Test status
Simulation time 172459262 ps
CPU time 0.97 seconds
Started Aug 18 05:36:12 PM PDT 24
Finished Aug 18 05:36:13 PM PDT 24
Peak memory 207508 kb
Host smart-a020417d-c3c8-45c7-a3fe-4641d63aab66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13667
07854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1366707854
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.2347980152
Short name T1169
Test name
Test status
Simulation time 177868976 ps
CPU time 0.87 seconds
Started Aug 18 05:36:18 PM PDT 24
Finished Aug 18 05:36:19 PM PDT 24
Peak memory 207460 kb
Host smart-7604be47-6f4b-40d3-a695-8b0c25b24639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23479
80152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.2347980152
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.1384035272
Short name T2767
Test name
Test status
Simulation time 172126326 ps
CPU time 0.89 seconds
Started Aug 18 05:36:17 PM PDT 24
Finished Aug 18 05:36:17 PM PDT 24
Peak memory 207460 kb
Host smart-53c883f5-a098-4b53-9cb2-b7f92f871c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13840
35272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.1384035272
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3448199183
Short name T2228
Test name
Test status
Simulation time 150281737 ps
CPU time 0.81 seconds
Started Aug 18 05:36:10 PM PDT 24
Finished Aug 18 05:36:10 PM PDT 24
Peak memory 207488 kb
Host smart-7335f535-0547-40a9-b2fd-a13e9c1de103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34481
99183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3448199183
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.4115916070
Short name T699
Test name
Test status
Simulation time 271226109 ps
CPU time 1.15 seconds
Started Aug 18 05:36:20 PM PDT 24
Finished Aug 18 05:36:21 PM PDT 24
Peak memory 207456 kb
Host smart-6b3c583d-ef3f-4727-82d1-750c15a5a518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41159
16070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.4115916070
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.2489723525
Short name T2494
Test name
Test status
Simulation time 3697562869 ps
CPU time 27.49 seconds
Started Aug 18 05:36:31 PM PDT 24
Finished Aug 18 05:36:59 PM PDT 24
Peak memory 217824 kb
Host smart-5c6c63a2-8a6c-42e1-8a06-7815d9d05a22
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2489723525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.2489723525
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3160654993
Short name T1373
Test name
Test status
Simulation time 207957737 ps
CPU time 0.93 seconds
Started Aug 18 05:36:10 PM PDT 24
Finished Aug 18 05:36:11 PM PDT 24
Peak memory 207384 kb
Host smart-9f4d4e21-16c7-4278-9264-2faf1861e6bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31606
54993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3160654993
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.249762862
Short name T1154
Test name
Test status
Simulation time 167881755 ps
CPU time 0.87 seconds
Started Aug 18 05:36:20 PM PDT 24
Finished Aug 18 05:36:22 PM PDT 24
Peak memory 207460 kb
Host smart-47b95277-49e6-40f6-a753-cf1c0ce1338d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24976
2862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.249762862
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.2916332533
Short name T3333
Test name
Test status
Simulation time 1313956873 ps
CPU time 3.02 seconds
Started Aug 18 05:36:21 PM PDT 24
Finished Aug 18 05:36:25 PM PDT 24
Peak memory 207704 kb
Host smart-029506d1-d774-4477-a64f-8c99e2b86b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29163
32533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.2916332533
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1566991544
Short name T1235
Test name
Test status
Simulation time 2651558891 ps
CPU time 26.66 seconds
Started Aug 18 05:36:12 PM PDT 24
Finished Aug 18 05:36:39 PM PDT 24
Peak memory 217516 kb
Host smart-6b3e4875-3eb4-476b-a2d4-7b851fa4a28a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15669
91544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1566991544
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.960974463
Short name T1490
Test name
Test status
Simulation time 492791221 ps
CPU time 8.2 seconds
Started Aug 18 05:36:14 PM PDT 24
Finished Aug 18 05:36:22 PM PDT 24
Peak memory 207688 kb
Host smart-f3974029-a991-42f5-85b9-02227e885b58
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960974463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_host
_handshake.960974463
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_tx_rx_disruption.2319794351
Short name T2197
Test name
Test status
Simulation time 475001663 ps
CPU time 1.45 seconds
Started Aug 18 05:36:16 PM PDT 24
Finished Aug 18 05:36:18 PM PDT 24
Peak memory 207508 kb
Host smart-3354e882-5bf9-4278-91eb-cf4f53ea4f60
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319794351 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.usbdev_tx_rx_disruption.2319794351
Directory /workspace/29.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/290.usbdev_tx_rx_disruption.3045367599
Short name T1037
Test name
Test status
Simulation time 452428143 ps
CPU time 1.43 seconds
Started Aug 18 05:39:45 PM PDT 24
Finished Aug 18 05:39:46 PM PDT 24
Peak memory 207552 kb
Host smart-1d0ea9ad-a465-45c2-9f7f-543a75ebb4e0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045367599 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.usbdev_tx_rx_disruption.3045367599
Directory /workspace/290.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/291.usbdev_tx_rx_disruption.1069218718
Short name T2572
Test name
Test status
Simulation time 610007811 ps
CPU time 1.61 seconds
Started Aug 18 05:39:59 PM PDT 24
Finished Aug 18 05:40:01 PM PDT 24
Peak memory 207564 kb
Host smart-d67a86e5-811e-40b4-99d7-321f65996311
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069218718 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.usbdev_tx_rx_disruption.1069218718
Directory /workspace/291.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/292.usbdev_tx_rx_disruption.2928266069
Short name T176
Test name
Test status
Simulation time 489385317 ps
CPU time 1.53 seconds
Started Aug 18 05:39:47 PM PDT 24
Finished Aug 18 05:39:49 PM PDT 24
Peak memory 207568 kb
Host smart-ae06813a-4d53-491d-b319-3ec87c0585a8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928266069 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.usbdev_tx_rx_disruption.2928266069
Directory /workspace/292.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/293.usbdev_tx_rx_disruption.49605833
Short name T1046
Test name
Test status
Simulation time 520616283 ps
CPU time 1.67 seconds
Started Aug 18 05:40:06 PM PDT 24
Finished Aug 18 05:40:08 PM PDT 24
Peak memory 207544 kb
Host smart-b5e5ef92-8e98-49ba-8682-43ffd82b2e15
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49605833 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 293.usbdev_tx_rx_disruption.49605833
Directory /workspace/293.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/294.usbdev_tx_rx_disruption.4193466256
Short name T1397
Test name
Test status
Simulation time 501946552 ps
CPU time 1.7 seconds
Started Aug 18 05:39:38 PM PDT 24
Finished Aug 18 05:39:40 PM PDT 24
Peak memory 207532 kb
Host smart-9a0ab617-b857-47e7-9cb7-b23ce44290bc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193466256 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 294.usbdev_tx_rx_disruption.4193466256
Directory /workspace/294.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/295.usbdev_tx_rx_disruption.1762588279
Short name T2869
Test name
Test status
Simulation time 640629974 ps
CPU time 1.85 seconds
Started Aug 18 05:39:49 PM PDT 24
Finished Aug 18 05:39:51 PM PDT 24
Peak memory 207568 kb
Host smart-bd6a04d9-e934-49b4-8084-8066ba6cfd35
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762588279 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 295.usbdev_tx_rx_disruption.1762588279
Directory /workspace/295.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/296.usbdev_tx_rx_disruption.1049600934
Short name T682
Test name
Test status
Simulation time 612373044 ps
CPU time 1.7 seconds
Started Aug 18 05:39:54 PM PDT 24
Finished Aug 18 05:39:56 PM PDT 24
Peak memory 207376 kb
Host smart-bc09b68f-31df-4223-80f6-617e9c2aa7c0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049600934 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 296.usbdev_tx_rx_disruption.1049600934
Directory /workspace/296.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/297.usbdev_tx_rx_disruption.947648093
Short name T736
Test name
Test status
Simulation time 624508216 ps
CPU time 1.75 seconds
Started Aug 18 05:39:56 PM PDT 24
Finished Aug 18 05:39:57 PM PDT 24
Peak memory 207456 kb
Host smart-ad0d4a5e-280e-425c-a9cf-1b1076f99825
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947648093 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 297.usbdev_tx_rx_disruption.947648093
Directory /workspace/297.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/298.usbdev_tx_rx_disruption.1591739900
Short name T2922
Test name
Test status
Simulation time 456155333 ps
CPU time 1.43 seconds
Started Aug 18 05:39:53 PM PDT 24
Finished Aug 18 05:39:54 PM PDT 24
Peak memory 207592 kb
Host smart-aa891f6d-7e2a-4cc6-a2b7-9e333a29468b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591739900 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.usbdev_tx_rx_disruption.1591739900
Directory /workspace/298.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/299.usbdev_tx_rx_disruption.3203329190
Short name T813
Test name
Test status
Simulation time 443275222 ps
CPU time 1.41 seconds
Started Aug 18 05:39:45 PM PDT 24
Finished Aug 18 05:39:46 PM PDT 24
Peak memory 207564 kb
Host smart-76cfa2b4-cb0c-4228-86c3-54aeb98b4da2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203329190 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.usbdev_tx_rx_disruption.3203329190
Directory /workspace/299.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.2056928082
Short name T2153
Test name
Test status
Simulation time 51834486 ps
CPU time 0.69 seconds
Started Aug 18 05:32:18 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 207364 kb
Host smart-f774fabd-c770-4d32-9b37-02e955f10095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2056928082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.2056928082
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.2489823010
Short name T2138
Test name
Test status
Simulation time 8907209216 ps
CPU time 14.85 seconds
Started Aug 18 05:32:03 PM PDT 24
Finished Aug 18 05:32:18 PM PDT 24
Peak memory 207764 kb
Host smart-c0240e52-b0f8-4668-abb0-292bae6fa298
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489823010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.2489823010
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.2872573532
Short name T3349
Test name
Test status
Simulation time 15535587658 ps
CPU time 20.21 seconds
Started Aug 18 05:32:16 PM PDT 24
Finished Aug 18 05:32:37 PM PDT 24
Peak memory 215960 kb
Host smart-4c96b522-1737-45a5-957a-a27bd72b3736
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872573532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.2872573532
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.1966966270
Short name T2427
Test name
Test status
Simulation time 24688751615 ps
CPU time 35.66 seconds
Started Aug 18 05:32:22 PM PDT 24
Finished Aug 18 05:32:58 PM PDT 24
Peak memory 215908 kb
Host smart-e7763126-c703-41e5-a8c6-84392f246f6f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966966270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_resume.1966966270
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2229090175
Short name T2737
Test name
Test status
Simulation time 171828233 ps
CPU time 0.92 seconds
Started Aug 18 05:32:05 PM PDT 24
Finished Aug 18 05:32:06 PM PDT 24
Peak memory 207404 kb
Host smart-b575f613-a4b9-4700-a0ff-cd13f551e385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22290
90175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2229090175
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.1761258941
Short name T49
Test name
Test status
Simulation time 145235418 ps
CPU time 0.85 seconds
Started Aug 18 05:32:02 PM PDT 24
Finished Aug 18 05:32:03 PM PDT 24
Peak memory 207480 kb
Host smart-79e1826d-cdd7-4d9c-a3bf-59fbbb972663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17612
58941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1761258941
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.2420806678
Short name T2992
Test name
Test status
Simulation time 161283760 ps
CPU time 0.85 seconds
Started Aug 18 05:32:10 PM PDT 24
Finished Aug 18 05:32:11 PM PDT 24
Peak memory 207556 kb
Host smart-8b8c3661-052c-4355-ae9b-a77c5444673f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24208
06678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.2420806678
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.110749863
Short name T1946
Test name
Test status
Simulation time 482029899 ps
CPU time 1.68 seconds
Started Aug 18 05:32:02 PM PDT 24
Finished Aug 18 05:32:04 PM PDT 24
Peak memory 207556 kb
Host smart-8e313706-a13f-4cb1-85ea-21abd79f2f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11074
9863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.110749863
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_device_address.2555313499
Short name T2030
Test name
Test status
Simulation time 18435391924 ps
CPU time 33.52 seconds
Started Aug 18 05:32:25 PM PDT 24
Finished Aug 18 05:32:59 PM PDT 24
Peak memory 207824 kb
Host smart-940009ea-75c6-45e2-a238-bb0a51824a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25553
13499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.2555313499
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.2997164719
Short name T2055
Test name
Test status
Simulation time 172533688 ps
CPU time 0.89 seconds
Started Aug 18 05:32:04 PM PDT 24
Finished Aug 18 05:32:05 PM PDT 24
Peak memory 207528 kb
Host smart-38fa23fc-bbcd-49ed-86c9-4078789512ec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997164719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.2997164719
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.791589957
Short name T1085
Test name
Test status
Simulation time 963612529 ps
CPU time 2.03 seconds
Started Aug 18 05:32:07 PM PDT 24
Finished Aug 18 05:32:09 PM PDT 24
Peak memory 207508 kb
Host smart-c751001c-b63a-45e1-adcc-b9553a9cee0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79158
9957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.791589957
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.4098323521
Short name T1341
Test name
Test status
Simulation time 145028027 ps
CPU time 0.79 seconds
Started Aug 18 05:32:13 PM PDT 24
Finished Aug 18 05:32:14 PM PDT 24
Peak memory 207548 kb
Host smart-a073ba16-bad6-4477-83d7-35dfd249209a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40983
23521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.4098323521
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.3684018688
Short name T726
Test name
Test status
Simulation time 38427609 ps
CPU time 0.71 seconds
Started Aug 18 05:32:13 PM PDT 24
Finished Aug 18 05:32:13 PM PDT 24
Peak memory 207356 kb
Host smart-fbd1ebca-9ddc-46e6-87dc-520d64ef56d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36840
18688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3684018688
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.197868452
Short name T2149
Test name
Test status
Simulation time 869739010 ps
CPU time 2.39 seconds
Started Aug 18 05:32:13 PM PDT 24
Finished Aug 18 05:32:15 PM PDT 24
Peak memory 207780 kb
Host smart-1fd9cee5-0114-445f-a06f-bf719775f1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19786
8452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.197868452
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.4221336483
Short name T3345
Test name
Test status
Simulation time 280965069 ps
CPU time 1.91 seconds
Started Aug 18 05:32:02 PM PDT 24
Finished Aug 18 05:32:04 PM PDT 24
Peak memory 206608 kb
Host smart-03fd091b-d0b7-4227-b3f8-9cd84d982c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42213
36483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.4221336483
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3897231658
Short name T1425
Test name
Test status
Simulation time 115254082776 ps
CPU time 188.19 seconds
Started Aug 18 05:32:16 PM PDT 24
Finished Aug 18 05:35:24 PM PDT 24
Peak memory 207732 kb
Host smart-b8a6f228-7e53-46e2-9871-0894ec63eb12
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3897231658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3897231658
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.3433374917
Short name T3137
Test name
Test status
Simulation time 120260063191 ps
CPU time 192.43 seconds
Started Aug 18 05:32:19 PM PDT 24
Finished Aug 18 05:35:31 PM PDT 24
Peak memory 207828 kb
Host smart-edfd2f8a-ffde-4324-aab8-6e754391c991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433374917 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.3433374917
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.3247179433
Short name T1148
Test name
Test status
Simulation time 94119176405 ps
CPU time 181.89 seconds
Started Aug 18 05:32:19 PM PDT 24
Finished Aug 18 05:35:21 PM PDT 24
Peak memory 207760 kb
Host smart-d8e2f80d-b1a0-42e5-ae73-a136d6c07875
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3247179433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.3247179433
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.3161097885
Short name T541
Test name
Test status
Simulation time 95048734342 ps
CPU time 143.83 seconds
Started Aug 18 05:32:04 PM PDT 24
Finished Aug 18 05:34:28 PM PDT 24
Peak memory 207812 kb
Host smart-9a262a10-6711-4281-8e6a-41955324c264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161097885 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.3161097885
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.4144800381
Short name T1981
Test name
Test status
Simulation time 109193674193 ps
CPU time 196.12 seconds
Started Aug 18 05:32:20 PM PDT 24
Finished Aug 18 05:35:36 PM PDT 24
Peak memory 207752 kb
Host smart-3c9d0f98-61f7-478d-b6ea-bb506faf5b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41448
00381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.4144800381
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.3737666713
Short name T3473
Test name
Test status
Simulation time 210118375 ps
CPU time 1.24 seconds
Started Aug 18 05:32:04 PM PDT 24
Finished Aug 18 05:32:06 PM PDT 24
Peak memory 215796 kb
Host smart-dedc5a4d-ea99-4005-8eec-c06015e6bf05
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3737666713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3737666713
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1865525908
Short name T2478
Test name
Test status
Simulation time 151207627 ps
CPU time 0.86 seconds
Started Aug 18 05:32:14 PM PDT 24
Finished Aug 18 05:32:15 PM PDT 24
Peak memory 207360 kb
Host smart-90e6baa6-fd18-4346-ab1d-56e75b5bd929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18655
25908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1865525908
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1188416830
Short name T3384
Test name
Test status
Simulation time 202115851 ps
CPU time 0.97 seconds
Started Aug 18 05:32:10 PM PDT 24
Finished Aug 18 05:32:11 PM PDT 24
Peak memory 207364 kb
Host smart-12878f2d-c050-4f31-9d87-9c0380419607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11884
16830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1188416830
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.3521331012
Short name T842
Test name
Test status
Simulation time 3006659794 ps
CPU time 88.37 seconds
Started Aug 18 05:31:59 PM PDT 24
Finished Aug 18 05:33:28 PM PDT 24
Peak memory 218408 kb
Host smart-10d8f01d-2792-4936-97bb-4e63d260bb09
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3521331012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3521331012
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.505916119
Short name T2743
Test name
Test status
Simulation time 12934613057 ps
CPU time 169.48 seconds
Started Aug 18 05:32:22 PM PDT 24
Finished Aug 18 05:35:12 PM PDT 24
Peak memory 207784 kb
Host smart-2b4b52b3-5719-482a-941c-77ea85f151ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=505916119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.505916119
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1909663196
Short name T1669
Test name
Test status
Simulation time 203578223 ps
CPU time 0.96 seconds
Started Aug 18 05:32:19 PM PDT 24
Finished Aug 18 05:32:20 PM PDT 24
Peak memory 207508 kb
Host smart-53b67d0b-e7d6-4afe-9913-e926bee69a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19096
63196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1909663196
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.480450398
Short name T1758
Test name
Test status
Simulation time 12247964964 ps
CPU time 17.02 seconds
Started Aug 18 05:32:08 PM PDT 24
Finished Aug 18 05:32:25 PM PDT 24
Peak memory 207656 kb
Host smart-63a18dd7-fa13-41e8-832e-53a2325c2145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48045
0398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.480450398
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.853661761
Short name T1876
Test name
Test status
Simulation time 9835178062 ps
CPU time 13.96 seconds
Started Aug 18 05:32:31 PM PDT 24
Finished Aug 18 05:32:45 PM PDT 24
Peak memory 207760 kb
Host smart-0bec0276-ca48-4a72-9a65-fd7c480d0e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85366
1761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.853661761
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.299413226
Short name T1801
Test name
Test status
Simulation time 3788645696 ps
CPU time 109.8 seconds
Started Aug 18 05:32:32 PM PDT 24
Finished Aug 18 05:34:22 PM PDT 24
Peak memory 218804 kb
Host smart-34456825-96f3-41f8-971f-2069383de17f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=299413226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.299413226
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.4230417938
Short name T3488
Test name
Test status
Simulation time 3417052563 ps
CPU time 25.88 seconds
Started Aug 18 05:32:18 PM PDT 24
Finished Aug 18 05:32:44 PM PDT 24
Peak memory 217704 kb
Host smart-d7c06b92-22ac-44ce-bbf4-a7c035fc0411
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4230417938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.4230417938
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.515818703
Short name T1014
Test name
Test status
Simulation time 257329059 ps
CPU time 1 seconds
Started Aug 18 05:32:29 PM PDT 24
Finished Aug 18 05:32:30 PM PDT 24
Peak memory 207484 kb
Host smart-9c404adf-39a6-4d14-b4b8-3d66afb5e09c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=515818703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.515818703
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.4131620354
Short name T2545
Test name
Test status
Simulation time 201886205 ps
CPU time 0.95 seconds
Started Aug 18 05:32:24 PM PDT 24
Finished Aug 18 05:32:25 PM PDT 24
Peak memory 207400 kb
Host smart-4cc51912-3654-42b5-9766-5ae927a3639e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41316
20354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.4131620354
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_non_iso_usb_traffic.1507185736
Short name T2862
Test name
Test status
Simulation time 1905006041 ps
CPU time 52.54 seconds
Started Aug 18 05:32:22 PM PDT 24
Finished Aug 18 05:33:14 PM PDT 24
Peak memory 223880 kb
Host smart-d941a25d-14ab-49ea-9521-4865d9dc1f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15071
85736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_non_iso_usb_traffic.1507185736
Directory /workspace/3.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.2998231178
Short name T2112
Test name
Test status
Simulation time 2505480479 ps
CPU time 26.65 seconds
Started Aug 18 05:32:44 PM PDT 24
Finished Aug 18 05:33:11 PM PDT 24
Peak memory 224148 kb
Host smart-3f7552b3-6351-4183-b897-92f4e7177ad9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2998231178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.2998231178
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.895694625
Short name T767
Test name
Test status
Simulation time 3295825103 ps
CPU time 86.97 seconds
Started Aug 18 05:32:27 PM PDT 24
Finished Aug 18 05:33:54 PM PDT 24
Peak memory 215996 kb
Host smart-123d87b2-a1d7-4731-9d9e-dc96f4fb30ba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=895694625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.895694625
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.2526148081
Short name T1386
Test name
Test status
Simulation time 172014197 ps
CPU time 0.93 seconds
Started Aug 18 05:32:16 PM PDT 24
Finished Aug 18 05:32:17 PM PDT 24
Peak memory 207452 kb
Host smart-47379c2e-d7c5-4472-960c-fd88b018204d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2526148081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.2526148081
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3564538711
Short name T2281
Test name
Test status
Simulation time 183401125 ps
CPU time 0.86 seconds
Started Aug 18 05:32:22 PM PDT 24
Finished Aug 18 05:32:23 PM PDT 24
Peak memory 207472 kb
Host smart-b4731654-a7da-4be9-a334-082e3c9fc3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35645
38711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3564538711
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3866496239
Short name T2872
Test name
Test status
Simulation time 235873866 ps
CPU time 0.95 seconds
Started Aug 18 05:32:21 PM PDT 24
Finished Aug 18 05:32:22 PM PDT 24
Peak memory 207452 kb
Host smart-144f555d-9d18-40fa-a897-32763f3f940c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38664
96239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3866496239
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3984995485
Short name T1156
Test name
Test status
Simulation time 154133408 ps
CPU time 0.9 seconds
Started Aug 18 05:32:20 PM PDT 24
Finished Aug 18 05:32:21 PM PDT 24
Peak memory 207504 kb
Host smart-3ce420e7-e00f-409a-98f8-898f3a787189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39849
95485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3984995485
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3037241951
Short name T3177
Test name
Test status
Simulation time 161836075 ps
CPU time 0.9 seconds
Started Aug 18 05:32:31 PM PDT 24
Finished Aug 18 05:32:32 PM PDT 24
Peak memory 207632 kb
Host smart-3139ebea-67d6-451a-8514-127910b515c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30372
41951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3037241951
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3246402771
Short name T2970
Test name
Test status
Simulation time 219493863 ps
CPU time 0.94 seconds
Started Aug 18 05:32:19 PM PDT 24
Finished Aug 18 05:32:20 PM PDT 24
Peak memory 207468 kb
Host smart-fff79571-4bd4-4e16-b60a-df4c7cec60df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32464
02771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3246402771
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2367382138
Short name T2040
Test name
Test status
Simulation time 154228509 ps
CPU time 0.84 seconds
Started Aug 18 05:32:19 PM PDT 24
Finished Aug 18 05:32:20 PM PDT 24
Peak memory 207568 kb
Host smart-580b10cb-d8df-47f6-9021-a4dbcd1e9469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23673
82138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2367382138
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.2238048195
Short name T3348
Test name
Test status
Simulation time 230101320 ps
CPU time 1.08 seconds
Started Aug 18 05:32:11 PM PDT 24
Finished Aug 18 05:32:12 PM PDT 24
Peak memory 207484 kb
Host smart-811b4882-f7e2-4bfa-9e31-a4b67d319d21
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2238048195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.2238048195
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.3085346486
Short name T1093
Test name
Test status
Simulation time 224021337 ps
CPU time 1.13 seconds
Started Aug 18 05:32:20 PM PDT 24
Finished Aug 18 05:32:21 PM PDT 24
Peak memory 207456 kb
Host smart-cb7e933c-b5cc-44ff-a336-bf83d4626cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30853
46486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.3085346486
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2409037192
Short name T2823
Test name
Test status
Simulation time 150704598 ps
CPU time 0.82 seconds
Started Aug 18 05:32:15 PM PDT 24
Finished Aug 18 05:32:16 PM PDT 24
Peak memory 207456 kb
Host smart-c09e5886-89c5-489e-acca-7d075503d904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24090
37192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2409037192
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1265313872
Short name T24
Test name
Test status
Simulation time 61374238 ps
CPU time 0.76 seconds
Started Aug 18 05:32:36 PM PDT 24
Finished Aug 18 05:32:37 PM PDT 24
Peak memory 207548 kb
Host smart-0a2adcf5-4556-4712-9328-f8f0cc384a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12653
13872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1265313872
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2005571340
Short name T1366
Test name
Test status
Simulation time 14108649846 ps
CPU time 39.97 seconds
Started Aug 18 05:32:17 PM PDT 24
Finished Aug 18 05:32:57 PM PDT 24
Peak memory 215940 kb
Host smart-0d34e7f1-362d-4cfa-8f92-3df0315c08eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20055
71340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2005571340
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1968081926
Short name T770
Test name
Test status
Simulation time 204390490 ps
CPU time 0.98 seconds
Started Aug 18 05:32:25 PM PDT 24
Finished Aug 18 05:32:27 PM PDT 24
Peak memory 207592 kb
Host smart-8cd49083-149c-4eb0-83a5-8892d656732b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19680
81926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1968081926
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1866785817
Short name T1144
Test name
Test status
Simulation time 234717182 ps
CPU time 1.03 seconds
Started Aug 18 05:32:39 PM PDT 24
Finished Aug 18 05:32:40 PM PDT 24
Peak memory 207480 kb
Host smart-c2c55b6d-b932-4840-be62-ecbd9b2af593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18667
85817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1866785817
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.1507899503
Short name T3234
Test name
Test status
Simulation time 3792695431 ps
CPU time 95.31 seconds
Started Aug 18 05:32:18 PM PDT 24
Finished Aug 18 05:33:53 PM PDT 24
Peak memory 218356 kb
Host smart-76e8e5ed-8fd9-4fa1-b708-2c2b891ec1d9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507899503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.1507899503
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.346247472
Short name T1948
Test name
Test status
Simulation time 6673849915 ps
CPU time 173.51 seconds
Started Aug 18 05:32:19 PM PDT 24
Finished Aug 18 05:35:13 PM PDT 24
Peak memory 216004 kb
Host smart-d51a3051-7e3a-412f-985e-228b9bff963e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=346247472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.346247472
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2451282332
Short name T2362
Test name
Test status
Simulation time 5066081216 ps
CPU time 17.92 seconds
Started Aug 18 05:32:25 PM PDT 24
Finished Aug 18 05:32:43 PM PDT 24
Peak memory 219592 kb
Host smart-a5223e14-5a03-4ed2-8ad9-17763536bd59
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451282332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2451282332
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.4274759102
Short name T837
Test name
Test status
Simulation time 174371689 ps
CPU time 0.93 seconds
Started Aug 18 05:32:19 PM PDT 24
Finished Aug 18 05:32:20 PM PDT 24
Peak memory 207412 kb
Host smart-d73ca611-477a-4573-b7ed-927f06bdaaa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42747
59102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.4274759102
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.3436602047
Short name T3276
Test name
Test status
Simulation time 191692943 ps
CPU time 1.02 seconds
Started Aug 18 05:32:35 PM PDT 24
Finished Aug 18 05:32:36 PM PDT 24
Peak memory 207412 kb
Host smart-60a61cca-3994-42a3-bf86-4d17ce3ea7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34366
02047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.3436602047
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_resume_link_active.2687174925
Short name T2297
Test name
Test status
Simulation time 20159354843 ps
CPU time 26.76 seconds
Started Aug 18 05:32:16 PM PDT 24
Finished Aug 18 05:32:42 PM PDT 24
Peak memory 207604 kb
Host smart-d3568165-c3b7-422d-b798-1d3c591f5ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26871
74925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_resume_link_active.2687174925
Directory /workspace/3.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.2960777966
Short name T1305
Test name
Test status
Simulation time 193639933 ps
CPU time 0.92 seconds
Started Aug 18 05:32:15 PM PDT 24
Finished Aug 18 05:32:16 PM PDT 24
Peak memory 207424 kb
Host smart-2e3878f5-e1d5-41f0-a45b-596b4a081cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29607
77966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.2960777966
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_full.1627607002
Short name T46
Test name
Test status
Simulation time 320543320 ps
CPU time 1.2 seconds
Started Aug 18 05:32:20 PM PDT 24
Finished Aug 18 05:32:21 PM PDT 24
Peak memory 207384 kb
Host smart-9e9a4845-5c3f-4ea5-b8c7-04b9287017ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16276
07002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_full.1627607002
Directory /workspace/3.usbdev_rx_full/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.563245466
Short name T74
Test name
Test status
Simulation time 167978465 ps
CPU time 0.86 seconds
Started Aug 18 05:32:16 PM PDT 24
Finished Aug 18 05:32:17 PM PDT 24
Peak memory 207528 kb
Host smart-c2cdf7c8-caee-448c-aad0-564ce525a5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56324
5466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.563245466
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3355253170
Short name T244
Test name
Test status
Simulation time 405238450 ps
CPU time 1.38 seconds
Started Aug 18 05:32:40 PM PDT 24
Finished Aug 18 05:32:42 PM PDT 24
Peak memory 224340 kb
Host smart-be9193f5-0e5a-4230-b18b-aac256bc9da5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3355253170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3355253170
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.670024175
Short name T2750
Test name
Test status
Simulation time 426235177 ps
CPU time 1.37 seconds
Started Aug 18 05:32:14 PM PDT 24
Finished Aug 18 05:32:15 PM PDT 24
Peak memory 207580 kb
Host smart-b67dcb62-68a7-4cc6-bd81-57c07cb44e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67002
4175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.670024175
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2369175331
Short name T188
Test name
Test status
Simulation time 310220013 ps
CPU time 1.16 seconds
Started Aug 18 05:32:17 PM PDT 24
Finished Aug 18 05:32:18 PM PDT 24
Peak memory 207636 kb
Host smart-1c244069-2f50-4222-b195-c6d42529c8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23691
75331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2369175331
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1148406645
Short name T1884
Test name
Test status
Simulation time 167031394 ps
CPU time 0.85 seconds
Started Aug 18 05:32:20 PM PDT 24
Finished Aug 18 05:32:21 PM PDT 24
Peak memory 207472 kb
Host smart-c781b228-c494-43fd-8b38-dba06ffd4976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11484
06645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1148406645
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.3835202107
Short name T2868
Test name
Test status
Simulation time 151606770 ps
CPU time 0.83 seconds
Started Aug 18 05:32:20 PM PDT 24
Finished Aug 18 05:32:21 PM PDT 24
Peak memory 207588 kb
Host smart-092d2604-d7e0-4acb-8d98-4fcb310e9b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38352
02107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3835202107
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1615863609
Short name T2776
Test name
Test status
Simulation time 233733546 ps
CPU time 1.05 seconds
Started Aug 18 05:32:31 PM PDT 24
Finished Aug 18 05:32:32 PM PDT 24
Peak memory 207524 kb
Host smart-b1ac90e0-726f-48c7-93c6-ebf6e3685f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16158
63609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1615863609
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.4177389771
Short name T3197
Test name
Test status
Simulation time 3081758187 ps
CPU time 88.39 seconds
Started Aug 18 05:32:24 PM PDT 24
Finished Aug 18 05:33:53 PM PDT 24
Peak memory 224072 kb
Host smart-5eba3027-86c1-4041-a588-1d391e066616
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4177389771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.4177389771
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1588797467
Short name T864
Test name
Test status
Simulation time 185673764 ps
CPU time 0.95 seconds
Started Aug 18 05:32:23 PM PDT 24
Finished Aug 18 05:32:24 PM PDT 24
Peak memory 207452 kb
Host smart-ace5956b-1cf5-4ac4-89a2-2adc79aced46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15887
97467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1588797467
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2787411000
Short name T3086
Test name
Test status
Simulation time 195567168 ps
CPU time 0.94 seconds
Started Aug 18 05:32:34 PM PDT 24
Finished Aug 18 05:32:35 PM PDT 24
Peak memory 207384 kb
Host smart-34d91c30-6b36-4049-94e9-346f7ee1b785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27874
11000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2787411000
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.3395555011
Short name T2377
Test name
Test status
Simulation time 1270067465 ps
CPU time 3.43 seconds
Started Aug 18 05:32:20 PM PDT 24
Finished Aug 18 05:32:24 PM PDT 24
Peak memory 207708 kb
Host smart-97ef5df9-88fb-4f14-adb1-00f5059b46c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33955
55011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.3395555011
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.1931997694
Short name T2242
Test name
Test status
Simulation time 4016846942 ps
CPU time 114.7 seconds
Started Aug 18 05:32:29 PM PDT 24
Finished Aug 18 05:34:24 PM PDT 24
Peak memory 217640 kb
Host smart-f6a3c7fe-95e9-4a85-ad30-a490b9f4d749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19319
97694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.1931997694
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2084363433
Short name T80
Test name
Test status
Simulation time 3674116572 ps
CPU time 31.58 seconds
Started Aug 18 05:32:18 PM PDT 24
Finished Aug 18 05:32:50 PM PDT 24
Peak memory 218720 kb
Host smart-322679f4-75fc-4f21-b75c-27776bd34510
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084363433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.2084363433
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.1630293578
Short name T3347
Test name
Test status
Simulation time 1147394392 ps
CPU time 26.56 seconds
Started Aug 18 05:32:11 PM PDT 24
Finished Aug 18 05:32:38 PM PDT 24
Peak memory 207692 kb
Host smart-ba4552cf-ed6f-4a70-b226-d58da1571a11
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630293578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.1630293578
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_tx_rx_disruption.2195249752
Short name T1502
Test name
Test status
Simulation time 564504813 ps
CPU time 1.53 seconds
Started Aug 18 05:32:17 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 207536 kb
Host smart-83a564e6-5804-45e0-b25e-b7abe8e6e0f2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195249752 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.usbdev_tx_rx_disruption.2195249752
Directory /workspace/3.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.3420344505
Short name T1668
Test name
Test status
Simulation time 71390851 ps
CPU time 0.71 seconds
Started Aug 18 05:36:35 PM PDT 24
Finished Aug 18 05:36:35 PM PDT 24
Peak memory 207456 kb
Host smart-5f9753df-a845-43bc-be23-b6d6e0d4802e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3420344505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3420344505
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3324231298
Short name T2269
Test name
Test status
Simulation time 11341509018 ps
CPU time 15.24 seconds
Started Aug 18 05:36:19 PM PDT 24
Finished Aug 18 05:36:35 PM PDT 24
Peak memory 207756 kb
Host smart-9a72a4ae-033b-489f-8b86-b26649ce8935
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324231298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.3324231298
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2015094014
Short name T2672
Test name
Test status
Simulation time 15981479589 ps
CPU time 21.57 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:36:53 PM PDT 24
Peak memory 215980 kb
Host smart-162b0faf-0b06-48c5-9519-1a27ae0027a8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015094014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2015094014
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.2807547434
Short name T3603
Test name
Test status
Simulation time 26411926557 ps
CPU time 30.8 seconds
Started Aug 18 05:36:20 PM PDT 24
Finished Aug 18 05:36:51 PM PDT 24
Peak memory 215928 kb
Host smart-b910e947-cea1-4e8d-9e70-de6f4d51d64d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807547434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_resume.2807547434
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1357114105
Short name T3438
Test name
Test status
Simulation time 158086650 ps
CPU time 0.85 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:36:25 PM PDT 24
Peak memory 207476 kb
Host smart-12829b9a-c00b-4a80-83be-e923726db608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13571
14105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1357114105
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.403248588
Short name T2900
Test name
Test status
Simulation time 148424340 ps
CPU time 0.86 seconds
Started Aug 18 05:36:20 PM PDT 24
Finished Aug 18 05:36:22 PM PDT 24
Peak memory 207496 kb
Host smart-da190dda-387a-4e27-b0ad-028e731c1772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40324
8588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.403248588
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.840070995
Short name T1775
Test name
Test status
Simulation time 275545756 ps
CPU time 1.08 seconds
Started Aug 18 05:36:17 PM PDT 24
Finished Aug 18 05:36:19 PM PDT 24
Peak memory 207540 kb
Host smart-bec630f6-f01a-476c-8437-5993b0ae9312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84007
0995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.840070995
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.3546656515
Short name T107
Test name
Test status
Simulation time 414870967 ps
CPU time 1.59 seconds
Started Aug 18 05:36:21 PM PDT 24
Finished Aug 18 05:36:23 PM PDT 24
Peak memory 207488 kb
Host smart-8d4488da-1835-4f03-ac0c-7466d0d3c368
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3546656515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.3546656515
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.2867829739
Short name T1308
Test name
Test status
Simulation time 39127233880 ps
CPU time 74.03 seconds
Started Aug 18 05:36:29 PM PDT 24
Finished Aug 18 05:37:43 PM PDT 24
Peak memory 207828 kb
Host smart-eaea42af-d16f-4ecf-a30b-64284e1623f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28678
29739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.2867829739
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.231136204
Short name T2078
Test name
Test status
Simulation time 296473450 ps
CPU time 4.63 seconds
Started Aug 18 05:36:20 PM PDT 24
Finished Aug 18 05:36:25 PM PDT 24
Peak memory 207728 kb
Host smart-4a8b2de6-973c-45d5-a184-76f794226dfb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231136204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.231136204
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3171740897
Short name T3331
Test name
Test status
Simulation time 657769456 ps
CPU time 1.88 seconds
Started Aug 18 05:36:27 PM PDT 24
Finished Aug 18 05:36:29 PM PDT 24
Peak memory 207492 kb
Host smart-2c880401-c3de-48da-ac9f-78ab5e153680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31717
40897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3171740897
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2798240150
Short name T909
Test name
Test status
Simulation time 145103011 ps
CPU time 0.81 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:36:24 PM PDT 24
Peak memory 207468 kb
Host smart-9e58127b-f665-486f-afe4-ffaca2e36ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27982
40150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2798240150
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.637358970
Short name T1190
Test name
Test status
Simulation time 36645027 ps
CPU time 0.72 seconds
Started Aug 18 05:36:44 PM PDT 24
Finished Aug 18 05:36:44 PM PDT 24
Peak memory 207460 kb
Host smart-51652976-ff81-4b12-869c-f61fcd31c255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63735
8970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.637358970
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.1107829768
Short name T2465
Test name
Test status
Simulation time 783989530 ps
CPU time 2.53 seconds
Started Aug 18 05:36:25 PM PDT 24
Finished Aug 18 05:36:27 PM PDT 24
Peak memory 207792 kb
Host smart-dc84a3bb-c3a5-4bff-9199-b4f0703434df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11078
29768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1107829768
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_types.1540930726
Short name T491
Test name
Test status
Simulation time 316080844 ps
CPU time 1.21 seconds
Started Aug 18 05:36:21 PM PDT 24
Finished Aug 18 05:36:22 PM PDT 24
Peak memory 207496 kb
Host smart-f11fd94c-9e0b-4e53-9301-c8bb4d77745c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1540930726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_types.1540930726
Directory /workspace/30.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.154764462
Short name T3394
Test name
Test status
Simulation time 180759415 ps
CPU time 2.08 seconds
Started Aug 18 05:36:27 PM PDT 24
Finished Aug 18 05:36:29 PM PDT 24
Peak memory 207624 kb
Host smart-a8efb726-2671-4204-a02a-56423cda657f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15476
4462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.154764462
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3058722869
Short name T3360
Test name
Test status
Simulation time 200113540 ps
CPU time 0.97 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:36:25 PM PDT 24
Peak memory 207424 kb
Host smart-eb296008-dd8c-4d2e-be35-33a2b468ab7e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3058722869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3058722869
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2623091031
Short name T3105
Test name
Test status
Simulation time 138371982 ps
CPU time 0.83 seconds
Started Aug 18 05:36:16 PM PDT 24
Finished Aug 18 05:36:17 PM PDT 24
Peak memory 207448 kb
Host smart-fe210b1a-076f-4cad-8d49-0bf1f31fba9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26230
91031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2623091031
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3940948109
Short name T1163
Test name
Test status
Simulation time 265913668 ps
CPU time 1.06 seconds
Started Aug 18 05:36:18 PM PDT 24
Finished Aug 18 05:36:20 PM PDT 24
Peak memory 207420 kb
Host smart-8deaf93b-eb29-4206-bf0b-9a51ee2d84e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39409
48109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3940948109
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.2012276792
Short name T2263
Test name
Test status
Simulation time 5219673215 ps
CPU time 39.5 seconds
Started Aug 18 05:36:25 PM PDT 24
Finished Aug 18 05:37:04 PM PDT 24
Peak memory 218268 kb
Host smart-e8ebf38e-2fed-43e8-b2bf-5fa688323e87
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2012276792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.2012276792
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.1742037126
Short name T2453
Test name
Test status
Simulation time 10816224092 ps
CPU time 131.17 seconds
Started Aug 18 05:36:21 PM PDT 24
Finished Aug 18 05:38:33 PM PDT 24
Peak memory 207756 kb
Host smart-3c017fef-1567-4197-b781-0dc14ac16099
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1742037126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.1742037126
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.4144731117
Short name T3005
Test name
Test status
Simulation time 202011080 ps
CPU time 0.96 seconds
Started Aug 18 05:36:21 PM PDT 24
Finished Aug 18 05:36:22 PM PDT 24
Peak memory 207568 kb
Host smart-db33c598-3cb9-4405-bf72-c9ec2d75f8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41447
31117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.4144731117
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.1520247277
Short name T952
Test name
Test status
Simulation time 22542289816 ps
CPU time 36.03 seconds
Started Aug 18 05:36:37 PM PDT 24
Finished Aug 18 05:37:13 PM PDT 24
Peak memory 207716 kb
Host smart-3c712ff5-0b8b-40f4-bd78-c1de7f66ff40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15202
47277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.1520247277
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.2226378585
Short name T2108
Test name
Test status
Simulation time 4486258165 ps
CPU time 6.35 seconds
Started Aug 18 05:36:07 PM PDT 24
Finished Aug 18 05:36:13 PM PDT 24
Peak memory 207808 kb
Host smart-466c7887-070d-4b87-9db9-2300b4b85012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22263
78585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.2226378585
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.2506651854
Short name T2305
Test name
Test status
Simulation time 3668683977 ps
CPU time 100.41 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:38:03 PM PDT 24
Peak memory 218348 kb
Host smart-eed64738-4bb1-4dd1-97e1-b4d62acbcb8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2506651854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.2506651854
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1760341008
Short name T1659
Test name
Test status
Simulation time 4245083250 ps
CPU time 32.83 seconds
Started Aug 18 05:36:19 PM PDT 24
Finished Aug 18 05:36:52 PM PDT 24
Peak memory 215940 kb
Host smart-648ee0c4-d00e-4686-bf57-6df65ac2225f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1760341008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1760341008
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.1066318675
Short name T3231
Test name
Test status
Simulation time 241026565 ps
CPU time 1.01 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:36:24 PM PDT 24
Peak memory 207496 kb
Host smart-ea7b5070-d4ab-4d45-9c76-c98fad157fc8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1066318675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.1066318675
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2234962400
Short name T1577
Test name
Test status
Simulation time 194176277 ps
CPU time 0.9 seconds
Started Aug 18 05:36:19 PM PDT 24
Finished Aug 18 05:36:20 PM PDT 24
Peak memory 207496 kb
Host smart-610fee12-9fe6-4c5c-9c3d-b7c09722a440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22349
62400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2234962400
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1596149499
Short name T3008
Test name
Test status
Simulation time 3819001959 ps
CPU time 106.18 seconds
Started Aug 18 05:36:27 PM PDT 24
Finished Aug 18 05:38:14 PM PDT 24
Peak memory 217600 kb
Host smart-02000afa-6626-4ae3-b5df-2c5627e64974
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1596149499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1596149499
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.2464664707
Short name T1778
Test name
Test status
Simulation time 167621121 ps
CPU time 0.88 seconds
Started Aug 18 05:36:24 PM PDT 24
Finished Aug 18 05:36:26 PM PDT 24
Peak memory 207496 kb
Host smart-6bd0a105-e319-4ae1-afd4-639f111b737a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2464664707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.2464664707
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2488738761
Short name T2371
Test name
Test status
Simulation time 183197570 ps
CPU time 0.82 seconds
Started Aug 18 05:36:16 PM PDT 24
Finished Aug 18 05:36:17 PM PDT 24
Peak memory 207484 kb
Host smart-3267d3a7-1cb4-434e-a22a-df4e169539e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24887
38761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2488738761
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2060627374
Short name T157
Test name
Test status
Simulation time 228038625 ps
CPU time 0.95 seconds
Started Aug 18 05:36:22 PM PDT 24
Finished Aug 18 05:36:23 PM PDT 24
Peak memory 207460 kb
Host smart-9a33475c-e7c1-435a-b89d-55e7f399bc44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20606
27374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2060627374
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.740378785
Short name T1889
Test name
Test status
Simulation time 164825919 ps
CPU time 0.88 seconds
Started Aug 18 05:36:22 PM PDT 24
Finished Aug 18 05:36:23 PM PDT 24
Peak memory 207484 kb
Host smart-7c3f373f-8ac8-4d1a-8e76-2c7ff9be9d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74037
8785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.740378785
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2964333312
Short name T2383
Test name
Test status
Simulation time 229551505 ps
CPU time 0.97 seconds
Started Aug 18 05:36:12 PM PDT 24
Finished Aug 18 05:36:13 PM PDT 24
Peak memory 207488 kb
Host smart-78c805bd-6abc-4485-ade4-3f71ce6450b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29643
33312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2964333312
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2835111505
Short name T1279
Test name
Test status
Simulation time 198114551 ps
CPU time 0.94 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:36:24 PM PDT 24
Peak memory 207584 kb
Host smart-38ab5ce6-ddd7-4aca-ba13-bb37820bee74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28351
11505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2835111505
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.4007750258
Short name T2125
Test name
Test status
Simulation time 179294191 ps
CPU time 0.88 seconds
Started Aug 18 05:36:09 PM PDT 24
Finished Aug 18 05:36:10 PM PDT 24
Peak memory 207536 kb
Host smart-edc8f94e-2a7c-42d2-9447-9f492e2020f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40077
50258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.4007750258
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.942416150
Short name T703
Test name
Test status
Simulation time 223709224 ps
CPU time 0.95 seconds
Started Aug 18 05:36:17 PM PDT 24
Finished Aug 18 05:36:18 PM PDT 24
Peak memory 207556 kb
Host smart-e6ebd74f-8c55-44b6-bc56-f3b698eecc58
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=942416150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.942416150
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.623756286
Short name T850
Test name
Test status
Simulation time 179390653 ps
CPU time 0.85 seconds
Started Aug 18 05:36:26 PM PDT 24
Finished Aug 18 05:36:27 PM PDT 24
Peak memory 207428 kb
Host smart-9bc67521-67d7-4c3d-9653-4015dc3451a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62375
6286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.623756286
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.849665808
Short name T1765
Test name
Test status
Simulation time 36093421 ps
CPU time 0.74 seconds
Started Aug 18 05:36:17 PM PDT 24
Finished Aug 18 05:36:18 PM PDT 24
Peak memory 207532 kb
Host smart-b57c9fa3-32b9-4789-a275-c152b7938d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84966
5808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.849665808
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.275682814
Short name T3530
Test name
Test status
Simulation time 23363128827 ps
CPU time 54.49 seconds
Started Aug 18 05:36:19 PM PDT 24
Finished Aug 18 05:37:14 PM PDT 24
Peak memory 215872 kb
Host smart-d8d42203-6b7c-4033-9a55-e07b7a2d3eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27568
2814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.275682814
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.879182220
Short name T648
Test name
Test status
Simulation time 169925372 ps
CPU time 0.88 seconds
Started Aug 18 05:36:18 PM PDT 24
Finished Aug 18 05:36:20 PM PDT 24
Peak memory 207536 kb
Host smart-f6ab8b73-e3af-44bd-aa67-c49b556ccc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87918
2220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.879182220
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.4010076396
Short name T1470
Test name
Test status
Simulation time 217012799 ps
CPU time 0.96 seconds
Started Aug 18 05:36:25 PM PDT 24
Finished Aug 18 05:36:27 PM PDT 24
Peak memory 207492 kb
Host smart-a35ab748-35bf-4ccb-b609-630aafbc7a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40100
76396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.4010076396
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.1306565066
Short name T2161
Test name
Test status
Simulation time 247022871 ps
CPU time 1.05 seconds
Started Aug 18 05:36:42 PM PDT 24
Finished Aug 18 05:36:43 PM PDT 24
Peak memory 207512 kb
Host smart-4ba3ee93-1b88-40bf-ba45-6c4670947384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13065
65066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.1306565066
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.51728873
Short name T2682
Test name
Test status
Simulation time 186877161 ps
CPU time 0.89 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:36:33 PM PDT 24
Peak memory 207492 kb
Host smart-6d570a41-731c-49d8-b280-602f14cf0a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51728
873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.51728873
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.1325689946
Short name T756
Test name
Test status
Simulation time 187021581 ps
CPU time 0.9 seconds
Started Aug 18 05:36:25 PM PDT 24
Finished Aug 18 05:36:26 PM PDT 24
Peak memory 207504 kb
Host smart-7d842cf6-32b1-4e8e-8809-0f2658d78843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13256
89946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.1325689946
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_rx_full.646092754
Short name T339
Test name
Test status
Simulation time 259994970 ps
CPU time 1.13 seconds
Started Aug 18 05:36:40 PM PDT 24
Finished Aug 18 05:36:41 PM PDT 24
Peak memory 207388 kb
Host smart-0018b5a8-3eda-4329-b3bb-e44abd911be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64609
2754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_full.646092754
Directory /workspace/30.usbdev_rx_full/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2636182822
Short name T2879
Test name
Test status
Simulation time 161221849 ps
CPU time 0.88 seconds
Started Aug 18 05:36:24 PM PDT 24
Finished Aug 18 05:36:25 PM PDT 24
Peak memory 207548 kb
Host smart-101c343a-9a32-41f6-87fa-c1905eac98c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26361
82822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2636182822
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3256484858
Short name T2582
Test name
Test status
Simulation time 168066113 ps
CPU time 0.85 seconds
Started Aug 18 05:36:29 PM PDT 24
Finished Aug 18 05:36:29 PM PDT 24
Peak memory 207500 kb
Host smart-daca31f1-40b0-4a66-a594-2e5d6d1a6ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32564
84858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3256484858
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3388832722
Short name T2415
Test name
Test status
Simulation time 233859964 ps
CPU time 1.03 seconds
Started Aug 18 05:36:22 PM PDT 24
Finished Aug 18 05:36:23 PM PDT 24
Peak memory 207496 kb
Host smart-4bdf6d1e-2316-4ff2-920e-11d6804a43d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33888
32722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3388832722
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.467669240
Short name T1053
Test name
Test status
Simulation time 3002716361 ps
CPU time 25.04 seconds
Started Aug 18 05:36:35 PM PDT 24
Finished Aug 18 05:37:00 PM PDT 24
Peak memory 217828 kb
Host smart-512f6f7c-2a7a-4f33-9985-210078ec943a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=467669240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.467669240
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1365401836
Short name T1738
Test name
Test status
Simulation time 202909605 ps
CPU time 0.91 seconds
Started Aug 18 05:36:28 PM PDT 24
Finished Aug 18 05:36:29 PM PDT 24
Peak memory 207416 kb
Host smart-4d2458f3-2bda-4385-b0a5-1ff6cad22130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13654
01836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1365401836
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3799807775
Short name T1250
Test name
Test status
Simulation time 167421902 ps
CPU time 0.87 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:36:33 PM PDT 24
Peak memory 207576 kb
Host smart-927600fc-ebc0-47f6-92d4-132760ca0b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37998
07775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3799807775
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.3819716863
Short name T809
Test name
Test status
Simulation time 210709208 ps
CPU time 0.93 seconds
Started Aug 18 05:36:19 PM PDT 24
Finished Aug 18 05:36:20 PM PDT 24
Peak memory 207496 kb
Host smart-444814ad-5981-4424-8517-447265203bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38197
16863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3819716863
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.3077781303
Short name T1382
Test name
Test status
Simulation time 2678989820 ps
CPU time 20.3 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:36:53 PM PDT 24
Peak memory 217796 kb
Host smart-f9df8a8d-87a5-4470-8215-87298b030d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30777
81303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.3077781303
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.624302068
Short name T1151
Test name
Test status
Simulation time 1152903398 ps
CPU time 26.53 seconds
Started Aug 18 05:36:18 PM PDT 24
Finished Aug 18 05:36:45 PM PDT 24
Peak memory 207628 kb
Host smart-5b8b0715-4a0a-4903-8891-02ff3c9d83cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624302068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_host
_handshake.624302068
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_tx_rx_disruption.1555614314
Short name T821
Test name
Test status
Simulation time 482060481 ps
CPU time 1.43 seconds
Started Aug 18 05:36:29 PM PDT 24
Finished Aug 18 05:36:30 PM PDT 24
Peak memory 207560 kb
Host smart-32c24060-d969-48b2-9e74-2171a4a57d59
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555614314 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.usbdev_tx_rx_disruption.1555614314
Directory /workspace/30.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/300.usbdev_tx_rx_disruption.539514321
Short name T3224
Test name
Test status
Simulation time 500225906 ps
CPU time 1.59 seconds
Started Aug 18 05:39:48 PM PDT 24
Finished Aug 18 05:39:50 PM PDT 24
Peak memory 207588 kb
Host smart-8bd58bc3-4fed-4036-a1ff-411a99db9a8e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539514321 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 300.usbdev_tx_rx_disruption.539514321
Directory /workspace/300.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/301.usbdev_tx_rx_disruption.513275384
Short name T2440
Test name
Test status
Simulation time 474686201 ps
CPU time 1.46 seconds
Started Aug 18 05:39:57 PM PDT 24
Finished Aug 18 05:39:58 PM PDT 24
Peak memory 207552 kb
Host smart-ea58c53c-1f31-4961-b93d-5f71853f7881
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513275384 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 301.usbdev_tx_rx_disruption.513275384
Directory /workspace/301.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/302.usbdev_tx_rx_disruption.467203695
Short name T2621
Test name
Test status
Simulation time 498478099 ps
CPU time 1.46 seconds
Started Aug 18 05:39:51 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207572 kb
Host smart-7db85b8e-4835-4aff-92de-108c8e788557
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467203695 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 302.usbdev_tx_rx_disruption.467203695
Directory /workspace/302.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/303.usbdev_tx_rx_disruption.4265408178
Short name T1131
Test name
Test status
Simulation time 558970478 ps
CPU time 1.69 seconds
Started Aug 18 05:40:20 PM PDT 24
Finished Aug 18 05:40:22 PM PDT 24
Peak memory 207576 kb
Host smart-245f0e16-086f-488a-bc3a-457e21b73b6c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265408178 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 303.usbdev_tx_rx_disruption.4265408178
Directory /workspace/303.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/304.usbdev_tx_rx_disruption.3812916313
Short name T802
Test name
Test status
Simulation time 647658187 ps
CPU time 1.76 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:07 PM PDT 24
Peak memory 207604 kb
Host smart-001c42ca-64ba-4e36-9425-1dae9064e079
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812916313 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 304.usbdev_tx_rx_disruption.3812916313
Directory /workspace/304.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/305.usbdev_tx_rx_disruption.1336270602
Short name T2178
Test name
Test status
Simulation time 567664665 ps
CPU time 1.56 seconds
Started Aug 18 05:39:59 PM PDT 24
Finished Aug 18 05:40:01 PM PDT 24
Peak memory 207564 kb
Host smart-dc2f0cbc-44a9-4c6d-b660-c5c7a1263c1a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336270602 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 305.usbdev_tx_rx_disruption.1336270602
Directory /workspace/305.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/306.usbdev_tx_rx_disruption.897487194
Short name T2035
Test name
Test status
Simulation time 532625753 ps
CPU time 1.56 seconds
Started Aug 18 05:39:55 PM PDT 24
Finished Aug 18 05:39:57 PM PDT 24
Peak memory 207576 kb
Host smart-48747142-7a4d-4358-8ab5-e13f822083ec
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897487194 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 306.usbdev_tx_rx_disruption.897487194
Directory /workspace/306.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/307.usbdev_tx_rx_disruption.3050779085
Short name T2552
Test name
Test status
Simulation time 434735985 ps
CPU time 1.47 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:01 PM PDT 24
Peak memory 207588 kb
Host smart-93609fbd-8d06-4859-bccd-0d46308156d1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050779085 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 307.usbdev_tx_rx_disruption.3050779085
Directory /workspace/307.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/308.usbdev_tx_rx_disruption.1450042236
Short name T2360
Test name
Test status
Simulation time 460248415 ps
CPU time 1.54 seconds
Started Aug 18 05:39:47 PM PDT 24
Finished Aug 18 05:39:49 PM PDT 24
Peak memory 207560 kb
Host smart-d88f31c9-78be-410c-825e-833ea973e886
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450042236 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 308.usbdev_tx_rx_disruption.1450042236
Directory /workspace/308.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/309.usbdev_tx_rx_disruption.620520521
Short name T865
Test name
Test status
Simulation time 548177534 ps
CPU time 1.6 seconds
Started Aug 18 05:39:55 PM PDT 24
Finished Aug 18 05:39:56 PM PDT 24
Peak memory 207552 kb
Host smart-0f9a796c-4260-4f24-9e9c-ff42999fe283
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620520521 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 309.usbdev_tx_rx_disruption.620520521
Directory /workspace/309.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.1061202955
Short name T234
Test name
Test status
Simulation time 44471110 ps
CPU time 0.68 seconds
Started Aug 18 05:36:47 PM PDT 24
Finished Aug 18 05:36:48 PM PDT 24
Peak memory 207192 kb
Host smart-9e6ca72a-1c46-406a-9b82-ae957c972627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1061202955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.1061202955
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3924655416
Short name T246
Test name
Test status
Simulation time 4071186615 ps
CPU time 6.4 seconds
Started Aug 18 05:36:30 PM PDT 24
Finished Aug 18 05:36:37 PM PDT 24
Peak memory 216008 kb
Host smart-e2f1b7e2-a54d-47ae-8105-37eda626e5a4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924655416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.3924655416
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2442988158
Short name T2322
Test name
Test status
Simulation time 21315367604 ps
CPU time 25.83 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:36:49 PM PDT 24
Peak memory 207824 kb
Host smart-35a97880-95fa-4d11-98bb-caedf6226193
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442988158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2442988158
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.613042124
Short name T235
Test name
Test status
Simulation time 24676578470 ps
CPU time 28.15 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:37:01 PM PDT 24
Peak memory 216008 kb
Host smart-8dc73d5a-ccbe-4aae-a8ee-01e8f344850e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613042124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_ao
n_wake_resume.613042124
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.724965618
Short name T3063
Test name
Test status
Simulation time 156192453 ps
CPU time 0.86 seconds
Started Aug 18 05:36:36 PM PDT 24
Finished Aug 18 05:36:37 PM PDT 24
Peak memory 207456 kb
Host smart-3f99d1bf-cd66-4b85-b550-8fc040998570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72496
5618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.724965618
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.881458240
Short name T804
Test name
Test status
Simulation time 152406583 ps
CPU time 0.86 seconds
Started Aug 18 05:36:29 PM PDT 24
Finished Aug 18 05:36:30 PM PDT 24
Peak memory 207456 kb
Host smart-2f9a4f49-602b-4241-8cf8-f0c7ae65c9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88145
8240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.881458240
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.578455854
Short name T2762
Test name
Test status
Simulation time 219494336 ps
CPU time 1.04 seconds
Started Aug 18 05:36:52 PM PDT 24
Finished Aug 18 05:36:53 PM PDT 24
Peak memory 207472 kb
Host smart-b2d45138-7e33-4472-92fd-332c4e3f2fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57845
5854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.578455854
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3735975553
Short name T1291
Test name
Test status
Simulation time 1334179980 ps
CPU time 3.31 seconds
Started Aug 18 05:36:43 PM PDT 24
Finished Aug 18 05:36:46 PM PDT 24
Peak memory 207680 kb
Host smart-bfa97cc6-fa84-42ae-a347-543d5f159fe4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3735975553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3735975553
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.123316831
Short name T1896
Test name
Test status
Simulation time 22287369775 ps
CPU time 36.1 seconds
Started Aug 18 05:36:20 PM PDT 24
Finished Aug 18 05:36:56 PM PDT 24
Peak memory 207760 kb
Host smart-8219c41a-d932-40bd-adc6-26ac92d81733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12331
6831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.123316831
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.2472481325
Short name T964
Test name
Test status
Simulation time 1574539227 ps
CPU time 12.88 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:36:36 PM PDT 24
Peak memory 207748 kb
Host smart-c6a445f8-4b58-4833-8208-f89e51b208f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472481325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.2472481325
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.585766442
Short name T3547
Test name
Test status
Simulation time 572058742 ps
CPU time 1.56 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:36:34 PM PDT 24
Peak memory 207540 kb
Host smart-1773b6d3-a7d2-4dda-abdc-4bc3ee728a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58576
6442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.585766442
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.114664780
Short name T56
Test name
Test status
Simulation time 140547471 ps
CPU time 0.83 seconds
Started Aug 18 05:36:33 PM PDT 24
Finished Aug 18 05:36:34 PM PDT 24
Peak memory 207552 kb
Host smart-2b298a5f-28ca-426b-937f-2482bf169106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11466
4780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.114664780
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.4192327544
Short name T3290
Test name
Test status
Simulation time 46166823 ps
CPU time 0.75 seconds
Started Aug 18 05:36:33 PM PDT 24
Finished Aug 18 05:36:34 PM PDT 24
Peak memory 207464 kb
Host smart-fb774279-b8c3-489a-b08f-4a5a2a7bdc06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41923
27544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.4192327544
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3845594977
Short name T3019
Test name
Test status
Simulation time 963762070 ps
CPU time 2.4 seconds
Started Aug 18 05:36:53 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207732 kb
Host smart-f6637199-ff02-4bc7-916b-7db8a49bdac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38455
94977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3845594977
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_types.2349480092
Short name T3497
Test name
Test status
Simulation time 438019016 ps
CPU time 1.31 seconds
Started Aug 18 05:36:43 PM PDT 24
Finished Aug 18 05:36:45 PM PDT 24
Peak memory 207524 kb
Host smart-8b1af5a1-28df-41b5-957b-78a13e7e442c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2349480092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.2349480092
Directory /workspace/31.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3418541986
Short name T2657
Test name
Test status
Simulation time 220343716 ps
CPU time 1.46 seconds
Started Aug 18 05:36:31 PM PDT 24
Finished Aug 18 05:36:32 PM PDT 24
Peak memory 207556 kb
Host smart-3bd2c6c0-f188-4888-b1ba-272a16e0a383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34185
41986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3418541986
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1686679159
Short name T2007
Test name
Test status
Simulation time 268565894 ps
CPU time 1.18 seconds
Started Aug 18 05:36:24 PM PDT 24
Finished Aug 18 05:36:25 PM PDT 24
Peak memory 215900 kb
Host smart-81bf48cf-aa4b-4f1c-b2c5-71516a7312d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1686679159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1686679159
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.760448468
Short name T1520
Test name
Test status
Simulation time 141286264 ps
CPU time 0.83 seconds
Started Aug 18 05:36:22 PM PDT 24
Finished Aug 18 05:36:23 PM PDT 24
Peak memory 207456 kb
Host smart-de4ede06-6040-482a-9ac3-904dd0928a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76044
8468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.760448468
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2275580686
Short name T2356
Test name
Test status
Simulation time 241769081 ps
CPU time 1 seconds
Started Aug 18 05:36:31 PM PDT 24
Finished Aug 18 05:36:32 PM PDT 24
Peak memory 207460 kb
Host smart-44f68405-c788-4a8b-94d1-086198ab9400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22755
80686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2275580686
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.3219409150
Short name T959
Test name
Test status
Simulation time 2700257884 ps
CPU time 18.98 seconds
Started Aug 18 05:36:29 PM PDT 24
Finished Aug 18 05:36:48 PM PDT 24
Peak memory 218136 kb
Host smart-fa4220d4-f60a-425e-a545-42424a2c135d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3219409150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.3219409150
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.436493432
Short name T2772
Test name
Test status
Simulation time 6799358476 ps
CPU time 81.43 seconds
Started Aug 18 05:36:22 PM PDT 24
Finished Aug 18 05:37:44 PM PDT 24
Peak memory 207800 kb
Host smart-f8e82d33-ac60-4338-ac72-454dd2af8564
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=436493432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.436493432
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.82412555
Short name T3283
Test name
Test status
Simulation time 236207292 ps
CPU time 0.97 seconds
Started Aug 18 05:36:44 PM PDT 24
Finished Aug 18 05:36:45 PM PDT 24
Peak memory 207464 kb
Host smart-c98f5191-b871-455e-9762-08d72dfaf88b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82412
555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.82412555
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.2125265190
Short name T1699
Test name
Test status
Simulation time 12739366834 ps
CPU time 20.27 seconds
Started Aug 18 05:36:44 PM PDT 24
Finished Aug 18 05:37:04 PM PDT 24
Peak memory 207748 kb
Host smart-28f1096b-2f22-4d47-b949-eeb0162a3495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21252
65190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.2125265190
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2513175165
Short name T2124
Test name
Test status
Simulation time 5724212451 ps
CPU time 8.2 seconds
Started Aug 18 05:36:24 PM PDT 24
Finished Aug 18 05:36:33 PM PDT 24
Peak memory 216112 kb
Host smart-6b17fe51-2fb8-4525-a0c8-50d80616e1b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25131
75165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2513175165
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1528595661
Short name T2813
Test name
Test status
Simulation time 3471896913 ps
CPU time 26.62 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:36:50 PM PDT 24
Peak memory 216000 kb
Host smart-e8b6ff68-3c6d-460e-89ad-5e0483a388cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1528595661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1528595661
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.505012694
Short name T3274
Test name
Test status
Simulation time 3926072787 ps
CPU time 37.36 seconds
Started Aug 18 05:36:27 PM PDT 24
Finished Aug 18 05:37:04 PM PDT 24
Peak memory 215904 kb
Host smart-bf721b7e-6fe7-418a-8830-0ad8ada6f148
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=505012694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.505012694
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.3564836371
Short name T2784
Test name
Test status
Simulation time 241449015 ps
CPU time 1.03 seconds
Started Aug 18 05:36:46 PM PDT 24
Finished Aug 18 05:36:48 PM PDT 24
Peak memory 207500 kb
Host smart-be3560eb-f45f-43c8-8182-242591efb044
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3564836371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.3564836371
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2869495814
Short name T1337
Test name
Test status
Simulation time 200432602 ps
CPU time 1 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:36:33 PM PDT 24
Peak memory 207220 kb
Host smart-f2dbf0fe-facd-4005-9deb-cb0b4a4f333b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28694
95814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2869495814
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.1988286835
Short name T1025
Test name
Test status
Simulation time 2677110413 ps
CPU time 21.12 seconds
Started Aug 18 05:36:29 PM PDT 24
Finished Aug 18 05:36:50 PM PDT 24
Peak memory 217532 kb
Host smart-5f02be67-7c8a-4306-bada-2c3a824a92e6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1988286835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.1988286835
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.978788554
Short name T3576
Test name
Test status
Simulation time 179023893 ps
CPU time 0.93 seconds
Started Aug 18 05:36:34 PM PDT 24
Finished Aug 18 05:36:35 PM PDT 24
Peak memory 207496 kb
Host smart-59b0aee2-fa10-4e06-b5b5-5cabbcd3fcbc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=978788554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.978788554
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2564324105
Short name T861
Test name
Test status
Simulation time 168947693 ps
CPU time 0.87 seconds
Started Aug 18 05:36:43 PM PDT 24
Finished Aug 18 05:36:44 PM PDT 24
Peak memory 207500 kb
Host smart-fdbd12c7-7500-4394-84be-7ba1e881724e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25643
24105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2564324105
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.4162058960
Short name T1653
Test name
Test status
Simulation time 210258000 ps
CPU time 0.96 seconds
Started Aug 18 05:36:59 PM PDT 24
Finished Aug 18 05:37:00 PM PDT 24
Peak memory 207460 kb
Host smart-0a39efae-9de6-40a0-bf54-ac6f1744bed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41620
58960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.4162058960
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.2653850411
Short name T922
Test name
Test status
Simulation time 164378080 ps
CPU time 0.86 seconds
Started Aug 18 05:36:28 PM PDT 24
Finished Aug 18 05:36:29 PM PDT 24
Peak memory 207456 kb
Host smart-b290933c-bbe0-4b30-8707-6928a212ea18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26538
50411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.2653850411
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2125308260
Short name T2706
Test name
Test status
Simulation time 172519661 ps
CPU time 0.98 seconds
Started Aug 18 05:36:25 PM PDT 24
Finished Aug 18 05:36:26 PM PDT 24
Peak memory 207492 kb
Host smart-136c664f-4ad4-48b0-929a-0f13318c1455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21253
08260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2125308260
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.828232145
Short name T1515
Test name
Test status
Simulation time 187277329 ps
CPU time 0.91 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:36:24 PM PDT 24
Peak memory 207544 kb
Host smart-3adb4535-4755-459e-8a1e-8f6735c41bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82823
2145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.828232145
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.260531172
Short name T1727
Test name
Test status
Simulation time 155981385 ps
CPU time 0.82 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:36:24 PM PDT 24
Peak memory 207548 kb
Host smart-1a30a405-2d38-4190-b2aa-b3e7431efa2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26053
1172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.260531172
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.2137827675
Short name T3475
Test name
Test status
Simulation time 232573465 ps
CPU time 0.97 seconds
Started Aug 18 05:36:35 PM PDT 24
Finished Aug 18 05:36:36 PM PDT 24
Peak memory 207320 kb
Host smart-e8b366c8-faf3-49b5-b0ed-436e16e2a176
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2137827675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.2137827675
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3493957883
Short name T1281
Test name
Test status
Simulation time 227984880 ps
CPU time 0.95 seconds
Started Aug 18 05:36:39 PM PDT 24
Finished Aug 18 05:36:41 PM PDT 24
Peak memory 207208 kb
Host smart-58d82cb1-f335-4135-a5a6-068c18e3f33d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34939
57883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3493957883
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.231395389
Short name T1453
Test name
Test status
Simulation time 39123865 ps
CPU time 0.7 seconds
Started Aug 18 05:36:25 PM PDT 24
Finished Aug 18 05:36:26 PM PDT 24
Peak memory 207548 kb
Host smart-1dd78ff1-a542-4451-b69c-909041f35a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23139
5389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.231395389
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1582857267
Short name T3089
Test name
Test status
Simulation time 12815457277 ps
CPU time 32.72 seconds
Started Aug 18 05:36:36 PM PDT 24
Finished Aug 18 05:37:09 PM PDT 24
Peak memory 215916 kb
Host smart-df10bdee-b44c-4e03-8e6e-2fb75229b6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15828
57267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1582857267
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.3701015104
Short name T2707
Test name
Test status
Simulation time 201251053 ps
CPU time 0.91 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:36:33 PM PDT 24
Peak memory 207572 kb
Host smart-28f2f4e5-bf23-428a-a626-6405aeff77cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37010
15104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3701015104
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.3336734270
Short name T1230
Test name
Test status
Simulation time 224540156 ps
CPU time 0.97 seconds
Started Aug 18 05:36:24 PM PDT 24
Finished Aug 18 05:36:25 PM PDT 24
Peak memory 207460 kb
Host smart-3c1e8b20-aa3d-4a9d-a6e2-73a119e1ac6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33367
34270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.3336734270
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.3064083515
Short name T544
Test name
Test status
Simulation time 180512372 ps
CPU time 0.87 seconds
Started Aug 18 05:36:19 PM PDT 24
Finished Aug 18 05:36:20 PM PDT 24
Peak memory 207492 kb
Host smart-04907252-a327-4eb1-a139-f84aed88d033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30640
83515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.3064083515
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.2725802865
Short name T1581
Test name
Test status
Simulation time 178200947 ps
CPU time 0.88 seconds
Started Aug 18 05:36:39 PM PDT 24
Finished Aug 18 05:36:39 PM PDT 24
Peak memory 207504 kb
Host smart-caee2095-2c7b-436d-b3c2-44f6dca97bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27258
02865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.2725802865
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2574503275
Short name T2944
Test name
Test status
Simulation time 199812245 ps
CPU time 0.88 seconds
Started Aug 18 05:36:24 PM PDT 24
Finished Aug 18 05:36:25 PM PDT 24
Peak memory 207488 kb
Host smart-8c950cce-3045-43b0-89f5-980e8fd25b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25745
03275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2574503275
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_rx_full.1313411669
Short name T2989
Test name
Test status
Simulation time 256472039 ps
CPU time 1.11 seconds
Started Aug 18 05:36:47 PM PDT 24
Finished Aug 18 05:36:49 PM PDT 24
Peak memory 207488 kb
Host smart-6f478eaf-4c95-4acd-9c0b-9d6e3fee03a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13134
11669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_full.1313411669
Directory /workspace/31.usbdev_rx_full/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.4156531271
Short name T2848
Test name
Test status
Simulation time 158248055 ps
CPU time 0.85 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:36:33 PM PDT 24
Peak memory 207548 kb
Host smart-5b22f365-ed82-47b8-8f5a-5e396008bc2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41565
31271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.4156531271
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3678653676
Short name T2344
Test name
Test status
Simulation time 149383468 ps
CPU time 0.84 seconds
Started Aug 18 05:36:29 PM PDT 24
Finished Aug 18 05:36:30 PM PDT 24
Peak memory 207400 kb
Host smart-fe0477dc-3560-4212-9c62-42287a58494f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36786
53676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3678653676
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2554698126
Short name T3154
Test name
Test status
Simulation time 261177891 ps
CPU time 1 seconds
Started Aug 18 05:36:30 PM PDT 24
Finished Aug 18 05:36:31 PM PDT 24
Peak memory 207468 kb
Host smart-e76f5fbf-b470-4bde-82c0-8298f22ac6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25546
98126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2554698126
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.3675316065
Short name T2336
Test name
Test status
Simulation time 2030249873 ps
CPU time 59.07 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:37:23 PM PDT 24
Peak memory 215824 kb
Host smart-19f67b44-751d-4300-905b-77df221c8812
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3675316065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.3675316065
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1450526457
Short name T2945
Test name
Test status
Simulation time 177654046 ps
CPU time 0.88 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:36:33 PM PDT 24
Peak memory 207408 kb
Host smart-58c8e2bc-9fa5-4a91-aaf1-8966004c178a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14505
26457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1450526457
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.325405225
Short name T1709
Test name
Test status
Simulation time 181049200 ps
CPU time 0.87 seconds
Started Aug 18 05:36:43 PM PDT 24
Finished Aug 18 05:36:44 PM PDT 24
Peak memory 207412 kb
Host smart-dea4832c-2e18-4177-90c3-971619ec8858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32540
5225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.325405225
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.3731158009
Short name T1049
Test name
Test status
Simulation time 448454493 ps
CPU time 1.43 seconds
Started Aug 18 05:36:29 PM PDT 24
Finished Aug 18 05:36:30 PM PDT 24
Peak memory 207532 kb
Host smart-406256ad-6ab4-4f84-a2a2-eb0adb454382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37311
58009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.3731158009
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.3804678072
Short name T900
Test name
Test status
Simulation time 2964070597 ps
CPU time 29.02 seconds
Started Aug 18 05:37:00 PM PDT 24
Finished Aug 18 05:37:29 PM PDT 24
Peak memory 216696 kb
Host smart-82db7f64-58d5-4e42-b64f-4e4e50374df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38046
78072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.3804678072
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.631299786
Short name T1379
Test name
Test status
Simulation time 6713303222 ps
CPU time 47.52 seconds
Started Aug 18 05:36:27 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 207700 kb
Host smart-41d1dd0d-0b42-4cd6-99cf-4e7fa53b0a5d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631299786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_host
_handshake.631299786
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_tx_rx_disruption.534674187
Short name T2351
Test name
Test status
Simulation time 531591625 ps
CPU time 1.54 seconds
Started Aug 18 05:36:34 PM PDT 24
Finished Aug 18 05:36:36 PM PDT 24
Peak memory 207316 kb
Host smart-9b60c93a-d6eb-43bf-8c44-fc57c93b7324
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534674187 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.usbdev_tx_rx_disruption.534674187
Directory /workspace/31.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/310.usbdev_tx_rx_disruption.1493052181
Short name T3399
Test name
Test status
Simulation time 547491399 ps
CPU time 1.65 seconds
Started Aug 18 05:39:54 PM PDT 24
Finished Aug 18 05:39:56 PM PDT 24
Peak memory 207488 kb
Host smart-3914cd9d-ebd5-46b3-9322-20250dede965
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493052181 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 310.usbdev_tx_rx_disruption.1493052181
Directory /workspace/310.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/311.usbdev_tx_rx_disruption.1812405243
Short name T1120
Test name
Test status
Simulation time 582568486 ps
CPU time 1.85 seconds
Started Aug 18 05:39:56 PM PDT 24
Finished Aug 18 05:39:58 PM PDT 24
Peak memory 207552 kb
Host smart-1d64f0e2-9969-4c38-8db1-a19324511888
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812405243 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 311.usbdev_tx_rx_disruption.1812405243
Directory /workspace/311.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/312.usbdev_tx_rx_disruption.677861675
Short name T1810
Test name
Test status
Simulation time 582602529 ps
CPU time 1.64 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:01 PM PDT 24
Peak memory 207564 kb
Host smart-6cc6227b-f734-461a-893e-8beb044d971e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677861675 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 312.usbdev_tx_rx_disruption.677861675
Directory /workspace/312.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/313.usbdev_tx_rx_disruption.1615535217
Short name T1706
Test name
Test status
Simulation time 454198773 ps
CPU time 1.37 seconds
Started Aug 18 05:39:46 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207580 kb
Host smart-8b33d9fc-7f1f-4b5c-aa8d-cfbef0519d2c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615535217 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 313.usbdev_tx_rx_disruption.1615535217
Directory /workspace/313.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/314.usbdev_tx_rx_disruption.2103230511
Short name T2650
Test name
Test status
Simulation time 551984637 ps
CPU time 1.61 seconds
Started Aug 18 05:39:55 PM PDT 24
Finished Aug 18 05:39:57 PM PDT 24
Peak memory 207588 kb
Host smart-df020af7-56cd-45dc-bcea-2eddfacef246
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103230511 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 314.usbdev_tx_rx_disruption.2103230511
Directory /workspace/314.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/315.usbdev_tx_rx_disruption.1960149132
Short name T2577
Test name
Test status
Simulation time 603788145 ps
CPU time 1.6 seconds
Started Aug 18 05:39:53 PM PDT 24
Finished Aug 18 05:39:55 PM PDT 24
Peak memory 207512 kb
Host smart-7c284eff-92b2-4f72-881e-16702fc57b38
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960149132 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 315.usbdev_tx_rx_disruption.1960149132
Directory /workspace/315.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/316.usbdev_tx_rx_disruption.3503504882
Short name T958
Test name
Test status
Simulation time 459820186 ps
CPU time 1.44 seconds
Started Aug 18 05:40:21 PM PDT 24
Finished Aug 18 05:40:23 PM PDT 24
Peak memory 207552 kb
Host smart-20eac45f-6a59-43c2-836f-367fa9a6818b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503504882 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 316.usbdev_tx_rx_disruption.3503504882
Directory /workspace/316.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/317.usbdev_tx_rx_disruption.2953039892
Short name T2472
Test name
Test status
Simulation time 596459656 ps
CPU time 1.66 seconds
Started Aug 18 05:39:50 PM PDT 24
Finished Aug 18 05:39:51 PM PDT 24
Peak memory 207544 kb
Host smart-7362c31f-926f-4624-8e30-9085035844de
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953039892 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 317.usbdev_tx_rx_disruption.2953039892
Directory /workspace/317.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/318.usbdev_tx_rx_disruption.2391330976
Short name T1900
Test name
Test status
Simulation time 584964695 ps
CPU time 1.61 seconds
Started Aug 18 05:40:17 PM PDT 24
Finished Aug 18 05:40:19 PM PDT 24
Peak memory 207552 kb
Host smart-a9dad336-c862-4526-875a-0a6868e45cdb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391330976 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 318.usbdev_tx_rx_disruption.2391330976
Directory /workspace/318.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/319.usbdev_tx_rx_disruption.2266902664
Short name T1043
Test name
Test status
Simulation time 540744595 ps
CPU time 1.66 seconds
Started Aug 18 05:39:56 PM PDT 24
Finished Aug 18 05:39:58 PM PDT 24
Peak memory 207572 kb
Host smart-0f2991e1-342f-4bbe-ba50-4d8bfccf9009
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266902664 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 319.usbdev_tx_rx_disruption.2266902664
Directory /workspace/319.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.3528091102
Short name T3020
Test name
Test status
Simulation time 36170514 ps
CPU time 0.68 seconds
Started Aug 18 05:36:30 PM PDT 24
Finished Aug 18 05:36:31 PM PDT 24
Peak memory 207444 kb
Host smart-4377195a-8a36-4bd3-b9dc-3c761896ca39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3528091102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.3528091102
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.1679635920
Short name T1089
Test name
Test status
Simulation time 11910990914 ps
CPU time 15.04 seconds
Started Aug 18 05:36:44 PM PDT 24
Finished Aug 18 05:36:59 PM PDT 24
Peak memory 207812 kb
Host smart-4741d3b2-e63f-43bf-babb-604c62ff8a15
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679635920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.1679635920
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.2526906861
Short name T3095
Test name
Test status
Simulation time 21127036368 ps
CPU time 29.2 seconds
Started Aug 18 05:36:28 PM PDT 24
Finished Aug 18 05:36:58 PM PDT 24
Peak memory 207808 kb
Host smart-880871c5-9785-489f-96e2-158ecf15825f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526906861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.2526906861
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3398268145
Short name T3456
Test name
Test status
Simulation time 29716255292 ps
CPU time 40.58 seconds
Started Aug 18 05:36:21 PM PDT 24
Finished Aug 18 05:37:02 PM PDT 24
Peak memory 207856 kb
Host smart-daaac11e-795c-47c8-8ea3-2f573c1964a1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398268145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.3398268145
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.4211353343
Short name T1006
Test name
Test status
Simulation time 163040991 ps
CPU time 0.86 seconds
Started Aug 18 05:36:27 PM PDT 24
Finished Aug 18 05:36:28 PM PDT 24
Peak memory 207508 kb
Host smart-ce8850d6-0099-4e2c-9a75-8ac65c3f1e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42113
53343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.4211353343
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2688797311
Short name T740
Test name
Test status
Simulation time 139130217 ps
CPU time 0.85 seconds
Started Aug 18 05:36:37 PM PDT 24
Finished Aug 18 05:36:38 PM PDT 24
Peak memory 207508 kb
Host smart-a02a7ca4-3f95-42ce-a061-552816ba54b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26887
97311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2688797311
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.2322353091
Short name T1637
Test name
Test status
Simulation time 405297631 ps
CPU time 1.54 seconds
Started Aug 18 05:36:27 PM PDT 24
Finished Aug 18 05:36:28 PM PDT 24
Peak memory 207488 kb
Host smart-af3e6d47-1c4a-43a9-b5d0-2e51c2dffa02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23223
53091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.2322353091
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.4094062327
Short name T3343
Test name
Test status
Simulation time 900927667 ps
CPU time 2.41 seconds
Started Aug 18 05:36:48 PM PDT 24
Finished Aug 18 05:36:51 PM PDT 24
Peak memory 207684 kb
Host smart-9fd85607-46c6-42f4-af35-1c05603be24a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4094062327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.4094062327
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.870473111
Short name T3550
Test name
Test status
Simulation time 45379713508 ps
CPU time 74.1 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:37:37 PM PDT 24
Peak memory 207800 kb
Host smart-64e77cb4-6de1-4ea8-ab21-1398d4a133cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87047
3111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.870473111
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.935404898
Short name T1912
Test name
Test status
Simulation time 2011086634 ps
CPU time 17.58 seconds
Started Aug 18 05:36:33 PM PDT 24
Finished Aug 18 05:36:51 PM PDT 24
Peak memory 207732 kb
Host smart-ab25504b-7dff-4dfe-aa8b-3a2ae0555fd8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935404898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.935404898
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.4152274876
Short name T3006
Test name
Test status
Simulation time 692708743 ps
CPU time 1.7 seconds
Started Aug 18 05:36:44 PM PDT 24
Finished Aug 18 05:36:46 PM PDT 24
Peak memory 207536 kb
Host smart-c814efb2-6189-4c0c-9e21-1830f4fa5074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41522
74876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.4152274876
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.64232365
Short name T33
Test name
Test status
Simulation time 170106334 ps
CPU time 0.94 seconds
Started Aug 18 05:36:35 PM PDT 24
Finished Aug 18 05:36:36 PM PDT 24
Peak memory 207464 kb
Host smart-5edbd34e-d92f-471e-9da4-c8d2448b6dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64232
365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.64232365
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.4323463
Short name T1770
Test name
Test status
Simulation time 37442062 ps
CPU time 0.67 seconds
Started Aug 18 05:36:28 PM PDT 24
Finished Aug 18 05:36:28 PM PDT 24
Peak memory 207440 kb
Host smart-e8545b6f-8b1f-41ea-8648-e8aa39f6c05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43234
63 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.4323463
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.2526451885
Short name T3057
Test name
Test status
Simulation time 931127965 ps
CPU time 2.46 seconds
Started Aug 18 05:36:36 PM PDT 24
Finished Aug 18 05:36:39 PM PDT 24
Peak memory 207808 kb
Host smart-aab99ae3-6c60-466b-98b7-5f20f8122d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25264
51885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.2526451885
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_types.1593956430
Short name T1930
Test name
Test status
Simulation time 362438593 ps
CPU time 1.17 seconds
Started Aug 18 05:36:21 PM PDT 24
Finished Aug 18 05:36:22 PM PDT 24
Peak memory 207524 kb
Host smart-a688dd34-2a10-4432-b703-7fd076e22ea9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1593956430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_types.1593956430
Directory /workspace/32.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2549835144
Short name T2029
Test name
Test status
Simulation time 239269966 ps
CPU time 1.67 seconds
Started Aug 18 05:36:23 PM PDT 24
Finished Aug 18 05:36:25 PM PDT 24
Peak memory 207668 kb
Host smart-7842e3ee-573a-4c1a-9896-e273e87b42bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25498
35144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2549835144
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.2710073330
Short name T3601
Test name
Test status
Simulation time 186380281 ps
CPU time 1.01 seconds
Started Aug 18 05:36:59 PM PDT 24
Finished Aug 18 05:37:00 PM PDT 24
Peak memory 215836 kb
Host smart-9ec0f462-9ce1-4284-bdf0-baf683438f1b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2710073330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2710073330
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2300727609
Short name T2049
Test name
Test status
Simulation time 148470808 ps
CPU time 0.81 seconds
Started Aug 18 05:36:39 PM PDT 24
Finished Aug 18 05:36:40 PM PDT 24
Peak memory 207448 kb
Host smart-1d904280-f587-4366-93f6-76fbc201a104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23007
27609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2300727609
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1829784944
Short name T2745
Test name
Test status
Simulation time 173088145 ps
CPU time 0.86 seconds
Started Aug 18 05:36:24 PM PDT 24
Finished Aug 18 05:36:26 PM PDT 24
Peak memory 207504 kb
Host smart-12fea101-0572-4849-bf2e-02f69b3fa98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18297
84944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1829784944
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.112771681
Short name T1639
Test name
Test status
Simulation time 3076540604 ps
CPU time 87.94 seconds
Started Aug 18 05:36:34 PM PDT 24
Finished Aug 18 05:38:02 PM PDT 24
Peak memory 224056 kb
Host smart-63cee5c4-5a68-45c7-bb09-442362eff35c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=112771681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.112771681
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.2306715578
Short name T298
Test name
Test status
Simulation time 12195200010 ps
CPU time 146.11 seconds
Started Aug 18 05:36:27 PM PDT 24
Finished Aug 18 05:38:53 PM PDT 24
Peak memory 207708 kb
Host smart-3e67d33d-e091-4dea-9b7a-9fcc5e47aa51
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2306715578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.2306715578
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1463237090
Short name T3311
Test name
Test status
Simulation time 184823085 ps
CPU time 0.94 seconds
Started Aug 18 05:36:33 PM PDT 24
Finished Aug 18 05:36:34 PM PDT 24
Peak memory 207552 kb
Host smart-e037e6ef-067c-44ee-9865-611df4489fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14632
37090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1463237090
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.3306577496
Short name T2084
Test name
Test status
Simulation time 8402678547 ps
CPU time 15.09 seconds
Started Aug 18 05:36:39 PM PDT 24
Finished Aug 18 05:36:54 PM PDT 24
Peak memory 207764 kb
Host smart-1821e0bd-5b33-4e49-b6b5-f65f95b9b5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33065
77496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.3306577496
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.4171326771
Short name T1644
Test name
Test status
Simulation time 11144640404 ps
CPU time 16.07 seconds
Started Aug 18 05:36:52 PM PDT 24
Finished Aug 18 05:37:08 PM PDT 24
Peak memory 207836 kb
Host smart-8579577e-4c85-4f77-a5e0-1db6f1f95261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41713
26771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.4171326771
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.1731231945
Short name T2246
Test name
Test status
Simulation time 4713189633 ps
CPU time 48.23 seconds
Started Aug 18 05:36:51 PM PDT 24
Finished Aug 18 05:37:40 PM PDT 24
Peak memory 218468 kb
Host smart-79af9766-d742-4475-9a63-5f62055b9a21
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1731231945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.1731231945
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.4081783915
Short name T3504
Test name
Test status
Simulation time 2148783168 ps
CPU time 20.43 seconds
Started Aug 18 05:36:38 PM PDT 24
Finished Aug 18 05:36:59 PM PDT 24
Peak memory 217368 kb
Host smart-6e1a9645-71e2-4e27-ade2-0f0471695b9c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4081783915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.4081783915
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.817297654
Short name T1507
Test name
Test status
Simulation time 243937444 ps
CPU time 1 seconds
Started Aug 18 05:36:31 PM PDT 24
Finished Aug 18 05:36:32 PM PDT 24
Peak memory 207472 kb
Host smart-734aebe1-e616-4902-b4a2-c94028a2ce77
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=817297654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.817297654
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3270779060
Short name T1227
Test name
Test status
Simulation time 191369333 ps
CPU time 0.9 seconds
Started Aug 18 05:36:24 PM PDT 24
Finished Aug 18 05:36:26 PM PDT 24
Peak memory 207368 kb
Host smart-4502fb32-9795-4345-87f5-4d142cec370e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32707
79060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3270779060
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.731757137
Short name T1954
Test name
Test status
Simulation time 2449863507 ps
CPU time 18.99 seconds
Started Aug 18 05:36:31 PM PDT 24
Finished Aug 18 05:36:50 PM PDT 24
Peak memory 217604 kb
Host smart-90fe63b0-a2bf-437b-a6b6-f223363d596a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=731757137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.731757137
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.2823748079
Short name T3571
Test name
Test status
Simulation time 155639976 ps
CPU time 0.92 seconds
Started Aug 18 05:36:56 PM PDT 24
Finished Aug 18 05:36:57 PM PDT 24
Peak memory 207424 kb
Host smart-cdfd9b18-fd6c-432a-80aa-cda15d3c7fb6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2823748079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.2823748079
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.129321876
Short name T2323
Test name
Test status
Simulation time 153237128 ps
CPU time 0.86 seconds
Started Aug 18 05:36:49 PM PDT 24
Finished Aug 18 05:36:50 PM PDT 24
Peak memory 207500 kb
Host smart-365c7725-0d5b-49df-b60d-a73ab3e5d6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12932
1876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.129321876
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2703851023
Short name T3441
Test name
Test status
Simulation time 209275340 ps
CPU time 0.94 seconds
Started Aug 18 05:36:36 PM PDT 24
Finished Aug 18 05:36:37 PM PDT 24
Peak memory 207480 kb
Host smart-276840f8-7431-40c1-8432-eeb29e250228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27038
51023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2703851023
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.2770966405
Short name T1191
Test name
Test status
Simulation time 202607824 ps
CPU time 0.98 seconds
Started Aug 18 05:36:45 PM PDT 24
Finished Aug 18 05:36:47 PM PDT 24
Peak memory 207480 kb
Host smart-41b0ca95-94b2-4134-9699-e8a462996509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27709
66405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.2770966405
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1929851364
Short name T1519
Test name
Test status
Simulation time 150913660 ps
CPU time 0.85 seconds
Started Aug 18 05:36:46 PM PDT 24
Finished Aug 18 05:36:52 PM PDT 24
Peak memory 207388 kb
Host smart-c5239f75-5c0b-4dcf-8a46-7073eb6ba39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19298
51364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1929851364
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1359279280
Short name T1309
Test name
Test status
Simulation time 176845878 ps
CPU time 0.92 seconds
Started Aug 18 05:36:37 PM PDT 24
Finished Aug 18 05:36:38 PM PDT 24
Peak memory 207512 kb
Host smart-f61e5d41-355e-44e2-b99b-84b67c5820a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13592
79280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1359279280
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.846599206
Short name T1745
Test name
Test status
Simulation time 149128635 ps
CPU time 0.87 seconds
Started Aug 18 05:36:58 PM PDT 24
Finished Aug 18 05:36:59 PM PDT 24
Peak memory 207604 kb
Host smart-ee9747aa-26bf-46e0-b321-4594f88e9d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84659
9206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.846599206
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.1856931341
Short name T2715
Test name
Test status
Simulation time 255622597 ps
CPU time 1 seconds
Started Aug 18 05:36:40 PM PDT 24
Finished Aug 18 05:36:41 PM PDT 24
Peak memory 207568 kb
Host smart-28a20a52-529b-45b0-a2d5-37962f9af3aa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1856931341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.1856931341
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.114798146
Short name T2452
Test name
Test status
Simulation time 145393134 ps
CPU time 0.8 seconds
Started Aug 18 05:36:30 PM PDT 24
Finished Aug 18 05:36:31 PM PDT 24
Peak memory 207488 kb
Host smart-35323722-15f8-4de4-ab83-f90e0d5d7449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11479
8146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.114798146
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.635285461
Short name T29
Test name
Test status
Simulation time 31087294 ps
CPU time 0.66 seconds
Started Aug 18 05:36:39 PM PDT 24
Finished Aug 18 05:36:40 PM PDT 24
Peak memory 207264 kb
Host smart-0a5c0f8c-3158-4407-b932-a6afa14c7aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63528
5461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.635285461
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1524837086
Short name T1253
Test name
Test status
Simulation time 12661824329 ps
CPU time 34.88 seconds
Started Aug 18 05:36:34 PM PDT 24
Finished Aug 18 05:37:09 PM PDT 24
Peak memory 215976 kb
Host smart-1c31b4ea-9132-47a9-a0d8-e3d7dca041c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15248
37086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1524837086
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3639391169
Short name T2877
Test name
Test status
Simulation time 148362908 ps
CPU time 0.85 seconds
Started Aug 18 05:36:31 PM PDT 24
Finished Aug 18 05:36:32 PM PDT 24
Peak memory 207552 kb
Host smart-9891ceeb-d0ab-41cc-9f77-8595fa82af00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36393
91169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3639391169
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.4091101471
Short name T2164
Test name
Test status
Simulation time 187819279 ps
CPU time 0.88 seconds
Started Aug 18 05:36:35 PM PDT 24
Finished Aug 18 05:36:36 PM PDT 24
Peak memory 207416 kb
Host smart-28751fb7-cd92-42ce-8544-cb11ec04b52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40911
01471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.4091101471
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.2615552610
Short name T1705
Test name
Test status
Simulation time 177337270 ps
CPU time 0.89 seconds
Started Aug 18 05:36:39 PM PDT 24
Finished Aug 18 05:36:40 PM PDT 24
Peak memory 207492 kb
Host smart-18fc0f17-5b19-46fd-8b9c-b8b419cb41a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26155
52610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.2615552610
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2408912853
Short name T2578
Test name
Test status
Simulation time 171288758 ps
CPU time 0.91 seconds
Started Aug 18 05:36:51 PM PDT 24
Finished Aug 18 05:36:57 PM PDT 24
Peak memory 207460 kb
Host smart-2fd87c8d-9e66-4950-b3fa-169859406a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24089
12853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2408912853
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3482777571
Short name T1249
Test name
Test status
Simulation time 216833493 ps
CPU time 0.92 seconds
Started Aug 18 05:36:36 PM PDT 24
Finished Aug 18 05:36:37 PM PDT 24
Peak memory 207636 kb
Host smart-736160ec-ce72-48a8-9992-42c63092491b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34827
77571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3482777571
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_rx_full.907466613
Short name T1545
Test name
Test status
Simulation time 251659680 ps
CPU time 1.04 seconds
Started Aug 18 05:36:34 PM PDT 24
Finished Aug 18 05:36:35 PM PDT 24
Peak memory 207488 kb
Host smart-ca211d70-927e-4a60-a3fd-966405eec263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90746
6613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_full.907466613
Directory /workspace/32.usbdev_rx_full/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2081576970
Short name T689
Test name
Test status
Simulation time 149569345 ps
CPU time 0.82 seconds
Started Aug 18 05:36:57 PM PDT 24
Finished Aug 18 05:36:58 PM PDT 24
Peak memory 207264 kb
Host smart-07d5e8f9-2669-4721-b020-fabab850c8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20815
76970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2081576970
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2038349164
Short name T2519
Test name
Test status
Simulation time 154428351 ps
CPU time 0.84 seconds
Started Aug 18 05:36:37 PM PDT 24
Finished Aug 18 05:36:38 PM PDT 24
Peak memory 207492 kb
Host smart-377ccd6f-0d91-4f6d-83e7-142509f4392c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20383
49164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2038349164
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1196868954
Short name T3250
Test name
Test status
Simulation time 212060099 ps
CPU time 0.99 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207444 kb
Host smart-697c4483-9791-4465-b6f6-32ad7dd4af2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11968
68954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1196868954
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.2876387455
Short name T1285
Test name
Test status
Simulation time 1928206061 ps
CPU time 53.15 seconds
Started Aug 18 05:36:34 PM PDT 24
Finished Aug 18 05:37:27 PM PDT 24
Peak memory 217552 kb
Host smart-f6c59c73-d794-459c-84f4-ed78a213321e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2876387455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.2876387455
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1061723188
Short name T2638
Test name
Test status
Simulation time 206800635 ps
CPU time 0.9 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:36:33 PM PDT 24
Peak memory 207504 kb
Host smart-fa0f3961-673e-4100-8180-6e7cf3a41cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10617
23188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1061723188
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2902413006
Short name T1807
Test name
Test status
Simulation time 208755335 ps
CPU time 0.97 seconds
Started Aug 18 05:36:51 PM PDT 24
Finished Aug 18 05:36:52 PM PDT 24
Peak memory 207708 kb
Host smart-20ea94e5-c317-4b09-b886-c76031dc08f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29024
13006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2902413006
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.3623765880
Short name T1358
Test name
Test status
Simulation time 992274085 ps
CPU time 2.7 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:36:35 PM PDT 24
Peak memory 207716 kb
Host smart-13203ab7-b6f9-438c-8f92-71b336c47f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36237
65880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.3623765880
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.2393408850
Short name T2064
Test name
Test status
Simulation time 3569765703 ps
CPU time 27.26 seconds
Started Aug 18 05:36:41 PM PDT 24
Finished Aug 18 05:37:08 PM PDT 24
Peak memory 215996 kb
Host smart-6749d490-022c-4ac4-94d2-0bd8a8acbee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23934
08850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2393408850
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.1727622706
Short name T3018
Test name
Test status
Simulation time 4290066615 ps
CPU time 28.26 seconds
Started Aug 18 05:36:27 PM PDT 24
Finished Aug 18 05:36:56 PM PDT 24
Peak memory 207740 kb
Host smart-72488086-b798-4f4e-a5b8-727e7804c380
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727622706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_hos
t_handshake.1727622706
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_tx_rx_disruption.3608243583
Short name T657
Test name
Test status
Simulation time 560104403 ps
CPU time 1.58 seconds
Started Aug 18 05:36:29 PM PDT 24
Finished Aug 18 05:36:30 PM PDT 24
Peak memory 207588 kb
Host smart-d95c9271-c8e5-43d4-9beb-cf6761b84ff5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608243583 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.usbdev_tx_rx_disruption.3608243583
Directory /workspace/32.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/320.usbdev_tx_rx_disruption.152006468
Short name T1272
Test name
Test status
Simulation time 472943179 ps
CPU time 1.44 seconds
Started Aug 18 05:39:48 PM PDT 24
Finished Aug 18 05:39:50 PM PDT 24
Peak memory 207584 kb
Host smart-a97d18af-741b-4653-840d-19d1cda2dd0d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152006468 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 320.usbdev_tx_rx_disruption.152006468
Directory /workspace/320.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/321.usbdev_tx_rx_disruption.3225229438
Short name T201
Test name
Test status
Simulation time 507366821 ps
CPU time 1.68 seconds
Started Aug 18 05:40:21 PM PDT 24
Finished Aug 18 05:40:23 PM PDT 24
Peak memory 207532 kb
Host smart-e410227e-51ed-4935-97e5-c4186173bf0f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225229438 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 321.usbdev_tx_rx_disruption.3225229438
Directory /workspace/321.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/322.usbdev_tx_rx_disruption.2531173816
Short name T1584
Test name
Test status
Simulation time 466930608 ps
CPU time 1.53 seconds
Started Aug 18 05:40:18 PM PDT 24
Finished Aug 18 05:40:19 PM PDT 24
Peak memory 207576 kb
Host smart-ad269e98-76c5-44fa-b0c4-779a6159dc1c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531173816 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 322.usbdev_tx_rx_disruption.2531173816
Directory /workspace/322.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/323.usbdev_tx_rx_disruption.4108644722
Short name T873
Test name
Test status
Simulation time 604175230 ps
CPU time 1.56 seconds
Started Aug 18 05:40:03 PM PDT 24
Finished Aug 18 05:40:05 PM PDT 24
Peak memory 207564 kb
Host smart-d57e0952-6f85-411c-b10c-cca9fcdab1ab
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108644722 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 323.usbdev_tx_rx_disruption.4108644722
Directory /workspace/323.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/324.usbdev_tx_rx_disruption.62111753
Short name T3411
Test name
Test status
Simulation time 627683203 ps
CPU time 1.59 seconds
Started Aug 18 05:39:56 PM PDT 24
Finished Aug 18 05:39:58 PM PDT 24
Peak memory 207496 kb
Host smart-de1d8af0-003f-4442-81af-106a0ddb9b18
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62111753 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 324.usbdev_tx_rx_disruption.62111753
Directory /workspace/324.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/325.usbdev_tx_rx_disruption.1909470526
Short name T991
Test name
Test status
Simulation time 570952440 ps
CPU time 1.7 seconds
Started Aug 18 05:39:45 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207732 kb
Host smart-4c317a9b-e341-42f8-8237-5ffaab45ce5b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909470526 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 325.usbdev_tx_rx_disruption.1909470526
Directory /workspace/325.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/326.usbdev_tx_rx_disruption.640201197
Short name T2137
Test name
Test status
Simulation time 635752437 ps
CPU time 1.61 seconds
Started Aug 18 05:39:57 PM PDT 24
Finished Aug 18 05:39:59 PM PDT 24
Peak memory 207584 kb
Host smart-ffaa9ee3-f62f-4c07-b0f0-301fc1a0eef8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640201197 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 326.usbdev_tx_rx_disruption.640201197
Directory /workspace/326.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/327.usbdev_tx_rx_disruption.1164334734
Short name T3602
Test name
Test status
Simulation time 571486387 ps
CPU time 1.59 seconds
Started Aug 18 05:39:51 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207576 kb
Host smart-15ad70d6-4ade-4043-8e31-50086cf0019d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164334734 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 327.usbdev_tx_rx_disruption.1164334734
Directory /workspace/327.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/328.usbdev_tx_rx_disruption.2393818730
Short name T698
Test name
Test status
Simulation time 444706163 ps
CPU time 1.46 seconds
Started Aug 18 05:39:56 PM PDT 24
Finished Aug 18 05:39:58 PM PDT 24
Peak memory 207576 kb
Host smart-04b1248c-e09f-44bc-bb6a-a638ac6f5b8c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393818730 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 328.usbdev_tx_rx_disruption.2393818730
Directory /workspace/328.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/329.usbdev_tx_rx_disruption.830318903
Short name T3344
Test name
Test status
Simulation time 432784992 ps
CPU time 1.36 seconds
Started Aug 18 05:40:11 PM PDT 24
Finished Aug 18 05:40:12 PM PDT 24
Peak memory 207564 kb
Host smart-b6beb29e-8abb-452e-8c2b-5dd51a5e53f3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830318903 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 329.usbdev_tx_rx_disruption.830318903
Directory /workspace/329.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.914034554
Short name T2783
Test name
Test status
Simulation time 38354959 ps
CPU time 0.68 seconds
Started Aug 18 05:36:44 PM PDT 24
Finished Aug 18 05:36:45 PM PDT 24
Peak memory 207424 kb
Host smart-323514aa-ec36-4d94-9d48-145ca4ffdfa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=914034554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.914034554
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.3957237515
Short name T1974
Test name
Test status
Simulation time 5552617711 ps
CPU time 8.29 seconds
Started Aug 18 05:36:52 PM PDT 24
Finished Aug 18 05:37:00 PM PDT 24
Peak memory 216000 kb
Host smart-4a00e48a-86fa-4376-aca7-b716dcd5bb01
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957237515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_disconnect.3957237515
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.368200606
Short name T3534
Test name
Test status
Simulation time 15667346369 ps
CPU time 20.15 seconds
Started Aug 18 05:36:45 PM PDT 24
Finished Aug 18 05:37:06 PM PDT 24
Peak memory 216136 kb
Host smart-07487dd8-ab67-4155-b76a-b06ead7da471
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=368200606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.368200606
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.3127659815
Short name T1895
Test name
Test status
Simulation time 23574006055 ps
CPU time 27.36 seconds
Started Aug 18 05:36:39 PM PDT 24
Finished Aug 18 05:37:06 PM PDT 24
Peak memory 215992 kb
Host smart-c17ea5d6-34ef-4aa4-adf8-446d0beb43ae
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127659815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.3127659815
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3347489994
Short name T3510
Test name
Test status
Simulation time 157697825 ps
CPU time 0.87 seconds
Started Aug 18 05:36:46 PM PDT 24
Finished Aug 18 05:36:47 PM PDT 24
Peak memory 207636 kb
Host smart-dfd8bf3d-9a10-4cb6-b038-bbfbc46ce722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33474
89994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3347489994
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2197417873
Short name T2826
Test name
Test status
Simulation time 184842785 ps
CPU time 0.85 seconds
Started Aug 18 05:36:26 PM PDT 24
Finished Aug 18 05:36:27 PM PDT 24
Peak memory 207596 kb
Host smart-246b20c2-9193-4d10-b03a-492bce05faad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21974
17873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2197417873
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.461656392
Short name T2392
Test name
Test status
Simulation time 279566763 ps
CPU time 1.06 seconds
Started Aug 18 05:36:45 PM PDT 24
Finished Aug 18 05:36:46 PM PDT 24
Peak memory 207300 kb
Host smart-13313449-5615-463f-a399-803a7d427c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46165
6392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.461656392
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.2380452353
Short name T349
Test name
Test status
Simulation time 1057613542 ps
CPU time 2.74 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:36:35 PM PDT 24
Peak memory 207736 kb
Host smart-78f8e198-6a8e-4132-9e25-ba120422c1d5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2380452353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2380452353
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.1927279115
Short name T2008
Test name
Test status
Simulation time 18803488055 ps
CPU time 28.39 seconds
Started Aug 18 05:36:25 PM PDT 24
Finished Aug 18 05:36:53 PM PDT 24
Peak memory 207792 kb
Host smart-349026d0-523d-4208-90a2-854ec4c926ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19272
79115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.1927279115
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.598578628
Short name T1460
Test name
Test status
Simulation time 2497772106 ps
CPU time 20.44 seconds
Started Aug 18 05:36:57 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 207480 kb
Host smart-438d7a90-bf9a-4d1c-ae07-202136e8b19f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598578628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.598578628
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.120218527
Short name T1057
Test name
Test status
Simulation time 531402544 ps
CPU time 1.54 seconds
Started Aug 18 05:36:47 PM PDT 24
Finished Aug 18 05:36:49 PM PDT 24
Peak memory 207536 kb
Host smart-4f95643a-801c-47d2-a8a4-70f65787fadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12021
8527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.120218527
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.3769584872
Short name T3361
Test name
Test status
Simulation time 154153140 ps
CPU time 0.89 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207676 kb
Host smart-5670538b-7e2d-419a-a145-e2ad48235a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37695
84872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.3769584872
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1819239560
Short name T1303
Test name
Test status
Simulation time 36312883 ps
CPU time 0.72 seconds
Started Aug 18 05:36:59 PM PDT 24
Finished Aug 18 05:37:00 PM PDT 24
Peak memory 207596 kb
Host smart-2b8c90cf-e265-496c-babf-864e2c00f03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18192
39560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1819239560
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.3713108581
Short name T1550
Test name
Test status
Simulation time 1045412279 ps
CPU time 2.64 seconds
Started Aug 18 05:36:46 PM PDT 24
Finished Aug 18 05:36:49 PM PDT 24
Peak memory 207752 kb
Host smart-4f427010-4668-4db7-97af-85a586565653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37131
08581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.3713108581
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_types.1647314005
Short name T405
Test name
Test status
Simulation time 371903179 ps
CPU time 1.2 seconds
Started Aug 18 05:36:37 PM PDT 24
Finished Aug 18 05:36:39 PM PDT 24
Peak memory 207544 kb
Host smart-debb473c-5b12-4b20-9688-24cbd9347120
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1647314005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_types.1647314005
Directory /workspace/33.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.515334082
Short name T1441
Test name
Test status
Simulation time 242555266 ps
CPU time 1.95 seconds
Started Aug 18 05:36:49 PM PDT 24
Finished Aug 18 05:36:51 PM PDT 24
Peak memory 207660 kb
Host smart-e45cefbf-7113-4581-85a4-f0a74f37bc9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51533
4082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.515334082
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.202943298
Short name T1959
Test name
Test status
Simulation time 188892855 ps
CPU time 1 seconds
Started Aug 18 05:36:29 PM PDT 24
Finished Aug 18 05:36:35 PM PDT 24
Peak memory 215900 kb
Host smart-822f695a-76f8-4b0a-9580-fa04b05988e9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=202943298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.202943298
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.128158167
Short name T2474
Test name
Test status
Simulation time 148160137 ps
CPU time 0.82 seconds
Started Aug 18 05:36:36 PM PDT 24
Finished Aug 18 05:36:37 PM PDT 24
Peak memory 207424 kb
Host smart-f493a336-aa55-403a-9c67-2dd182f7943c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12815
8167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.128158167
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2727868885
Short name T593
Test name
Test status
Simulation time 208462433 ps
CPU time 0.98 seconds
Started Aug 18 05:36:52 PM PDT 24
Finished Aug 18 05:36:53 PM PDT 24
Peak memory 207500 kb
Host smart-b5fed8e0-dfeb-4938-af4e-698b7914d7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27278
68885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2727868885
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.1206239573
Short name T3206
Test name
Test status
Simulation time 5341715463 ps
CPU time 157.37 seconds
Started Aug 18 05:36:47 PM PDT 24
Finished Aug 18 05:39:24 PM PDT 24
Peak memory 215964 kb
Host smart-33305d02-9740-432e-80d8-e6158bc8a846
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1206239573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.1206239573
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.1294183527
Short name T1417
Test name
Test status
Simulation time 7174782454 ps
CPU time 84.05 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:38:19 PM PDT 24
Peak memory 207592 kb
Host smart-09c1e331-0286-4ddd-aa5a-83e9d8e19f80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1294183527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.1294183527
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2827157823
Short name T897
Test name
Test status
Simulation time 198311381 ps
CPU time 0.85 seconds
Started Aug 18 05:36:47 PM PDT 24
Finished Aug 18 05:36:48 PM PDT 24
Peak memory 207560 kb
Host smart-fde32c3d-52d1-46cd-8290-0273902eedd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28271
57823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2827157823
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.660609157
Short name T1074
Test name
Test status
Simulation time 25483060681 ps
CPU time 38.78 seconds
Started Aug 18 05:36:35 PM PDT 24
Finished Aug 18 05:37:14 PM PDT 24
Peak memory 215960 kb
Host smart-b5abe2d3-0687-458e-a33a-1cba7faa233d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66060
9157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.660609157
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.10631226
Short name T1648
Test name
Test status
Simulation time 10939066956 ps
CPU time 14.64 seconds
Started Aug 18 05:36:39 PM PDT 24
Finished Aug 18 05:36:53 PM PDT 24
Peak memory 207744 kb
Host smart-901b9e15-ec2c-45f1-93d6-3f075345d0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10631
226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.10631226
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.1545166556
Short name T1627
Test name
Test status
Simulation time 5518600409 ps
CPU time 58.79 seconds
Started Aug 18 05:36:34 PM PDT 24
Finished Aug 18 05:37:33 PM PDT 24
Peak memory 218728 kb
Host smart-416ca567-8676-4e41-9550-472c2925967e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1545166556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.1545166556
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.2554803598
Short name T1995
Test name
Test status
Simulation time 2669560023 ps
CPU time 77.56 seconds
Started Aug 18 05:36:41 PM PDT 24
Finished Aug 18 05:37:59 PM PDT 24
Peak memory 217636 kb
Host smart-93796a40-6e26-487c-aa5f-1bfca352ae8e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2554803598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.2554803598
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.1814110519
Short name T2937
Test name
Test status
Simulation time 255647916 ps
CPU time 1.04 seconds
Started Aug 18 05:36:56 PM PDT 24
Finished Aug 18 05:36:57 PM PDT 24
Peak memory 207296 kb
Host smart-b41d5df5-e230-441e-bed5-0db6608df089
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1814110519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.1814110519
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3210634570
Short name T2094
Test name
Test status
Simulation time 192324683 ps
CPU time 0.92 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:36:33 PM PDT 24
Peak memory 207500 kb
Host smart-c3c94ae3-f7f1-4b96-8657-076b80da2555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32106
34570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3210634570
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.174053016
Short name T2345
Test name
Test status
Simulation time 2617194714 ps
CPU time 21.35 seconds
Started Aug 18 05:36:52 PM PDT 24
Finished Aug 18 05:37:13 PM PDT 24
Peak memory 207840 kb
Host smart-e3f5ade9-c80a-4ccd-89b9-531633bf828a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=174053016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.174053016
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2412011757
Short name T536
Test name
Test status
Simulation time 155018451 ps
CPU time 0.81 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207296 kb
Host smart-49c711a3-6430-4c3d-a812-b499a9ce3778
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2412011757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2412011757
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.514308769
Short name T3513
Test name
Test status
Simulation time 174299468 ps
CPU time 0.86 seconds
Started Aug 18 05:36:48 PM PDT 24
Finished Aug 18 05:36:49 PM PDT 24
Peak memory 207504 kb
Host smart-be8938b3-2f98-4451-8250-9c6394548a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51430
8769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.514308769
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.1418099500
Short name T3040
Test name
Test status
Simulation time 221245438 ps
CPU time 1.05 seconds
Started Aug 18 05:36:47 PM PDT 24
Finished Aug 18 05:36:48 PM PDT 24
Peak memory 207468 kb
Host smart-93a961dc-856c-45fb-96fc-6a9acd6a03ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14180
99500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.1418099500
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.3079925817
Short name T601
Test name
Test status
Simulation time 156155968 ps
CPU time 0.82 seconds
Started Aug 18 05:36:56 PM PDT 24
Finished Aug 18 05:36:57 PM PDT 24
Peak memory 207292 kb
Host smart-b8fd310c-dd76-45d0-8438-defbe2b707ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30799
25817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.3079925817
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2551502868
Short name T635
Test name
Test status
Simulation time 190394996 ps
CPU time 0.93 seconds
Started Aug 18 05:36:53 PM PDT 24
Finished Aug 18 05:36:54 PM PDT 24
Peak memory 207272 kb
Host smart-c1bca57d-f0a0-442e-9d19-4acb99dc95ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25515
02868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2551502868
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2536721610
Short name T2806
Test name
Test status
Simulation time 173375153 ps
CPU time 0.89 seconds
Started Aug 18 05:36:41 PM PDT 24
Finished Aug 18 05:36:42 PM PDT 24
Peak memory 207448 kb
Host smart-8daae5d5-38db-4e4c-84ff-6bdebe769842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25367
21610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2536721610
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1296170059
Short name T2114
Test name
Test status
Simulation time 201290522 ps
CPU time 0.89 seconds
Started Aug 18 05:36:59 PM PDT 24
Finished Aug 18 05:37:00 PM PDT 24
Peak memory 207560 kb
Host smart-85074f06-3ab4-49bf-bda7-d71420b56db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12961
70059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1296170059
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.3453274238
Short name T1152
Test name
Test status
Simulation time 223384421 ps
CPU time 0.96 seconds
Started Aug 18 05:36:34 PM PDT 24
Finished Aug 18 05:36:35 PM PDT 24
Peak memory 207440 kb
Host smart-dd143690-e13e-47af-bfc2-fccabace8588
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3453274238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.3453274238
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1548300760
Short name T1393
Test name
Test status
Simulation time 157651147 ps
CPU time 0.83 seconds
Started Aug 18 05:36:55 PM PDT 24
Finished Aug 18 05:36:56 PM PDT 24
Peak memory 207464 kb
Host smart-6d2aef7f-780a-4d42-950b-4e85aeaa2b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15483
00760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1548300760
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.99394248
Short name T1177
Test name
Test status
Simulation time 48196542 ps
CPU time 0.68 seconds
Started Aug 18 05:36:25 PM PDT 24
Finished Aug 18 05:36:26 PM PDT 24
Peak memory 207412 kb
Host smart-6fc68be1-bd57-4294-bfd3-4a63c0849873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99394
248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.99394248
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.682858114
Short name T1915
Test name
Test status
Simulation time 6278353161 ps
CPU time 17.26 seconds
Started Aug 18 05:36:43 PM PDT 24
Finished Aug 18 05:37:00 PM PDT 24
Peak memory 215892 kb
Host smart-f80e9f3b-599f-4868-83c5-e8c8b0be8588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68285
8114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.682858114
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3645979555
Short name T360
Test name
Test status
Simulation time 196639220 ps
CPU time 0.94 seconds
Started Aug 18 05:36:52 PM PDT 24
Finished Aug 18 05:36:54 PM PDT 24
Peak memory 207532 kb
Host smart-6badb00b-7a70-4bc8-a51e-ef8a93b35a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36459
79555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3645979555
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1247297416
Short name T2439
Test name
Test status
Simulation time 196052149 ps
CPU time 0.92 seconds
Started Aug 18 05:36:40 PM PDT 24
Finished Aug 18 05:36:41 PM PDT 24
Peak memory 207468 kb
Host smart-06ecf6e4-d207-4249-bd54-0e746d3bdd8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12472
97416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1247297416
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.4212785213
Short name T656
Test name
Test status
Simulation time 172414860 ps
CPU time 0.89 seconds
Started Aug 18 05:36:39 PM PDT 24
Finished Aug 18 05:36:40 PM PDT 24
Peak memory 207468 kb
Host smart-9c6c7448-4b5a-4051-9956-e467c77e94b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42127
85213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.4212785213
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.137880829
Short name T2481
Test name
Test status
Simulation time 189299442 ps
CPU time 0.91 seconds
Started Aug 18 05:36:59 PM PDT 24
Finished Aug 18 05:37:00 PM PDT 24
Peak memory 207288 kb
Host smart-782e23ea-0b01-49cc-b377-f818838ab00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13788
0829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.137880829
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.561248554
Short name T680
Test name
Test status
Simulation time 139075544 ps
CPU time 0.8 seconds
Started Aug 18 05:36:37 PM PDT 24
Finished Aug 18 05:36:38 PM PDT 24
Peak memory 207428 kb
Host smart-5557fc61-aa8d-46b6-9dd2-2a3df8759f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56124
8554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.561248554
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_rx_full.1735545392
Short name T3578
Test name
Test status
Simulation time 375433475 ps
CPU time 1.31 seconds
Started Aug 18 05:36:49 PM PDT 24
Finished Aug 18 05:36:51 PM PDT 24
Peak memory 207416 kb
Host smart-024b8f16-9bc2-4eb7-963b-7006ba0da701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17355
45392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_full.1735545392
Directory /workspace/33.usbdev_rx_full/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2592361579
Short name T1559
Test name
Test status
Simulation time 154199738 ps
CPU time 0.85 seconds
Started Aug 18 05:36:51 PM PDT 24
Finished Aug 18 05:36:52 PM PDT 24
Peak memory 207564 kb
Host smart-1ae68d94-a54c-4d4a-bb57-4172fe9fbe8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25923
61579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2592361579
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.794354796
Short name T2496
Test name
Test status
Simulation time 180832299 ps
CPU time 0.85 seconds
Started Aug 18 05:36:37 PM PDT 24
Finished Aug 18 05:36:38 PM PDT 24
Peak memory 207528 kb
Host smart-c18861fc-da96-434d-bcf9-ccf8d111113b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79435
4796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.794354796
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.948808602
Short name T776
Test name
Test status
Simulation time 215291633 ps
CPU time 1.03 seconds
Started Aug 18 05:36:44 PM PDT 24
Finished Aug 18 05:36:45 PM PDT 24
Peak memory 207464 kb
Host smart-d80c5d2f-3d98-4f08-baaf-1d5e3f7a1045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94880
8602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.948808602
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2118522163
Short name T1446
Test name
Test status
Simulation time 191615403 ps
CPU time 0.92 seconds
Started Aug 18 05:37:07 PM PDT 24
Finished Aug 18 05:37:08 PM PDT 24
Peak memory 207408 kb
Host smart-faa7e7de-45da-4d2e-972d-251bb688448d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21185
22163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2118522163
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1568430106
Short name T3337
Test name
Test status
Simulation time 217806890 ps
CPU time 1.06 seconds
Started Aug 18 05:37:00 PM PDT 24
Finished Aug 18 05:37:01 PM PDT 24
Peak memory 207576 kb
Host smart-a2aa2c89-1e2f-45dd-8355-10841a398661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15684
30106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1568430106
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.2916681208
Short name T1906
Test name
Test status
Simulation time 1333685093 ps
CPU time 3.06 seconds
Started Aug 18 05:36:58 PM PDT 24
Finished Aug 18 05:37:01 PM PDT 24
Peak memory 207784 kb
Host smart-b7818e4c-789c-4b35-8d7c-670ce4941af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29166
81208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.2916681208
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.2519601926
Short name T2973
Test name
Test status
Simulation time 2569333241 ps
CPU time 25.89 seconds
Started Aug 18 05:36:51 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 216044 kb
Host smart-868375b1-a882-4df4-a038-a3e066556c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25196
01926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.2519601926
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.4016040653
Short name T1647
Test name
Test status
Simulation time 3415169810 ps
CPU time 29.63 seconds
Started Aug 18 05:36:32 PM PDT 24
Finished Aug 18 05:37:02 PM PDT 24
Peak memory 207696 kb
Host smart-e9e26ab7-38fe-41e8-b81b-b4d48e4ab3ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016040653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.4016040653
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_tx_rx_disruption.4290172661
Short name T199
Test name
Test status
Simulation time 492189312 ps
CPU time 1.47 seconds
Started Aug 18 05:36:53 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207572 kb
Host smart-83da6140-4939-447c-a589-385cf1c22318
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290172661 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.usbdev_tx_rx_disruption.4290172661
Directory /workspace/33.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/330.usbdev_tx_rx_disruption.2208158213
Short name T1570
Test name
Test status
Simulation time 433905903 ps
CPU time 1.4 seconds
Started Aug 18 05:39:49 PM PDT 24
Finished Aug 18 05:39:50 PM PDT 24
Peak memory 207544 kb
Host smart-52082740-95cd-4e90-93f6-284a843feb1b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208158213 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 330.usbdev_tx_rx_disruption.2208158213
Directory /workspace/330.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/331.usbdev_tx_rx_disruption.3971684952
Short name T1707
Test name
Test status
Simulation time 500517320 ps
CPU time 1.59 seconds
Started Aug 18 05:39:46 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 207528 kb
Host smart-d8ddeea8-ad11-4958-8a83-a413a5cac3b8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971684952 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 331.usbdev_tx_rx_disruption.3971684952
Directory /workspace/331.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/332.usbdev_tx_rx_disruption.3015659074
Short name T1783
Test name
Test status
Simulation time 465691621 ps
CPU time 1.35 seconds
Started Aug 18 05:39:56 PM PDT 24
Finished Aug 18 05:39:57 PM PDT 24
Peak memory 207564 kb
Host smart-290e1388-43fd-4f50-a348-456ea2cd941e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015659074 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 332.usbdev_tx_rx_disruption.3015659074
Directory /workspace/332.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/333.usbdev_tx_rx_disruption.1240909100
Short name T1468
Test name
Test status
Simulation time 571495647 ps
CPU time 1.65 seconds
Started Aug 18 05:40:02 PM PDT 24
Finished Aug 18 05:40:04 PM PDT 24
Peak memory 207556 kb
Host smart-44f92e7d-bff5-410c-af80-13d13ef3ad9a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240909100 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 333.usbdev_tx_rx_disruption.1240909100
Directory /workspace/333.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/334.usbdev_tx_rx_disruption.529128215
Short name T2785
Test name
Test status
Simulation time 530360377 ps
CPU time 1.57 seconds
Started Aug 18 05:39:59 PM PDT 24
Finished Aug 18 05:40:00 PM PDT 24
Peak memory 207584 kb
Host smart-e258294e-621b-4a33-a5b4-3d8a4191c91b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529128215 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 334.usbdev_tx_rx_disruption.529128215
Directory /workspace/334.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/335.usbdev_tx_rx_disruption.452490566
Short name T3002
Test name
Test status
Simulation time 579535460 ps
CPU time 1.7 seconds
Started Aug 18 05:40:08 PM PDT 24
Finished Aug 18 05:40:10 PM PDT 24
Peak memory 207544 kb
Host smart-08522fe4-09ed-4cc0-9f95-18b676c4f92c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452490566 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 335.usbdev_tx_rx_disruption.452490566
Directory /workspace/335.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/336.usbdev_tx_rx_disruption.265395816
Short name T124
Test name
Test status
Simulation time 512323972 ps
CPU time 1.48 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207580 kb
Host smart-0175327c-63b6-402d-bdb6-7bcf43b3a300
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265395816 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 336.usbdev_tx_rx_disruption.265395816
Directory /workspace/336.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/337.usbdev_tx_rx_disruption.140856500
Short name T3637
Test name
Test status
Simulation time 463419866 ps
CPU time 1.42 seconds
Started Aug 18 05:40:09 PM PDT 24
Finished Aug 18 05:40:11 PM PDT 24
Peak memory 207588 kb
Host smart-e34ca9a8-7406-40fe-b96a-170d23e74ab5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140856500 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 337.usbdev_tx_rx_disruption.140856500
Directory /workspace/337.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/338.usbdev_tx_rx_disruption.4048216821
Short name T1695
Test name
Test status
Simulation time 544324792 ps
CPU time 1.65 seconds
Started Aug 18 05:39:58 PM PDT 24
Finished Aug 18 05:40:00 PM PDT 24
Peak memory 207472 kb
Host smart-3b072e49-0f7d-4877-9996-bc77f3873078
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048216821 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 338.usbdev_tx_rx_disruption.4048216821
Directory /workspace/338.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/339.usbdev_tx_rx_disruption.3953789036
Short name T940
Test name
Test status
Simulation time 478169608 ps
CPU time 1.49 seconds
Started Aug 18 05:40:01 PM PDT 24
Finished Aug 18 05:40:03 PM PDT 24
Peak memory 207540 kb
Host smart-a5c5e229-3e6c-4a3c-a3c6-93427f5880f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953789036 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 339.usbdev_tx_rx_disruption.3953789036
Directory /workspace/339.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.2939503529
Short name T3336
Test name
Test status
Simulation time 33777680 ps
CPU time 0.67 seconds
Started Aug 18 05:36:57 PM PDT 24
Finished Aug 18 05:36:58 PM PDT 24
Peak memory 207460 kb
Host smart-6d920a6b-0cd4-4b05-ada5-e380cd0a2a89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2939503529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.2939503529
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.2204478694
Short name T1890
Test name
Test status
Simulation time 4481468320 ps
CPU time 6.2 seconds
Started Aug 18 05:36:51 PM PDT 24
Finished Aug 18 05:36:57 PM PDT 24
Peak memory 215964 kb
Host smart-0e60868c-d2c3-428f-aea6-473be9d7403c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204478694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.2204478694
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.1715792320
Short name T3559
Test name
Test status
Simulation time 20951309200 ps
CPU time 26.58 seconds
Started Aug 18 05:36:45 PM PDT 24
Finished Aug 18 05:37:11 PM PDT 24
Peak memory 207864 kb
Host smart-cf90a676-c1c9-4141-9658-47f5fc14e38c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715792320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.1715792320
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1031316603
Short name T2152
Test name
Test status
Simulation time 29205576510 ps
CPU time 43.21 seconds
Started Aug 18 05:37:06 PM PDT 24
Finished Aug 18 05:37:49 PM PDT 24
Peak memory 207772 kb
Host smart-8b93f09b-5d0a-4daa-b3b1-503a4282bf41
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031316603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.1031316603
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.295257291
Short name T1476
Test name
Test status
Simulation time 155017486 ps
CPU time 0.89 seconds
Started Aug 18 05:36:42 PM PDT 24
Finished Aug 18 05:36:43 PM PDT 24
Peak memory 207444 kb
Host smart-7e679c63-8afb-4e6a-81b8-419453da1c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29525
7291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.295257291
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.2615497726
Short name T1790
Test name
Test status
Simulation time 157866011 ps
CPU time 0.87 seconds
Started Aug 18 05:36:42 PM PDT 24
Finished Aug 18 05:36:42 PM PDT 24
Peak memory 207556 kb
Host smart-55474d57-ca93-4bf3-93a3-f14ad5ebd889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26154
97726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.2615497726
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.3107576759
Short name T3209
Test name
Test status
Simulation time 252201292 ps
CPU time 1.09 seconds
Started Aug 18 05:36:42 PM PDT 24
Finished Aug 18 05:36:43 PM PDT 24
Peak memory 207576 kb
Host smart-3ecf6b8d-119c-4b4e-bc3d-8b696b8af8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31075
76759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.3107576759
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1628530829
Short name T1406
Test name
Test status
Simulation time 467752578 ps
CPU time 1.6 seconds
Started Aug 18 05:36:43 PM PDT 24
Finished Aug 18 05:36:45 PM PDT 24
Peak memory 207480 kb
Host smart-4e8c2b64-10dd-480b-ba89-5bfd5842d5be
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1628530829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1628530829
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.872836557
Short name T2610
Test name
Test status
Simulation time 28736890767 ps
CPU time 43.54 seconds
Started Aug 18 05:36:43 PM PDT 24
Finished Aug 18 05:37:27 PM PDT 24
Peak memory 207828 kb
Host smart-53de6d9d-8465-4f07-82f2-01460a13982f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87283
6557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.872836557
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.1708464694
Short name T2232
Test name
Test status
Simulation time 1124993633 ps
CPU time 9.07 seconds
Started Aug 18 05:37:10 PM PDT 24
Finished Aug 18 05:37:19 PM PDT 24
Peak memory 207720 kb
Host smart-56037f4d-d554-4e80-8b25-186f27cab4db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708464694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.1708464694
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.1184742223
Short name T2918
Test name
Test status
Simulation time 925855911 ps
CPU time 2.13 seconds
Started Aug 18 05:36:41 PM PDT 24
Finished Aug 18 05:36:44 PM PDT 24
Peak memory 207540 kb
Host smart-0fd4f8d2-ef0d-4213-8ebe-218ea4446187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11847
42223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.1184742223
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.975797929
Short name T2858
Test name
Test status
Simulation time 138328336 ps
CPU time 0.83 seconds
Started Aug 18 05:36:33 PM PDT 24
Finished Aug 18 05:36:34 PM PDT 24
Peak memory 207492 kb
Host smart-4048be30-4ee0-4af9-a81e-468a040f3ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97579
7929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.975797929
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.3609822795
Short name T3090
Test name
Test status
Simulation time 42033861 ps
CPU time 0.73 seconds
Started Aug 18 05:36:40 PM PDT 24
Finished Aug 18 05:36:41 PM PDT 24
Peak memory 207444 kb
Host smart-085cb77b-e820-459a-b442-f1f406a19577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36098
22795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3609822795
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.315051833
Short name T2751
Test name
Test status
Simulation time 751504642 ps
CPU time 2.07 seconds
Started Aug 18 05:36:51 PM PDT 24
Finished Aug 18 05:36:53 PM PDT 24
Peak memory 207780 kb
Host smart-dfa7b137-97a2-4fb1-b2eb-eab6de36289c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31505
1833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.315051833
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_types.845677171
Short name T382
Test name
Test status
Simulation time 416092778 ps
CPU time 1.34 seconds
Started Aug 18 05:36:53 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207524 kb
Host smart-c54301fa-fd5c-4a14-9c8b-26b86dbee1b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=845677171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_types.845677171
Directory /workspace/34.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2259565490
Short name T2647
Test name
Test status
Simulation time 269877226 ps
CPU time 2.05 seconds
Started Aug 18 05:36:40 PM PDT 24
Finished Aug 18 05:36:42 PM PDT 24
Peak memory 207564 kb
Host smart-85df3267-4f2c-43e3-9339-f90e650e1a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22595
65490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2259565490
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.1235997459
Short name T644
Test name
Test status
Simulation time 240473387 ps
CPU time 1.22 seconds
Started Aug 18 05:36:44 PM PDT 24
Finished Aug 18 05:36:45 PM PDT 24
Peak memory 215844 kb
Host smart-26cf0770-ee11-43c4-8827-586ad89a8cd9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1235997459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.1235997459
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2460965769
Short name T2841
Test name
Test status
Simulation time 149032898 ps
CPU time 0.81 seconds
Started Aug 18 05:37:04 PM PDT 24
Finished Aug 18 05:37:05 PM PDT 24
Peak memory 207456 kb
Host smart-6cae5d51-493a-4581-832d-68a694c7e661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24609
65769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2460965769
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.3140338625
Short name T816
Test name
Test status
Simulation time 245903716 ps
CPU time 1.14 seconds
Started Aug 18 05:36:42 PM PDT 24
Finished Aug 18 05:36:44 PM PDT 24
Peak memory 207508 kb
Host smart-7492d09b-db5f-40e8-b828-768537c1ceb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31403
38625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.3140338625
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.2476312080
Short name T1980
Test name
Test status
Simulation time 3240357606 ps
CPU time 89.22 seconds
Started Aug 18 05:36:33 PM PDT 24
Finished Aug 18 05:38:02 PM PDT 24
Peak memory 218412 kb
Host smart-05a56475-c1a8-4053-b43d-23e04035c231
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2476312080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.2476312080
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.470344840
Short name T2867
Test name
Test status
Simulation time 6232596017 ps
CPU time 84.07 seconds
Started Aug 18 05:36:51 PM PDT 24
Finished Aug 18 05:38:16 PM PDT 24
Peak memory 207808 kb
Host smart-c49a206f-64d5-41e2-b785-3d402ce3b915
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=470344840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.470344840
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.1600316327
Short name T3104
Test name
Test status
Simulation time 187077268 ps
CPU time 0.9 seconds
Started Aug 18 05:36:55 PM PDT 24
Finished Aug 18 05:36:56 PM PDT 24
Peak memory 207576 kb
Host smart-ca57720e-a0b7-424a-99dd-e61e55b478e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16003
16327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.1600316327
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.3492337295
Short name T60
Test name
Test status
Simulation time 28460833634 ps
CPU time 53.75 seconds
Started Aug 18 05:36:47 PM PDT 24
Finished Aug 18 05:37:41 PM PDT 24
Peak memory 207804 kb
Host smart-fc04508d-f64e-4609-afff-1875ed477381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34923
37295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.3492337295
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3081823490
Short name T3266
Test name
Test status
Simulation time 5142369031 ps
CPU time 7.05 seconds
Started Aug 18 05:36:43 PM PDT 24
Finished Aug 18 05:36:51 PM PDT 24
Peak memory 216780 kb
Host smart-fce7a09f-6a13-481e-8bae-7792fdb568ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30818
23490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3081823490
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.3673215853
Short name T3631
Test name
Test status
Simulation time 4612946640 ps
CPU time 130.45 seconds
Started Aug 18 05:37:01 PM PDT 24
Finished Aug 18 05:39:11 PM PDT 24
Peak memory 218452 kb
Host smart-85f9dfe7-8476-4c7f-8096-fad3bee571a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3673215853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.3673215853
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2571295957
Short name T1129
Test name
Test status
Simulation time 2779366734 ps
CPU time 20.88 seconds
Started Aug 18 05:36:34 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 215976 kb
Host smart-c14aa502-4cf8-4e77-a45b-f7dd81343480
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2571295957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2571295957
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.4144066225
Short name T3569
Test name
Test status
Simulation time 274256882 ps
CPU time 1.04 seconds
Started Aug 18 05:36:36 PM PDT 24
Finished Aug 18 05:36:38 PM PDT 24
Peak memory 207500 kb
Host smart-6752b81e-3865-434c-8323-8109b93bd5e7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4144066225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.4144066225
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1069498301
Short name T820
Test name
Test status
Simulation time 187530924 ps
CPU time 0.96 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207524 kb
Host smart-d49b060c-7901-43f5-88ed-f74ffed7ce07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10694
98301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1069498301
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.363120024
Short name T685
Test name
Test status
Simulation time 1758817087 ps
CPU time 14.38 seconds
Started Aug 18 05:36:56 PM PDT 24
Finished Aug 18 05:37:10 PM PDT 24
Peak memory 215976 kb
Host smart-034a8569-ae45-437f-8e93-3b8664e8302c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=363120024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.363120024
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.811108113
Short name T2217
Test name
Test status
Simulation time 158729627 ps
CPU time 0.86 seconds
Started Aug 18 05:36:48 PM PDT 24
Finished Aug 18 05:36:49 PM PDT 24
Peak memory 207412 kb
Host smart-f80ef643-44f5-4f0b-ae8c-b5fb813fe9f9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=811108113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.811108113
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3249569139
Short name T1919
Test name
Test status
Simulation time 159488797 ps
CPU time 0.8 seconds
Started Aug 18 05:36:40 PM PDT 24
Finished Aug 18 05:36:41 PM PDT 24
Peak memory 207504 kb
Host smart-5e6220e4-86c1-4036-a8b5-b75e5a7a0756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32495
69139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3249569139
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2223443738
Short name T149
Test name
Test status
Simulation time 159238427 ps
CPU time 0.85 seconds
Started Aug 18 05:36:39 PM PDT 24
Finished Aug 18 05:36:40 PM PDT 24
Peak memory 207500 kb
Host smart-44ddc2f6-b925-4680-b995-101d0f19683d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22234
43738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2223443738
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.2208861446
Short name T594
Test name
Test status
Simulation time 196113773 ps
CPU time 1.02 seconds
Started Aug 18 05:36:52 PM PDT 24
Finished Aug 18 05:36:53 PM PDT 24
Peak memory 207636 kb
Host smart-524b3424-2453-4e6f-a48b-35f60f0caf6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22088
61446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.2208861446
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.910615759
Short name T1492
Test name
Test status
Simulation time 203312494 ps
CPU time 0.91 seconds
Started Aug 18 05:36:53 PM PDT 24
Finished Aug 18 05:36:54 PM PDT 24
Peak memory 207444 kb
Host smart-3058b6bb-e291-4360-8dc8-337b149b5c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91061
5759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.910615759
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3855096871
Short name T3129
Test name
Test status
Simulation time 164397463 ps
CPU time 0.89 seconds
Started Aug 18 05:36:55 PM PDT 24
Finished Aug 18 05:36:56 PM PDT 24
Peak memory 207436 kb
Host smart-3e76335f-5053-49a4-afac-881cb09ee814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38550
96871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3855096871
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.3185607101
Short name T204
Test name
Test status
Simulation time 189581949 ps
CPU time 0.91 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207584 kb
Host smart-62c80b41-9b07-4ca5-8b1e-b72c33262124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31856
07101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.3185607101
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.3336090134
Short name T2505
Test name
Test status
Simulation time 263952068 ps
CPU time 1.08 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207372 kb
Host smart-98be9beb-27ae-4f3f-abe3-412dd2ffdd10
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3336090134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.3336090134
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1139098016
Short name T2590
Test name
Test status
Simulation time 139396988 ps
CPU time 0.82 seconds
Started Aug 18 05:37:00 PM PDT 24
Finished Aug 18 05:37:01 PM PDT 24
Peak memory 207384 kb
Host smart-33166f67-172f-41cb-b525-04f0c1c26a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11390
98016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1139098016
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3246380494
Short name T1252
Test name
Test status
Simulation time 31504909 ps
CPU time 0.68 seconds
Started Aug 18 05:36:46 PM PDT 24
Finished Aug 18 05:36:47 PM PDT 24
Peak memory 207544 kb
Host smart-c2456d56-d6f8-46df-872a-33a28c9a4d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32463
80494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3246380494
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2457116890
Short name T92
Test name
Test status
Simulation time 16085252499 ps
CPU time 40.54 seconds
Started Aug 18 05:36:57 PM PDT 24
Finished Aug 18 05:37:38 PM PDT 24
Peak memory 215976 kb
Host smart-dd60e59e-df16-4b82-b21e-aa20b9cb0472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24571
16890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2457116890
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.302737893
Short name T796
Test name
Test status
Simulation time 180820373 ps
CPU time 0.95 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207544 kb
Host smart-5b0cbb9f-918a-437d-a55d-f2c67ff8259f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30273
7893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.302737893
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2188518154
Short name T2355
Test name
Test status
Simulation time 221681905 ps
CPU time 0.95 seconds
Started Aug 18 05:36:53 PM PDT 24
Finished Aug 18 05:36:54 PM PDT 24
Peak memory 207192 kb
Host smart-795e5bb8-4071-4a47-a7c1-9d4cad76fb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21885
18154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2188518154
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.2302833319
Short name T2925
Test name
Test status
Simulation time 224038551 ps
CPU time 1.01 seconds
Started Aug 18 05:37:01 PM PDT 24
Finished Aug 18 05:37:02 PM PDT 24
Peak memory 207492 kb
Host smart-2388c2e1-c451-412a-a998-9d1984814980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23028
33319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.2302833319
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.279833598
Short name T2844
Test name
Test status
Simulation time 222868930 ps
CPU time 0.92 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207444 kb
Host smart-422a94ca-fb41-4cd9-ad5e-4fde3a83aca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27983
3598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.279833598
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.503303083
Short name T1805
Test name
Test status
Simulation time 167409709 ps
CPU time 0.84 seconds
Started Aug 18 05:37:13 PM PDT 24
Finished Aug 18 05:37:14 PM PDT 24
Peak memory 207444 kb
Host smart-4e6aeb25-2e5d-4b85-8a0c-b3c82bff94d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50330
3083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.503303083
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_rx_full.3018774812
Short name T3295
Test name
Test status
Simulation time 254082686 ps
CPU time 1.08 seconds
Started Aug 18 05:37:06 PM PDT 24
Finished Aug 18 05:37:07 PM PDT 24
Peak memory 207468 kb
Host smart-3c87d102-9bb2-4747-96bc-c69890666b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30187
74812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_full.3018774812
Directory /workspace/34.usbdev_rx_full/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.3689447292
Short name T551
Test name
Test status
Simulation time 224848927 ps
CPU time 0.95 seconds
Started Aug 18 05:37:00 PM PDT 24
Finished Aug 18 05:37:01 PM PDT 24
Peak memory 207544 kb
Host smart-8bce9ba2-aeed-46b0-a1b4-bd423a3c16f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36894
47292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3689447292
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2136417317
Short name T870
Test name
Test status
Simulation time 150016123 ps
CPU time 0.88 seconds
Started Aug 18 05:37:01 PM PDT 24
Finished Aug 18 05:37:02 PM PDT 24
Peak memory 207500 kb
Host smart-34f7818f-04c5-4bdc-911f-4e6d39108f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21364
17317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2136417317
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1343383074
Short name T654
Test name
Test status
Simulation time 212506904 ps
CPU time 1.04 seconds
Started Aug 18 05:37:04 PM PDT 24
Finished Aug 18 05:37:05 PM PDT 24
Peak memory 207440 kb
Host smart-86ed2785-a37e-442b-9a45-ded177f68424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13433
83074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1343383074
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.3296137979
Short name T2374
Test name
Test status
Simulation time 2453436085 ps
CPU time 68.19 seconds
Started Aug 18 05:37:10 PM PDT 24
Finished Aug 18 05:38:18 PM PDT 24
Peak memory 224068 kb
Host smart-f69734de-b638-4927-b6a4-d2493ac439a1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3296137979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.3296137979
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1727759460
Short name T1988
Test name
Test status
Simulation time 199516832 ps
CPU time 0.92 seconds
Started Aug 18 05:37:04 PM PDT 24
Finished Aug 18 05:37:05 PM PDT 24
Peak memory 207492 kb
Host smart-2f91207a-1a72-4653-a14f-ee819653252a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17277
59460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1727759460
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.355680903
Short name T2548
Test name
Test status
Simulation time 163343353 ps
CPU time 0.83 seconds
Started Aug 18 05:36:50 PM PDT 24
Finished Aug 18 05:36:51 PM PDT 24
Peak memory 207484 kb
Host smart-fc51bec9-9f6f-46c5-9a7f-95bb3f0ad432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35568
0903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.355680903
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.4061232652
Short name T1735
Test name
Test status
Simulation time 381434447 ps
CPU time 1.32 seconds
Started Aug 18 05:37:06 PM PDT 24
Finished Aug 18 05:37:07 PM PDT 24
Peak memory 207524 kb
Host smart-29078773-ff55-44b1-af4b-167f8c4f3522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40612
32652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.4061232652
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.2681124034
Short name T1353
Test name
Test status
Simulation time 2001755113 ps
CPU time 55.3 seconds
Started Aug 18 05:36:52 PM PDT 24
Finished Aug 18 05:37:47 PM PDT 24
Peak memory 217308 kb
Host smart-c3f8def4-b3b9-4f9b-a019-3d11456d3617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26811
24034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.2681124034
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.789866792
Short name T51
Test name
Test status
Simulation time 1555401617 ps
CPU time 13.82 seconds
Started Aug 18 05:36:47 PM PDT 24
Finished Aug 18 05:37:01 PM PDT 24
Peak memory 207572 kb
Host smart-3322255a-7d6d-48d2-bbb5-10569490f85e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789866792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_host
_handshake.789866792
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_tx_rx_disruption.2845209440
Short name T182
Test name
Test status
Simulation time 653990635 ps
CPU time 2 seconds
Started Aug 18 05:36:43 PM PDT 24
Finished Aug 18 05:36:45 PM PDT 24
Peak memory 207492 kb
Host smart-36c5a693-607e-4c7e-bdd8-bf678d172deb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845209440 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.usbdev_tx_rx_disruption.2845209440
Directory /workspace/34.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/340.usbdev_tx_rx_disruption.381169705
Short name T3012
Test name
Test status
Simulation time 539851405 ps
CPU time 1.57 seconds
Started Aug 18 05:39:59 PM PDT 24
Finished Aug 18 05:40:01 PM PDT 24
Peak memory 207508 kb
Host smart-232819c0-ee0f-4a88-b734-c71bbe01b68a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381169705 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 340.usbdev_tx_rx_disruption.381169705
Directory /workspace/340.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/341.usbdev_tx_rx_disruption.3267856912
Short name T2136
Test name
Test status
Simulation time 551949281 ps
CPU time 1.54 seconds
Started Aug 18 05:40:25 PM PDT 24
Finished Aug 18 05:40:27 PM PDT 24
Peak memory 207592 kb
Host smart-d18357fd-2b82-4744-b48c-448904830675
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267856912 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 341.usbdev_tx_rx_disruption.3267856912
Directory /workspace/341.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/342.usbdev_tx_rx_disruption.2836551473
Short name T197
Test name
Test status
Simulation time 534056183 ps
CPU time 1.56 seconds
Started Aug 18 05:40:06 PM PDT 24
Finished Aug 18 05:40:08 PM PDT 24
Peak memory 207556 kb
Host smart-27c4269e-7776-4907-8969-3f8ce4fa0f2c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836551473 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 342.usbdev_tx_rx_disruption.2836551473
Directory /workspace/342.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/343.usbdev_tx_rx_disruption.3480019179
Short name T227
Test name
Test status
Simulation time 526507633 ps
CPU time 1.57 seconds
Started Aug 18 05:40:04 PM PDT 24
Finished Aug 18 05:40:06 PM PDT 24
Peak memory 207568 kb
Host smart-ca5d02d3-e31c-45e1-84a0-05681c371094
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480019179 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 343.usbdev_tx_rx_disruption.3480019179
Directory /workspace/343.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/344.usbdev_tx_rx_disruption.1652081208
Short name T2585
Test name
Test status
Simulation time 537386038 ps
CPU time 1.63 seconds
Started Aug 18 05:40:27 PM PDT 24
Finished Aug 18 05:40:28 PM PDT 24
Peak memory 207456 kb
Host smart-e79f4c4d-6e00-4f4a-89a1-e167cfa31217
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652081208 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 344.usbdev_tx_rx_disruption.1652081208
Directory /workspace/344.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/345.usbdev_tx_rx_disruption.4028426634
Short name T3010
Test name
Test status
Simulation time 589558778 ps
CPU time 1.52 seconds
Started Aug 18 05:40:03 PM PDT 24
Finished Aug 18 05:40:05 PM PDT 24
Peak memory 207548 kb
Host smart-c26ed548-01ff-4c38-bf8b-63639e715135
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028426634 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 345.usbdev_tx_rx_disruption.4028426634
Directory /workspace/345.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/346.usbdev_tx_rx_disruption.1636447946
Short name T843
Test name
Test status
Simulation time 591628932 ps
CPU time 1.69 seconds
Started Aug 18 05:40:20 PM PDT 24
Finished Aug 18 05:40:22 PM PDT 24
Peak memory 207560 kb
Host smart-93534072-7af3-4360-ae25-3103eb6e396c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636447946 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 346.usbdev_tx_rx_disruption.1636447946
Directory /workspace/346.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/347.usbdev_tx_rx_disruption.3792913812
Short name T2725
Test name
Test status
Simulation time 626375938 ps
CPU time 1.61 seconds
Started Aug 18 05:40:03 PM PDT 24
Finished Aug 18 05:40:05 PM PDT 24
Peak memory 207592 kb
Host smart-5393c1bf-fd97-4179-b639-cf95aeb50416
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792913812 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 347.usbdev_tx_rx_disruption.3792913812
Directory /workspace/347.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/348.usbdev_tx_rx_disruption.3448539199
Short name T2319
Test name
Test status
Simulation time 609379950 ps
CPU time 1.71 seconds
Started Aug 18 05:40:07 PM PDT 24
Finished Aug 18 05:40:09 PM PDT 24
Peak memory 207584 kb
Host smart-7c005c26-b737-43fa-9ea8-939bd78594e4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448539199 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 348.usbdev_tx_rx_disruption.3448539199
Directory /workspace/348.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/349.usbdev_tx_rx_disruption.2258334169
Short name T1330
Test name
Test status
Simulation time 620058229 ps
CPU time 1.64 seconds
Started Aug 18 05:39:57 PM PDT 24
Finished Aug 18 05:39:59 PM PDT 24
Peak memory 207524 kb
Host smart-1ff29f25-51b0-451f-a4ef-3d460d7b4475
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258334169 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 349.usbdev_tx_rx_disruption.2258334169
Directory /workspace/349.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.3939771877
Short name T3358
Test name
Test status
Simulation time 45775732 ps
CPU time 0.72 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 207452 kb
Host smart-c116dc98-90dd-4c45-b6f0-e20ec7464bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3939771877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.3939771877
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2885683903
Short name T799
Test name
Test status
Simulation time 9332989580 ps
CPU time 12.31 seconds
Started Aug 18 05:36:59 PM PDT 24
Finished Aug 18 05:37:12 PM PDT 24
Peak memory 207792 kb
Host smart-fc4facf2-f752-453f-abc0-28b0bf7c9453
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885683903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.2885683903
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.1634379575
Short name T3050
Test name
Test status
Simulation time 19599779179 ps
CPU time 22.9 seconds
Started Aug 18 05:36:49 PM PDT 24
Finished Aug 18 05:37:12 PM PDT 24
Peak memory 207524 kb
Host smart-e1dfd6d2-1103-4161-9f2f-00732578c488
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634379575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.1634379575
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.1640800823
Short name T830
Test name
Test status
Simulation time 26212573476 ps
CPU time 31.94 seconds
Started Aug 18 05:37:03 PM PDT 24
Finished Aug 18 05:37:35 PM PDT 24
Peak memory 215960 kb
Host smart-04b55763-0c3c-4078-90a1-fca83a86d2a1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640800823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_resume.1640800823
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1105506945
Short name T116
Test name
Test status
Simulation time 142157905 ps
CPU time 0.79 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207484 kb
Host smart-bfa2326a-4bc1-456f-be3f-18471dd80075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11055
06945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1105506945
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.1955117191
Short name T1004
Test name
Test status
Simulation time 405421502 ps
CPU time 1.54 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:36:56 PM PDT 24
Peak memory 207528 kb
Host smart-e4c838a6-adb8-4423-b628-dca65b7ababe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19551
17191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.1955117191
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.656504052
Short name T2163
Test name
Test status
Simulation time 441526787 ps
CPU time 1.42 seconds
Started Aug 18 05:37:00 PM PDT 24
Finished Aug 18 05:37:02 PM PDT 24
Peak memory 207564 kb
Host smart-358959ab-7bd7-41bb-b9aa-78174033277f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=656504052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.656504052
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.483160840
Short name T1602
Test name
Test status
Simulation time 47159555948 ps
CPU time 81.7 seconds
Started Aug 18 05:36:53 PM PDT 24
Finished Aug 18 05:38:15 PM PDT 24
Peak memory 207792 kb
Host smart-af32f54c-5fbe-4ddd-9978-2469c0f5d82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48316
0840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.483160840
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.412754627
Short name T1102
Test name
Test status
Simulation time 221218700 ps
CPU time 0.97 seconds
Started Aug 18 05:37:00 PM PDT 24
Finished Aug 18 05:37:01 PM PDT 24
Peak memory 207460 kb
Host smart-e3aedc64-7b63-470d-9cbc-d105fea1a866
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412754627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.412754627
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.4004846697
Short name T2123
Test name
Test status
Simulation time 904413562 ps
CPU time 2.06 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:19 PM PDT 24
Peak memory 207564 kb
Host smart-0efc5a09-c7d6-4c13-b8ad-6223094bcf55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40048
46697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.4004846697
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1676869992
Short name T1812
Test name
Test status
Simulation time 160304801 ps
CPU time 0.82 seconds
Started Aug 18 05:36:50 PM PDT 24
Finished Aug 18 05:36:51 PM PDT 24
Peak memory 207552 kb
Host smart-af115755-25a7-4621-8197-361f995da2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16768
69992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1676869992
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.1676870942
Short name T1887
Test name
Test status
Simulation time 102254596 ps
CPU time 0.76 seconds
Started Aug 18 05:36:57 PM PDT 24
Finished Aug 18 05:36:58 PM PDT 24
Peak memory 207468 kb
Host smart-2688857e-e188-4e82-95eb-16359e93b0c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16768
70942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1676870942
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3127276284
Short name T2788
Test name
Test status
Simulation time 872948703 ps
CPU time 2.3 seconds
Started Aug 18 05:37:07 PM PDT 24
Finished Aug 18 05:37:09 PM PDT 24
Peak memory 207800 kb
Host smart-3746e010-880a-48a4-86d0-920036a49e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31272
76284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3127276284
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_types.186201529
Short name T2464
Test name
Test status
Simulation time 287674910 ps
CPU time 1.07 seconds
Started Aug 18 05:36:58 PM PDT 24
Finished Aug 18 05:37:00 PM PDT 24
Peak memory 207424 kb
Host smart-18479d07-3958-41ae-8365-85681f431a6b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=186201529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_types.186201529
Directory /workspace/35.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1282661836
Short name T2489
Test name
Test status
Simulation time 292049217 ps
CPU time 2.18 seconds
Started Aug 18 05:36:57 PM PDT 24
Finished Aug 18 05:36:59 PM PDT 24
Peak memory 207688 kb
Host smart-9d338152-db35-46b2-bb02-1f9ed4d86a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12826
61836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1282661836
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.495435297
Short name T1539
Test name
Test status
Simulation time 211524965 ps
CPU time 1.13 seconds
Started Aug 18 05:36:59 PM PDT 24
Finished Aug 18 05:37:01 PM PDT 24
Peak memory 215892 kb
Host smart-71e5a329-b7ed-4f80-b4d7-7e559bea136e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=495435297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.495435297
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1745743769
Short name T935
Test name
Test status
Simulation time 143158115 ps
CPU time 0.82 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:36:55 PM PDT 24
Peak memory 207476 kb
Host smart-79343d9f-a936-4a61-b45c-7402ea9af423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17457
43769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1745743769
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1924847429
Short name T1038
Test name
Test status
Simulation time 247985361 ps
CPU time 1.01 seconds
Started Aug 18 05:36:57 PM PDT 24
Finished Aug 18 05:36:59 PM PDT 24
Peak memory 207452 kb
Host smart-23c2ca34-8a68-4dda-af79-a3def069106e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19248
47429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1924847429
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.2862264363
Short name T2668
Test name
Test status
Simulation time 2848867895 ps
CPU time 27.38 seconds
Started Aug 18 05:37:02 PM PDT 24
Finished Aug 18 05:37:29 PM PDT 24
Peak memory 218048 kb
Host smart-cf7c4f1b-3757-4169-95c4-3da2653ee23e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2862264363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.2862264363
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.3973067271
Short name T566
Test name
Test status
Simulation time 4739798155 ps
CPU time 37.44 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:37:31 PM PDT 24
Peak memory 207772 kb
Host smart-864851a1-7063-4458-be10-499503106fac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3973067271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.3973067271
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1678498101
Short name T647
Test name
Test status
Simulation time 207320031 ps
CPU time 1.01 seconds
Started Aug 18 05:37:01 PM PDT 24
Finished Aug 18 05:37:02 PM PDT 24
Peak memory 207572 kb
Host smart-7cbf6ef0-cbe8-43d8-9a70-b95ac5b35895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16784
98101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1678498101
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.442733721
Short name T2295
Test name
Test status
Simulation time 26118376794 ps
CPU time 38.3 seconds
Started Aug 18 05:37:08 PM PDT 24
Finished Aug 18 05:37:47 PM PDT 24
Peak memory 215884 kb
Host smart-0052f743-a95e-41bb-8ab6-415565139287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44273
3721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.442733721
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.1367736274
Short name T2348
Test name
Test status
Simulation time 5566692074 ps
CPU time 7.28 seconds
Started Aug 18 05:37:06 PM PDT 24
Finished Aug 18 05:37:13 PM PDT 24
Peak memory 215816 kb
Host smart-da2826ed-acb2-4de6-94f5-0e2d4205b76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13677
36274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1367736274
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.4254296281
Short name T2833
Test name
Test status
Simulation time 6194771710 ps
CPU time 191.4 seconds
Started Aug 18 05:37:08 PM PDT 24
Finished Aug 18 05:40:19 PM PDT 24
Peak memory 218552 kb
Host smart-69d08c79-56a2-4138-9d78-d6fc5737fa72
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4254296281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.4254296281
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2003257617
Short name T282
Test name
Test status
Simulation time 2854162102 ps
CPU time 22.77 seconds
Started Aug 18 05:36:54 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 215976 kb
Host smart-bb76610b-10f4-4850-ab62-65293760c723
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2003257617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2003257617
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.1085009625
Short name T1867
Test name
Test status
Simulation time 268445295 ps
CPU time 1.11 seconds
Started Aug 18 05:37:20 PM PDT 24
Finished Aug 18 05:37:22 PM PDT 24
Peak memory 207500 kb
Host smart-b1a86e8b-abfb-4156-80e5-a1b062f27da3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1085009625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1085009625
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2991304430
Short name T678
Test name
Test status
Simulation time 195629703 ps
CPU time 0.98 seconds
Started Aug 18 05:37:07 PM PDT 24
Finished Aug 18 05:37:08 PM PDT 24
Peak memory 207500 kb
Host smart-e4967113-5d43-43fe-9cbc-9ffa3a88580b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29913
04430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2991304430
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2539230764
Short name T2699
Test name
Test status
Simulation time 2643435847 ps
CPU time 26.11 seconds
Started Aug 18 05:37:05 PM PDT 24
Finished Aug 18 05:37:31 PM PDT 24
Peak memory 215920 kb
Host smart-f20e9ac4-2d17-4a27-b700-e3cbd8456ecd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2539230764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2539230764
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.2889369680
Short name T833
Test name
Test status
Simulation time 174424422 ps
CPU time 0.87 seconds
Started Aug 18 05:37:05 PM PDT 24
Finished Aug 18 05:37:06 PM PDT 24
Peak memory 207412 kb
Host smart-53043f1e-2da1-4d49-a853-0a973fe95cd1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2889369680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.2889369680
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3971427053
Short name T3621
Test name
Test status
Simulation time 185832146 ps
CPU time 0.94 seconds
Started Aug 18 05:36:58 PM PDT 24
Finished Aug 18 05:36:59 PM PDT 24
Peak memory 207456 kb
Host smart-858e85cc-6200-49f1-b241-79f0dc9a78a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39714
27053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3971427053
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3924564517
Short name T166
Test name
Test status
Simulation time 245535498 ps
CPU time 1.04 seconds
Started Aug 18 05:37:00 PM PDT 24
Finished Aug 18 05:37:02 PM PDT 24
Peak memory 207504 kb
Host smart-f8a1df7c-6cbd-4495-8507-8c474b84e1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39245
64517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3924564517
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.2988518708
Short name T738
Test name
Test status
Simulation time 207273176 ps
CPU time 0.93 seconds
Started Aug 18 05:37:04 PM PDT 24
Finished Aug 18 05:37:05 PM PDT 24
Peak memory 207476 kb
Host smart-2cc88a52-5cfe-4e33-a5bf-b92725d725c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29885
18708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.2988518708
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2965860506
Short name T3288
Test name
Test status
Simulation time 160680961 ps
CPU time 0.83 seconds
Started Aug 18 05:37:06 PM PDT 24
Finished Aug 18 05:37:07 PM PDT 24
Peak memory 207492 kb
Host smart-c224f73f-ac3e-47d0-b5fd-6bb68e12e53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29658
60506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2965860506
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1403982510
Short name T1138
Test name
Test status
Simulation time 156620590 ps
CPU time 0.93 seconds
Started Aug 18 05:37:02 PM PDT 24
Finished Aug 18 05:37:03 PM PDT 24
Peak memory 207556 kb
Host smart-220c83a7-3564-4a15-800b-e4941ba524d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14039
82510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1403982510
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1840946530
Short name T591
Test name
Test status
Simulation time 166462674 ps
CPU time 0.85 seconds
Started Aug 18 05:37:12 PM PDT 24
Finished Aug 18 05:37:13 PM PDT 24
Peak memory 207564 kb
Host smart-2dbf4dae-7fed-4204-bbec-f3196ae0d4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18409
46530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1840946530
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.705493643
Short name T3455
Test name
Test status
Simulation time 216850059 ps
CPU time 1.09 seconds
Started Aug 18 05:37:03 PM PDT 24
Finished Aug 18 05:37:05 PM PDT 24
Peak memory 207532 kb
Host smart-cc842feb-bbe1-4ae7-9315-93ea09d1a927
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=705493643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.705493643
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2139124013
Short name T239
Test name
Test status
Simulation time 212746220 ps
CPU time 0.88 seconds
Started Aug 18 05:37:10 PM PDT 24
Finished Aug 18 05:37:11 PM PDT 24
Peak memory 207448 kb
Host smart-4584e57e-3229-4341-9975-53fa42ae67d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21391
24013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2139124013
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2685635892
Short name T3144
Test name
Test status
Simulation time 38243328 ps
CPU time 0.7 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 207520 kb
Host smart-b63b75ca-e804-4dd8-b812-581e9c94ace0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26856
35892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2685635892
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.2302817303
Short name T2010
Test name
Test status
Simulation time 22396988487 ps
CPU time 56.51 seconds
Started Aug 18 05:37:07 PM PDT 24
Finished Aug 18 05:38:04 PM PDT 24
Peak memory 224052 kb
Host smart-e9409f2e-7f95-4515-bb96-ba7b92267a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23028
17303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.2302817303
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.619606936
Short name T361
Test name
Test status
Simulation time 150793518 ps
CPU time 0.86 seconds
Started Aug 18 05:36:59 PM PDT 24
Finished Aug 18 05:37:00 PM PDT 24
Peak memory 207496 kb
Host smart-31144c69-691c-4a66-b373-f5770bb5832c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61960
6936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.619606936
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3581406669
Short name T1967
Test name
Test status
Simulation time 191182999 ps
CPU time 0.92 seconds
Started Aug 18 05:37:04 PM PDT 24
Finished Aug 18 05:37:05 PM PDT 24
Peak memory 207480 kb
Host smart-259a3a3a-9187-404c-a796-21f0088790db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35814
06669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3581406669
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.2471435073
Short name T1383
Test name
Test status
Simulation time 210970398 ps
CPU time 1.02 seconds
Started Aug 18 05:37:05 PM PDT 24
Finished Aug 18 05:37:06 PM PDT 24
Peak memory 207504 kb
Host smart-20df50ca-4e73-4d86-9795-c01799674556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24714
35073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2471435073
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.223419694
Short name T878
Test name
Test status
Simulation time 183567077 ps
CPU time 0.94 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:16 PM PDT 24
Peak memory 207480 kb
Host smart-af3b97a2-8780-4a41-8947-c8474ffffedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22341
9694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.223419694
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.95494751
Short name T1369
Test name
Test status
Simulation time 155116691 ps
CPU time 0.86 seconds
Started Aug 18 05:37:11 PM PDT 24
Finished Aug 18 05:37:12 PM PDT 24
Peak memory 207464 kb
Host smart-e9ba9ecf-406a-4384-9f0e-7888e19c4401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95494
751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.95494751
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_rx_full.877114370
Short name T41
Test name
Test status
Simulation time 251464959 ps
CPU time 1.09 seconds
Started Aug 18 05:37:08 PM PDT 24
Finished Aug 18 05:37:09 PM PDT 24
Peak memory 207508 kb
Host smart-853258c1-262a-4369-9d66-853b67c1e1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87711
4370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_full.877114370
Directory /workspace/35.usbdev_rx_full/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1644059153
Short name T2694
Test name
Test status
Simulation time 167637753 ps
CPU time 0.91 seconds
Started Aug 18 05:37:11 PM PDT 24
Finished Aug 18 05:37:12 PM PDT 24
Peak memory 207544 kb
Host smart-2c36999e-fcde-45b5-99c4-aab989e9f492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16440
59153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1644059153
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1965981940
Short name T1161
Test name
Test status
Simulation time 209168610 ps
CPU time 0.95 seconds
Started Aug 18 05:37:08 PM PDT 24
Finished Aug 18 05:37:09 PM PDT 24
Peak memory 207452 kb
Host smart-ca6e5027-537b-4173-8de4-ad9faae9d963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19659
81940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1965981940
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.522627493
Short name T690
Test name
Test status
Simulation time 201128288 ps
CPU time 1.03 seconds
Started Aug 18 05:37:12 PM PDT 24
Finished Aug 18 05:37:13 PM PDT 24
Peak memory 207448 kb
Host smart-9f0be734-9e7c-40a0-92a7-6f3ddf038a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52262
7493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.522627493
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.800843449
Short name T1736
Test name
Test status
Simulation time 2678792534 ps
CPU time 78.9 seconds
Started Aug 18 05:37:01 PM PDT 24
Finished Aug 18 05:38:20 PM PDT 24
Peak memory 217596 kb
Host smart-33c589da-ebff-45ce-948b-145d5b87efaf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=800843449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.800843449
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3265374753
Short name T3270
Test name
Test status
Simulation time 170905764 ps
CPU time 0.89 seconds
Started Aug 18 05:37:03 PM PDT 24
Finished Aug 18 05:37:03 PM PDT 24
Peak memory 207504 kb
Host smart-4168399d-cff4-48d3-8e2a-a71714cb0521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32653
74753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3265374753
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1525682117
Short name T1456
Test name
Test status
Simulation time 178014858 ps
CPU time 0.91 seconds
Started Aug 18 05:37:21 PM PDT 24
Finished Aug 18 05:37:22 PM PDT 24
Peak memory 207484 kb
Host smart-64103447-d398-4104-81b4-e793cfcf3528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15256
82117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1525682117
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.3095981031
Short name T1929
Test name
Test status
Simulation time 626125659 ps
CPU time 1.78 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:37:11 PM PDT 24
Peak memory 207544 kb
Host smart-49fd9284-f76f-4b91-b69b-439415733c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30959
81031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.3095981031
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.1803055379
Short name T1276
Test name
Test status
Simulation time 1776624917 ps
CPU time 16 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:37:26 PM PDT 24
Peak memory 216016 kb
Host smart-5dff0622-00b4-4e41-b306-050a3297f219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18030
55379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1803055379
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.743129088
Short name T2175
Test name
Test status
Simulation time 177607111 ps
CPU time 0.87 seconds
Started Aug 18 05:37:08 PM PDT 24
Finished Aug 18 05:37:09 PM PDT 24
Peak memory 207476 kb
Host smart-a33541f8-7bf1-436f-9207-bfeee9ba7d67
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743129088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_host
_handshake.743129088
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_tx_rx_disruption.753521751
Short name T2721
Test name
Test status
Simulation time 478141392 ps
CPU time 1.54 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 207576 kb
Host smart-1b48551c-62cb-43bb-b3c9-9b69601a3ce1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753521751 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.usbdev_tx_rx_disruption.753521751
Directory /workspace/35.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/350.usbdev_tx_rx_disruption.1503040780
Short name T2328
Test name
Test status
Simulation time 489223952 ps
CPU time 1.5 seconds
Started Aug 18 05:40:04 PM PDT 24
Finished Aug 18 05:40:06 PM PDT 24
Peak memory 207508 kb
Host smart-6a9cf8b0-7751-4036-bf4e-b3aed3695ce0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503040780 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 350.usbdev_tx_rx_disruption.1503040780
Directory /workspace/350.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/351.usbdev_tx_rx_disruption.709788053
Short name T2162
Test name
Test status
Simulation time 580631258 ps
CPU time 1.65 seconds
Started Aug 18 05:39:57 PM PDT 24
Finished Aug 18 05:39:58 PM PDT 24
Peak memory 207588 kb
Host smart-9e37cc91-e213-4964-9b97-19b5dd19b353
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709788053 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 351.usbdev_tx_rx_disruption.709788053
Directory /workspace/351.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/352.usbdev_tx_rx_disruption.3451532604
Short name T3397
Test name
Test status
Simulation time 554287300 ps
CPU time 1.7 seconds
Started Aug 18 05:40:03 PM PDT 24
Finished Aug 18 05:40:05 PM PDT 24
Peak memory 207540 kb
Host smart-eaa50efb-432e-442c-ae87-fa57c85dd41d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451532604 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 352.usbdev_tx_rx_disruption.3451532604
Directory /workspace/352.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/353.usbdev_tx_rx_disruption.2870176754
Short name T1670
Test name
Test status
Simulation time 448522955 ps
CPU time 1.39 seconds
Started Aug 18 05:39:55 PM PDT 24
Finished Aug 18 05:39:57 PM PDT 24
Peak memory 207456 kb
Host smart-f1448ea8-c4b9-45b6-a46e-9d71f112a5b1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870176754 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 353.usbdev_tx_rx_disruption.2870176754
Directory /workspace/353.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/354.usbdev_tx_rx_disruption.354191318
Short name T3292
Test name
Test status
Simulation time 522016150 ps
CPU time 1.6 seconds
Started Aug 18 05:40:05 PM PDT 24
Finished Aug 18 05:40:07 PM PDT 24
Peak memory 207548 kb
Host smart-6bc6aa2d-5721-4f2b-86eb-178b9886de22
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354191318 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 354.usbdev_tx_rx_disruption.354191318
Directory /workspace/354.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/355.usbdev_tx_rx_disruption.1932024840
Short name T3474
Test name
Test status
Simulation time 582272419 ps
CPU time 1.57 seconds
Started Aug 18 05:40:03 PM PDT 24
Finished Aug 18 05:40:04 PM PDT 24
Peak memory 207376 kb
Host smart-dd0fdc13-01fa-4eb7-b106-d84cf2738763
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932024840 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 355.usbdev_tx_rx_disruption.1932024840
Directory /workspace/355.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/356.usbdev_tx_rx_disruption.345876677
Short name T3359
Test name
Test status
Simulation time 586413902 ps
CPU time 1.65 seconds
Started Aug 18 05:40:03 PM PDT 24
Finished Aug 18 05:40:05 PM PDT 24
Peak memory 207592 kb
Host smart-4de9c839-4e1f-4a25-a9b7-990ea28b690c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345876677 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 356.usbdev_tx_rx_disruption.345876677
Directory /workspace/356.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/357.usbdev_tx_rx_disruption.306985194
Short name T3176
Test name
Test status
Simulation time 584009754 ps
CPU time 1.72 seconds
Started Aug 18 05:40:09 PM PDT 24
Finished Aug 18 05:40:11 PM PDT 24
Peak memory 207612 kb
Host smart-8cff1c59-1424-403b-a7bf-c0a76350850f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306985194 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 357.usbdev_tx_rx_disruption.306985194
Directory /workspace/357.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/358.usbdev_tx_rx_disruption.1888927530
Short name T2292
Test name
Test status
Simulation time 479620076 ps
CPU time 1.44 seconds
Started Aug 18 05:40:09 PM PDT 24
Finished Aug 18 05:40:11 PM PDT 24
Peak memory 207572 kb
Host smart-a8b70381-e611-461f-ad3a-6d98c8a0daa2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888927530 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 358.usbdev_tx_rx_disruption.1888927530
Directory /workspace/358.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/359.usbdev_tx_rx_disruption.1470232462
Short name T2649
Test name
Test status
Simulation time 616700888 ps
CPU time 1.64 seconds
Started Aug 18 05:40:15 PM PDT 24
Finished Aug 18 05:40:17 PM PDT 24
Peak memory 207552 kb
Host smart-2d1514cc-f4cd-4a25-a5d7-d1cf09be1dc7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470232462 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 359.usbdev_tx_rx_disruption.1470232462
Directory /workspace/359.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.1676789016
Short name T923
Test name
Test status
Simulation time 44433102 ps
CPU time 0.67 seconds
Started Aug 18 05:37:04 PM PDT 24
Finished Aug 18 05:37:05 PM PDT 24
Peak memory 207460 kb
Host smart-b60d69c9-7890-4b9e-bbe4-a86f8a1d5044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1676789016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.1676789016
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2742143946
Short name T2483
Test name
Test status
Simulation time 6777504858 ps
CPU time 9.08 seconds
Started Aug 18 05:37:05 PM PDT 24
Finished Aug 18 05:37:14 PM PDT 24
Peak memory 216008 kb
Host smart-6497812b-0a60-4da0-b040-eec4a5807ed7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742143946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.2742143946
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.4148369841
Short name T2087
Test name
Test status
Simulation time 19740305611 ps
CPU time 23.46 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:37:32 PM PDT 24
Peak memory 207768 kb
Host smart-4df7cc83-3a90-41b7-b59e-957f86fb0738
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148369841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.4148369841
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.1325613374
Short name T1785
Test name
Test status
Simulation time 24796083447 ps
CPU time 29.13 seconds
Started Aug 18 05:37:11 PM PDT 24
Finished Aug 18 05:37:40 PM PDT 24
Peak memory 215912 kb
Host smart-e9635531-3d81-43da-8833-4c779d97bbdf
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325613374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.1325613374
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2292896623
Short name T990
Test name
Test status
Simulation time 216947801 ps
CPU time 0.95 seconds
Started Aug 18 05:37:11 PM PDT 24
Finished Aug 18 05:37:13 PM PDT 24
Peak memory 207460 kb
Host smart-11a8410b-8d9f-4952-8d55-161f8e30d439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22928
96623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2292896623
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.278677206
Short name T2875
Test name
Test status
Simulation time 148036657 ps
CPU time 0.84 seconds
Started Aug 18 05:37:06 PM PDT 24
Finished Aug 18 05:37:07 PM PDT 24
Peak memory 207508 kb
Host smart-760f15ce-d75f-4e2a-a87e-5814e06d6868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
7206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.278677206
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3235715516
Short name T1086
Test name
Test status
Simulation time 256226236 ps
CPU time 1.08 seconds
Started Aug 18 05:36:57 PM PDT 24
Finished Aug 18 05:36:59 PM PDT 24
Peak memory 207492 kb
Host smart-77844647-1ee4-4dfa-8d27-b840a338b082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32357
15516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3235715516
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.328398578
Short name T1766
Test name
Test status
Simulation time 732789317 ps
CPU time 2.05 seconds
Started Aug 18 05:37:10 PM PDT 24
Finished Aug 18 05:37:12 PM PDT 24
Peak memory 207808 kb
Host smart-d0450981-edbd-498c-b6f3-7ba3358939af
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=328398578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.328398578
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.2479756350
Short name T3148
Test name
Test status
Simulation time 28983419976 ps
CPU time 52.45 seconds
Started Aug 18 05:37:06 PM PDT 24
Finished Aug 18 05:37:59 PM PDT 24
Peak memory 207748 kb
Host smart-723a865f-673a-433d-8553-64a4c226340e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24797
56350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.2479756350
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.2355156525
Short name T2077
Test name
Test status
Simulation time 3119412185 ps
CPU time 22.54 seconds
Started Aug 18 05:37:08 PM PDT 24
Finished Aug 18 05:37:30 PM PDT 24
Peak memory 207852 kb
Host smart-eeb7e8cd-c819-4573-946a-d560638dac58
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355156525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.2355156525
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.3508163081
Short name T2651
Test name
Test status
Simulation time 944923581 ps
CPU time 2.02 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:37:11 PM PDT 24
Peak memory 207496 kb
Host smart-1b6c3f5f-bb97-4943-a2b4-e5a93792dc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35081
63081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.3508163081
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2957558489
Short name T1005
Test name
Test status
Simulation time 154284092 ps
CPU time 0.88 seconds
Started Aug 18 05:37:10 PM PDT 24
Finished Aug 18 05:37:11 PM PDT 24
Peak memory 207564 kb
Host smart-afa0b0b4-060a-42ad-8eb5-7b28443d36fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29575
58489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2957558489
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3053118503
Short name T3442
Test name
Test status
Simulation time 94206122 ps
CPU time 0.75 seconds
Started Aug 18 05:36:57 PM PDT 24
Finished Aug 18 05:36:58 PM PDT 24
Peak memory 207448 kb
Host smart-6a55f83e-07e1-42a2-8e47-4db84e899a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30531
18503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3053118503
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.1557239033
Short name T2126
Test name
Test status
Simulation time 1060464883 ps
CPU time 2.98 seconds
Started Aug 18 05:36:59 PM PDT 24
Finished Aug 18 05:37:02 PM PDT 24
Peak memory 207736 kb
Host smart-a2c509b9-7b68-4c17-818f-1e1967722b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15572
39033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.1557239033
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_types.3552919911
Short name T412
Test name
Test status
Simulation time 487434697 ps
CPU time 1.38 seconds
Started Aug 18 05:37:23 PM PDT 24
Finished Aug 18 05:37:24 PM PDT 24
Peak memory 207540 kb
Host smart-50ebf492-08dd-4375-b635-681272c3f71b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3552919911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_types.3552919911
Directory /workspace/36.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.135264268
Short name T919
Test name
Test status
Simulation time 344816661 ps
CPU time 2.47 seconds
Started Aug 18 05:37:01 PM PDT 24
Finished Aug 18 05:37:04 PM PDT 24
Peak memory 207616 kb
Host smart-b9daf67a-7877-4828-8429-b1518d1fc1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13526
4268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.135264268
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3702402346
Short name T744
Test name
Test status
Simulation time 238499274 ps
CPU time 1.19 seconds
Started Aug 18 05:37:24 PM PDT 24
Finished Aug 18 05:37:25 PM PDT 24
Peak memory 215864 kb
Host smart-6a8b730c-2b12-4c13-aa96-c21e477a21fc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3702402346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3702402346
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1323401621
Short name T1334
Test name
Test status
Simulation time 168397377 ps
CPU time 0.9 seconds
Started Aug 18 05:37:13 PM PDT 24
Finished Aug 18 05:37:14 PM PDT 24
Peak memory 207476 kb
Host smart-5d748b5f-3155-4183-a639-8ed618182c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13234
01621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1323401621
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.932906013
Short name T3443
Test name
Test status
Simulation time 167001061 ps
CPU time 0.9 seconds
Started Aug 18 05:37:11 PM PDT 24
Finished Aug 18 05:37:12 PM PDT 24
Peak memory 207500 kb
Host smart-1087b013-1467-43a8-9f4e-c025c51d2edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93290
6013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.932906013
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.2209116218
Short name T2895
Test name
Test status
Simulation time 4062395005 ps
CPU time 31.85 seconds
Started Aug 18 05:37:33 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 218020 kb
Host smart-e1237207-5cbb-457c-a602-8829ec165e7c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2209116218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.2209116218
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.2589793783
Short name T1718
Test name
Test status
Simulation time 10416537493 ps
CPU time 81.51 seconds
Started Aug 18 05:37:13 PM PDT 24
Finished Aug 18 05:38:35 PM PDT 24
Peak memory 207800 kb
Host smart-e0d65fe7-34eb-4664-93f6-ec3afb7f29f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2589793783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.2589793783
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.643067605
Short name T874
Test name
Test status
Simulation time 258418053 ps
CPU time 1.01 seconds
Started Aug 18 05:37:17 PM PDT 24
Finished Aug 18 05:37:18 PM PDT 24
Peak memory 207492 kb
Host smart-51cb5516-9097-4efb-9b76-2a8b5f0ade06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64306
7605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.643067605
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.1973004564
Short name T2364
Test name
Test status
Simulation time 25280484778 ps
CPU time 38.48 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:52 PM PDT 24
Peak memory 216196 kb
Host smart-9c859969-f6bf-45b2-a34b-1128ccdcae27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19730
04564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1973004564
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.2202083701
Short name T3485
Test name
Test status
Simulation time 10768458216 ps
CPU time 15.41 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:37:24 PM PDT 24
Peak memory 207800 kb
Host smart-97970019-6d6a-4ee0-bbd7-29bd9c964e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22020
83701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.2202083701
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.3398250370
Short name T1278
Test name
Test status
Simulation time 4053187175 ps
CPU time 39.85 seconds
Started Aug 18 05:37:22 PM PDT 24
Finished Aug 18 05:38:03 PM PDT 24
Peak memory 218668 kb
Host smart-fc9ee666-59de-4f16-b5c7-de28894b0c54
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3398250370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.3398250370
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.37201527
Short name T1799
Test name
Test status
Simulation time 2525280363 ps
CPU time 68.87 seconds
Started Aug 18 05:37:10 PM PDT 24
Finished Aug 18 05:38:19 PM PDT 24
Peak memory 217428 kb
Host smart-4388dc3c-a0e4-442c-9b79-016a37855659
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=37201527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.37201527
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.3854094090
Short name T2667
Test name
Test status
Simulation time 264158490 ps
CPU time 1.02 seconds
Started Aug 18 05:37:12 PM PDT 24
Finished Aug 18 05:37:13 PM PDT 24
Peak memory 207480 kb
Host smart-05123726-200c-45b8-a2f4-7e67da758aa8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3854094090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.3854094090
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.905366619
Short name T545
Test name
Test status
Simulation time 219818540 ps
CPU time 0.98 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:37:10 PM PDT 24
Peak memory 207488 kb
Host smart-64f9e805-65ca-4ffd-aad2-4ce0d9dc541a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90536
6619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.905366619
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1467867426
Short name T2338
Test name
Test status
Simulation time 1637458895 ps
CPU time 16.65 seconds
Started Aug 18 05:37:07 PM PDT 24
Finished Aug 18 05:37:24 PM PDT 24
Peak memory 216672 kb
Host smart-d8389bab-81cb-430f-a804-9e02f7da052a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1467867426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1467867426
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.2648788320
Short name T1904
Test name
Test status
Simulation time 172039434 ps
CPU time 0.83 seconds
Started Aug 18 05:37:04 PM PDT 24
Finished Aug 18 05:37:05 PM PDT 24
Peak memory 207416 kb
Host smart-6eb21b33-c0e3-49cb-8412-a0ec87e7e3c3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2648788320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.2648788320
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2794352076
Short name T986
Test name
Test status
Simulation time 168660736 ps
CPU time 0.9 seconds
Started Aug 18 05:37:10 PM PDT 24
Finished Aug 18 05:37:11 PM PDT 24
Peak memory 207504 kb
Host smart-82ad76cc-196a-465a-b465-4c64cd9ac18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27943
52076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2794352076
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3054764965
Short name T2544
Test name
Test status
Simulation time 243319583 ps
CPU time 1.01 seconds
Started Aug 18 05:37:13 PM PDT 24
Finished Aug 18 05:37:14 PM PDT 24
Peak memory 207460 kb
Host smart-69e8319f-d712-46cb-8e3e-45ee3864a048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30547
64965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3054764965
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.152868319
Short name T2365
Test name
Test status
Simulation time 189593232 ps
CPU time 0.94 seconds
Started Aug 18 05:37:17 PM PDT 24
Finished Aug 18 05:37:18 PM PDT 24
Peak memory 207432 kb
Host smart-f72cb3d4-e420-42db-bac7-19d0b80acfe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15286
8319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.152868319
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1747277379
Short name T3484
Test name
Test status
Simulation time 152180322 ps
CPU time 0.84 seconds
Started Aug 18 05:37:19 PM PDT 24
Finished Aug 18 05:37:19 PM PDT 24
Peak memory 207484 kb
Host smart-137968b6-a7d5-4946-b927-65b99ccbce75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17472
77379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1747277379
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3200310730
Short name T1566
Test name
Test status
Simulation time 156979209 ps
CPU time 0.87 seconds
Started Aug 18 05:37:12 PM PDT 24
Finished Aug 18 05:37:13 PM PDT 24
Peak memory 207584 kb
Host smart-5c8a85af-1341-45f6-88a1-c4a60f364ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32003
10730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3200310730
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.4067606159
Short name T2196
Test name
Test status
Simulation time 191776497 ps
CPU time 0.92 seconds
Started Aug 18 05:37:17 PM PDT 24
Finished Aug 18 05:37:18 PM PDT 24
Peak memory 207488 kb
Host smart-fbd281a2-d59c-4f3f-b98a-5a3eecfa498f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40676
06159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.4067606159
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.2228240981
Short name T2227
Test name
Test status
Simulation time 238813474 ps
CPU time 1.11 seconds
Started Aug 18 05:37:10 PM PDT 24
Finished Aug 18 05:37:11 PM PDT 24
Peak memory 207492 kb
Host smart-1476ba8d-1c5b-48fa-af27-e2ebe4535d8d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2228240981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.2228240981
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3394949578
Short name T2976
Test name
Test status
Simulation time 137482077 ps
CPU time 0.88 seconds
Started Aug 18 05:37:22 PM PDT 24
Finished Aug 18 05:37:24 PM PDT 24
Peak memory 207456 kb
Host smart-6ddf3383-c240-4847-93f5-b6ebf3ae56c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33949
49578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3394949578
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1150622018
Short name T1116
Test name
Test status
Simulation time 17070660094 ps
CPU time 45.44 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:38:02 PM PDT 24
Peak memory 215940 kb
Host smart-57e4a6ce-4655-4988-a2df-5818cc952c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11506
22018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1150622018
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2096150422
Short name T1458
Test name
Test status
Simulation time 164321200 ps
CPU time 0.85 seconds
Started Aug 18 05:37:19 PM PDT 24
Finished Aug 18 05:37:20 PM PDT 24
Peak memory 207520 kb
Host smart-24a9607b-a7a7-48d5-890a-1d56c47b087f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20961
50422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2096150422
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3722009703
Short name T1549
Test name
Test status
Simulation time 200756182 ps
CPU time 0.91 seconds
Started Aug 18 05:37:13 PM PDT 24
Finished Aug 18 05:37:14 PM PDT 24
Peak memory 207484 kb
Host smart-7fbd1556-b33a-4f09-ac8e-b29c316b3a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37220
09703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3722009703
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.3485959184
Short name T3573
Test name
Test status
Simulation time 276373955 ps
CPU time 1.04 seconds
Started Aug 18 05:37:10 PM PDT 24
Finished Aug 18 05:37:12 PM PDT 24
Peak memory 207424 kb
Host smart-aecf8f7f-e278-43c5-9a2d-6db832add390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34859
59184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.3485959184
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2113800703
Short name T2192
Test name
Test status
Simulation time 186861142 ps
CPU time 0.93 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:37:11 PM PDT 24
Peak memory 207420 kb
Host smart-012737a8-cd6e-403f-bb23-cd8f3ead6d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21138
00703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2113800703
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2381432778
Short name T105
Test name
Test status
Simulation time 144240943 ps
CPU time 0.91 seconds
Started Aug 18 05:37:23 PM PDT 24
Finished Aug 18 05:37:24 PM PDT 24
Peak memory 207472 kb
Host smart-6aa6a3c8-9a2b-4a9e-969c-f8a285e52c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23814
32778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2381432778
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_rx_full.3786902405
Short name T2843
Test name
Test status
Simulation time 249394426 ps
CPU time 1.08 seconds
Started Aug 18 05:37:08 PM PDT 24
Finished Aug 18 05:37:10 PM PDT 24
Peak memory 207484 kb
Host smart-8f158bba-ea51-4f06-8f2d-070f6dd9b433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37869
02405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_full.3786902405
Directory /workspace/36.usbdev_rx_full/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1510316607
Short name T629
Test name
Test status
Simulation time 152903157 ps
CPU time 0.8 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 207508 kb
Host smart-94bc8feb-5a47-4611-b1f6-f58d867b85da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15103
16607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1510316607
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.840119764
Short name T3125
Test name
Test status
Simulation time 148872076 ps
CPU time 0.9 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:16 PM PDT 24
Peak memory 207572 kb
Host smart-da12d3cc-d152-4652-9205-da89738aae18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84011
9764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.840119764
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3096290166
Short name T1526
Test name
Test status
Simulation time 202113722 ps
CPU time 0.95 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:16 PM PDT 24
Peak memory 207516 kb
Host smart-b60181dd-15ad-445a-bb64-3d8174af24bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30962
90166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3096290166
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.4132577460
Short name T3486
Test name
Test status
Simulation time 2983518368 ps
CPU time 29.88 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:37:39 PM PDT 24
Peak memory 217868 kb
Host smart-b5453416-bf3d-4bfd-8085-097076ed3205
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4132577460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.4132577460
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3851985915
Short name T1465
Test name
Test status
Simulation time 189963320 ps
CPU time 0.92 seconds
Started Aug 18 05:37:10 PM PDT 24
Finished Aug 18 05:37:11 PM PDT 24
Peak memory 207456 kb
Host smart-b4e61f32-56fc-4315-b698-b88b39a3c218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38519
85915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3851985915
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3230120583
Short name T1603
Test name
Test status
Simulation time 192498379 ps
CPU time 0.91 seconds
Started Aug 18 05:37:17 PM PDT 24
Finished Aug 18 05:37:18 PM PDT 24
Peak memory 207536 kb
Host smart-e6e1b709-32d0-4e54-87fa-28397063944a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32301
20583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3230120583
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.126961845
Short name T1489
Test name
Test status
Simulation time 679900795 ps
CPU time 1.9 seconds
Started Aug 18 05:37:19 PM PDT 24
Finished Aug 18 05:37:21 PM PDT 24
Peak memory 207496 kb
Host smart-f6f1366b-1596-48ef-957d-239bc26ede5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12696
1845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.126961845
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1193139718
Short name T765
Test name
Test status
Simulation time 2777911608 ps
CPU time 80.57 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:38:35 PM PDT 24
Peak memory 224072 kb
Host smart-d263f5a7-82fa-4c7a-bd40-f4af8a906f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11931
39718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1193139718
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.2505218095
Short name T3014
Test name
Test status
Simulation time 716813570 ps
CPU time 15.75 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:37:25 PM PDT 24
Peak memory 207668 kb
Host smart-9a4d18b9-3f32-4eda-81cf-70b99b636191
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505218095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.2505218095
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_tx_rx_disruption.3124864076
Short name T2509
Test name
Test status
Simulation time 492719336 ps
CPU time 1.6 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:18 PM PDT 24
Peak memory 207376 kb
Host smart-17129de6-6505-4287-b749-1d7991358fd5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124864076 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.usbdev_tx_rx_disruption.3124864076
Directory /workspace/36.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/360.usbdev_tx_rx_disruption.1939919476
Short name T3626
Test name
Test status
Simulation time 651207858 ps
CPU time 1.72 seconds
Started Aug 18 05:39:58 PM PDT 24
Finished Aug 18 05:40:00 PM PDT 24
Peak memory 207520 kb
Host smart-eef469f1-b9f6-43e2-b7f1-fcd16a91cfa5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939919476 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 360.usbdev_tx_rx_disruption.1939919476
Directory /workspace/360.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/361.usbdev_tx_rx_disruption.3047004505
Short name T3587
Test name
Test status
Simulation time 463831982 ps
CPU time 1.54 seconds
Started Aug 18 05:40:01 PM PDT 24
Finished Aug 18 05:40:03 PM PDT 24
Peak memory 207612 kb
Host smart-4d138775-a792-4d26-b28b-20602431e835
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047004505 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 361.usbdev_tx_rx_disruption.3047004505
Directory /workspace/361.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/362.usbdev_tx_rx_disruption.2613852770
Short name T1586
Test name
Test status
Simulation time 533855241 ps
CPU time 1.6 seconds
Started Aug 18 05:39:54 PM PDT 24
Finished Aug 18 05:39:55 PM PDT 24
Peak memory 207528 kb
Host smart-409c1e5b-56ec-4570-a7c6-3580f3094910
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613852770 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 362.usbdev_tx_rx_disruption.2613852770
Directory /workspace/362.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/363.usbdev_tx_rx_disruption.3555719695
Short name T2202
Test name
Test status
Simulation time 607453762 ps
CPU time 1.69 seconds
Started Aug 18 05:40:17 PM PDT 24
Finished Aug 18 05:40:18 PM PDT 24
Peak memory 207508 kb
Host smart-7dd63b94-23ec-415a-98ad-f8159e625628
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555719695 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 363.usbdev_tx_rx_disruption.3555719695
Directory /workspace/363.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/364.usbdev_tx_rx_disruption.3876288180
Short name T663
Test name
Test status
Simulation time 578840991 ps
CPU time 1.55 seconds
Started Aug 18 05:39:56 PM PDT 24
Finished Aug 18 05:39:58 PM PDT 24
Peak memory 207588 kb
Host smart-d576c2a0-8e0a-46f0-a91c-49299a1930fc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876288180 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 364.usbdev_tx_rx_disruption.3876288180
Directory /workspace/364.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/365.usbdev_tx_rx_disruption.3813043046
Short name T1937
Test name
Test status
Simulation time 445323876 ps
CPU time 1.36 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207572 kb
Host smart-41daeac9-900f-4721-8a20-25c207ad78b6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813043046 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 365.usbdev_tx_rx_disruption.3813043046
Directory /workspace/365.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/366.usbdev_tx_rx_disruption.168983762
Short name T806
Test name
Test status
Simulation time 561060931 ps
CPU time 1.56 seconds
Started Aug 18 05:39:53 PM PDT 24
Finished Aug 18 05:39:54 PM PDT 24
Peak memory 207572 kb
Host smart-89dee2be-0b72-48e3-8c40-46c1e72c5fe9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168983762 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 366.usbdev_tx_rx_disruption.168983762
Directory /workspace/366.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/367.usbdev_tx_rx_disruption.1561132970
Short name T1009
Test name
Test status
Simulation time 534793385 ps
CPU time 1.79 seconds
Started Aug 18 05:39:53 PM PDT 24
Finished Aug 18 05:39:55 PM PDT 24
Peak memory 207524 kb
Host smart-fb7a7915-a687-4fd0-8ac3-531e5a1b4de1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561132970 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 367.usbdev_tx_rx_disruption.1561132970
Directory /workspace/367.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/368.usbdev_tx_rx_disruption.824972586
Short name T1750
Test name
Test status
Simulation time 559336605 ps
CPU time 1.51 seconds
Started Aug 18 05:40:09 PM PDT 24
Finished Aug 18 05:40:11 PM PDT 24
Peak memory 207580 kb
Host smart-b4e3a8f0-d5ae-4d7f-b290-5b21cbdb8293
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824972586 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 368.usbdev_tx_rx_disruption.824972586
Directory /workspace/368.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/369.usbdev_tx_rx_disruption.4188882858
Short name T567
Test name
Test status
Simulation time 548328674 ps
CPU time 1.45 seconds
Started Aug 18 05:40:05 PM PDT 24
Finished Aug 18 05:40:07 PM PDT 24
Peak memory 207552 kb
Host smart-9f441fd0-7193-47f4-bd1e-b5b825ef517a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188882858 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 369.usbdev_tx_rx_disruption.4188882858
Directory /workspace/369.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.1007885879
Short name T3592
Test name
Test status
Simulation time 47276398 ps
CPU time 0.71 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:16 PM PDT 24
Peak memory 207372 kb
Host smart-4502b8db-c210-4df9-9d04-026410842646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1007885879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.1007885879
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2331971989
Short name T3597
Test name
Test status
Simulation time 9623837623 ps
CPU time 13.92 seconds
Started Aug 18 05:37:10 PM PDT 24
Finished Aug 18 05:37:24 PM PDT 24
Peak memory 207840 kb
Host smart-3b65a6bb-2cd7-4e83-9617-629a279274ba
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331971989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.2331971989
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.1411798974
Short name T1849
Test name
Test status
Simulation time 14279916269 ps
CPU time 16.4 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:37:26 PM PDT 24
Peak memory 215980 kb
Host smart-6420d801-16b1-4913-aab5-be5460888f0b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411798974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.1411798974
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.554100879
Short name T1066
Test name
Test status
Simulation time 30733614055 ps
CPU time 36.06 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:51 PM PDT 24
Peak memory 207796 kb
Host smart-2bde686a-54ac-4946-96a9-c939f70e6452
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554100879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ao
n_wake_resume.554100879
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.391544896
Short name T857
Test name
Test status
Simulation time 162040520 ps
CPU time 0.87 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 207424 kb
Host smart-c607b7b6-ea1f-459d-a6f5-94de9b7ba0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39154
4896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.391544896
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.1118774839
Short name T1569
Test name
Test status
Simulation time 145113154 ps
CPU time 0.85 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:37:10 PM PDT 24
Peak memory 207444 kb
Host smart-7e4f0621-7070-49c3-af19-ae1f55f0c3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11187
74839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1118774839
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2328888076
Short name T1338
Test name
Test status
Simulation time 472608206 ps
CPU time 1.57 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:37:11 PM PDT 24
Peak memory 207472 kb
Host smart-74a49a54-57c4-4380-9d1b-c4a6f1039090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23288
88076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2328888076
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2209885737
Short name T2419
Test name
Test status
Simulation time 1257341066 ps
CPU time 3.57 seconds
Started Aug 18 05:37:13 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 207676 kb
Host smart-f4c954d6-7793-46da-8159-45b193bd1fd6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2209885737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2209885737
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.2208125463
Short name T1402
Test name
Test status
Simulation time 47718050830 ps
CPU time 84.66 seconds
Started Aug 18 05:37:21 PM PDT 24
Finished Aug 18 05:38:46 PM PDT 24
Peak memory 207700 kb
Host smart-4dde372f-f737-4336-a87c-4e1952b61352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22081
25463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.2208125463
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.1902219788
Short name T2276
Test name
Test status
Simulation time 875644725 ps
CPU time 18.7 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:34 PM PDT 24
Peak memory 207740 kb
Host smart-b7820552-a419-4989-b20b-5d3f9dd1d0fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902219788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.1902219788
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.2822497274
Short name T3099
Test name
Test status
Simulation time 904634095 ps
CPU time 1.97 seconds
Started Aug 18 05:37:13 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 207456 kb
Host smart-b981c96d-5d67-4eab-8481-fc5b36723ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28224
97274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.2822497274
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2162772841
Short name T2827
Test name
Test status
Simulation time 171152685 ps
CPU time 0.86 seconds
Started Aug 18 05:37:08 PM PDT 24
Finished Aug 18 05:37:09 PM PDT 24
Peak memory 207492 kb
Host smart-a3be24cb-51f1-4440-8cdd-66fb452913eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21627
72841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2162772841
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2661330892
Short name T2961
Test name
Test status
Simulation time 31669493 ps
CPU time 0.75 seconds
Started Aug 18 05:37:12 PM PDT 24
Finished Aug 18 05:37:12 PM PDT 24
Peak memory 207448 kb
Host smart-44b8d93a-2dd4-44bc-aa2e-55b43a79c258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26613
30892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2661330892
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.125304309
Short name T3218
Test name
Test status
Simulation time 893003747 ps
CPU time 2.27 seconds
Started Aug 18 05:37:19 PM PDT 24
Finished Aug 18 05:37:21 PM PDT 24
Peak memory 207780 kb
Host smart-fd23962c-7581-4b8e-9e47-276cd5444777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12530
4309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.125304309
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_types.4127753535
Short name T481
Test name
Test status
Simulation time 199375367 ps
CPU time 0.95 seconds
Started Aug 18 05:37:17 PM PDT 24
Finished Aug 18 05:37:18 PM PDT 24
Peak memory 207516 kb
Host smart-99d6a452-ceb4-4540-9472-cd9ef1972dad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4127753535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_types.4127753535
Directory /workspace/37.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3877632021
Short name T1987
Test name
Test status
Simulation time 291748094 ps
CPU time 2.49 seconds
Started Aug 18 05:37:29 PM PDT 24
Finished Aug 18 05:37:32 PM PDT 24
Peak memory 207628 kb
Host smart-69d6a5b4-54d1-4332-804e-d0a162b3ba29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38776
32021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3877632021
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2003091159
Short name T1662
Test name
Test status
Simulation time 201993559 ps
CPU time 1.06 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 215816 kb
Host smart-e6327e54-4b95-4de3-87f9-f377bd8ac5a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2003091159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2003091159
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.928232600
Short name T3210
Test name
Test status
Simulation time 165329453 ps
CPU time 0.85 seconds
Started Aug 18 05:37:25 PM PDT 24
Finished Aug 18 05:37:31 PM PDT 24
Peak memory 207448 kb
Host smart-ddf64283-fa29-420c-b465-a8889c0f02da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92823
2600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.928232600
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.221148193
Short name T785
Test name
Test status
Simulation time 169506115 ps
CPU time 0.94 seconds
Started Aug 18 05:37:18 PM PDT 24
Finished Aug 18 05:37:19 PM PDT 24
Peak memory 207500 kb
Host smart-4c95335b-4305-4f85-8c82-e5cdbb09e7b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22114
8193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.221148193
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.4112812544
Short name T3477
Test name
Test status
Simulation time 3162651327 ps
CPU time 90.07 seconds
Started Aug 18 05:37:11 PM PDT 24
Finished Aug 18 05:38:42 PM PDT 24
Peak memory 218376 kb
Host smart-aaa30d5e-d01a-4297-b430-b36a8317efa9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4112812544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.4112812544
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.2763287884
Short name T782
Test name
Test status
Simulation time 10751012890 ps
CPU time 129.87 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:39:19 PM PDT 24
Peak memory 207756 kb
Host smart-8c125fa6-57a3-469d-b99c-d373b33c4779
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2763287884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.2763287884
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3867347691
Short name T2257
Test name
Test status
Simulation time 217004112 ps
CPU time 0.93 seconds
Started Aug 18 05:37:12 PM PDT 24
Finished Aug 18 05:37:13 PM PDT 24
Peak memory 207492 kb
Host smart-d64d2ec4-1ccf-4874-acf9-3a105f030e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38673
47691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3867347691
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.3863391563
Short name T2431
Test name
Test status
Simulation time 26641263921 ps
CPU time 43.73 seconds
Started Aug 18 05:37:09 PM PDT 24
Finished Aug 18 05:37:53 PM PDT 24
Peak memory 207800 kb
Host smart-4eaacf0f-7741-4f92-8d23-58e6f5a5d81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38633
91563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.3863391563
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.886838510
Short name T2518
Test name
Test status
Simulation time 4809288872 ps
CPU time 6.55 seconds
Started Aug 18 05:37:08 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 207780 kb
Host smart-3a9adab7-cbf4-495a-8fa1-fe15e7d83b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88683
8510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.886838510
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3930658234
Short name T2501
Test name
Test status
Simulation time 2099718066 ps
CPU time 59.16 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:38:14 PM PDT 24
Peak memory 217248 kb
Host smart-136cfc99-067e-4dff-bed1-5175423d46bc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3930658234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3930658234
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1820251834
Short name T1976
Test name
Test status
Simulation time 263670602 ps
CPU time 1.02 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 207504 kb
Host smart-616e63ca-9602-4755-b2c1-3b0936a6eb8f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1820251834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1820251834
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2763624466
Short name T1994
Test name
Test status
Simulation time 198817262 ps
CPU time 0.95 seconds
Started Aug 18 05:37:28 PM PDT 24
Finished Aug 18 05:37:30 PM PDT 24
Peak memory 207484 kb
Host smart-9ad38314-d0b4-4b75-aed9-d0163e3e2d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27636
24466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2763624466
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.1273265857
Short name T815
Test name
Test status
Simulation time 2621487093 ps
CPU time 20.13 seconds
Started Aug 18 05:37:33 PM PDT 24
Finished Aug 18 05:37:53 PM PDT 24
Peak memory 215888 kb
Host smart-3c258955-713c-48c4-990c-52c49ecc8a90
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1273265857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.1273265857
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.1959183180
Short name T1271
Test name
Test status
Simulation time 202462420 ps
CPU time 0.92 seconds
Started Aug 18 05:37:26 PM PDT 24
Finished Aug 18 05:37:27 PM PDT 24
Peak memory 207460 kb
Host smart-9941da6d-9f2e-4684-b8ec-b9511c3b8d26
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1959183180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1959183180
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3371877262
Short name T828
Test name
Test status
Simulation time 148441075 ps
CPU time 0.9 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 207504 kb
Host smart-862d3d0c-5397-42db-85dc-573e34cde2a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33718
77262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3371877262
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3519627026
Short name T1989
Test name
Test status
Simulation time 168593971 ps
CPU time 0.95 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 207460 kb
Host smart-c0877052-aa57-4fb9-b1c4-d10d253e9024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35196
27026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3519627026
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.1838147539
Short name T3329
Test name
Test status
Simulation time 199965084 ps
CPU time 0.95 seconds
Started Aug 18 05:37:28 PM PDT 24
Finished Aug 18 05:37:29 PM PDT 24
Peak memory 207396 kb
Host smart-002e2ac5-a1aa-47b7-9fd1-c0966c730235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18381
47539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1838147539
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.653123774
Short name T982
Test name
Test status
Simulation time 183927475 ps
CPU time 0.89 seconds
Started Aug 18 05:37:34 PM PDT 24
Finished Aug 18 05:37:35 PM PDT 24
Peak memory 207364 kb
Host smart-9f152bb8-202e-44cb-b1b4-610b15fab100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65312
3774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.653123774
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.480156944
Short name T1380
Test name
Test status
Simulation time 195473449 ps
CPU time 0.9 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 207572 kb
Host smart-63c18c61-da99-4e97-b42f-870c054aa523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48015
6944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.480156944
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.739183169
Short name T2205
Test name
Test status
Simulation time 152493313 ps
CPU time 0.87 seconds
Started Aug 18 05:37:21 PM PDT 24
Finished Aug 18 05:37:22 PM PDT 24
Peak memory 207484 kb
Host smart-8b9c3c2d-7935-4198-bbc6-180118fc1181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73918
3169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.739183169
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.2041407916
Short name T3560
Test name
Test status
Simulation time 252857220 ps
CPU time 1.04 seconds
Started Aug 18 05:37:38 PM PDT 24
Finished Aug 18 05:37:40 PM PDT 24
Peak memory 207540 kb
Host smart-2681b934-ebb8-4c17-b283-3043f13d4d5f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2041407916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.2041407916
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3611423845
Short name T1409
Test name
Test status
Simulation time 155455402 ps
CPU time 0.82 seconds
Started Aug 18 05:37:22 PM PDT 24
Finished Aug 18 05:37:24 PM PDT 24
Peak memory 207468 kb
Host smart-36051009-94d2-4d1e-a74c-71be36d4c896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36114
23845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3611423845
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2505214430
Short name T28
Test name
Test status
Simulation time 83716377 ps
CPU time 0.77 seconds
Started Aug 18 05:37:32 PM PDT 24
Finished Aug 18 05:37:33 PM PDT 24
Peak memory 207504 kb
Host smart-ae9682a9-3882-4833-8456-99248d4e627c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25052
14430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2505214430
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3396039508
Short name T299
Test name
Test status
Simulation time 16349968760 ps
CPU time 41.93 seconds
Started Aug 18 05:37:11 PM PDT 24
Finished Aug 18 05:37:53 PM PDT 24
Peak memory 215976 kb
Host smart-4aa91d76-651d-4feb-8e56-4d0975ef5c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33960
39508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3396039508
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2333276257
Short name T1242
Test name
Test status
Simulation time 197916588 ps
CPU time 0.89 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:16 PM PDT 24
Peak memory 207568 kb
Host smart-aaaea8f7-2204-4861-8916-b957f9d0e611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23332
76257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2333276257
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1809716416
Short name T655
Test name
Test status
Simulation time 189618458 ps
CPU time 0.92 seconds
Started Aug 18 05:37:34 PM PDT 24
Finished Aug 18 05:37:35 PM PDT 24
Peak memory 207356 kb
Host smart-be8b3fe7-a324-4b63-863a-ad87cc8fe6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18097
16416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1809716416
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.4246868277
Short name T2085
Test name
Test status
Simulation time 195734127 ps
CPU time 0.92 seconds
Started Aug 18 05:37:21 PM PDT 24
Finished Aug 18 05:37:22 PM PDT 24
Peak memory 207492 kb
Host smart-9a0ee10d-f108-4e73-897b-19eaa87f9a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42468
68277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.4246868277
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.1159235486
Short name T3071
Test name
Test status
Simulation time 189210446 ps
CPU time 0.93 seconds
Started Aug 18 05:37:13 PM PDT 24
Finished Aug 18 05:37:14 PM PDT 24
Peak memory 207412 kb
Host smart-a0eacf29-77f6-4f8c-962e-867514c3a659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11592
35486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.1159235486
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3849457372
Short name T1582
Test name
Test status
Simulation time 202989708 ps
CPU time 0.93 seconds
Started Aug 18 05:37:18 PM PDT 24
Finished Aug 18 05:37:19 PM PDT 24
Peak memory 207368 kb
Host smart-211f507e-64cf-490a-b909-8eb135734886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38494
57372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3849457372
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_rx_full.3836252510
Short name T3241
Test name
Test status
Simulation time 319914999 ps
CPU time 1.27 seconds
Started Aug 18 05:37:13 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 207508 kb
Host smart-8512de66-abd3-4b79-aa5a-1300abf76f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38362
52510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_full.3836252510
Directory /workspace/37.usbdev_rx_full/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.1200148095
Short name T1432
Test name
Test status
Simulation time 148636025 ps
CPU time 0.85 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:16 PM PDT 24
Peak memory 207512 kb
Host smart-6e19c700-b449-4ad6-8d35-abdf153aeefd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12001
48095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1200148095
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1328697379
Short name T2041
Test name
Test status
Simulation time 203651382 ps
CPU time 0.9 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 207492 kb
Host smart-3c9607dd-8854-4264-9f23-4843bb2bc175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13286
97379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1328697379
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3576890954
Short name T1121
Test name
Test status
Simulation time 206457673 ps
CPU time 1 seconds
Started Aug 18 05:37:19 PM PDT 24
Finished Aug 18 05:37:20 PM PDT 24
Peak memory 207488 kb
Host smart-4a730281-6f62-4c5f-b642-bb2533e2f601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35768
90954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3576890954
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.1616064958
Short name T1348
Test name
Test status
Simulation time 1656669250 ps
CPU time 16.3 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:30 PM PDT 24
Peak memory 216536 kb
Host smart-9a52455d-420f-4ed9-8927-92c6709eebd5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1616064958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.1616064958
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.282050460
Short name T3251
Test name
Test status
Simulation time 156421103 ps
CPU time 0.82 seconds
Started Aug 18 05:37:18 PM PDT 24
Finished Aug 18 05:37:19 PM PDT 24
Peak memory 207476 kb
Host smart-1375fd45-2e6c-4a0e-9812-4c93966c92fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28205
0460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.282050460
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1193863422
Short name T2676
Test name
Test status
Simulation time 164209518 ps
CPU time 0.9 seconds
Started Aug 18 05:37:19 PM PDT 24
Finished Aug 18 05:37:20 PM PDT 24
Peak memory 207576 kb
Host smart-9730a440-ddec-4a03-a9af-601f07dd367a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11938
63422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1193863422
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.1372689184
Short name T2220
Test name
Test status
Simulation time 490725607 ps
CPU time 1.45 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:16 PM PDT 24
Peak memory 207536 kb
Host smart-47160ce1-5295-4ddf-b608-a6a22dded44c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13726
89184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.1372689184
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.1184524365
Short name T1259
Test name
Test status
Simulation time 2691827468 ps
CPU time 74.85 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:38:29 PM PDT 24
Peak memory 224128 kb
Host smart-c648eb68-c42e-4492-85ff-1b102fb50551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11845
24365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.1184524365
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.3634661864
Short name T2954
Test name
Test status
Simulation time 1312334542 ps
CPU time 30.72 seconds
Started Aug 18 05:37:13 PM PDT 24
Finished Aug 18 05:37:44 PM PDT 24
Peak memory 207660 kb
Host smart-17343918-5e44-4750-b94b-79244dfb2910
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634661864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_hos
t_handshake.3634661864
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_tx_rx_disruption.2402960090
Short name T563
Test name
Test status
Simulation time 517559226 ps
CPU time 1.63 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:16 PM PDT 24
Peak memory 207584 kb
Host smart-c08e695d-e822-47a3-99b8-1959e5af0898
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402960090 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.usbdev_tx_rx_disruption.2402960090
Directory /workspace/37.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/370.usbdev_tx_rx_disruption.3170076787
Short name T1579
Test name
Test status
Simulation time 509171094 ps
CPU time 1.51 seconds
Started Aug 18 05:40:12 PM PDT 24
Finished Aug 18 05:40:14 PM PDT 24
Peak memory 207584 kb
Host smart-9a2a6c92-301b-48d1-8076-5aee11b6357c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170076787 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 370.usbdev_tx_rx_disruption.3170076787
Directory /workspace/370.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/371.usbdev_tx_rx_disruption.1531414972
Short name T3126
Test name
Test status
Simulation time 489603567 ps
CPU time 1.4 seconds
Started Aug 18 05:39:52 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 207532 kb
Host smart-b466b136-07eb-4a7e-9f2d-144bad6b2c7f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531414972 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 371.usbdev_tx_rx_disruption.1531414972
Directory /workspace/371.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/373.usbdev_tx_rx_disruption.347165596
Short name T3223
Test name
Test status
Simulation time 542399804 ps
CPU time 1.54 seconds
Started Aug 18 05:40:32 PM PDT 24
Finished Aug 18 05:40:34 PM PDT 24
Peak memory 207556 kb
Host smart-c385d963-bbae-45e6-a388-85a1811dd90e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347165596 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 373.usbdev_tx_rx_disruption.347165596
Directory /workspace/373.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/374.usbdev_tx_rx_disruption.823778540
Short name T191
Test name
Test status
Simulation time 479065187 ps
CPU time 1.42 seconds
Started Aug 18 05:39:59 PM PDT 24
Finished Aug 18 05:40:01 PM PDT 24
Peak memory 207552 kb
Host smart-f1179903-c975-4a88-8f38-49cde404f708
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823778540 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 374.usbdev_tx_rx_disruption.823778540
Directory /workspace/374.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/375.usbdev_tx_rx_disruption.2281372402
Short name T670
Test name
Test status
Simulation time 459575504 ps
CPU time 1.45 seconds
Started Aug 18 05:40:09 PM PDT 24
Finished Aug 18 05:40:10 PM PDT 24
Peak memory 207544 kb
Host smart-3ca23508-3c01-4407-b9b0-39a45b971aa3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281372402 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 375.usbdev_tx_rx_disruption.2281372402
Directory /workspace/375.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/376.usbdev_tx_rx_disruption.2795376152
Short name T2291
Test name
Test status
Simulation time 565227258 ps
CPU time 1.6 seconds
Started Aug 18 05:40:29 PM PDT 24
Finished Aug 18 05:40:30 PM PDT 24
Peak memory 207556 kb
Host smart-9f0191ea-6714-4a8d-a93d-d1a5c289b085
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795376152 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 376.usbdev_tx_rx_disruption.2795376152
Directory /workspace/376.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/377.usbdev_tx_rx_disruption.3428163268
Short name T2324
Test name
Test status
Simulation time 505424328 ps
CPU time 1.47 seconds
Started Aug 18 05:39:55 PM PDT 24
Finished Aug 18 05:39:56 PM PDT 24
Peak memory 207544 kb
Host smart-572599d1-ac42-4cba-8adf-0c1dd9d9a56f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428163268 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 377.usbdev_tx_rx_disruption.3428163268
Directory /workspace/377.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/378.usbdev_tx_rx_disruption.1006899542
Short name T2212
Test name
Test status
Simulation time 462225647 ps
CPU time 1.43 seconds
Started Aug 18 05:40:15 PM PDT 24
Finished Aug 18 05:40:17 PM PDT 24
Peak memory 207556 kb
Host smart-412d5518-9c9d-409c-909e-0c67dba89e1b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006899542 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 378.usbdev_tx_rx_disruption.1006899542
Directory /workspace/378.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/379.usbdev_tx_rx_disruption.3863370094
Short name T69
Test name
Test status
Simulation time 611939905 ps
CPU time 1.68 seconds
Started Aug 18 05:40:26 PM PDT 24
Finished Aug 18 05:40:28 PM PDT 24
Peak memory 207548 kb
Host smart-fea09c00-15a9-43eb-bed8-58dbca6bc888
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863370094 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 379.usbdev_tx_rx_disruption.3863370094
Directory /workspace/379.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.3894319988
Short name T2113
Test name
Test status
Simulation time 48128155 ps
CPU time 0.69 seconds
Started Aug 18 05:37:18 PM PDT 24
Finished Aug 18 05:37:19 PM PDT 24
Peak memory 207476 kb
Host smart-952eed66-6cc7-479b-9dd1-625a6a6d59cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3894319988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.3894319988
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1979383299
Short name T761
Test name
Test status
Simulation time 8743897425 ps
CPU time 11.38 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:27 PM PDT 24
Peak memory 207812 kb
Host smart-a340e94c-46da-4f57-952d-55f5795dacb5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979383299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_disconnect.1979383299
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.276192053
Short name T1482
Test name
Test status
Simulation time 21061000924 ps
CPU time 24.66 seconds
Started Aug 18 05:37:17 PM PDT 24
Finished Aug 18 05:37:42 PM PDT 24
Peak memory 207784 kb
Host smart-15d41836-8ce1-4bc8-b196-5ca22dc6068f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=276192053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.276192053
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.1204717079
Short name T3074
Test name
Test status
Simulation time 29825920166 ps
CPU time 41.66 seconds
Started Aug 18 05:37:17 PM PDT 24
Finished Aug 18 05:37:59 PM PDT 24
Peak memory 207820 kb
Host smart-a93f703e-17c0-4287-aae8-28443f624808
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204717079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_resume.1204717079
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.4149094830
Short name T1137
Test name
Test status
Simulation time 169886871 ps
CPU time 0.88 seconds
Started Aug 18 05:37:11 PM PDT 24
Finished Aug 18 05:37:12 PM PDT 24
Peak memory 207396 kb
Host smart-e9456818-1aae-4e88-84fe-a94be622ea6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41490
94830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.4149094830
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.534099330
Short name T2051
Test name
Test status
Simulation time 143157770 ps
CPU time 0.84 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 207556 kb
Host smart-084df387-c39f-4f3b-ac72-06d99ef9b4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53409
9330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.534099330
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.593319077
Short name T1636
Test name
Test status
Simulation time 685874898 ps
CPU time 2.25 seconds
Started Aug 18 05:37:23 PM PDT 24
Finished Aug 18 05:37:25 PM PDT 24
Peak memory 207760 kb
Host smart-bbce9e3d-bb81-45ce-8e74-27431fe3413e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59331
9077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.593319077
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.651622570
Short name T2397
Test name
Test status
Simulation time 879964305 ps
CPU time 2.31 seconds
Started Aug 18 05:37:20 PM PDT 24
Finished Aug 18 05:37:22 PM PDT 24
Peak memory 207636 kb
Host smart-c1428f3f-1e64-47cc-af35-a6070b98a84a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=651622570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.651622570
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.1808123205
Short name T1427
Test name
Test status
Simulation time 50401722357 ps
CPU time 77.24 seconds
Started Aug 18 05:37:30 PM PDT 24
Finished Aug 18 05:38:48 PM PDT 24
Peak memory 207744 kb
Host smart-094abcb5-32bd-4d3c-b6d1-31cbf72fdcea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18081
23205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1808123205
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.3378158260
Short name T2658
Test name
Test status
Simulation time 4357645595 ps
CPU time 28.49 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:43 PM PDT 24
Peak memory 207552 kb
Host smart-22543f58-5b43-4c55-83ca-cf940edd68c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378158260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.3378158260
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2527656731
Short name T771
Test name
Test status
Simulation time 796405039 ps
CPU time 1.8 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 207532 kb
Host smart-14a365d5-c4cb-4b4f-b2e9-2f6d53b76d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25276
56731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2527656731
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.555683250
Short name T3117
Test name
Test status
Simulation time 163986515 ps
CPU time 0.88 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 207512 kb
Host smart-11f249fe-768b-4f3f-841a-adb8d15fc085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55568
3250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.555683250
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.1133476939
Short name T627
Test name
Test status
Simulation time 36159826 ps
CPU time 0.71 seconds
Started Aug 18 05:37:17 PM PDT 24
Finished Aug 18 05:37:18 PM PDT 24
Peak memory 207444 kb
Host smart-c088002f-e084-47aa-9468-e16221279164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11334
76939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1133476939
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3929398753
Short name T2598
Test name
Test status
Simulation time 913639500 ps
CPU time 2.37 seconds
Started Aug 18 05:37:22 PM PDT 24
Finished Aug 18 05:37:24 PM PDT 24
Peak memory 207764 kb
Host smart-e6dde649-11a7-4ac2-ae2b-7d2032cd862e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39293
98753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3929398753
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_types.4174743836
Short name T398
Test name
Test status
Simulation time 351735697 ps
CPU time 1.29 seconds
Started Aug 18 05:37:37 PM PDT 24
Finished Aug 18 05:37:39 PM PDT 24
Peak memory 207672 kb
Host smart-97eee9fa-a06a-4f7b-87c5-19efc7596862
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4174743836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_types.4174743836
Directory /workspace/38.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2890668528
Short name T2803
Test name
Test status
Simulation time 231024267 ps
CPU time 1.68 seconds
Started Aug 18 05:37:18 PM PDT 24
Finished Aug 18 05:37:20 PM PDT 24
Peak memory 207688 kb
Host smart-0912e9ce-abf0-47e0-a068-403d46488ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28906
68528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2890668528
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.311940155
Short name T1813
Test name
Test status
Simulation time 201759737 ps
CPU time 1.11 seconds
Started Aug 18 05:37:20 PM PDT 24
Finished Aug 18 05:37:22 PM PDT 24
Peak memory 215916 kb
Host smart-13a16d66-5832-45a5-887e-e5886933c6f1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=311940155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.311940155
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2379046051
Short name T743
Test name
Test status
Simulation time 146404234 ps
CPU time 0.83 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 207448 kb
Host smart-3e2c80a8-5cf8-4e6a-b014-7570ded237b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790
46051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2379046051
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3870195371
Short name T1241
Test name
Test status
Simulation time 222551455 ps
CPU time 1.05 seconds
Started Aug 18 05:37:32 PM PDT 24
Finished Aug 18 05:37:33 PM PDT 24
Peak memory 207504 kb
Host smart-f8e87f34-0836-44aa-baff-a29223c8189d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38701
95371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3870195371
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.633900914
Short name T2315
Test name
Test status
Simulation time 5003143944 ps
CPU time 49.55 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:38:04 PM PDT 24
Peak memory 217208 kb
Host smart-73800e2a-6c5a-4cd5-bd76-be15fb91a86d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=633900914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.633900914
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.3902634786
Short name T829
Test name
Test status
Simulation time 10661601921 ps
CPU time 73.15 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:38:29 PM PDT 24
Peak memory 207756 kb
Host smart-cd3d0462-bf32-4250-ba07-76698c47484e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3902634786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.3902634786
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.583757699
Short name T1475
Test name
Test status
Simulation time 242163637 ps
CPU time 0.99 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 207408 kb
Host smart-bdc4005b-2a5b-4129-8beb-c9b320fc4417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58375
7699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.583757699
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.2331392422
Short name T2802
Test name
Test status
Simulation time 27975267154 ps
CPU time 32.56 seconds
Started Aug 18 05:37:30 PM PDT 24
Finished Aug 18 05:38:03 PM PDT 24
Peak memory 215912 kb
Host smart-e4853890-f17c-480d-a445-891af7901bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23313
92422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.2331392422
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3830001709
Short name T910
Test name
Test status
Simulation time 4618168278 ps
CPU time 7.31 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:23 PM PDT 24
Peak memory 215956 kb
Host smart-7ed7a8fb-5f4f-4a40-95bc-270c196d8c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38300
01709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3830001709
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.98346248
Short name T720
Test name
Test status
Simulation time 3042102464 ps
CPU time 29.32 seconds
Started Aug 18 05:37:43 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 218540 kb
Host smart-69a8762f-38f5-4b75-99a6-8d6383882809
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=98346248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.98346248
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3175868175
Short name T2204
Test name
Test status
Simulation time 2870123948 ps
CPU time 82.22 seconds
Started Aug 18 05:37:12 PM PDT 24
Finished Aug 18 05:38:35 PM PDT 24
Peak memory 215912 kb
Host smart-831b1599-2a38-405e-819b-766492f6fb98
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3175868175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3175868175
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.652670833
Short name T3110
Test name
Test status
Simulation time 248856292 ps
CPU time 1.01 seconds
Started Aug 18 05:37:27 PM PDT 24
Finished Aug 18 05:37:28 PM PDT 24
Peak memory 207460 kb
Host smart-cf656fec-20c0-4af4-a54a-2a6ac8386daa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=652670833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.652670833
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1786365644
Short name T546
Test name
Test status
Simulation time 193720518 ps
CPU time 0.95 seconds
Started Aug 18 05:37:26 PM PDT 24
Finished Aug 18 05:37:28 PM PDT 24
Peak memory 207436 kb
Host smart-f3a0b13f-36b8-424c-90c1-0f7b63f8e32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17863
65644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1786365644
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1483418441
Short name T1756
Test name
Test status
Simulation time 2278816292 ps
CPU time 17.73 seconds
Started Aug 18 05:37:33 PM PDT 24
Finished Aug 18 05:37:51 PM PDT 24
Peak memory 215896 kb
Host smart-bc9d7052-b04b-4afc-aab4-a6d8316bc3a4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1483418441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1483418441
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.3678739736
Short name T1395
Test name
Test status
Simulation time 178114338 ps
CPU time 0.88 seconds
Started Aug 18 05:37:29 PM PDT 24
Finished Aug 18 05:37:30 PM PDT 24
Peak memory 207496 kb
Host smart-4e51f54f-be9c-472c-a086-57167713d96d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3678739736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.3678739736
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.4173066628
Short name T3296
Test name
Test status
Simulation time 154906237 ps
CPU time 0.85 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:16 PM PDT 24
Peak memory 207456 kb
Host smart-03973616-1811-4e64-be35-7e92d1852ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41730
66628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.4173066628
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.769716301
Short name T167
Test name
Test status
Simulation time 215989487 ps
CPU time 0.97 seconds
Started Aug 18 05:37:18 PM PDT 24
Finished Aug 18 05:37:20 PM PDT 24
Peak memory 207472 kb
Host smart-14d7251e-79c6-4b8a-b576-2a85590007b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76971
6301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.769716301
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.4270434376
Short name T1597
Test name
Test status
Simulation time 202106511 ps
CPU time 0.96 seconds
Started Aug 18 05:37:29 PM PDT 24
Finished Aug 18 05:37:30 PM PDT 24
Peak memory 207432 kb
Host smart-df69d910-b4ec-44fa-821a-b3cf2bacf9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42704
34376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.4270434376
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2510795635
Short name T1196
Test name
Test status
Simulation time 163529347 ps
CPU time 0.84 seconds
Started Aug 18 05:37:36 PM PDT 24
Finished Aug 18 05:37:37 PM PDT 24
Peak memory 207456 kb
Host smart-7ad289cc-568b-47a8-9b76-ca2abdd6f4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25107
95635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2510795635
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1095010446
Short name T817
Test name
Test status
Simulation time 164222661 ps
CPU time 0.85 seconds
Started Aug 18 05:37:15 PM PDT 24
Finished Aug 18 05:37:16 PM PDT 24
Peak memory 207540 kb
Host smart-6421ae63-37f9-442e-af0f-c32c4e9e9876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10950
10446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1095010446
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.233484554
Short name T3563
Test name
Test status
Simulation time 196956054 ps
CPU time 0.86 seconds
Started Aug 18 05:37:21 PM PDT 24
Finished Aug 18 05:37:22 PM PDT 24
Peak memory 207548 kb
Host smart-08f2d0d9-ab38-4bf7-8a65-d096056854ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23348
4554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.233484554
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.366902080
Short name T2048
Test name
Test status
Simulation time 230834328 ps
CPU time 1 seconds
Started Aug 18 05:37:24 PM PDT 24
Finished Aug 18 05:37:25 PM PDT 24
Peak memory 207584 kb
Host smart-2fccc3d0-6dcc-458b-85fd-2dee09c2d137
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=366902080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.366902080
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1199020954
Short name T2695
Test name
Test status
Simulation time 167457024 ps
CPU time 0.85 seconds
Started Aug 18 05:37:20 PM PDT 24
Finished Aug 18 05:37:21 PM PDT 24
Peak memory 207380 kb
Host smart-d65bccdf-9637-4d74-83a6-7a2d90e4cb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11990
20954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1199020954
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.4076794398
Short name T2435
Test name
Test status
Simulation time 41803100 ps
CPU time 0.68 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 207488 kb
Host smart-30209950-7cdc-41f1-a94d-ba0bb491604e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40767
94398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.4076794398
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.619121559
Short name T87
Test name
Test status
Simulation time 12757561270 ps
CPU time 33.05 seconds
Started Aug 18 05:37:54 PM PDT 24
Finished Aug 18 05:38:27 PM PDT 24
Peak memory 215928 kb
Host smart-47cbc97d-e349-4534-8ce4-836961ad794e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61912
1559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.619121559
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1771586724
Short name T2543
Test name
Test status
Simulation time 155615824 ps
CPU time 0.89 seconds
Started Aug 18 05:37:44 PM PDT 24
Finished Aug 18 05:37:45 PM PDT 24
Peak memory 207540 kb
Host smart-a09066a3-04b9-4f73-8431-a581ff226087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17715
86724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1771586724
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.999452392
Short name T1457
Test name
Test status
Simulation time 224299410 ps
CPU time 0.99 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:16 PM PDT 24
Peak memory 207444 kb
Host smart-005be6ee-dba9-4d4b-9646-4837891e32a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99945
2392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.999452392
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.706623273
Short name T2845
Test name
Test status
Simulation time 244545138 ps
CPU time 1.1 seconds
Started Aug 18 05:37:25 PM PDT 24
Finished Aug 18 05:37:27 PM PDT 24
Peak memory 207532 kb
Host smart-9b593dd4-7ebf-4367-9b95-965c5605ea25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70662
3273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.706623273
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.2656636061
Short name T3158
Test name
Test status
Simulation time 187117864 ps
CPU time 0.96 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 207448 kb
Host smart-14e55c5c-0ca2-4d4d-a019-8ccc26055592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26566
36061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.2656636061
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3405776627
Short name T3410
Test name
Test status
Simulation time 153834691 ps
CPU time 0.87 seconds
Started Aug 18 05:37:44 PM PDT 24
Finished Aug 18 05:37:45 PM PDT 24
Peak memory 207408 kb
Host smart-ba8e4073-ee86-43fa-a2e3-09a3cc4748d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34057
76627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3405776627
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_rx_full.3323060188
Short name T2058
Test name
Test status
Simulation time 252799866 ps
CPU time 1.12 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:17 PM PDT 24
Peak memory 207508 kb
Host smart-e3b3fd69-e1cd-4848-9f32-ef560731d29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33230
60188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_full.3323060188
Directory /workspace/38.usbdev_rx_full/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3806923542
Short name T3351
Test name
Test status
Simulation time 151332255 ps
CPU time 0.81 seconds
Started Aug 18 05:37:30 PM PDT 24
Finished Aug 18 05:37:31 PM PDT 24
Peak memory 207524 kb
Host smart-b7900411-bd3a-4c1b-84ca-e0816bdff184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38069
23542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3806923542
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.4239325857
Short name T2797
Test name
Test status
Simulation time 188329269 ps
CPU time 0.94 seconds
Started Aug 18 05:37:26 PM PDT 24
Finished Aug 18 05:37:27 PM PDT 24
Peak memory 207500 kb
Host smart-93426aad-4973-4fee-93cc-222f9784ffc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42393
25857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.4239325857
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2849798193
Short name T2888
Test name
Test status
Simulation time 224813361 ps
CPU time 1.04 seconds
Started Aug 18 05:37:20 PM PDT 24
Finished Aug 18 05:37:21 PM PDT 24
Peak memory 207524 kb
Host smart-e7ae9127-b1fd-4c1e-86a2-41d746325ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28497
98193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2849798193
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.164647701
Short name T2830
Test name
Test status
Simulation time 1580002842 ps
CPU time 43.31 seconds
Started Aug 18 05:37:32 PM PDT 24
Finished Aug 18 05:38:15 PM PDT 24
Peak memory 217476 kb
Host smart-c02223aa-a628-41dc-ac93-a686df64f79a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=164647701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.164647701
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3827976855
Short name T1831
Test name
Test status
Simulation time 190001389 ps
CPU time 0.98 seconds
Started Aug 18 05:37:27 PM PDT 24
Finished Aug 18 05:37:29 PM PDT 24
Peak memory 207420 kb
Host smart-e5dc5a9b-6020-4522-b5e1-8fee82c798f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38279
76855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3827976855
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1430871174
Short name T1150
Test name
Test status
Simulation time 174656055 ps
CPU time 0.86 seconds
Started Aug 18 05:37:25 PM PDT 24
Finished Aug 18 05:37:26 PM PDT 24
Peak memory 207548 kb
Host smart-dfe56477-2261-4169-98ec-28f0135f68bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14308
71174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1430871174
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.186066649
Short name T3308
Test name
Test status
Simulation time 1069855452 ps
CPU time 2.55 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:18 PM PDT 24
Peak memory 207748 kb
Host smart-a8fc8ef3-e743-4abb-8eee-dc94556bc531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18606
6649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.186066649
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.838228210
Short name T3424
Test name
Test status
Simulation time 2046896794 ps
CPU time 56.03 seconds
Started Aug 18 05:37:19 PM PDT 24
Finished Aug 18 05:38:15 PM PDT 24
Peak memory 217272 kb
Host smart-768fdb33-a594-40a2-9b28-02b1d1ecaca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83822
8210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.838228210
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.1293904071
Short name T750
Test name
Test status
Simulation time 3446690959 ps
CPU time 29.02 seconds
Started Aug 18 05:37:14 PM PDT 24
Finished Aug 18 05:37:44 PM PDT 24
Peak memory 207628 kb
Host smart-47ecceaa-09e2-499b-9583-060861b75301
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293904071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.1293904071
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_tx_rx_disruption.1181225267
Short name T2648
Test name
Test status
Simulation time 478623179 ps
CPU time 1.6 seconds
Started Aug 18 05:37:13 PM PDT 24
Finished Aug 18 05:37:15 PM PDT 24
Peak memory 207500 kb
Host smart-984ce404-572e-41b4-90ca-4cf5b23d80ed
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181225267 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.usbdev_tx_rx_disruption.1181225267
Directory /workspace/38.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/380.usbdev_tx_rx_disruption.1619620150
Short name T206
Test name
Test status
Simulation time 572334849 ps
CPU time 1.7 seconds
Started Aug 18 05:40:22 PM PDT 24
Finished Aug 18 05:40:23 PM PDT 24
Peak memory 207500 kb
Host smart-a4b1f90c-b63b-4101-9b58-cf371c522a0e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619620150 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 380.usbdev_tx_rx_disruption.1619620150
Directory /workspace/380.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/381.usbdev_tx_rx_disruption.190429269
Short name T1673
Test name
Test status
Simulation time 709133080 ps
CPU time 1.8 seconds
Started Aug 18 05:40:33 PM PDT 24
Finished Aug 18 05:40:35 PM PDT 24
Peak memory 207588 kb
Host smart-1dacafef-86e8-4f5c-a167-ac19f9372c56
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190429269 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 381.usbdev_tx_rx_disruption.190429269
Directory /workspace/381.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/382.usbdev_tx_rx_disruption.2821195187
Short name T3502
Test name
Test status
Simulation time 584373579 ps
CPU time 1.65 seconds
Started Aug 18 05:39:54 PM PDT 24
Finished Aug 18 05:39:56 PM PDT 24
Peak memory 207524 kb
Host smart-b6de4753-9dee-4478-abfa-2fac62eee8ad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821195187 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 382.usbdev_tx_rx_disruption.2821195187
Directory /workspace/382.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/384.usbdev_tx_rx_disruption.1192364975
Short name T1335
Test name
Test status
Simulation time 487638711 ps
CPU time 1.55 seconds
Started Aug 18 05:40:15 PM PDT 24
Finished Aug 18 05:40:17 PM PDT 24
Peak memory 207560 kb
Host smart-2208c12f-3ee7-4256-94c4-dccd32ec3c8a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192364975 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 384.usbdev_tx_rx_disruption.1192364975
Directory /workspace/384.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/385.usbdev_tx_rx_disruption.1094341086
Short name T1187
Test name
Test status
Simulation time 608942884 ps
CPU time 1.7 seconds
Started Aug 18 05:40:02 PM PDT 24
Finished Aug 18 05:40:04 PM PDT 24
Peak memory 207476 kb
Host smart-4d5a7934-7607-489e-afdf-4d1e6581969d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094341086 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 385.usbdev_tx_rx_disruption.1094341086
Directory /workspace/385.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/386.usbdev_tx_rx_disruption.2795481912
Short name T907
Test name
Test status
Simulation time 544614830 ps
CPU time 1.55 seconds
Started Aug 18 05:40:10 PM PDT 24
Finished Aug 18 05:40:12 PM PDT 24
Peak memory 207556 kb
Host smart-d2623263-785c-4bdf-93b3-0adf833a5fa6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795481912 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 386.usbdev_tx_rx_disruption.2795481912
Directory /workspace/386.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/387.usbdev_tx_rx_disruption.3442339157
Short name T3622
Test name
Test status
Simulation time 469392906 ps
CPU time 1.54 seconds
Started Aug 18 05:40:11 PM PDT 24
Finished Aug 18 05:40:12 PM PDT 24
Peak memory 206560 kb
Host smart-71b14011-4f51-4981-a908-3d18deb51995
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442339157 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 387.usbdev_tx_rx_disruption.3442339157
Directory /workspace/387.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/388.usbdev_tx_rx_disruption.3561621873
Short name T1389
Test name
Test status
Simulation time 417184727 ps
CPU time 1.31 seconds
Started Aug 18 05:40:11 PM PDT 24
Finished Aug 18 05:40:12 PM PDT 24
Peak memory 207552 kb
Host smart-ade53012-618c-4a2c-820b-2e3be7f86934
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561621873 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 388.usbdev_tx_rx_disruption.3561621873
Directory /workspace/388.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/389.usbdev_tx_rx_disruption.341968323
Short name T2361
Test name
Test status
Simulation time 513056852 ps
CPU time 1.44 seconds
Started Aug 18 05:40:16 PM PDT 24
Finished Aug 18 05:40:18 PM PDT 24
Peak memory 207548 kb
Host smart-0b8f6012-79f6-4443-a78d-3fd2033af082
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341968323 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 389.usbdev_tx_rx_disruption.341968323
Directory /workspace/389.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.434474641
Short name T1609
Test name
Test status
Simulation time 39065066 ps
CPU time 0.63 seconds
Started Aug 18 05:37:37 PM PDT 24
Finished Aug 18 05:37:43 PM PDT 24
Peak memory 207452 kb
Host smart-022cd880-2f17-44b7-b19f-5e33f3093350
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=434474641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.434474641
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1306398949
Short name T1517
Test name
Test status
Simulation time 5386940796 ps
CPU time 7.64 seconds
Started Aug 18 05:37:25 PM PDT 24
Finished Aug 18 05:37:32 PM PDT 24
Peak memory 216012 kb
Host smart-39d9479e-ade7-4a96-91b9-0561006c6860
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306398949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_disconnect.1306398949
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.2092062055
Short name T3458
Test name
Test status
Simulation time 20990439213 ps
CPU time 26.3 seconds
Started Aug 18 05:37:31 PM PDT 24
Finished Aug 18 05:37:58 PM PDT 24
Peak memory 207764 kb
Host smart-2d07abdf-c47a-4152-9cf5-85080fb1a063
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092062055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.2092062055
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.3874235551
Short name T2539
Test name
Test status
Simulation time 25901025845 ps
CPU time 32.21 seconds
Started Aug 18 05:37:31 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 216016 kb
Host smart-ab9a8b18-9db0-475b-aee0-3c59d9ec6acd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874235551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.3874235551
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.4223744788
Short name T2446
Test name
Test status
Simulation time 172433953 ps
CPU time 0.86 seconds
Started Aug 18 05:37:26 PM PDT 24
Finished Aug 18 05:37:27 PM PDT 24
Peak memory 207484 kb
Host smart-544fdb57-427c-4fdd-8442-02bf3f44c9fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42237
44788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.4223744788
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.2696240381
Short name T1211
Test name
Test status
Simulation time 162683538 ps
CPU time 0.83 seconds
Started Aug 18 05:37:29 PM PDT 24
Finished Aug 18 05:37:30 PM PDT 24
Peak memory 207564 kb
Host smart-4a49da0a-cce2-49c8-a2d2-73d14b4e3f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26962
40381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.2696240381
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.2774115663
Short name T1297
Test name
Test status
Simulation time 330773554 ps
CPU time 1.28 seconds
Started Aug 18 05:37:20 PM PDT 24
Finished Aug 18 05:37:21 PM PDT 24
Peak memory 207564 kb
Host smart-327da98b-30a2-4170-9e2a-3517d337cf45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27741
15663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.2774115663
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.3853024709
Short name T353
Test name
Test status
Simulation time 441708661 ps
CPU time 1.3 seconds
Started Aug 18 05:37:16 PM PDT 24
Finished Aug 18 05:37:18 PM PDT 24
Peak memory 207480 kb
Host smart-4cc4cc53-e1c2-4823-ae70-1f0767c563b6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3853024709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.3853024709
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.4154862171
Short name T1028
Test name
Test status
Simulation time 23549770124 ps
CPU time 42.96 seconds
Started Aug 18 05:37:13 PM PDT 24
Finished Aug 18 05:37:56 PM PDT 24
Peak memory 207812 kb
Host smart-aec00663-638b-4b25-a694-5f904280f24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41548
62171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.4154862171
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.1721101988
Short name T2896
Test name
Test status
Simulation time 1571164221 ps
CPU time 13.18 seconds
Started Aug 18 05:37:21 PM PDT 24
Finished Aug 18 05:37:34 PM PDT 24
Peak memory 207736 kb
Host smart-c69a15cb-ecb2-4774-86a5-f64129294fa9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721101988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.1721101988
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1151919576
Short name T2611
Test name
Test status
Simulation time 774574734 ps
CPU time 1.81 seconds
Started Aug 18 05:37:28 PM PDT 24
Finished Aug 18 05:37:30 PM PDT 24
Peak memory 207508 kb
Host smart-f1b9b99e-814a-4c91-9cdc-14fbc4d91b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11519
19576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1151919576
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.4034331758
Short name T1640
Test name
Test status
Simulation time 141543577 ps
CPU time 0.87 seconds
Started Aug 18 05:37:33 PM PDT 24
Finished Aug 18 05:37:34 PM PDT 24
Peak memory 207500 kb
Host smart-9423e859-6c75-4d65-a574-58f37a85f153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40343
31758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.4034331758
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.824122495
Short name T3286
Test name
Test status
Simulation time 54611485 ps
CPU time 0.71 seconds
Started Aug 18 05:37:19 PM PDT 24
Finished Aug 18 05:37:20 PM PDT 24
Peak memory 207484 kb
Host smart-e64b0827-828f-4605-aa6c-53d0e1f0ecdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82412
2495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.824122495
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.518997849
Short name T1675
Test name
Test status
Simulation time 769964455 ps
CPU time 2.2 seconds
Started Aug 18 05:37:24 PM PDT 24
Finished Aug 18 05:37:27 PM PDT 24
Peak memory 207748 kb
Host smart-203d97ec-0196-4a8d-a979-6bca7e40020f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51899
7849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.518997849
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_types.2390885314
Short name T421
Test name
Test status
Simulation time 676581978 ps
CPU time 1.53 seconds
Started Aug 18 05:37:39 PM PDT 24
Finished Aug 18 05:37:41 PM PDT 24
Peak memory 207516 kb
Host smart-0b19f58a-fea5-4e3e-b4c4-45c4d04335aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2390885314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_types.2390885314
Directory /workspace/39.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.7189050
Short name T2350
Test name
Test status
Simulation time 236568659 ps
CPU time 2.11 seconds
Started Aug 18 05:37:42 PM PDT 24
Finished Aug 18 05:37:44 PM PDT 24
Peak memory 207688 kb
Host smart-08d8122d-4739-43ab-86ea-5c2ef9460d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71890
50 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.7189050
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.670516540
Short name T2958
Test name
Test status
Simulation time 173308165 ps
CPU time 0.99 seconds
Started Aug 18 05:37:17 PM PDT 24
Finished Aug 18 05:37:18 PM PDT 24
Peak memory 215900 kb
Host smart-91b2090e-78a3-4716-ac74-bc81c1e9142b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=670516540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.670516540
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3606098928
Short name T125
Test name
Test status
Simulation time 140468574 ps
CPU time 0.85 seconds
Started Aug 18 05:37:18 PM PDT 24
Finished Aug 18 05:37:19 PM PDT 24
Peak memory 207472 kb
Host smart-6b0209a6-441a-4d43-a369-4446b98ca08c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36060
98928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3606098928
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3717821945
Short name T2728
Test name
Test status
Simulation time 240904587 ps
CPU time 1.03 seconds
Started Aug 18 05:37:24 PM PDT 24
Finished Aug 18 05:37:25 PM PDT 24
Peak memory 207504 kb
Host smart-3cf88824-555b-4484-9c22-24743878a5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37178
21945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3717821945
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.120719401
Short name T3625
Test name
Test status
Simulation time 2753137437 ps
CPU time 73.1 seconds
Started Aug 18 05:37:23 PM PDT 24
Finished Aug 18 05:38:36 PM PDT 24
Peak memory 224108 kb
Host smart-0f033414-cbc8-4278-9239-9a62e19fc73f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=120719401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.120719401
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.954054599
Short name T908
Test name
Test status
Simulation time 6983263453 ps
CPU time 47.15 seconds
Started Aug 18 05:37:23 PM PDT 24
Finished Aug 18 05:38:10 PM PDT 24
Peak memory 207828 kb
Host smart-b35ee04f-166c-47aa-8e71-84a3b47480dd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=954054599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.954054599
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.945213195
Short name T1968
Test name
Test status
Simulation time 174774158 ps
CPU time 0.95 seconds
Started Aug 18 05:37:50 PM PDT 24
Finished Aug 18 05:37:52 PM PDT 24
Peak memory 207480 kb
Host smart-3f5b54dd-b0ab-4458-acea-a15818bb0ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94521
3195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.945213195
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.225382010
Short name T2428
Test name
Test status
Simulation time 29387149748 ps
CPU time 42.91 seconds
Started Aug 18 05:37:49 PM PDT 24
Finished Aug 18 05:38:33 PM PDT 24
Peak memory 207744 kb
Host smart-5fe23194-0e97-4ae3-88d4-6cc3994b650e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22538
2010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.225382010
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.2612039998
Short name T2340
Test name
Test status
Simulation time 9497576111 ps
CPU time 12.42 seconds
Started Aug 18 05:37:34 PM PDT 24
Finished Aug 18 05:37:46 PM PDT 24
Peak memory 207808 kb
Host smart-20a491c9-059c-49aa-8a68-0f0a35aca024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26120
39998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.2612039998
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2538866504
Short name T1848
Test name
Test status
Simulation time 4288815446 ps
CPU time 121.77 seconds
Started Aug 18 05:37:34 PM PDT 24
Finished Aug 18 05:39:36 PM PDT 24
Peak memory 218456 kb
Host smart-d66d30a2-0461-40e7-9a79-000df8967087
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2538866504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2538866504
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.1708277217
Short name T970
Test name
Test status
Simulation time 1833483600 ps
CPU time 50.86 seconds
Started Aug 18 05:37:42 PM PDT 24
Finished Aug 18 05:38:33 PM PDT 24
Peak memory 223984 kb
Host smart-7ccb51bd-37bd-4281-a70f-c1562a98261c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1708277217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.1708277217
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.1791420136
Short name T3327
Test name
Test status
Simulation time 245593883 ps
CPU time 1.07 seconds
Started Aug 18 05:37:33 PM PDT 24
Finished Aug 18 05:37:34 PM PDT 24
Peak memory 207480 kb
Host smart-af4a9344-1a83-402e-8cfd-fe2889aec1ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1791420136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.1791420136
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1008549586
Short name T3253
Test name
Test status
Simulation time 190698422 ps
CPU time 0.92 seconds
Started Aug 18 05:37:43 PM PDT 24
Finished Aug 18 05:37:44 PM PDT 24
Peak memory 207460 kb
Host smart-4f7ddc5a-c5a4-4a76-88d0-02ce389c86ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10085
49586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1008549586
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.1253335202
Short name T1614
Test name
Test status
Simulation time 1921805248 ps
CPU time 55.12 seconds
Started Aug 18 05:37:44 PM PDT 24
Finished Aug 18 05:38:44 PM PDT 24
Peak memory 215816 kb
Host smart-fc2b447f-69e1-4b3c-a893-703232aabb6f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1253335202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1253335202
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.3653134337
Short name T2195
Test name
Test status
Simulation time 157823692 ps
CPU time 0.87 seconds
Started Aug 18 05:37:45 PM PDT 24
Finished Aug 18 05:37:46 PM PDT 24
Peak memory 207508 kb
Host smart-8bb5976b-47d4-4402-8aee-d25771b3b94a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3653134337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3653134337
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2097115594
Short name T1916
Test name
Test status
Simulation time 157849292 ps
CPU time 0.86 seconds
Started Aug 18 05:37:44 PM PDT 24
Finished Aug 18 05:37:45 PM PDT 24
Peak memory 207444 kb
Host smart-76a50dcc-8aac-40fd-b80d-9b2ab1e46fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20971
15594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2097115594
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1152060950
Short name T152
Test name
Test status
Simulation time 204476017 ps
CPU time 0.96 seconds
Started Aug 18 05:37:41 PM PDT 24
Finished Aug 18 05:37:42 PM PDT 24
Peak memory 207504 kb
Host smart-a280c39f-7fcd-4b4e-a7a6-c9cd2725211d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11520
60950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1152060950
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.4102588075
Short name T1996
Test name
Test status
Simulation time 207551345 ps
CPU time 0.97 seconds
Started Aug 18 05:37:36 PM PDT 24
Finished Aug 18 05:37:37 PM PDT 24
Peak memory 207520 kb
Host smart-e7159681-5f96-4915-824c-fc75e6a2cf47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41025
88075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.4102588075
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.801148109
Short name T898
Test name
Test status
Simulation time 160084347 ps
CPU time 0.87 seconds
Started Aug 18 05:37:36 PM PDT 24
Finished Aug 18 05:37:37 PM PDT 24
Peak memory 207504 kb
Host smart-0a779f15-ab36-4aab-b242-e1476b846dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80114
8109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.801148109
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2608727260
Short name T2688
Test name
Test status
Simulation time 160415995 ps
CPU time 0.83 seconds
Started Aug 18 05:37:29 PM PDT 24
Finished Aug 18 05:37:30 PM PDT 24
Peak memory 207524 kb
Host smart-4c7d51d7-4139-4454-ad69-0e570ee2a345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26087
27260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2608727260
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1952063662
Short name T2735
Test name
Test status
Simulation time 150073367 ps
CPU time 0.83 seconds
Started Aug 18 05:37:28 PM PDT 24
Finished Aug 18 05:37:29 PM PDT 24
Peak memory 207564 kb
Host smart-23086e93-e863-4011-be31-b556eb81b741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19520
63662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1952063662
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.559200255
Short name T2537
Test name
Test status
Simulation time 246273194 ps
CPU time 1.02 seconds
Started Aug 18 05:37:27 PM PDT 24
Finished Aug 18 05:37:28 PM PDT 24
Peak memory 207548 kb
Host smart-a815f7e7-212f-473e-ab27-60e292a3eaf1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=559200255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.559200255
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2194510474
Short name T3157
Test name
Test status
Simulation time 135239130 ps
CPU time 0.81 seconds
Started Aug 18 05:37:28 PM PDT 24
Finished Aug 18 05:37:29 PM PDT 24
Peak memory 207416 kb
Host smart-fc87ea21-839b-401e-a63f-919047b8da97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21945
10474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2194510474
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3829976647
Short name T1991
Test name
Test status
Simulation time 63662938 ps
CPU time 0.72 seconds
Started Aug 18 05:37:47 PM PDT 24
Finished Aug 18 05:37:48 PM PDT 24
Peak memory 207536 kb
Host smart-602f071c-b83b-4e2b-89ef-b23567b7fa4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38299
76647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3829976647
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.826681719
Short name T1149
Test name
Test status
Simulation time 19058413426 ps
CPU time 47.1 seconds
Started Aug 18 05:37:45 PM PDT 24
Finished Aug 18 05:38:37 PM PDT 24
Peak memory 215924 kb
Host smart-1ff2d000-7e19-4dec-afc5-e81275ea8b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82668
1719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.826681719
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1329106869
Short name T1823
Test name
Test status
Simulation time 153236787 ps
CPU time 0.9 seconds
Started Aug 18 05:37:23 PM PDT 24
Finished Aug 18 05:37:24 PM PDT 24
Peak memory 207512 kb
Host smart-cb16b62f-660b-47f6-ab30-b075f0857509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13291
06869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1329106869
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.4061027979
Short name T2614
Test name
Test status
Simulation time 189034625 ps
CPU time 0.93 seconds
Started Aug 18 05:37:25 PM PDT 24
Finished Aug 18 05:37:26 PM PDT 24
Peak memory 207448 kb
Host smart-b19f44fb-f553-4e9e-a8b3-3c68f352688c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40610
27979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.4061027979
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.1431743542
Short name T1616
Test name
Test status
Simulation time 232701102 ps
CPU time 0.96 seconds
Started Aug 18 05:37:38 PM PDT 24
Finished Aug 18 05:37:39 PM PDT 24
Peak memory 207488 kb
Host smart-9c4a5762-c59c-40ad-ab29-cd887d00cf8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14317
43542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.1431743542
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2405983563
Short name T714
Test name
Test status
Simulation time 185721907 ps
CPU time 0.9 seconds
Started Aug 18 05:37:30 PM PDT 24
Finished Aug 18 05:37:31 PM PDT 24
Peak memory 207504 kb
Host smart-469db39f-ec01-4e65-8354-2650c417fcbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24059
83563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2405983563
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.1080733670
Short name T66
Test name
Test status
Simulation time 159831344 ps
CPU time 0.84 seconds
Started Aug 18 05:37:53 PM PDT 24
Finished Aug 18 05:37:54 PM PDT 24
Peak memory 207464 kb
Host smart-a48d26c9-2fbc-4486-b3c1-f31e21b33b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10807
33670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.1080733670
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_rx_full.1930851474
Short name T1081
Test name
Test status
Simulation time 380950943 ps
CPU time 1.29 seconds
Started Aug 18 05:37:42 PM PDT 24
Finished Aug 18 05:37:43 PM PDT 24
Peak memory 207508 kb
Host smart-a9b65a76-acb3-48d4-bb07-ae4c868a5e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19308
51474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_full.1930851474
Directory /workspace/39.usbdev_rx_full/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2697039474
Short name T2082
Test name
Test status
Simulation time 162727972 ps
CPU time 0.87 seconds
Started Aug 18 05:37:33 PM PDT 24
Finished Aug 18 05:37:34 PM PDT 24
Peak memory 207548 kb
Host smart-86bf6d31-e8ef-4b6f-a914-8b6af657f11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26970
39474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2697039474
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1754069482
Short name T117
Test name
Test status
Simulation time 168772494 ps
CPU time 0.9 seconds
Started Aug 18 05:37:50 PM PDT 24
Finished Aug 18 05:37:51 PM PDT 24
Peak memory 207412 kb
Host smart-532fc799-21cd-44c5-b804-cb1a35a6c2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17540
69482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1754069482
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.765772482
Short name T3423
Test name
Test status
Simulation time 190066855 ps
CPU time 0.91 seconds
Started Aug 18 05:37:26 PM PDT 24
Finished Aug 18 05:37:27 PM PDT 24
Peak memory 207520 kb
Host smart-c439ec0e-f053-4bad-b84d-31ef958782b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76577
2482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.765772482
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.2365840378
Short name T1671
Test name
Test status
Simulation time 2364682860 ps
CPU time 67.21 seconds
Started Aug 18 05:37:27 PM PDT 24
Finished Aug 18 05:38:35 PM PDT 24
Peak memory 217548 kb
Host smart-c44f30ee-35b0-4604-88b2-4cbbdf067d3d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2365840378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.2365840378
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3434857786
Short name T667
Test name
Test status
Simulation time 202233059 ps
CPU time 0.92 seconds
Started Aug 18 05:37:30 PM PDT 24
Finished Aug 18 05:37:31 PM PDT 24
Peak memory 207484 kb
Host smart-98b39e38-de1e-46ee-8384-2268a82f26de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34348
57786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3434857786
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.2662353925
Short name T3284
Test name
Test status
Simulation time 172181621 ps
CPU time 0.93 seconds
Started Aug 18 05:37:38 PM PDT 24
Finished Aug 18 05:37:39 PM PDT 24
Peak memory 207488 kb
Host smart-f9b7b6ab-9f18-41d4-9a4a-66db186395b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26623
53925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2662353925
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.1135835526
Short name T1544
Test name
Test status
Simulation time 1369882395 ps
CPU time 3.28 seconds
Started Aug 18 05:37:40 PM PDT 24
Finished Aug 18 05:37:44 PM PDT 24
Peak memory 207644 kb
Host smart-84f22e03-2957-443c-9632-e59e4360579d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11358
35526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.1135835526
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.2818338145
Short name T2115
Test name
Test status
Simulation time 2277731766 ps
CPU time 17.42 seconds
Started Aug 18 05:37:23 PM PDT 24
Finished Aug 18 05:37:40 PM PDT 24
Peak memory 217588 kb
Host smart-453fbce2-1324-4f40-a408-c1d5b3a43da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28183
38145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.2818338145
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.2880510990
Short name T606
Test name
Test status
Simulation time 1506441822 ps
CPU time 34.24 seconds
Started Aug 18 05:37:37 PM PDT 24
Finished Aug 18 05:38:12 PM PDT 24
Peak memory 207648 kb
Host smart-995ccd0b-3198-4159-925c-ffef1a920933
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880510990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_hos
t_handshake.2880510990
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_tx_rx_disruption.3079878811
Short name T762
Test name
Test status
Simulation time 580207056 ps
CPU time 1.56 seconds
Started Aug 18 05:37:39 PM PDT 24
Finished Aug 18 05:37:41 PM PDT 24
Peak memory 207576 kb
Host smart-c1c05f75-f666-4c26-9516-9711780497de
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079878811 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.usbdev_tx_rx_disruption.3079878811
Directory /workspace/39.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/390.usbdev_tx_rx_disruption.907810069
Short name T890
Test name
Test status
Simulation time 532891385 ps
CPU time 1.66 seconds
Started Aug 18 05:40:20 PM PDT 24
Finished Aug 18 05:40:22 PM PDT 24
Peak memory 206560 kb
Host smart-9a54a9f7-b8d5-499d-8e91-002f63be216b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907810069 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 390.usbdev_tx_rx_disruption.907810069
Directory /workspace/390.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/391.usbdev_tx_rx_disruption.2281038739
Short name T754
Test name
Test status
Simulation time 608319223 ps
CPU time 1.64 seconds
Started Aug 18 05:40:19 PM PDT 24
Finished Aug 18 05:40:20 PM PDT 24
Peak memory 207556 kb
Host smart-ba40ae6c-8819-4342-8c58-d55d66888872
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281038739 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 391.usbdev_tx_rx_disruption.2281038739
Directory /workspace/391.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/392.usbdev_tx_rx_disruption.2315148793
Short name T3388
Test name
Test status
Simulation time 694554644 ps
CPU time 2.01 seconds
Started Aug 18 05:40:17 PM PDT 24
Finished Aug 18 05:40:19 PM PDT 24
Peak memory 206560 kb
Host smart-0d665415-5aa3-4e99-bd98-c4b337475eb8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315148793 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 392.usbdev_tx_rx_disruption.2315148793
Directory /workspace/392.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/393.usbdev_tx_rx_disruption.168045109
Short name T207
Test name
Test status
Simulation time 710798034 ps
CPU time 1.82 seconds
Started Aug 18 05:39:54 PM PDT 24
Finished Aug 18 05:39:56 PM PDT 24
Peak memory 207584 kb
Host smart-4db9713d-399c-49f7-ac2c-a92e1f36e5b8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168045109 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 393.usbdev_tx_rx_disruption.168045109
Directory /workspace/393.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/394.usbdev_tx_rx_disruption.3952979834
Short name T2696
Test name
Test status
Simulation time 689119332 ps
CPU time 1.7 seconds
Started Aug 18 05:39:56 PM PDT 24
Finished Aug 18 05:39:57 PM PDT 24
Peak memory 207520 kb
Host smart-80e5115d-4c30-4ac3-8674-064fa38425c3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952979834 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 394.usbdev_tx_rx_disruption.3952979834
Directory /workspace/394.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/395.usbdev_tx_rx_disruption.3089813082
Short name T1698
Test name
Test status
Simulation time 497323352 ps
CPU time 1.65 seconds
Started Aug 18 05:40:04 PM PDT 24
Finished Aug 18 05:40:06 PM PDT 24
Peak memory 207480 kb
Host smart-5e5f4a0b-7d02-4136-8563-e067a8bb2ec3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089813082 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 395.usbdev_tx_rx_disruption.3089813082
Directory /workspace/395.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/396.usbdev_tx_rx_disruption.1163191597
Short name T1791
Test name
Test status
Simulation time 614162018 ps
CPU time 1.56 seconds
Started Aug 18 05:40:18 PM PDT 24
Finished Aug 18 05:40:20 PM PDT 24
Peak memory 206560 kb
Host smart-a67eb693-75a6-4bbe-9a94-7913f072ccaf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163191597 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 396.usbdev_tx_rx_disruption.1163191597
Directory /workspace/396.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/397.usbdev_tx_rx_disruption.4064509095
Short name T3229
Test name
Test status
Simulation time 517857826 ps
CPU time 1.66 seconds
Started Aug 18 05:40:07 PM PDT 24
Finished Aug 18 05:40:08 PM PDT 24
Peak memory 207532 kb
Host smart-8e15f63a-302e-4e91-a607-42861fc67a83
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064509095 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 397.usbdev_tx_rx_disruption.4064509095
Directory /workspace/397.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/398.usbdev_tx_rx_disruption.1923241247
Short name T1036
Test name
Test status
Simulation time 446369832 ps
CPU time 1.36 seconds
Started Aug 18 05:40:24 PM PDT 24
Finished Aug 18 05:40:25 PM PDT 24
Peak memory 206560 kb
Host smart-f60018df-3858-4e7b-a23f-f280a08cbaa6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923241247 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 398.usbdev_tx_rx_disruption.1923241247
Directory /workspace/398.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/399.usbdev_tx_rx_disruption.2662432461
Short name T3084
Test name
Test status
Simulation time 495892654 ps
CPU time 1.49 seconds
Started Aug 18 05:39:53 PM PDT 24
Finished Aug 18 05:39:55 PM PDT 24
Peak memory 207480 kb
Host smart-9b6f8141-0167-4d17-8c68-414f3a75cce4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662432461 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 399.usbdev_tx_rx_disruption.2662432461
Directory /workspace/399.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.3555131262
Short name T3061
Test name
Test status
Simulation time 38594896 ps
CPU time 0.68 seconds
Started Aug 18 05:32:43 PM PDT 24
Finished Aug 18 05:32:44 PM PDT 24
Peak memory 207444 kb
Host smart-030633eb-556a-4bf4-bf41-44318db1a515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3555131262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.3555131262
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.1090860493
Short name T1186
Test name
Test status
Simulation time 4877700523 ps
CPU time 6.99 seconds
Started Aug 18 05:32:22 PM PDT 24
Finished Aug 18 05:32:29 PM PDT 24
Peak memory 215988 kb
Host smart-1347db6a-374b-4b6f-b1c3-35282336f769
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090860493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_disconnect.1090860493
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2176672932
Short name T3598
Test name
Test status
Simulation time 18471539567 ps
CPU time 24.78 seconds
Started Aug 18 05:32:51 PM PDT 24
Finished Aug 18 05:33:16 PM PDT 24
Peak memory 207728 kb
Host smart-80fe75d4-81f0-4f24-96a3-2d5d3b3a833b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176672932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2176672932
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.1431764382
Short name T1125
Test name
Test status
Simulation time 30206137729 ps
CPU time 37.03 seconds
Started Aug 18 05:32:15 PM PDT 24
Finished Aug 18 05:32:52 PM PDT 24
Peak memory 207804 kb
Host smart-7f43d04d-cd5e-4bae-9eb2-685cf0ce3120
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431764382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.1431764382
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2140784127
Short name T1654
Test name
Test status
Simulation time 161258257 ps
CPU time 0.88 seconds
Started Aug 18 05:32:29 PM PDT 24
Finished Aug 18 05:32:30 PM PDT 24
Peak memory 207492 kb
Host smart-df0edae5-f703-4d4c-b576-fe0c18a647a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21407
84127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2140784127
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.1240137712
Short name T48
Test name
Test status
Simulation time 146708721 ps
CPU time 0.87 seconds
Started Aug 18 05:32:34 PM PDT 24
Finished Aug 18 05:32:35 PM PDT 24
Peak memory 207420 kb
Host smart-a4694133-8abf-4b86-8a42-7cb0dd671b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12401
37712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.1240137712
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.1839974141
Short name T52
Test name
Test status
Simulation time 165509153 ps
CPU time 0.9 seconds
Started Aug 18 05:32:18 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 207444 kb
Host smart-ddf5907d-2cc0-4a04-93d2-4ae8d86aa61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18399
74141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.1839974141
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.2508424179
Short name T1844
Test name
Test status
Simulation time 199206951 ps
CPU time 0.89 seconds
Started Aug 18 05:32:32 PM PDT 24
Finished Aug 18 05:32:33 PM PDT 24
Peak memory 207552 kb
Host smart-3c83b658-d3b0-4f52-9af0-9cc08d066ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084
24179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.2508424179
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.809531819
Short name T1642
Test name
Test status
Simulation time 248661308 ps
CPU time 1.11 seconds
Started Aug 18 05:32:23 PM PDT 24
Finished Aug 18 05:32:24 PM PDT 24
Peak memory 207440 kb
Host smart-115b6f24-1217-4c8d-865a-450d8fdc9685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80953
1819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.809531819
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_device_address.3919786003
Short name T521
Test name
Test status
Simulation time 32314862909 ps
CPU time 55.98 seconds
Started Aug 18 05:32:29 PM PDT 24
Finished Aug 18 05:33:25 PM PDT 24
Peak memory 207752 kb
Host smart-10eab524-1781-41aa-b65b-321284f04b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39197
86003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.3919786003
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.2268100900
Short name T780
Test name
Test status
Simulation time 598733652 ps
CPU time 11.57 seconds
Started Aug 18 05:32:25 PM PDT 24
Finished Aug 18 05:32:37 PM PDT 24
Peak memory 207736 kb
Host smart-497956cb-3c98-44e5-99f1-b3a5246995e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268100900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.2268100900
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.3421994215
Short name T3431
Test name
Test status
Simulation time 544173956 ps
CPU time 1.57 seconds
Started Aug 18 05:32:37 PM PDT 24
Finished Aug 18 05:32:39 PM PDT 24
Peak memory 207536 kb
Host smart-6b94c7a3-9723-43ce-be39-7d32ada890f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34219
94215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.3421994215
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.845654262
Short name T3068
Test name
Test status
Simulation time 138551098 ps
CPU time 0.89 seconds
Started Aug 18 05:32:30 PM PDT 24
Finished Aug 18 05:32:31 PM PDT 24
Peak memory 207472 kb
Host smart-f4360278-323f-4610-9a22-61a5d49aee6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84565
4262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.845654262
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.4090386310
Short name T2882
Test name
Test status
Simulation time 34562068 ps
CPU time 0.69 seconds
Started Aug 18 05:32:30 PM PDT 24
Finished Aug 18 05:32:30 PM PDT 24
Peak memory 207444 kb
Host smart-5f3a0572-c8c4-4703-be0b-1670168e7214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40903
86310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.4090386310
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2701173044
Short name T2116
Test name
Test status
Simulation time 1021618726 ps
CPU time 2.83 seconds
Started Aug 18 05:32:16 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 207796 kb
Host smart-6262f23a-825a-4b5b-a694-df4149a85be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27011
73044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2701173044
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_types.1626432153
Short name T404
Test name
Test status
Simulation time 367871837 ps
CPU time 1.17 seconds
Started Aug 18 05:32:34 PM PDT 24
Finished Aug 18 05:32:35 PM PDT 24
Peak memory 207512 kb
Host smart-68b3f2d0-d743-4ac0-89da-3a5541faa206
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1626432153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_types.1626432153
Directory /workspace/4.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1444786524
Short name T228
Test name
Test status
Simulation time 307483700 ps
CPU time 2.21 seconds
Started Aug 18 05:32:32 PM PDT 24
Finished Aug 18 05:32:34 PM PDT 24
Peak memory 207644 kb
Host smart-327aa90e-6b12-42d4-bd27-b8218d4334ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14447
86524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1444786524
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2751142797
Short name T91
Test name
Test status
Simulation time 94210418338 ps
CPU time 149.34 seconds
Started Aug 18 05:32:37 PM PDT 24
Finished Aug 18 05:35:07 PM PDT 24
Peak memory 207648 kb
Host smart-997cebbd-db51-44f8-905a-a3b7438604e1
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2751142797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2751142797
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.767559936
Short name T538
Test name
Test status
Simulation time 108191081317 ps
CPU time 174.67 seconds
Started Aug 18 05:32:26 PM PDT 24
Finished Aug 18 05:35:20 PM PDT 24
Peak memory 207800 kb
Host smart-0699d852-47cb-42a1-a184-fb6af71834f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767559936 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.767559936
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.1835072647
Short name T1932
Test name
Test status
Simulation time 108097767542 ps
CPU time 188.43 seconds
Started Aug 18 05:32:28 PM PDT 24
Finished Aug 18 05:35:37 PM PDT 24
Peak memory 207712 kb
Host smart-82e87bb5-bd7a-4ec8-8c93-ce4946fff63f
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1835072647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1835072647
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.3948196010
Short name T2684
Test name
Test status
Simulation time 96241555548 ps
CPU time 147.81 seconds
Started Aug 18 05:32:38 PM PDT 24
Finished Aug 18 05:35:06 PM PDT 24
Peak memory 207764 kb
Host smart-e4b69610-e449-4be6-bc99-855c7e31b487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948196010 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.3948196010
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.1976384702
Short name T3194
Test name
Test status
Simulation time 106176750527 ps
CPU time 157.31 seconds
Started Aug 18 05:32:45 PM PDT 24
Finished Aug 18 05:35:22 PM PDT 24
Peak memory 207700 kb
Host smart-d34b96c1-7d7d-49d5-adfa-8c215addb886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19763
84702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.1976384702
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.2208377011
Short name T1700
Test name
Test status
Simulation time 204646318 ps
CPU time 1.07 seconds
Started Aug 18 05:32:33 PM PDT 24
Finished Aug 18 05:32:34 PM PDT 24
Peak memory 215868 kb
Host smart-b2191ca6-5c46-4ba2-a1eb-0eca80d2c1a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2208377011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.2208377011
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.48273560
Short name T2402
Test name
Test status
Simulation time 147772531 ps
CPU time 0.84 seconds
Started Aug 18 05:32:19 PM PDT 24
Finished Aug 18 05:32:20 PM PDT 24
Peak memory 207400 kb
Host smart-d0278aa9-ccb8-49ce-8d0a-f4b5b069a0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48273
560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.48273560
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2029661407
Short name T1493
Test name
Test status
Simulation time 186161577 ps
CPU time 0.93 seconds
Started Aug 18 05:32:18 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 207460 kb
Host smart-880a6788-9244-4e76-8097-8bd83db3b494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20296
61407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2029661407
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.3820325181
Short name T2773
Test name
Test status
Simulation time 4233060503 ps
CPU time 42.21 seconds
Started Aug 18 05:32:31 PM PDT 24
Finished Aug 18 05:33:13 PM PDT 24
Peak memory 218300 kb
Host smart-4ed17a1f-b0ec-4552-a7e0-e7ee21852372
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3820325181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.3820325181
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.3713596282
Short name T86
Test name
Test status
Simulation time 6234659269 ps
CPU time 71.5 seconds
Started Aug 18 05:32:16 PM PDT 24
Finished Aug 18 05:33:28 PM PDT 24
Peak memory 207784 kb
Host smart-86e8fb03-a7c4-4802-8262-db50cf50230b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3713596282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.3713596282
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3594989607
Short name T3338
Test name
Test status
Simulation time 176533456 ps
CPU time 0.93 seconds
Started Aug 18 05:32:15 PM PDT 24
Finished Aug 18 05:32:16 PM PDT 24
Peak memory 207420 kb
Host smart-6986511c-eb29-4a0c-8490-5b935dd2eab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35949
89607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3594989607
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.129716250
Short name T2892
Test name
Test status
Simulation time 22863524146 ps
CPU time 36.09 seconds
Started Aug 18 05:32:32 PM PDT 24
Finished Aug 18 05:33:08 PM PDT 24
Peak memory 207720 kb
Host smart-ef705ab3-39d2-4f96-a91b-fde06755fe43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12971
6250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.129716250
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.1231853499
Short name T2495
Test name
Test status
Simulation time 9955258080 ps
CPU time 13.03 seconds
Started Aug 18 05:32:39 PM PDT 24
Finished Aug 18 05:32:52 PM PDT 24
Peak memory 207816 kb
Host smart-2c6d16f1-d2ad-4e8d-bf02-5cb10f464f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12318
53499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1231853499
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.781374713
Short name T2846
Test name
Test status
Simulation time 3282592742 ps
CPU time 95.94 seconds
Started Aug 18 05:32:31 PM PDT 24
Finished Aug 18 05:34:07 PM PDT 24
Peak memory 218412 kb
Host smart-21355634-ae13-4433-aec7-7253aa9ba979
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=781374713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.781374713
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.3135522239
Short name T1198
Test name
Test status
Simulation time 2260652631 ps
CPU time 22.26 seconds
Started Aug 18 05:32:31 PM PDT 24
Finished Aug 18 05:32:53 PM PDT 24
Peak memory 216044 kb
Host smart-36fc1bb4-6e7d-4e53-810f-0fd38996d05c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3135522239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.3135522239
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.3322000272
Short name T3301
Test name
Test status
Simulation time 258712430 ps
CPU time 1.01 seconds
Started Aug 18 05:32:37 PM PDT 24
Finished Aug 18 05:32:38 PM PDT 24
Peak memory 207500 kb
Host smart-e3a20b57-f3ba-42df-bc26-3a51a2f26aab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3322000272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.3322000272
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.489223660
Short name T1433
Test name
Test status
Simulation time 197976843 ps
CPU time 0.92 seconds
Started Aug 18 05:32:39 PM PDT 24
Finished Aug 18 05:32:40 PM PDT 24
Peak memory 207396 kb
Host smart-1e393268-d3bd-49bb-82c0-c091d5dbea02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48922
3660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.489223660
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_non_iso_usb_traffic.44641144
Short name T2566
Test name
Test status
Simulation time 2108678298 ps
CPU time 15.99 seconds
Started Aug 18 05:32:17 PM PDT 24
Finished Aug 18 05:32:33 PM PDT 24
Peak memory 217524 kb
Host smart-2faf4c5b-1e86-438d-bfa7-bd5dba2f1e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44641
144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_non_iso_usb_traffic.44641144
Directory /workspace/4.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3103201793
Short name T2448
Test name
Test status
Simulation time 2709427259 ps
CPU time 30.75 seconds
Started Aug 18 05:32:18 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 218712 kb
Host smart-a695f84b-0086-496d-ad3b-e3a4df67d1f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3103201793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3103201793
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.816470571
Short name T2536
Test name
Test status
Simulation time 1968497205 ps
CPU time 14.56 seconds
Started Aug 18 05:32:34 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207744 kb
Host smart-506d2e78-a8a3-4bf2-8de6-5a6ae066b5bd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=816470571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.816470571
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1992921886
Short name T2965
Test name
Test status
Simulation time 157039145 ps
CPU time 0.9 seconds
Started Aug 18 05:32:18 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 207508 kb
Host smart-bc3daddd-4ba7-4479-87e8-e8cf956ea32c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1992921886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1992921886
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3587292311
Short name T1372
Test name
Test status
Simulation time 189331083 ps
CPU time 0.94 seconds
Started Aug 18 05:32:30 PM PDT 24
Finished Aug 18 05:32:32 PM PDT 24
Peak memory 207448 kb
Host smart-45a887ac-1687-4ad0-a588-0db8097a8f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35872
92311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3587292311
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.1955754719
Short name T146
Test name
Test status
Simulation time 226156476 ps
CPU time 0.99 seconds
Started Aug 18 05:32:31 PM PDT 24
Finished Aug 18 05:32:32 PM PDT 24
Peak memory 207488 kb
Host smart-2df6b3f8-77f1-4907-81e0-254843917761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19557
54719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1955754719
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2445087246
Short name T2052
Test name
Test status
Simulation time 191489609 ps
CPU time 0.93 seconds
Started Aug 18 05:32:21 PM PDT 24
Finished Aug 18 05:32:22 PM PDT 24
Peak memory 207468 kb
Host smart-41672515-a4d7-4177-9b84-c004268e4d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24450
87246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2445087246
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1531659776
Short name T604
Test name
Test status
Simulation time 202459363 ps
CPU time 0.92 seconds
Started Aug 18 05:32:29 PM PDT 24
Finished Aug 18 05:32:30 PM PDT 24
Peak memory 207508 kb
Host smart-b1475c9d-bec8-4fb7-915d-4e476c95ee25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15316
59776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1531659776
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.219570166
Short name T1683
Test name
Test status
Simulation time 176081653 ps
CPU time 0.91 seconds
Started Aug 18 05:32:19 PM PDT 24
Finished Aug 18 05:32:20 PM PDT 24
Peak memory 207508 kb
Host smart-87e0b486-b7ed-4266-9984-5baa7a427fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21957
0166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.219570166
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2260916090
Short name T198
Test name
Test status
Simulation time 202626693 ps
CPU time 0.96 seconds
Started Aug 18 05:32:32 PM PDT 24
Finished Aug 18 05:32:33 PM PDT 24
Peak memory 207584 kb
Host smart-6b307cef-e4e5-4142-89d3-2f2478929446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22609
16090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2260916090
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.2797749754
Short name T2516
Test name
Test status
Simulation time 198239178 ps
CPU time 0.96 seconds
Started Aug 18 05:32:29 PM PDT 24
Finished Aug 18 05:32:30 PM PDT 24
Peak memory 207580 kb
Host smart-de57213f-b7d5-4d51-80c7-daf5d95dcf1c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2797749754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2797749754
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.3737821345
Short name T1444
Test name
Test status
Simulation time 185738100 ps
CPU time 0.94 seconds
Started Aug 18 05:32:18 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 207460 kb
Host smart-9f3755f0-67d1-4264-910d-ee88c5618f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37378
21345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.3737821345
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.1479284642
Short name T238
Test name
Test status
Simulation time 141627593 ps
CPU time 0.8 seconds
Started Aug 18 05:32:27 PM PDT 24
Finished Aug 18 05:32:27 PM PDT 24
Peak memory 206436 kb
Host smart-b9eb5e1d-9735-4503-9670-39a7678aee7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14792
84642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.1479284642
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3603021600
Short name T2469
Test name
Test status
Simulation time 79280214 ps
CPU time 0.74 seconds
Started Aug 18 05:32:16 PM PDT 24
Finished Aug 18 05:32:17 PM PDT 24
Peak memory 207504 kb
Host smart-cf204b1d-5739-48b8-8a90-db798721f6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36030
21600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3603021600
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3750520717
Short name T293
Test name
Test status
Simulation time 15184327287 ps
CPU time 37.33 seconds
Started Aug 18 05:32:19 PM PDT 24
Finished Aug 18 05:32:56 PM PDT 24
Peak memory 215896 kb
Host smart-07ac3cca-e612-43b7-8736-7ca28937d5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37505
20717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3750520717
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.2887253354
Short name T2403
Test name
Test status
Simulation time 171540827 ps
CPU time 0.9 seconds
Started Aug 18 05:32:31 PM PDT 24
Finished Aug 18 05:32:32 PM PDT 24
Peak memory 207548 kb
Host smart-e3ffd437-c72a-47b2-8a3d-8d7f045f61e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28872
53354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2887253354
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3914828778
Short name T3281
Test name
Test status
Simulation time 222036414 ps
CPU time 1.04 seconds
Started Aug 18 05:32:21 PM PDT 24
Finished Aug 18 05:32:22 PM PDT 24
Peak memory 207368 kb
Host smart-315107ed-5688-4c1a-a524-34f51d467949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39148
28778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3914828778
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.3610185578
Short name T1957
Test name
Test status
Simulation time 2414829097 ps
CPU time 15.44 seconds
Started Aug 18 05:32:32 PM PDT 24
Finished Aug 18 05:32:48 PM PDT 24
Peak memory 218184 kb
Host smart-bf1c4d6a-0a55-482c-8b36-fd70f1ba017b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3610185578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.3610185578
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.3483025064
Short name T531
Test name
Test status
Simulation time 9592462059 ps
CPU time 49.7 seconds
Started Aug 18 05:32:45 PM PDT 24
Finished Aug 18 05:33:35 PM PDT 24
Peak memory 216024 kb
Host smart-d3236894-28d6-4bb5-92ff-91d285864be2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483025064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.3483025064
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.3733749051
Short name T3025
Test name
Test status
Simulation time 231203211 ps
CPU time 0.94 seconds
Started Aug 18 05:32:18 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 207488 kb
Host smart-ca036d7a-4720-4284-8ba6-6c26e4bd2d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37337
49051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.3733749051
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3633105785
Short name T825
Test name
Test status
Simulation time 206845740 ps
CPU time 0.96 seconds
Started Aug 18 05:32:22 PM PDT 24
Finished Aug 18 05:32:23 PM PDT 24
Peak memory 207452 kb
Host smart-95cbfb17-af9b-4bcb-bfa2-93a055b86016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36331
05785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3633105785
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_resume_link_active.2541317068
Short name T1964
Test name
Test status
Simulation time 20185640991 ps
CPU time 25.17 seconds
Started Aug 18 05:32:31 PM PDT 24
Finished Aug 18 05:32:57 PM PDT 24
Peak memory 207596 kb
Host smart-2e737758-98e1-42fd-8901-b60d82dd4f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25413
17068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_resume_link_active.2541317068
Directory /workspace/4.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.282491923
Short name T1776
Test name
Test status
Simulation time 136644005 ps
CPU time 0.81 seconds
Started Aug 18 05:32:34 PM PDT 24
Finished Aug 18 05:32:35 PM PDT 24
Peak memory 207476 kb
Host smart-2bb04ca4-71ea-448f-b227-0609144802e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28249
1923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.282491923
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_full.1559681346
Short name T2952
Test name
Test status
Simulation time 242325259 ps
CPU time 1.07 seconds
Started Aug 18 05:32:40 PM PDT 24
Finished Aug 18 05:32:41 PM PDT 24
Peak memory 207444 kb
Host smart-cec76665-5dfb-4adf-baaf-298fc615ea6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15596
81346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_full.1559681346
Directory /workspace/4.usbdev_rx_full/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.2025698412
Short name T1872
Test name
Test status
Simulation time 191972940 ps
CPU time 0.92 seconds
Started Aug 18 05:32:32 PM PDT 24
Finished Aug 18 05:32:33 PM PDT 24
Peak memory 207492 kb
Host smart-1e075dab-a819-400c-8a8f-38e42f93ae53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20256
98412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.2025698412
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1336802606
Short name T254
Test name
Test status
Simulation time 630466801 ps
CPU time 1.59 seconds
Started Aug 18 05:33:01 PM PDT 24
Finished Aug 18 05:33:03 PM PDT 24
Peak memory 223204 kb
Host smart-c58204f0-9920-4b37-8e35-517f750a8701
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1336802606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1336802606
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.2091190151
Short name T39
Test name
Test status
Simulation time 423487267 ps
CPU time 1.38 seconds
Started Aug 18 05:32:40 PM PDT 24
Finished Aug 18 05:32:42 PM PDT 24
Peak memory 207512 kb
Host smart-8c52227e-6005-4b22-9693-c7659fd1760e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20911
90151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.2091190151
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.453603238
Short name T2311
Test name
Test status
Simulation time 312083047 ps
CPU time 1.08 seconds
Started Aug 18 05:32:20 PM PDT 24
Finished Aug 18 05:32:21 PM PDT 24
Peak memory 207512 kb
Host smart-23d5159d-261a-4141-8779-f4cea1c12b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45360
3238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.453603238
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.4224765541
Short name T2977
Test name
Test status
Simulation time 165799408 ps
CPU time 0.86 seconds
Started Aug 18 05:32:28 PM PDT 24
Finished Aug 18 05:32:29 PM PDT 24
Peak memory 207464 kb
Host smart-6199ab1a-1355-4dd1-919e-293ae3c6ddb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42247
65541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.4224765541
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3328037115
Short name T1324
Test name
Test status
Simulation time 170231894 ps
CPU time 0.84 seconds
Started Aug 18 05:32:33 PM PDT 24
Finished Aug 18 05:32:34 PM PDT 24
Peak memory 207572 kb
Host smart-5070d59e-8f90-4d87-8aef-2848e4cdbdcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33280
37115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3328037115
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2514251261
Short name T2224
Test name
Test status
Simulation time 230037782 ps
CPU time 1 seconds
Started Aug 18 05:32:37 PM PDT 24
Finished Aug 18 05:32:38 PM PDT 24
Peak memory 207492 kb
Host smart-75e09a3f-3de6-4077-af4c-3d4a85d85b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25142
51261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2514251261
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.736255856
Short name T1513
Test name
Test status
Simulation time 1816698361 ps
CPU time 14.58 seconds
Started Aug 18 05:32:28 PM PDT 24
Finished Aug 18 05:32:43 PM PDT 24
Peak memory 217596 kb
Host smart-896de4be-a5be-4372-80e8-aba8315a81df
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=736255856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.736255856
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1351910669
Short name T2218
Test name
Test status
Simulation time 197301787 ps
CPU time 0.94 seconds
Started Aug 18 05:32:28 PM PDT 24
Finished Aug 18 05:32:29 PM PDT 24
Peak memory 207500 kb
Host smart-0db8d163-a3f4-48c9-b4ce-8b7d0bc6a34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13519
10669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1351910669
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1975593477
Short name T3574
Test name
Test status
Simulation time 168681526 ps
CPU time 0.91 seconds
Started Aug 18 05:32:17 PM PDT 24
Finished Aug 18 05:32:18 PM PDT 24
Peak memory 207472 kb
Host smart-6992e250-959f-40c5-a297-bf3117b8d13c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19755
93477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1975593477
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.2791370704
Short name T2214
Test name
Test status
Simulation time 1366348148 ps
CPU time 3.22 seconds
Started Aug 18 05:32:17 PM PDT 24
Finished Aug 18 05:32:21 PM PDT 24
Peak memory 207760 kb
Host smart-1d9cbfc9-e4f0-4233-9be6-83948c78760d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27913
70704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.2791370704
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1209215669
Short name T2994
Test name
Test status
Simulation time 1868546474 ps
CPU time 19.19 seconds
Started Aug 18 05:32:28 PM PDT 24
Finished Aug 18 05:32:48 PM PDT 24
Peak memory 216120 kb
Host smart-e757404e-14cc-4e7f-bd90-8a1082b2f30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12092
15669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1209215669
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.3493044064
Short name T2009
Test name
Test status
Simulation time 1343855679 ps
CPU time 8.96 seconds
Started Aug 18 05:32:19 PM PDT 24
Finished Aug 18 05:32:33 PM PDT 24
Peak memory 207652 kb
Host smart-daa6e878-6d64-4c13-84fa-06499c850b33
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493044064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.3493044064
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_tx_rx_disruption.3302916575
Short name T1920
Test name
Test status
Simulation time 585863887 ps
CPU time 1.66 seconds
Started Aug 18 05:32:43 PM PDT 24
Finished Aug 18 05:32:45 PM PDT 24
Peak memory 207528 kb
Host smart-6078be3a-19c6-483b-8e14-b031d2ebde86
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302916575 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.usbdev_tx_rx_disruption.3302916575
Directory /workspace/4.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3749610533
Short name T2326
Test name
Test status
Simulation time 56368056 ps
CPU time 0.68 seconds
Started Aug 18 05:37:43 PM PDT 24
Finished Aug 18 05:37:44 PM PDT 24
Peak memory 207424 kb
Host smart-cbdc141c-9ebb-4f43-8f0c-53798a5b96a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3749610533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3749610533
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.199185608
Short name T709
Test name
Test status
Simulation time 11090642602 ps
CPU time 14.56 seconds
Started Aug 18 05:37:39 PM PDT 24
Finished Aug 18 05:37:54 PM PDT 24
Peak memory 207840 kb
Host smart-6859d716-116a-4719-8ceb-82b92d92b77c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199185608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_ao
n_wake_disconnect.199185608
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.4215774375
Short name T3340
Test name
Test status
Simulation time 20244894284 ps
CPU time 28.6 seconds
Started Aug 18 05:37:29 PM PDT 24
Finished Aug 18 05:37:58 PM PDT 24
Peak memory 207820 kb
Host smart-dbc5e194-9844-40a8-aa04-3d8f123b2c71
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215774375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.4215774375
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3811597823
Short name T775
Test name
Test status
Simulation time 26187448146 ps
CPU time 30.28 seconds
Started Aug 18 05:37:31 PM PDT 24
Finished Aug 18 05:38:01 PM PDT 24
Peak memory 216020 kb
Host smart-c7711183-a9b2-4f3a-9786-9fd72b87f6c7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811597823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.3811597823
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3600469879
Short name T2437
Test name
Test status
Simulation time 162044181 ps
CPU time 0.88 seconds
Started Aug 18 05:37:46 PM PDT 24
Finished Aug 18 05:37:46 PM PDT 24
Peak memory 207508 kb
Host smart-af8fb02c-623c-40c8-8f74-57a1ee8fea24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36004
69879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3600469879
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.2687045546
Short name T1311
Test name
Test status
Simulation time 185908250 ps
CPU time 0.9 seconds
Started Aug 18 05:37:30 PM PDT 24
Finished Aug 18 05:37:31 PM PDT 24
Peak memory 207676 kb
Host smart-2eb490f9-2c16-4e18-a451-be7436d0e2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26870
45546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.2687045546
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.295859322
Short name T2957
Test name
Test status
Simulation time 453366614 ps
CPU time 1.48 seconds
Started Aug 18 05:37:50 PM PDT 24
Finished Aug 18 05:37:51 PM PDT 24
Peak memory 207564 kb
Host smart-62d15303-dea0-4ba0-8c8c-4e2b75790a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29585
9322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.295859322
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.1389265725
Short name T2476
Test name
Test status
Simulation time 913591430 ps
CPU time 2.49 seconds
Started Aug 18 05:37:43 PM PDT 24
Finished Aug 18 05:37:45 PM PDT 24
Peak memory 207696 kb
Host smart-433c2081-5672-4810-825a-304bfde9ea9f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1389265725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.1389265725
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.2799686850
Short name T2013
Test name
Test status
Simulation time 32027687392 ps
CPU time 47.93 seconds
Started Aug 18 05:37:25 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 207796 kb
Host smart-ca5aeeb2-3f40-485a-ae37-9d8b6c814222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27996
86850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.2799686850
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.3213333705
Short name T1322
Test name
Test status
Simulation time 822994888 ps
CPU time 5.26 seconds
Started Aug 18 05:37:47 PM PDT 24
Finished Aug 18 05:37:53 PM PDT 24
Peak memory 207728 kb
Host smart-8abda5e0-5c29-49cb-80dd-1e70dc6ed54e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213333705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.3213333705
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.1926342670
Short name T2375
Test name
Test status
Simulation time 641691844 ps
CPU time 1.52 seconds
Started Aug 18 05:37:48 PM PDT 24
Finished Aug 18 05:37:49 PM PDT 24
Peak memory 207552 kb
Host smart-3d3b484f-7c25-461f-b0e9-a712f9a2a74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19263
42670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.1926342670
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.2758815033
Short name T2504
Test name
Test status
Simulation time 167728127 ps
CPU time 0.83 seconds
Started Aug 18 05:37:46 PM PDT 24
Finished Aug 18 05:37:47 PM PDT 24
Peak memory 207548 kb
Host smart-68266bf7-399c-48f2-b810-a8b34343493a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27588
15033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2758815033
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.982068346
Short name T2167
Test name
Test status
Simulation time 33959901 ps
CPU time 0.7 seconds
Started Aug 18 05:37:51 PM PDT 24
Finished Aug 18 05:37:52 PM PDT 24
Peak memory 207448 kb
Host smart-b4840992-a70b-41ba-90a6-746dff81235d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98206
8346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.982068346
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2620863978
Short name T849
Test name
Test status
Simulation time 986614399 ps
CPU time 2.55 seconds
Started Aug 18 05:37:28 PM PDT 24
Finished Aug 18 05:37:30 PM PDT 24
Peak memory 207816 kb
Host smart-e1457fe6-5e5b-4e21-8b96-bb5d879c949e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26208
63978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2620863978
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_types.3457336719
Short name T445
Test name
Test status
Simulation time 521194124 ps
CPU time 1.44 seconds
Started Aug 18 05:37:31 PM PDT 24
Finished Aug 18 05:37:33 PM PDT 24
Peak memory 207532 kb
Host smart-f629d3b1-bb5f-4071-a321-d1cf9e46d0bc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3457336719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_types.3457336719
Directory /workspace/40.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2191978322
Short name T1993
Test name
Test status
Simulation time 377850280 ps
CPU time 2.69 seconds
Started Aug 18 05:37:46 PM PDT 24
Finished Aug 18 05:37:49 PM PDT 24
Peak memory 207668 kb
Host smart-278b7d07-8ff4-47fd-a9d8-db399b2345f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21919
78322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2191978322
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.890534089
Short name T746
Test name
Test status
Simulation time 164839216 ps
CPU time 0.9 seconds
Started Aug 18 05:37:35 PM PDT 24
Finished Aug 18 05:37:36 PM PDT 24
Peak memory 207500 kb
Host smart-42671aba-482d-4185-9e8b-a40c443602d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=890534089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.890534089
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1460136335
Short name T2625
Test name
Test status
Simulation time 183818571 ps
CPU time 0.88 seconds
Started Aug 18 05:37:51 PM PDT 24
Finished Aug 18 05:37:53 PM PDT 24
Peak memory 207448 kb
Host smart-5cf6fd65-d54b-4616-921c-1453c560fe09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14601
36335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1460136335
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1776428688
Short name T1118
Test name
Test status
Simulation time 237290948 ps
CPU time 1.09 seconds
Started Aug 18 05:37:35 PM PDT 24
Finished Aug 18 05:37:36 PM PDT 24
Peak memory 207444 kb
Host smart-7aceb122-1828-4a9d-b2a0-92e5456fabd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17764
28688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1776428688
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.3853974748
Short name T3449
Test name
Test status
Simulation time 3931167097 ps
CPU time 38.76 seconds
Started Aug 18 05:37:25 PM PDT 24
Finished Aug 18 05:38:04 PM PDT 24
Peak memory 217472 kb
Host smart-4c3b9668-91a6-4129-8a15-c7011a9fd172
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3853974748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.3853974748
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.1729975908
Short name T2503
Test name
Test status
Simulation time 9621003129 ps
CPU time 61.69 seconds
Started Aug 18 05:37:42 PM PDT 24
Finished Aug 18 05:38:44 PM PDT 24
Peak memory 207804 kb
Host smart-6ae6b8ba-b956-4d07-b3fe-7c5cf0510c35
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1729975908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.1729975908
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2168023810
Short name T3636
Test name
Test status
Simulation time 217693776 ps
CPU time 0.91 seconds
Started Aug 18 05:37:46 PM PDT 24
Finished Aug 18 05:37:47 PM PDT 24
Peak memory 207488 kb
Host smart-e1bbff37-4d88-40cb-bb99-120f64fffbff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21680
23810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2168023810
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.38938897
Short name T34
Test name
Test status
Simulation time 29552812307 ps
CPU time 45.58 seconds
Started Aug 18 05:37:44 PM PDT 24
Finished Aug 18 05:38:30 PM PDT 24
Peak memory 207660 kb
Host smart-033248f9-8720-4342-a001-2c146109897d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38938
897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.38938897
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.569856287
Short name T2438
Test name
Test status
Simulation time 10561989820 ps
CPU time 15.45 seconds
Started Aug 18 05:37:31 PM PDT 24
Finished Aug 18 05:37:47 PM PDT 24
Peak memory 207804 kb
Host smart-726dc9dd-f611-4eb1-a26c-2eee3fa45fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56985
6287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.569856287
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.3345302493
Short name T3164
Test name
Test status
Simulation time 2239956189 ps
CPU time 61.91 seconds
Started Aug 18 05:37:33 PM PDT 24
Finished Aug 18 05:38:35 PM PDT 24
Peak memory 218444 kb
Host smart-79e54fa8-58c0-4273-8994-60819622b118
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3345302493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.3345302493
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2158755353
Short name T988
Test name
Test status
Simulation time 2463473670 ps
CPU time 19.47 seconds
Started Aug 18 05:37:50 PM PDT 24
Finished Aug 18 05:38:10 PM PDT 24
Peak memory 217636 kb
Host smart-5f5329d2-0bf8-4f01-99e2-21addf972457
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2158755353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2158755353
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.3177121114
Short name T2718
Test name
Test status
Simulation time 256788978 ps
CPU time 0.97 seconds
Started Aug 18 05:37:40 PM PDT 24
Finished Aug 18 05:37:41 PM PDT 24
Peak memory 207516 kb
Host smart-a804f59f-0cd7-44ff-9c52-14f150145563
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3177121114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.3177121114
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3089555508
Short name T2071
Test name
Test status
Simulation time 279899864 ps
CPU time 0.99 seconds
Started Aug 18 05:37:40 PM PDT 24
Finished Aug 18 05:37:41 PM PDT 24
Peak memory 207504 kb
Host smart-321dce93-e214-454b-812b-b2d798e3d5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30895
55508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3089555508
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.3836761211
Short name T2128
Test name
Test status
Simulation time 2826719266 ps
CPU time 21.79 seconds
Started Aug 18 05:37:28 PM PDT 24
Finished Aug 18 05:37:50 PM PDT 24
Peak memory 217800 kb
Host smart-80cb0013-5a62-4fad-b79a-f36ae7da0f3d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3836761211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.3836761211
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.2753015948
Short name T3317
Test name
Test status
Simulation time 153431927 ps
CPU time 0.86 seconds
Started Aug 18 05:37:46 PM PDT 24
Finished Aug 18 05:37:47 PM PDT 24
Peak memory 207640 kb
Host smart-5d7112df-0238-409e-9606-ca19fea326ad
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2753015948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.2753015948
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1979765240
Short name T2700
Test name
Test status
Simulation time 150026658 ps
CPU time 0.82 seconds
Started Aug 18 05:37:38 PM PDT 24
Finished Aug 18 05:37:39 PM PDT 24
Peak memory 207480 kb
Host smart-13226070-695d-42ba-9df3-284a5b957980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19797
65240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1979765240
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2277180047
Short name T161
Test name
Test status
Simulation time 274247188 ps
CPU time 1.07 seconds
Started Aug 18 05:37:48 PM PDT 24
Finished Aug 18 05:37:50 PM PDT 24
Peak memory 207448 kb
Host smart-19e27dde-8f62-4d15-a02c-18500d7390ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22771
80047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2277180047
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.53952922
Short name T835
Test name
Test status
Simulation time 179412093 ps
CPU time 0.97 seconds
Started Aug 18 05:37:46 PM PDT 24
Finished Aug 18 05:37:47 PM PDT 24
Peak memory 207480 kb
Host smart-ab61303b-2fc9-4ebd-b54c-1154cb946326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53952
922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.53952922
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.387110422
Short name T2546
Test name
Test status
Simulation time 197169112 ps
CPU time 0.88 seconds
Started Aug 18 05:37:38 PM PDT 24
Finished Aug 18 05:37:39 PM PDT 24
Peak memory 207464 kb
Host smart-061e1164-c70e-40ec-b59a-ce819aa7362d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38711
0422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.387110422
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3946663240
Short name T3180
Test name
Test status
Simulation time 208806911 ps
CPU time 0.9 seconds
Started Aug 18 05:37:40 PM PDT 24
Finished Aug 18 05:37:41 PM PDT 24
Peak memory 207572 kb
Host smart-4104358d-0077-452c-b7a0-388ffead3f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39466
63240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3946663240
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3322191423
Short name T3489
Test name
Test status
Simulation time 190787590 ps
CPU time 0.89 seconds
Started Aug 18 05:37:39 PM PDT 24
Finished Aug 18 05:37:40 PM PDT 24
Peak memory 207568 kb
Host smart-eda420fa-8e8a-4931-956a-2a0a92134e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33221
91423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3322191423
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.1583749188
Short name T1686
Test name
Test status
Simulation time 265693725 ps
CPU time 1.1 seconds
Started Aug 18 05:37:30 PM PDT 24
Finished Aug 18 05:37:31 PM PDT 24
Peak memory 207540 kb
Host smart-c0cfbb55-cd6b-4ef4-9f6b-7ba8f5985b73
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1583749188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.1583749188
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.291308479
Short name T1652
Test name
Test status
Simulation time 165395673 ps
CPU time 0.86 seconds
Started Aug 18 05:37:49 PM PDT 24
Finished Aug 18 05:37:50 PM PDT 24
Peak memory 207380 kb
Host smart-addac6e2-ff0a-4b8b-821d-ba6f18de5def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29130
8479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.291308479
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.968342567
Short name T2066
Test name
Test status
Simulation time 30072861 ps
CPU time 0.69 seconds
Started Aug 18 05:37:41 PM PDT 24
Finished Aug 18 05:37:42 PM PDT 24
Peak memory 207516 kb
Host smart-ed623e36-20cd-4497-ba42-a9cefa34d41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96834
2567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.968342567
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.252521315
Short name T1516
Test name
Test status
Simulation time 18279013148 ps
CPU time 52.96 seconds
Started Aug 18 05:37:31 PM PDT 24
Finished Aug 18 05:38:25 PM PDT 24
Peak memory 215936 kb
Host smart-03912a64-04e7-4f4c-840e-d3e9c6bab760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25252
1315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.252521315
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2299655556
Short name T3548
Test name
Test status
Simulation time 211681791 ps
CPU time 0.95 seconds
Started Aug 18 05:37:42 PM PDT 24
Finished Aug 18 05:37:43 PM PDT 24
Peak memory 207472 kb
Host smart-0366ac94-f510-4654-9a89-612818e512b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22996
55556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2299655556
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2643718682
Short name T2400
Test name
Test status
Simulation time 175846882 ps
CPU time 0.93 seconds
Started Aug 18 05:37:50 PM PDT 24
Finished Aug 18 05:37:51 PM PDT 24
Peak memory 207500 kb
Host smart-ae53ccbc-e6ff-4d1e-8ef7-07c640e4359a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26437
18682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2643718682
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1010668246
Short name T1878
Test name
Test status
Simulation time 255851552 ps
CPU time 1.03 seconds
Started Aug 18 05:37:35 PM PDT 24
Finished Aug 18 05:37:36 PM PDT 24
Peak memory 207456 kb
Host smart-b6fde44c-e1c2-434e-8dc4-fce7c2e16144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10106
68246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1010668246
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.265253505
Short name T599
Test name
Test status
Simulation time 213121936 ps
CPU time 0.97 seconds
Started Aug 18 05:37:38 PM PDT 24
Finished Aug 18 05:37:39 PM PDT 24
Peak memory 207468 kb
Host smart-4dac3a83-6709-412d-9ad3-63fe64f74c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26525
3505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.265253505
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.3685941552
Short name T2689
Test name
Test status
Simulation time 175759505 ps
CPU time 0.88 seconds
Started Aug 18 05:37:45 PM PDT 24
Finished Aug 18 05:37:46 PM PDT 24
Peak memory 207368 kb
Host smart-adb60b5a-29b7-4aef-b0b7-fc51ab32ad71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36859
41552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.3685941552
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_rx_full.3843681095
Short name T42
Test name
Test status
Simulation time 300660729 ps
CPU time 1.24 seconds
Started Aug 18 05:37:38 PM PDT 24
Finished Aug 18 05:37:40 PM PDT 24
Peak memory 207504 kb
Host smart-9aa97ba4-a667-4c25-95d3-c8837a96d356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38436
81095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_full.3843681095
Directory /workspace/40.usbdev_rx_full/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.228550373
Short name T1212
Test name
Test status
Simulation time 165325476 ps
CPU time 0.81 seconds
Started Aug 18 05:37:41 PM PDT 24
Finished Aug 18 05:37:42 PM PDT 24
Peak memory 207208 kb
Host smart-f0e51855-1068-4d82-9930-4854cf67b691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22855
0373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.228550373
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.4137877171
Short name T1106
Test name
Test status
Simulation time 164002216 ps
CPU time 0.81 seconds
Started Aug 18 05:37:35 PM PDT 24
Finished Aug 18 05:37:36 PM PDT 24
Peak memory 207228 kb
Host smart-a272d3b5-b9b0-440d-b13a-c30f9678baac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41378
77171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.4137877171
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1514174489
Short name T562
Test name
Test status
Simulation time 196979583 ps
CPU time 0.97 seconds
Started Aug 18 05:37:39 PM PDT 24
Finished Aug 18 05:37:40 PM PDT 24
Peak memory 207460 kb
Host smart-16cd6a08-5a2e-4340-bd5d-27ce63a7db0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15141
74489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1514174489
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.202477576
Short name T2321
Test name
Test status
Simulation time 2014581640 ps
CPU time 19.82 seconds
Started Aug 18 05:37:33 PM PDT 24
Finished Aug 18 05:37:53 PM PDT 24
Peak memory 223960 kb
Host smart-0348cc76-3814-4d87-9222-980c2e93d66f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=202477576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.202477576
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2162833603
Short name T1189
Test name
Test status
Simulation time 146634936 ps
CPU time 0.87 seconds
Started Aug 18 05:37:44 PM PDT 24
Finished Aug 18 05:37:45 PM PDT 24
Peak memory 207484 kb
Host smart-826d848e-49de-426c-a0ce-43f28dd88dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21628
33603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2162833603
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.3979321237
Short name T3532
Test name
Test status
Simulation time 177455285 ps
CPU time 0.87 seconds
Started Aug 18 05:37:52 PM PDT 24
Finished Aug 18 05:37:53 PM PDT 24
Peak memory 207584 kb
Host smart-4a7bbe88-b3b5-4b6e-b374-91ef98ac37b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39793
21237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.3979321237
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.2112011958
Short name T1399
Test name
Test status
Simulation time 200103403 ps
CPU time 0.97 seconds
Started Aug 18 05:37:44 PM PDT 24
Finished Aug 18 05:37:45 PM PDT 24
Peak memory 207540 kb
Host smart-ccbfbda0-f084-4516-8ccf-f683066a5d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21120
11958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.2112011958
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3210539528
Short name T904
Test name
Test status
Simulation time 3775166598 ps
CPU time 37.64 seconds
Started Aug 18 05:37:46 PM PDT 24
Finished Aug 18 05:38:24 PM PDT 24
Peak memory 215984 kb
Host smart-f20bb386-beae-4115-a61a-c100814105e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32105
39528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3210539528
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.3241339729
Short name T3289
Test name
Test status
Simulation time 2095029017 ps
CPU time 18.56 seconds
Started Aug 18 05:37:26 PM PDT 24
Finished Aug 18 05:37:44 PM PDT 24
Peak memory 207596 kb
Host smart-e2bf2546-cbec-453c-bcd1-43c4ef9b8329
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241339729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.3241339729
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_tx_rx_disruption.991735819
Short name T2993
Test name
Test status
Simulation time 512392075 ps
CPU time 1.54 seconds
Started Aug 18 05:37:45 PM PDT 24
Finished Aug 18 05:37:47 PM PDT 24
Peak memory 207576 kb
Host smart-6898d0f2-3214-40c4-961b-d26ca6a61958
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991735819 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.usbdev_tx_rx_disruption.991735819
Directory /workspace/40.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/400.usbdev_tx_rx_disruption.2608475384
Short name T2097
Test name
Test status
Simulation time 527817798 ps
CPU time 1.7 seconds
Started Aug 18 05:40:06 PM PDT 24
Finished Aug 18 05:40:08 PM PDT 24
Peak memory 207528 kb
Host smart-6a0b1cda-1990-40e9-aac9-31e57757dfd9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608475384 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 400.usbdev_tx_rx_disruption.2608475384
Directory /workspace/400.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/401.usbdev_tx_rx_disruption.2018900189
Short name T728
Test name
Test status
Simulation time 529587137 ps
CPU time 1.52 seconds
Started Aug 18 05:40:01 PM PDT 24
Finished Aug 18 05:40:03 PM PDT 24
Peak memory 207532 kb
Host smart-c5d1c2c1-8575-42c6-9299-8b863d237d48
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018900189 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 401.usbdev_tx_rx_disruption.2018900189
Directory /workspace/401.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/402.usbdev_tx_rx_disruption.3774047563
Short name T2560
Test name
Test status
Simulation time 520891997 ps
CPU time 1.69 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207544 kb
Host smart-15644dd9-ceb5-43bc-a47b-1b433a74c2c7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774047563 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 402.usbdev_tx_rx_disruption.3774047563
Directory /workspace/402.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/403.usbdev_tx_rx_disruption.1142073671
Short name T2140
Test name
Test status
Simulation time 611674401 ps
CPU time 1.6 seconds
Started Aug 18 05:40:16 PM PDT 24
Finished Aug 18 05:40:18 PM PDT 24
Peak memory 207592 kb
Host smart-05f3409e-7d22-4097-9dcf-09a7ea9a11e0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142073671 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 403.usbdev_tx_rx_disruption.1142073671
Directory /workspace/403.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/404.usbdev_tx_rx_disruption.3784863274
Short name T1553
Test name
Test status
Simulation time 576437734 ps
CPU time 1.53 seconds
Started Aug 18 05:40:16 PM PDT 24
Finished Aug 18 05:40:17 PM PDT 24
Peak memory 207584 kb
Host smart-e8ea9ec5-fc3c-4103-a0ce-f7710a715214
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784863274 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 404.usbdev_tx_rx_disruption.3784863274
Directory /workspace/404.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/405.usbdev_tx_rx_disruption.2365874724
Short name T1091
Test name
Test status
Simulation time 434632741 ps
CPU time 1.31 seconds
Started Aug 18 05:40:24 PM PDT 24
Finished Aug 18 05:40:25 PM PDT 24
Peak memory 207500 kb
Host smart-e5471a3f-99de-4de7-a44e-670e8897820c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365874724 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 405.usbdev_tx_rx_disruption.2365874724
Directory /workspace/405.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/406.usbdev_tx_rx_disruption.2135313442
Short name T2618
Test name
Test status
Simulation time 565451277 ps
CPU time 1.67 seconds
Started Aug 18 05:39:54 PM PDT 24
Finished Aug 18 05:39:56 PM PDT 24
Peak memory 207480 kb
Host smart-f970f6ac-5aeb-4253-aff6-e077f5184a1d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135313442 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 406.usbdev_tx_rx_disruption.2135313442
Directory /workspace/406.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/407.usbdev_tx_rx_disruption.587759263
Short name T1646
Test name
Test status
Simulation time 607082114 ps
CPU time 1.67 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207464 kb
Host smart-54c99584-81e6-4257-9fa4-f3c039a1e725
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587759263 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 407.usbdev_tx_rx_disruption.587759263
Directory /workspace/407.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/408.usbdev_tx_rx_disruption.197385953
Short name T3380
Test name
Test status
Simulation time 537268023 ps
CPU time 1.63 seconds
Started Aug 18 05:40:06 PM PDT 24
Finished Aug 18 05:40:08 PM PDT 24
Peak memory 207572 kb
Host smart-360d4769-e9bd-4da3-9ce4-0051968a61c3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197385953 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 408.usbdev_tx_rx_disruption.197385953
Directory /workspace/408.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/409.usbdev_tx_rx_disruption.570478737
Short name T875
Test name
Test status
Simulation time 428470032 ps
CPU time 1.39 seconds
Started Aug 18 05:40:04 PM PDT 24
Finished Aug 18 05:40:06 PM PDT 24
Peak memory 207500 kb
Host smart-885c8fa2-9900-4a98-ba61-bd26c9b13336
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570478737 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 409.usbdev_tx_rx_disruption.570478737
Directory /workspace/409.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.2950728424
Short name T3611
Test name
Test status
Simulation time 53756668 ps
CPU time 0.68 seconds
Started Aug 18 05:37:52 PM PDT 24
Finished Aug 18 05:37:53 PM PDT 24
Peak memory 207376 kb
Host smart-59368617-1b49-406c-965c-5522d46ac7e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2950728424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.2950728424
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3698518455
Short name T3033
Test name
Test status
Simulation time 3878274706 ps
CPU time 6.07 seconds
Started Aug 18 05:37:48 PM PDT 24
Finished Aug 18 05:37:54 PM PDT 24
Peak memory 215992 kb
Host smart-1cceb70f-18c0-4a40-8703-c531718cc482
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698518455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.3698518455
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1960550253
Short name T1218
Test name
Test status
Simulation time 16075496180 ps
CPU time 24.22 seconds
Started Aug 18 05:37:51 PM PDT 24
Finished Aug 18 05:38:16 PM PDT 24
Peak memory 216000 kb
Host smart-44ef4c62-6998-4a75-9124-316b4887d49b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960550253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1960550253
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.1911318444
Short name T10
Test name
Test status
Simulation time 24043156052 ps
CPU time 28.57 seconds
Started Aug 18 05:37:53 PM PDT 24
Finished Aug 18 05:38:21 PM PDT 24
Peak memory 216016 kb
Host smart-29493424-339b-4f6c-9d05-888f2bacfd69
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911318444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.1911318444
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.771316857
Short name T2479
Test name
Test status
Simulation time 157687814 ps
CPU time 0.86 seconds
Started Aug 18 05:37:49 PM PDT 24
Finished Aug 18 05:37:50 PM PDT 24
Peak memory 207452 kb
Host smart-090f7146-d6ba-4746-b358-b6bc42ff149c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77131
6857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.771316857
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.25631941
Short name T1873
Test name
Test status
Simulation time 153928186 ps
CPU time 0.93 seconds
Started Aug 18 05:38:06 PM PDT 24
Finished Aug 18 05:38:07 PM PDT 24
Peak memory 207436 kb
Host smart-02bfa309-cdc7-431b-9b4e-de701e5eef4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25631
941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.25631941
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.151227004
Short name T2302
Test name
Test status
Simulation time 448747480 ps
CPU time 1.49 seconds
Started Aug 18 05:37:47 PM PDT 24
Finished Aug 18 05:37:49 PM PDT 24
Peak memory 207544 kb
Host smart-a7a657bc-b346-466b-8c10-711eca85b97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15122
7004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.151227004
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1543606591
Short name T2460
Test name
Test status
Simulation time 1053500072 ps
CPU time 2.78 seconds
Started Aug 18 05:37:48 PM PDT 24
Finished Aug 18 05:37:51 PM PDT 24
Peak memory 207596 kb
Host smart-9c8ec1ff-5460-4f80-a91a-6602787d6f47
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1543606591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1543606591
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.491588065
Short name T1843
Test name
Test status
Simulation time 23246181068 ps
CPU time 40.65 seconds
Started Aug 18 05:37:52 PM PDT 24
Finished Aug 18 05:38:32 PM PDT 24
Peak memory 207796 kb
Host smart-cf83b0b9-d7de-49b8-96af-93d1c5a98037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49158
8065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.491588065
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.2917686091
Short name T3439
Test name
Test status
Simulation time 7709513142 ps
CPU time 52.12 seconds
Started Aug 18 05:37:52 PM PDT 24
Finished Aug 18 05:38:45 PM PDT 24
Peak memory 207744 kb
Host smart-e4185f8f-107f-46cc-8f02-83e031a1ce1d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917686091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.2917686091
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.2994335607
Short name T3036
Test name
Test status
Simulation time 755238300 ps
CPU time 2 seconds
Started Aug 18 05:37:56 PM PDT 24
Finished Aug 18 05:37:58 PM PDT 24
Peak memory 207532 kb
Host smart-107407bd-42c2-4fd3-aa4d-98ecc0513941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29943
35607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.2994335607
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.3483255253
Short name T3248
Test name
Test status
Simulation time 151690968 ps
CPU time 0.85 seconds
Started Aug 18 05:38:05 PM PDT 24
Finished Aug 18 05:38:06 PM PDT 24
Peak memory 207548 kb
Host smart-6d62714e-9684-4880-84d7-411e4a602ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34832
55253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.3483255253
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3082075069
Short name T2213
Test name
Test status
Simulation time 38636280 ps
CPU time 0.72 seconds
Started Aug 18 05:37:54 PM PDT 24
Finished Aug 18 05:37:55 PM PDT 24
Peak memory 207488 kb
Host smart-6177a2c0-2b0a-4b4f-95a8-5b2f5f2cde28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30820
75069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3082075069
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.1642805940
Short name T1965
Test name
Test status
Simulation time 1025224179 ps
CPU time 2.48 seconds
Started Aug 18 05:37:55 PM PDT 24
Finished Aug 18 05:37:57 PM PDT 24
Peak memory 207748 kb
Host smart-63a3798c-acca-4065-91c7-517e7eb07934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16428
05940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.1642805940
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_types.3836308271
Short name T460
Test name
Test status
Simulation time 260764305 ps
CPU time 1.11 seconds
Started Aug 18 05:37:58 PM PDT 24
Finished Aug 18 05:37:59 PM PDT 24
Peak memory 207672 kb
Host smart-8cc8efc7-fcf1-4912-9906-13c7eb7e2233
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3836308271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_types.3836308271
Directory /workspace/41.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2834911491
Short name T971
Test name
Test status
Simulation time 243175905 ps
CPU time 1.6 seconds
Started Aug 18 05:37:46 PM PDT 24
Finished Aug 18 05:37:48 PM PDT 24
Peak memory 207664 kb
Host smart-8d42b395-bdf7-44b3-8544-6d425d75b7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28349
11491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2834911491
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.2728906679
Short name T3552
Test name
Test status
Simulation time 172888172 ps
CPU time 1 seconds
Started Aug 18 05:37:47 PM PDT 24
Finished Aug 18 05:37:48 PM PDT 24
Peak memory 215764 kb
Host smart-5083facc-72a1-4d57-aaba-13b77e3f6553
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2728906679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.2728906679
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2383909119
Short name T1951
Test name
Test status
Simulation time 134881802 ps
CPU time 0.76 seconds
Started Aug 18 05:37:51 PM PDT 24
Finished Aug 18 05:37:52 PM PDT 24
Peak memory 207448 kb
Host smart-89b6237b-3fc4-42dd-940e-c11505a59682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23839
09119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2383909119
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2108585860
Short name T731
Test name
Test status
Simulation time 211258944 ps
CPU time 0.94 seconds
Started Aug 18 05:37:53 PM PDT 24
Finished Aug 18 05:37:54 PM PDT 24
Peak memory 207508 kb
Host smart-48e7f0fe-2969-4466-9e5a-9ecd36a4e135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21085
85860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2108585860
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.1916345347
Short name T716
Test name
Test status
Simulation time 4025440320 ps
CPU time 117.89 seconds
Started Aug 18 05:37:52 PM PDT 24
Finished Aug 18 05:39:50 PM PDT 24
Peak memory 215916 kb
Host smart-cde58dde-e3ee-4b25-a5ab-7ce2ea2b87ee
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1916345347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.1916345347
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.1503254467
Short name T2385
Test name
Test status
Simulation time 6353666053 ps
CPU time 44.3 seconds
Started Aug 18 05:37:49 PM PDT 24
Finished Aug 18 05:38:33 PM PDT 24
Peak memory 207768 kb
Host smart-c90503b7-133c-474c-84ed-22e95c9347d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1503254467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.1503254467
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.3138204351
Short name T901
Test name
Test status
Simulation time 282441445 ps
CPU time 1.11 seconds
Started Aug 18 05:37:54 PM PDT 24
Finished Aug 18 05:37:55 PM PDT 24
Peak memory 207568 kb
Host smart-46554748-b255-4ea1-9b89-b76acb00bd2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31382
04351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.3138204351
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3308308134
Short name T2287
Test name
Test status
Simulation time 24831716074 ps
CPU time 41.18 seconds
Started Aug 18 05:37:53 PM PDT 24
Finished Aug 18 05:38:35 PM PDT 24
Peak memory 216552 kb
Host smart-cc5a23cd-a4a2-4599-90d3-427bf2f5aa85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33083
08134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3308308134
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.3930066737
Short name T101
Test name
Test status
Simulation time 4722894770 ps
CPU time 6.09 seconds
Started Aug 18 05:38:01 PM PDT 24
Finished Aug 18 05:38:17 PM PDT 24
Peak memory 215872 kb
Host smart-03299afd-5f80-4015-939d-fd8980d9d09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39300
66737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.3930066737
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.383035252
Short name T2524
Test name
Test status
Simulation time 4534877411 ps
CPU time 39.26 seconds
Started Aug 18 05:37:47 PM PDT 24
Finished Aug 18 05:38:26 PM PDT 24
Peak memory 215960 kb
Host smart-dd819b91-2953-4e3b-9462-bd82aee69030
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=383035252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.383035252
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3590049240
Short name T1391
Test name
Test status
Simulation time 2609496836 ps
CPU time 73.29 seconds
Started Aug 18 05:37:51 PM PDT 24
Finished Aug 18 05:39:05 PM PDT 24
Peak memory 217328 kb
Host smart-fd93bcaa-b3f4-4c7c-8b8e-09e3672730b6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3590049240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3590049240
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.3699110259
Short name T3004
Test name
Test status
Simulation time 280283496 ps
CPU time 0.98 seconds
Started Aug 18 05:37:52 PM PDT 24
Finished Aug 18 05:37:53 PM PDT 24
Peak memory 207488 kb
Host smart-ee4e899c-2dae-4d56-964f-de777bf80c00
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3699110259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.3699110259
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1432179604
Short name T257
Test name
Test status
Simulation time 188451263 ps
CPU time 0.94 seconds
Started Aug 18 05:37:48 PM PDT 24
Finished Aug 18 05:37:49 PM PDT 24
Peak memory 207384 kb
Host smart-7be23f2c-6cbc-4fbe-bed7-93e1199dba47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14321
79604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1432179604
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.2339628646
Short name T2712
Test name
Test status
Simulation time 2523952785 ps
CPU time 18.6 seconds
Started Aug 18 05:37:46 PM PDT 24
Finished Aug 18 05:38:04 PM PDT 24
Peak memory 215928 kb
Host smart-883e5464-6ddf-4038-b99d-0eb00ffdfa10
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2339628646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.2339628646
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.87724313
Short name T2002
Test name
Test status
Simulation time 247345359 ps
CPU time 0.94 seconds
Started Aug 18 05:38:01 PM PDT 24
Finished Aug 18 05:38:02 PM PDT 24
Peak memory 207492 kb
Host smart-28a84e3c-a6ca-4e25-a415-f4edd2d455f3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=87724313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.87724313
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1836354067
Short name T3116
Test name
Test status
Simulation time 144395573 ps
CPU time 0.87 seconds
Started Aug 18 05:38:01 PM PDT 24
Finished Aug 18 05:38:02 PM PDT 24
Peak memory 207368 kb
Host smart-a16e1cbd-9465-45d9-ac1a-4aba2055f041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18363
54067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1836354067
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.681702535
Short name T144
Test name
Test status
Simulation time 204863211 ps
CPU time 0.95 seconds
Started Aug 18 05:38:00 PM PDT 24
Finished Aug 18 05:38:01 PM PDT 24
Peak memory 207464 kb
Host smart-bae23e08-f557-4094-9e38-6037da85de8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68170
2535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.681702535
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2171389015
Short name T1688
Test name
Test status
Simulation time 172748472 ps
CPU time 0.95 seconds
Started Aug 18 05:37:48 PM PDT 24
Finished Aug 18 05:37:49 PM PDT 24
Peak memory 207480 kb
Host smart-dc9346cf-964f-476c-9d1e-107916b8ad35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21713
89015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2171389015
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1473163517
Short name T1855
Test name
Test status
Simulation time 151395721 ps
CPU time 0.86 seconds
Started Aug 18 05:37:54 PM PDT 24
Finished Aug 18 05:37:55 PM PDT 24
Peak memory 207520 kb
Host smart-da2363a5-d496-4012-89c2-29ad9395e15c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14731
63517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1473163517
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.459488138
Short name T791
Test name
Test status
Simulation time 148625195 ps
CPU time 0.82 seconds
Started Aug 18 05:37:52 PM PDT 24
Finished Aug 18 05:37:53 PM PDT 24
Peak memory 207368 kb
Host smart-d70b0259-3afc-4e2b-ad0a-5fab7f06eac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45948
8138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.459488138
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.35018006
Short name T1464
Test name
Test status
Simulation time 156653431 ps
CPU time 0.83 seconds
Started Aug 18 05:37:49 PM PDT 24
Finished Aug 18 05:37:49 PM PDT 24
Peak memory 207536 kb
Host smart-860bb29b-1438-453d-944e-b8c4a1bcaef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35018
006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.35018006
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.522339216
Short name T231
Test name
Test status
Simulation time 191687391 ps
CPU time 0.95 seconds
Started Aug 18 05:37:50 PM PDT 24
Finished Aug 18 05:37:51 PM PDT 24
Peak memory 207532 kb
Host smart-1beb0e8f-f065-447e-b6a0-a07fa026c747
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=522339216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.522339216
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1333240107
Short name T23
Test name
Test status
Simulation time 151982870 ps
CPU time 0.87 seconds
Started Aug 18 05:37:50 PM PDT 24
Finished Aug 18 05:37:51 PM PDT 24
Peak memory 207360 kb
Host smart-c4ef1989-cd34-4d53-b871-9c14976eb718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13332
40107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1333240107
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2592643991
Short name T1365
Test name
Test status
Simulation time 34811800 ps
CPU time 0.67 seconds
Started Aug 18 05:37:53 PM PDT 24
Finished Aug 18 05:37:54 PM PDT 24
Peak memory 207536 kb
Host smart-bc177677-5197-4b6c-9a20-ee6a17a454b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25926
43991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2592643991
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.506877718
Short name T1345
Test name
Test status
Simulation time 15729741523 ps
CPU time 38.66 seconds
Started Aug 18 05:37:58 PM PDT 24
Finished Aug 18 05:38:37 PM PDT 24
Peak memory 215896 kb
Host smart-83587ea1-9db4-44e3-a178-3183851a2b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50687
7718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.506877718
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.3730503544
Short name T2024
Test name
Test status
Simulation time 241413882 ps
CPU time 0.95 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 207568 kb
Host smart-48609440-c84a-4dfb-aa68-70dc8f706c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37305
03544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.3730503544
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2892364291
Short name T3200
Test name
Test status
Simulation time 186783078 ps
CPU time 0.9 seconds
Started Aug 18 05:37:52 PM PDT 24
Finished Aug 18 05:37:53 PM PDT 24
Peak memory 207372 kb
Host smart-25f6c165-96a9-4bfd-89cf-563451782824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28923
64291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2892364291
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.1225949372
Short name T853
Test name
Test status
Simulation time 183827256 ps
CPU time 1.01 seconds
Started Aug 18 05:37:54 PM PDT 24
Finished Aug 18 05:37:55 PM PDT 24
Peak memory 207496 kb
Host smart-15c97bbf-f245-4aa0-ae71-dbc28051287f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12259
49372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1225949372
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.3158834558
Short name T2492
Test name
Test status
Simulation time 182770165 ps
CPU time 0.95 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:04 PM PDT 24
Peak memory 207476 kb
Host smart-2ea06598-9423-446d-a951-d9f01ac97bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31588
34558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3158834558
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.855175724
Short name T3425
Test name
Test status
Simulation time 166261513 ps
CPU time 0.9 seconds
Started Aug 18 05:37:55 PM PDT 24
Finished Aug 18 05:37:56 PM PDT 24
Peak memory 207488 kb
Host smart-48dfe26d-8019-41e3-a318-d057fb9fd7b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85517
5724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.855175724
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_rx_full.3533416656
Short name T40
Test name
Test status
Simulation time 269029983 ps
CPU time 1.14 seconds
Started Aug 18 05:37:56 PM PDT 24
Finished Aug 18 05:37:58 PM PDT 24
Peak memory 207500 kb
Host smart-6c35b8b2-20f5-4d1c-88c4-1ef32b6a355f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35334
16656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_full.3533416656
Directory /workspace/41.usbdev_rx_full/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3258434093
Short name T3102
Test name
Test status
Simulation time 211266138 ps
CPU time 0.86 seconds
Started Aug 18 05:37:48 PM PDT 24
Finished Aug 18 05:37:49 PM PDT 24
Peak memory 207416 kb
Host smart-d8b0a6fe-3ddf-456c-8f5f-e635240394ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32584
34093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3258434093
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2094378273
Short name T845
Test name
Test status
Simulation time 203034177 ps
CPU time 1.01 seconds
Started Aug 18 05:37:38 PM PDT 24
Finished Aug 18 05:37:40 PM PDT 24
Peak memory 207472 kb
Host smart-d29cf80e-f222-4b3d-b81c-28f363646884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20943
78273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2094378273
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3123605861
Short name T2619
Test name
Test status
Simulation time 255632185 ps
CPU time 1.05 seconds
Started Aug 18 05:37:54 PM PDT 24
Finished Aug 18 05:37:56 PM PDT 24
Peak memory 207288 kb
Host smart-060e7d27-3e3a-4d3c-9c49-ee4773e57cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31236
05861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3123605861
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3746438980
Short name T1060
Test name
Test status
Simulation time 2260531498 ps
CPU time 63.34 seconds
Started Aug 18 05:37:50 PM PDT 24
Finished Aug 18 05:38:54 PM PDT 24
Peak memory 217316 kb
Host smart-1c00283c-3e69-4c08-919c-2274af972260
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3746438980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3746438980
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3679072510
Short name T2208
Test name
Test status
Simulation time 229526987 ps
CPU time 0.9 seconds
Started Aug 18 05:38:05 PM PDT 24
Finished Aug 18 05:38:06 PM PDT 24
Peak memory 207492 kb
Host smart-2761297c-3ee8-45f7-bfc1-35531d5a1f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36790
72510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3679072510
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2318463400
Short name T1587
Test name
Test status
Simulation time 219371390 ps
CPU time 1 seconds
Started Aug 18 05:37:58 PM PDT 24
Finished Aug 18 05:37:59 PM PDT 24
Peak memory 207580 kb
Host smart-9f86d8bc-678f-4527-8f94-5b479fd3a3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23184
63400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2318463400
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.1084619117
Short name T20
Test name
Test status
Simulation time 693442721 ps
CPU time 1.94 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 207444 kb
Host smart-00897872-471f-47f2-b679-743a02a74319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10846
19117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.1084619117
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.1691154275
Short name T553
Test name
Test status
Simulation time 2508276927 ps
CPU time 25.25 seconds
Started Aug 18 05:37:44 PM PDT 24
Finished Aug 18 05:38:09 PM PDT 24
Peak memory 217732 kb
Host smart-5678fbf5-d826-4318-bc9e-5b72dadecfd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16911
54275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.1691154275
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.1000688614
Short name T2016
Test name
Test status
Simulation time 459163417 ps
CPU time 7.62 seconds
Started Aug 18 05:38:02 PM PDT 24
Finished Aug 18 05:38:10 PM PDT 24
Peak memory 207656 kb
Host smart-99a81902-623b-4b58-8f7e-2a9ef1118447
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000688614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.1000688614
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_tx_rx_disruption.3565258443
Short name T1107
Test name
Test status
Simulation time 445419759 ps
CPU time 1.48 seconds
Started Aug 18 05:37:56 PM PDT 24
Finished Aug 18 05:37:58 PM PDT 24
Peak memory 207588 kb
Host smart-2a28b0d2-976e-487b-83f6-17b030a77a7f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565258443 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.usbdev_tx_rx_disruption.3565258443
Directory /workspace/41.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/410.usbdev_tx_rx_disruption.926475483
Short name T787
Test name
Test status
Simulation time 443288158 ps
CPU time 1.51 seconds
Started Aug 18 05:40:12 PM PDT 24
Finished Aug 18 05:40:13 PM PDT 24
Peak memory 207500 kb
Host smart-65f1361f-930b-4308-b571-7d7672e98698
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926475483 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 410.usbdev_tx_rx_disruption.926475483
Directory /workspace/410.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/411.usbdev_tx_rx_disruption.3281719710
Short name T3511
Test name
Test status
Simulation time 523491182 ps
CPU time 1.55 seconds
Started Aug 18 05:39:53 PM PDT 24
Finished Aug 18 05:39:55 PM PDT 24
Peak memory 207472 kb
Host smart-57e57536-28a2-43bc-9a78-b6429f3a3970
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281719710 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 411.usbdev_tx_rx_disruption.3281719710
Directory /workspace/411.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/412.usbdev_tx_rx_disruption.598350017
Short name T1301
Test name
Test status
Simulation time 507742141 ps
CPU time 1.56 seconds
Started Aug 18 05:39:56 PM PDT 24
Finished Aug 18 05:39:57 PM PDT 24
Peak memory 207500 kb
Host smart-345529b2-bde6-46d9-afca-7ec00b92979e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598350017 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 412.usbdev_tx_rx_disruption.598350017
Directory /workspace/412.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/413.usbdev_tx_rx_disruption.4180929348
Short name T954
Test name
Test status
Simulation time 518646123 ps
CPU time 1.63 seconds
Started Aug 18 05:39:55 PM PDT 24
Finished Aug 18 05:39:57 PM PDT 24
Peak memory 207528 kb
Host smart-c232d2d9-924d-4f48-88bc-40e92b3456a4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180929348 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 413.usbdev_tx_rx_disruption.4180929348
Directory /workspace/413.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/414.usbdev_tx_rx_disruption.1902022917
Short name T1820
Test name
Test status
Simulation time 539369798 ps
CPU time 1.54 seconds
Started Aug 18 05:40:27 PM PDT 24
Finished Aug 18 05:40:29 PM PDT 24
Peak memory 207500 kb
Host smart-26440896-5fce-4963-ac7f-e7af05b4678a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902022917 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 414.usbdev_tx_rx_disruption.1902022917
Directory /workspace/414.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/415.usbdev_tx_rx_disruption.1059011553
Short name T1868
Test name
Test status
Simulation time 524326199 ps
CPU time 1.55 seconds
Started Aug 18 05:40:23 PM PDT 24
Finished Aug 18 05:40:34 PM PDT 24
Peak memory 207508 kb
Host smart-4a6083e5-a3e4-4bc7-94b1-4847d1d3ff16
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059011553 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 415.usbdev_tx_rx_disruption.1059011553
Directory /workspace/415.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/416.usbdev_tx_rx_disruption.3263621945
Short name T2565
Test name
Test status
Simulation time 574934493 ps
CPU time 1.72 seconds
Started Aug 18 05:40:08 PM PDT 24
Finished Aug 18 05:40:10 PM PDT 24
Peak memory 207564 kb
Host smart-d788442b-7651-416e-ba8b-071bf177b15c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263621945 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 416.usbdev_tx_rx_disruption.3263621945
Directory /workspace/416.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/417.usbdev_tx_rx_disruption.3304249869
Short name T2602
Test name
Test status
Simulation time 644184379 ps
CPU time 1.85 seconds
Started Aug 18 05:40:07 PM PDT 24
Finished Aug 18 05:40:09 PM PDT 24
Peak memory 207588 kb
Host smart-283b9279-a353-4721-9e3a-59abd5a41f0a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304249869 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 417.usbdev_tx_rx_disruption.3304249869
Directory /workspace/417.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/418.usbdev_tx_rx_disruption.3963408460
Short name T2100
Test name
Test status
Simulation time 473112715 ps
CPU time 1.43 seconds
Started Aug 18 05:40:12 PM PDT 24
Finished Aug 18 05:40:14 PM PDT 24
Peak memory 207564 kb
Host smart-c5fcc0b4-ecb3-44fb-a7ec-76e1f2ee5cd7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963408460 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 418.usbdev_tx_rx_disruption.3963408460
Directory /workspace/418.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/419.usbdev_tx_rx_disruption.3954755225
Short name T260
Test name
Test status
Simulation time 620841380 ps
CPU time 1.64 seconds
Started Aug 18 05:40:03 PM PDT 24
Finished Aug 18 05:40:04 PM PDT 24
Peak memory 207560 kb
Host smart-e55228fa-ae1f-4db0-9c9d-dfd4a106e2c7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954755225 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 419.usbdev_tx_rx_disruption.3954755225
Directory /workspace/419.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.3493653865
Short name T1174
Test name
Test status
Simulation time 50594999 ps
CPU time 0.65 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:04 PM PDT 24
Peak memory 207464 kb
Host smart-f7df14ae-6ee9-4f11-ac02-490214eb4587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3493653865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.3493653865
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.4025819329
Short name T237
Test name
Test status
Simulation time 6084812168 ps
CPU time 8.85 seconds
Started Aug 18 05:37:53 PM PDT 24
Finished Aug 18 05:38:02 PM PDT 24
Peak memory 216140 kb
Host smart-af4477eb-cce5-472d-85bd-b23776662c5b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025819329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.4025819329
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3793322910
Short name T13
Test name
Test status
Simulation time 14353912432 ps
CPU time 15.97 seconds
Started Aug 18 05:37:56 PM PDT 24
Finished Aug 18 05:38:12 PM PDT 24
Peak memory 215992 kb
Host smart-c40c6e2b-2939-4b04-906b-b2455caf48b3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793322910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3793322910
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1698375565
Short name T3300
Test name
Test status
Simulation time 25312069985 ps
CPU time 33.36 seconds
Started Aug 18 05:37:55 PM PDT 24
Finished Aug 18 05:38:29 PM PDT 24
Peak memory 215960 kb
Host smart-a4309367-70e6-420d-b186-c32e555f2cb8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698375565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.1698375565
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2838853581
Short name T2622
Test name
Test status
Simulation time 225061897 ps
CPU time 1.02 seconds
Started Aug 18 05:37:57 PM PDT 24
Finished Aug 18 05:37:58 PM PDT 24
Peak memory 207444 kb
Host smart-2b680dbe-01ea-47d3-8d93-15ce4c898dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28388
53581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2838853581
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.4085232764
Short name T2720
Test name
Test status
Simulation time 188900676 ps
CPU time 0.91 seconds
Started Aug 18 05:38:00 PM PDT 24
Finished Aug 18 05:38:01 PM PDT 24
Peak memory 207552 kb
Host smart-b0bb3161-4b63-4d60-a7ac-ce0fc6ca5ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40852
32764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.4085232764
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.738591210
Short name T2517
Test name
Test status
Simulation time 234761741 ps
CPU time 0.98 seconds
Started Aug 18 05:37:56 PM PDT 24
Finished Aug 18 05:37:57 PM PDT 24
Peak memory 207584 kb
Host smart-7941e781-9ac8-4121-af94-abefcc50614a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73859
1210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.738591210
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1603792666
Short name T3039
Test name
Test status
Simulation time 755353699 ps
CPU time 2.25 seconds
Started Aug 18 05:37:55 PM PDT 24
Finished Aug 18 05:37:58 PM PDT 24
Peak memory 207716 kb
Host smart-fa8360d2-9a32-4899-8f2c-eb000d3d8a18
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1603792666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1603792666
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.1725311208
Short name T1522
Test name
Test status
Simulation time 781583148 ps
CPU time 15.45 seconds
Started Aug 18 05:37:54 PM PDT 24
Finished Aug 18 05:38:10 PM PDT 24
Peak memory 207712 kb
Host smart-a65cc260-d2a6-429a-a858-0fcf1a319423
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725311208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.1725311208
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.1929483907
Short name T530
Test name
Test status
Simulation time 805281593 ps
CPU time 1.94 seconds
Started Aug 18 05:38:12 PM PDT 24
Finished Aug 18 05:38:14 PM PDT 24
Peak memory 207412 kb
Host smart-1666c710-592b-4d29-8d2c-870283890d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19294
83907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.1929483907
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3407539136
Short name T894
Test name
Test status
Simulation time 146133431 ps
CPU time 0.82 seconds
Started Aug 18 05:37:50 PM PDT 24
Finished Aug 18 05:37:51 PM PDT 24
Peak memory 207540 kb
Host smart-22a805f2-cdaa-4e94-b222-85f392fa97c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34075
39136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3407539136
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.782310061
Short name T2719
Test name
Test status
Simulation time 65471914 ps
CPU time 0.75 seconds
Started Aug 18 05:37:54 PM PDT 24
Finished Aug 18 05:37:54 PM PDT 24
Peak memory 207448 kb
Host smart-ada8280e-cac9-467d-bf7a-1df571f5dc41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78231
0061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.782310061
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3193172974
Short name T729
Test name
Test status
Simulation time 676140102 ps
CPU time 2.03 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 207680 kb
Host smart-d84594e7-b227-437d-b558-9d70601b6020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31931
72974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3193172974
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_types.449517345
Short name T383
Test name
Test status
Simulation time 821469056 ps
CPU time 1.81 seconds
Started Aug 18 05:38:09 PM PDT 24
Finished Aug 18 05:38:11 PM PDT 24
Peak memory 207540 kb
Host smart-b8e87411-75a0-4661-aa79-e5443fc453e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=449517345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_types.449517345
Directory /workspace/42.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1724061958
Short name T2459
Test name
Test status
Simulation time 251090780 ps
CPU time 1.82 seconds
Started Aug 18 05:38:08 PM PDT 24
Finished Aug 18 05:38:10 PM PDT 24
Peak memory 207624 kb
Host smart-d5e8ae18-87d8-49e5-892a-c133a27ceb36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17240
61958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1724061958
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3060939849
Short name T3585
Test name
Test status
Simulation time 203431594 ps
CPU time 1.11 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 217056 kb
Host smart-704efdfa-5104-4adf-ba11-95d1d4c098e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3060939849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3060939849
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3900325931
Short name T2631
Test name
Test status
Simulation time 148865587 ps
CPU time 0.83 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207408 kb
Host smart-150f0198-8ebf-422b-abcd-eb8947b6c20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39003
25931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3900325931
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1362949001
Short name T696
Test name
Test status
Simulation time 278445125 ps
CPU time 1.07 seconds
Started Aug 18 05:37:52 PM PDT 24
Finished Aug 18 05:37:53 PM PDT 24
Peak memory 207412 kb
Host smart-9105958b-c726-4007-ba83-8ddaa32e6d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13629
49001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1362949001
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.105693003
Short name T2596
Test name
Test status
Simulation time 4575672488 ps
CPU time 33.74 seconds
Started Aug 18 05:37:52 PM PDT 24
Finished Aug 18 05:38:26 PM PDT 24
Peak memory 215928 kb
Host smart-a2dc7ce8-9ab8-4c0c-945e-05c4f7b73f07
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=105693003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.105693003
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.2977841958
Short name T2683
Test name
Test status
Simulation time 9435271324 ps
CPU time 61.65 seconds
Started Aug 18 05:38:00 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207764 kb
Host smart-94da5a3b-cee7-40b9-a9f2-0ab7b419e823
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2977841958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.2977841958
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.2703022470
Short name T1898
Test name
Test status
Simulation time 176937158 ps
CPU time 0.84 seconds
Started Aug 18 05:37:54 PM PDT 24
Finished Aug 18 05:37:55 PM PDT 24
Peak memory 207584 kb
Host smart-5f42c54a-06a3-4784-87e4-2c3ea37acf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27030
22470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.2703022470
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1554879155
Short name T2782
Test name
Test status
Simulation time 29845356887 ps
CPU time 44.08 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:47 PM PDT 24
Peak memory 207740 kb
Host smart-d2174711-f854-42d7-a732-d869754c1730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15548
79155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1554879155
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.833750170
Short name T1548
Test name
Test status
Simulation time 5997218000 ps
CPU time 8.15 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:12 PM PDT 24
Peak memory 215920 kb
Host smart-e03e71a1-54d8-485e-b8da-df6969011da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83375
0170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.833750170
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.1566449534
Short name T3407
Test name
Test status
Simulation time 4030513394 ps
CPU time 114.7 seconds
Started Aug 18 05:37:53 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 224172 kb
Host smart-1c88081b-3aeb-4ffb-b358-1c7c4973e6b4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1566449534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.1566449534
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.537251613
Short name T2106
Test name
Test status
Simulation time 1565882337 ps
CPU time 14.79 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:19 PM PDT 24
Peak memory 216552 kb
Host smart-0db4d967-65c1-44df-b1a3-b1c8960ac248
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=537251613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.537251613
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.11005165
Short name T2394
Test name
Test status
Simulation time 239538973 ps
CPU time 0.98 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:04 PM PDT 24
Peak memory 207456 kb
Host smart-719f14ca-b0cb-4c56-802c-0bc08d89dca9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=11005165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.11005165
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1228525737
Short name T733
Test name
Test status
Simulation time 186981399 ps
CPU time 0.95 seconds
Started Aug 18 05:37:50 PM PDT 24
Finished Aug 18 05:37:51 PM PDT 24
Peak memory 207504 kb
Host smart-1ed0d5b8-8bdc-421c-8091-7c9004871266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12285
25737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1228525737
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3536406319
Short name T3536
Test name
Test status
Simulation time 2315883583 ps
CPU time 18.85 seconds
Started Aug 18 05:38:00 PM PDT 24
Finished Aug 18 05:38:19 PM PDT 24
Peak memory 215920 kb
Host smart-d79ee981-457c-4311-a620-ae20a0b5a917
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3536406319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3536406319
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.499857708
Short name T979
Test name
Test status
Simulation time 155170657 ps
CPU time 0.89 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:04 PM PDT 24
Peak memory 207456 kb
Host smart-a293eba9-a965-4224-81d4-5bf655af2b95
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=499857708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.499857708
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.275825658
Short name T3239
Test name
Test status
Simulation time 146111594 ps
CPU time 0.85 seconds
Started Aug 18 05:37:57 PM PDT 24
Finished Aug 18 05:37:57 PM PDT 24
Peak memory 207528 kb
Host smart-152f5c62-676a-4818-8fda-31f633ca721f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27582
5658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.275825658
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2037930474
Short name T2381
Test name
Test status
Simulation time 228147648 ps
CPU time 0.98 seconds
Started Aug 18 05:38:05 PM PDT 24
Finished Aug 18 05:38:06 PM PDT 24
Peak memory 207484 kb
Host smart-eecf8902-83bf-4ef6-8d17-637b0d45608f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20379
30474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2037930474
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.1638945732
Short name T3507
Test name
Test status
Simulation time 180831056 ps
CPU time 1 seconds
Started Aug 18 05:37:58 PM PDT 24
Finished Aug 18 05:37:59 PM PDT 24
Peak memory 207472 kb
Host smart-7b02e23a-d01d-44f7-8f3d-d95f4c57d475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16389
45732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.1638945732
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3825153157
Short name T1067
Test name
Test status
Simulation time 203804131 ps
CPU time 0.95 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:04 PM PDT 24
Peak memory 207480 kb
Host smart-bf0325c9-d6be-441c-a941-783982c708a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38251
53157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3825153157
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3691702302
Short name T2836
Test name
Test status
Simulation time 183521123 ps
CPU time 0.92 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 207524 kb
Host smart-e540f184-5bc9-456b-ad41-08e78dfd6cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36917
02302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3691702302
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.873003205
Short name T798
Test name
Test status
Simulation time 153232154 ps
CPU time 0.82 seconds
Started Aug 18 05:38:00 PM PDT 24
Finished Aug 18 05:38:01 PM PDT 24
Peak memory 207564 kb
Host smart-8199103e-9514-49bb-b003-11fb5a94f118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87300
3205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.873003205
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.1022653782
Short name T3582
Test name
Test status
Simulation time 191557685 ps
CPU time 1.01 seconds
Started Aug 18 05:37:54 PM PDT 24
Finished Aug 18 05:37:55 PM PDT 24
Peak memory 207592 kb
Host smart-1b9bdbe2-c21d-479f-8ed2-850fd210b5ea
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1022653782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.1022653782
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.862790305
Short name T3097
Test name
Test status
Simulation time 159457884 ps
CPU time 0.84 seconds
Started Aug 18 05:37:54 PM PDT 24
Finished Aug 18 05:37:55 PM PDT 24
Peak memory 207456 kb
Host smart-e7771120-8c5d-40d5-bb55-528446bc16f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86279
0305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.862790305
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3938024347
Short name T2579
Test name
Test status
Simulation time 32892816 ps
CPU time 0.7 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:04 PM PDT 24
Peak memory 207496 kb
Host smart-bec159d7-211a-4adf-a395-3ccab6d0ab37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39380
24347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3938024347
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.4041440663
Short name T1575
Test name
Test status
Simulation time 16746607519 ps
CPU time 45.13 seconds
Started Aug 18 05:37:52 PM PDT 24
Finished Aug 18 05:38:38 PM PDT 24
Peak memory 215944 kb
Host smart-dc4a4347-a4a3-4965-bb0f-806f0fce726e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40414
40663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.4041440663
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.219797733
Short name T834
Test name
Test status
Simulation time 201267919 ps
CPU time 0.96 seconds
Started Aug 18 05:37:50 PM PDT 24
Finished Aug 18 05:37:51 PM PDT 24
Peak memory 207708 kb
Host smart-55e357ad-7fe5-4444-9691-348d2a2c2508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21979
7733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.219797733
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.6598433
Short name T1926
Test name
Test status
Simulation time 241643624 ps
CPU time 1.06 seconds
Started Aug 18 05:37:57 PM PDT 24
Finished Aug 18 05:37:58 PM PDT 24
Peak memory 207504 kb
Host smart-00d7f4a5-befd-4736-930a-6989955330c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65984
33 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.6598433
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.3833843046
Short name T1781
Test name
Test status
Simulation time 172546764 ps
CPU time 0.89 seconds
Started Aug 18 05:37:54 PM PDT 24
Finished Aug 18 05:37:55 PM PDT 24
Peak memory 207504 kb
Host smart-cedb2cf2-6f17-41ee-85a7-7e12a44b9a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38338
43046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.3833843046
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.4153464141
Short name T255
Test name
Test status
Simulation time 182874045 ps
CPU time 0.93 seconds
Started Aug 18 05:37:57 PM PDT 24
Finished Aug 18 05:37:58 PM PDT 24
Peak memory 207492 kb
Host smart-dc163f73-009d-4406-8532-261ba800bf38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41534
64141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.4153464141
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.2013848277
Short name T1026
Test name
Test status
Simulation time 174658030 ps
CPU time 0.9 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:04 PM PDT 24
Peak memory 207404 kb
Host smart-1a88615c-7935-47dc-ab4f-197341411bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20138
48277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2013848277
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_rx_full.269163070
Short name T3146
Test name
Test status
Simulation time 274884941 ps
CPU time 1.18 seconds
Started Aug 18 05:37:57 PM PDT 24
Finished Aug 18 05:37:59 PM PDT 24
Peak memory 207492 kb
Host smart-000f2066-ef64-403b-964e-0b9780aaba0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26916
3070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_full.269163070
Directory /workspace/42.usbdev_rx_full/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3100342587
Short name T2301
Test name
Test status
Simulation time 144488045 ps
CPU time 0.83 seconds
Started Aug 18 05:37:48 PM PDT 24
Finished Aug 18 05:37:49 PM PDT 24
Peak memory 207528 kb
Host smart-fc8c1338-5aad-4502-9b7c-a3320d74ae56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31003
42587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3100342587
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2747836846
Short name T1554
Test name
Test status
Simulation time 170562166 ps
CPU time 0.88 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 207508 kb
Host smart-69b3426e-e6b0-4570-a364-c78cbb952a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27478
36846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2747836846
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1362872018
Short name T2997
Test name
Test status
Simulation time 260737486 ps
CPU time 1.12 seconds
Started Aug 18 05:37:51 PM PDT 24
Finished Aug 18 05:37:53 PM PDT 24
Peak memory 207488 kb
Host smart-aaf09a01-073e-4538-8c0e-3c271e689af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13628
72018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1362872018
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.4291569296
Short name T2985
Test name
Test status
Simulation time 2266908446 ps
CPU time 70.03 seconds
Started Aug 18 05:37:58 PM PDT 24
Finished Aug 18 05:39:08 PM PDT 24
Peak memory 217364 kb
Host smart-75b1e560-5e31-4463-b6ed-f6761881cfc2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4291569296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.4291569296
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2688918499
Short name T1610
Test name
Test status
Simulation time 216431104 ps
CPU time 0.95 seconds
Started Aug 18 05:37:55 PM PDT 24
Finished Aug 18 05:37:56 PM PDT 24
Peak memory 207464 kb
Host smart-290cd355-e526-45c0-90d9-d03a3fd372a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26889
18499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2688918499
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3763245531
Short name T3617
Test name
Test status
Simulation time 206149667 ps
CPU time 0.94 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 207492 kb
Host smart-a5cf4003-b2c9-48fd-9fbe-f9a31a78dfc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37632
45531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3763245531
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.2903739673
Short name T882
Test name
Test status
Simulation time 531050480 ps
CPU time 1.72 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207496 kb
Host smart-47a5b96e-fe3a-4677-b1c9-785d5c901290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29037
39673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.2903739673
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.87318520
Short name T1270
Test name
Test status
Simulation time 1746442290 ps
CPU time 17.3 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:21 PM PDT 24
Peak memory 216472 kb
Host smart-c07139ac-e3f9-4f4b-911c-742b0557a1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87318
520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.87318520
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.411687022
Short name T3463
Test name
Test status
Simulation time 828434902 ps
CPU time 5.67 seconds
Started Aug 18 05:37:52 PM PDT 24
Finished Aug 18 05:37:58 PM PDT 24
Peak memory 207600 kb
Host smart-cfe24fb2-54fc-4ccd-bf63-48d263dca755
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411687022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_host
_handshake.411687022
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_tx_rx_disruption.152398540
Short name T3615
Test name
Test status
Simulation time 450678628 ps
CPU time 1.5 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:06 PM PDT 24
Peak memory 207552 kb
Host smart-2766799d-e7fe-4cb4-91e8-3c0a7ea2d9a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152398540 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.usbdev_tx_rx_disruption.152398540
Directory /workspace/42.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/420.usbdev_tx_rx_disruption.2410117157
Short name T3444
Test name
Test status
Simulation time 505067568 ps
CPU time 1.46 seconds
Started Aug 18 05:40:13 PM PDT 24
Finished Aug 18 05:40:14 PM PDT 24
Peak memory 207500 kb
Host smart-ebebe830-20ff-4bce-bd7e-de2074d4655b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410117157 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 420.usbdev_tx_rx_disruption.2410117157
Directory /workspace/420.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/421.usbdev_tx_rx_disruption.3787921792
Short name T1692
Test name
Test status
Simulation time 614605553 ps
CPU time 1.65 seconds
Started Aug 18 05:40:26 PM PDT 24
Finished Aug 18 05:40:28 PM PDT 24
Peak memory 207592 kb
Host smart-88334009-ee35-4700-832c-6c5e713700a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787921792 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 421.usbdev_tx_rx_disruption.3787921792
Directory /workspace/421.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/422.usbdev_tx_rx_disruption.783561106
Short name T693
Test name
Test status
Simulation time 518295481 ps
CPU time 1.53 seconds
Started Aug 18 05:40:02 PM PDT 24
Finished Aug 18 05:40:04 PM PDT 24
Peak memory 207548 kb
Host smart-7c6eb197-0583-4c6b-8e7f-6426027f380d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783561106 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 422.usbdev_tx_rx_disruption.783561106
Directory /workspace/422.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/423.usbdev_tx_rx_disruption.3840790189
Short name T2508
Test name
Test status
Simulation time 642817909 ps
CPU time 1.61 seconds
Started Aug 18 05:40:10 PM PDT 24
Finished Aug 18 05:40:11 PM PDT 24
Peak memory 207540 kb
Host smart-4c13a86f-9cf3-442c-af76-cae09ef1b162
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840790189 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 423.usbdev_tx_rx_disruption.3840790189
Directory /workspace/423.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/424.usbdev_tx_rx_disruption.3544053751
Short name T2484
Test name
Test status
Simulation time 549272571 ps
CPU time 1.64 seconds
Started Aug 18 05:40:10 PM PDT 24
Finished Aug 18 05:40:11 PM PDT 24
Peak memory 207496 kb
Host smart-88f87a8e-6658-4f82-9f06-cd139331a886
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544053751 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 424.usbdev_tx_rx_disruption.3544053751
Directory /workspace/424.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/425.usbdev_tx_rx_disruption.3929664493
Short name T262
Test name
Test status
Simulation time 542376148 ps
CPU time 1.72 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207524 kb
Host smart-42a72e92-420b-4cc6-8df0-157e7e897d00
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929664493 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 425.usbdev_tx_rx_disruption.3929664493
Directory /workspace/425.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/426.usbdev_tx_rx_disruption.919068736
Short name T559
Test name
Test status
Simulation time 538880547 ps
CPU time 1.75 seconds
Started Aug 18 05:40:29 PM PDT 24
Finished Aug 18 05:40:31 PM PDT 24
Peak memory 207584 kb
Host smart-2b6cb073-30da-4a40-9d9d-cbe945c6d1b2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919068736 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 426.usbdev_tx_rx_disruption.919068736
Directory /workspace/426.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/427.usbdev_tx_rx_disruption.2707953533
Short name T2307
Test name
Test status
Simulation time 438327919 ps
CPU time 1.41 seconds
Started Aug 18 05:40:23 PM PDT 24
Finished Aug 18 05:40:24 PM PDT 24
Peak memory 207588 kb
Host smart-0318ad5e-33b9-4c84-a38c-51892b43ccfb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707953533 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 427.usbdev_tx_rx_disruption.2707953533
Directory /workspace/427.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/428.usbdev_tx_rx_disruption.1149117069
Short name T2382
Test name
Test status
Simulation time 525170380 ps
CPU time 1.53 seconds
Started Aug 18 05:40:01 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207580 kb
Host smart-5a5182b1-1269-4409-ba64-65f3ccb3007b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149117069 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 428.usbdev_tx_rx_disruption.1149117069
Directory /workspace/428.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/429.usbdev_tx_rx_disruption.2553702732
Short name T3436
Test name
Test status
Simulation time 556089146 ps
CPU time 1.5 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207512 kb
Host smart-d2293e86-96e4-4a69-9efc-426276d08104
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553702732 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 429.usbdev_tx_rx_disruption.2553702732
Directory /workspace/429.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.1630487470
Short name T3054
Test name
Test status
Simulation time 47152833 ps
CPU time 0.74 seconds
Started Aug 18 05:38:02 PM PDT 24
Finished Aug 18 05:38:03 PM PDT 24
Peak memory 207464 kb
Host smart-1b3e2036-bccb-44b7-949c-faf42b0aa6c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1630487470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.1630487470
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.3842902386
Short name T1484
Test name
Test status
Simulation time 10075452773 ps
CPU time 15.98 seconds
Started Aug 18 05:37:49 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 207836 kb
Host smart-db4e3b01-17d7-4181-8636-b75abf79b4c2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842902386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_disconnect.3842902386
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.413430911
Short name T1628
Test name
Test status
Simulation time 20908871043 ps
CPU time 31.01 seconds
Started Aug 18 05:38:08 PM PDT 24
Finished Aug 18 05:38:39 PM PDT 24
Peak memory 207804 kb
Host smart-c5f3b28e-dd2a-435a-a96e-d2bf27698d50
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=413430911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.413430911
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.2081292013
Short name T1228
Test name
Test status
Simulation time 23827197268 ps
CPU time 27.1 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:30 PM PDT 24
Peak memory 215956 kb
Host smart-3323b928-b8c7-4f56-9201-afa08e74f626
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081292013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.2081292013
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1731874614
Short name T2060
Test name
Test status
Simulation time 226095151 ps
CPU time 0.9 seconds
Started Aug 18 05:38:14 PM PDT 24
Finished Aug 18 05:38:15 PM PDT 24
Peak memory 207464 kb
Host smart-243cc8c9-be82-4e2f-8085-4077aa58fd8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17318
74614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1731874614
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.3383660874
Short name T75
Test name
Test status
Simulation time 147590755 ps
CPU time 0.9 seconds
Started Aug 18 05:37:57 PM PDT 24
Finished Aug 18 05:37:58 PM PDT 24
Peak memory 207536 kb
Host smart-77bce18f-4141-4198-988b-b8c3affb4f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33836
60874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.3383660874
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.986441032
Short name T1748
Test name
Test status
Simulation time 356164315 ps
CPU time 1.39 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:06 PM PDT 24
Peak memory 207536 kb
Host smart-bc81638a-2176-46a7-ac80-146329fc80a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98644
1032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.986441032
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3881587179
Short name T3428
Test name
Test status
Simulation time 955509123 ps
CPU time 2.72 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:07 PM PDT 24
Peak memory 207636 kb
Host smart-9f11f6b5-df24-42e5-915c-fb9d57a5678c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3881587179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3881587179
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.3314685886
Short name T1834
Test name
Test status
Simulation time 34728818111 ps
CPU time 57.84 seconds
Started Aug 18 05:38:08 PM PDT 24
Finished Aug 18 05:39:06 PM PDT 24
Peak memory 207792 kb
Host smart-0613ab18-93b7-4b93-8215-b7463c122f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33146
85886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.3314685886
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.3081068096
Short name T660
Test name
Test status
Simulation time 2925804409 ps
CPU time 18.77 seconds
Started Aug 18 05:38:23 PM PDT 24
Finished Aug 18 05:38:42 PM PDT 24
Peak memory 207728 kb
Host smart-298ea7c9-f3d6-4f1e-8ed5-6463f1e4cbc0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081068096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.3081068096
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.1180706595
Short name T3255
Test name
Test status
Simulation time 816344793 ps
CPU time 2.03 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:10 PM PDT 24
Peak memory 207488 kb
Host smart-c68fc6b9-1129-424d-98ff-6d03050c86ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11807
06595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.1180706595
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3007271056
Short name T3555
Test name
Test status
Simulation time 140454370 ps
CPU time 0.84 seconds
Started Aug 18 05:38:01 PM PDT 24
Finished Aug 18 05:38:02 PM PDT 24
Peak memory 207492 kb
Host smart-44696d2f-0078-4b31-aad8-bee623848ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30072
71056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3007271056
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.149171013
Short name T1478
Test name
Test status
Simulation time 49652192 ps
CPU time 0.71 seconds
Started Aug 18 05:38:14 PM PDT 24
Finished Aug 18 05:38:15 PM PDT 24
Peak memory 207464 kb
Host smart-6cd566a7-9ea4-480c-8b8b-e43a49dda356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14917
1013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.149171013
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.727062197
Short name T1947
Test name
Test status
Simulation time 822912091 ps
CPU time 2.35 seconds
Started Aug 18 05:38:09 PM PDT 24
Finished Aug 18 05:38:12 PM PDT 24
Peak memory 207912 kb
Host smart-2a038d1c-f6c8-45ca-a144-643ec925104e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72706
2197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.727062197
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3036330360
Short name T2386
Test name
Test status
Simulation time 248441913 ps
CPU time 1.75 seconds
Started Aug 18 05:38:05 PM PDT 24
Finished Aug 18 05:38:07 PM PDT 24
Peak memory 207580 kb
Host smart-1654f987-2c6e-4162-8284-a430372be27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30363
30360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3036330360
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.4197031231
Short name T2303
Test name
Test status
Simulation time 216615056 ps
CPU time 1 seconds
Started Aug 18 05:38:01 PM PDT 24
Finished Aug 18 05:38:02 PM PDT 24
Peak memory 215804 kb
Host smart-df074502-7e56-4a2f-96a8-89757d28deb2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4197031231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.4197031231
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.203446025
Short name T2252
Test name
Test status
Simulation time 171772314 ps
CPU time 0.85 seconds
Started Aug 18 05:38:05 PM PDT 24
Finished Aug 18 05:38:06 PM PDT 24
Peak memory 207464 kb
Host smart-bb0b140e-c37e-45bc-b68c-f095cd76cf62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20344
6025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.203446025
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.2906341413
Short name T3469
Test name
Test status
Simulation time 206063796 ps
CPU time 0.97 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207460 kb
Host smart-195fec86-c158-4fef-bd52-d4fae006c8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29063
41413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.2906341413
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.2063221512
Short name T1306
Test name
Test status
Simulation time 2566907739 ps
CPU time 76.24 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:39:19 PM PDT 24
Peak memory 218476 kb
Host smart-e35ba89a-7f8a-4668-87fc-cc0533d0d6a6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2063221512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.2063221512
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.378632556
Short name T987
Test name
Test status
Simulation time 9196627647 ps
CPU time 116.43 seconds
Started Aug 18 05:38:05 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207772 kb
Host smart-2ef126e4-886d-415e-842c-45f3db03a310
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=378632556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.378632556
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.2230840722
Short name T918
Test name
Test status
Simulation time 209182555 ps
CPU time 0.91 seconds
Started Aug 18 05:38:16 PM PDT 24
Finished Aug 18 05:38:17 PM PDT 24
Peak memory 207580 kb
Host smart-98811798-b7ef-4b96-b436-2eb7b5580d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22308
40722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2230840722
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1557511056
Short name T978
Test name
Test status
Simulation time 15163785933 ps
CPU time 23.55 seconds
Started Aug 18 05:38:06 PM PDT 24
Finished Aug 18 05:38:29 PM PDT 24
Peak memory 207752 kb
Host smart-0fc4f15d-f904-4241-9615-275690747cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15575
11056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1557511056
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1224011850
Short name T2333
Test name
Test status
Simulation time 4036189122 ps
CPU time 5.81 seconds
Started Aug 18 05:38:02 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207752 kb
Host smart-83a559a1-a371-472d-82c8-f628fbd1ce06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12240
11850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1224011850
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.410750648
Short name T1215
Test name
Test status
Simulation time 3513738374 ps
CPU time 28.04 seconds
Started Aug 18 05:37:58 PM PDT 24
Finished Aug 18 05:38:26 PM PDT 24
Peak memory 219396 kb
Host smart-1d150db7-997d-4128-9903-b3d9e4b8eefc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=410750648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.410750648
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.270283168
Short name T1839
Test name
Test status
Simulation time 2633799575 ps
CPU time 75.44 seconds
Started Aug 18 05:38:06 PM PDT 24
Finished Aug 18 05:39:22 PM PDT 24
Peak memory 224092 kb
Host smart-5fd1cfe7-2b5d-498c-a243-26c61702c8bc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=270283168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.270283168
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.385931663
Short name T2885
Test name
Test status
Simulation time 254758296 ps
CPU time 1.01 seconds
Started Aug 18 05:38:08 PM PDT 24
Finished Aug 18 05:38:09 PM PDT 24
Peak memory 207468 kb
Host smart-074e7c86-4a40-4cb8-a565-9e2603b65ea5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=385931663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.385931663
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1758189510
Short name T668
Test name
Test status
Simulation time 251528060 ps
CPU time 1.01 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207472 kb
Host smart-824df33a-7d43-4dd1-afe4-e063a54b97a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17581
89510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1758189510
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.2075205689
Short name T3541
Test name
Test status
Simulation time 4414758757 ps
CPU time 128.64 seconds
Started Aug 18 05:38:06 PM PDT 24
Finished Aug 18 05:40:15 PM PDT 24
Peak memory 217244 kb
Host smart-7d36720c-6f4b-4543-8b23-58b8e3869048
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2075205689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.2075205689
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.971846842
Short name T2758
Test name
Test status
Simulation time 175444740 ps
CPU time 0.9 seconds
Started Aug 18 05:38:12 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 207472 kb
Host smart-2b7e924b-b22a-4798-8c9d-c70999da73f3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=971846842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.971846842
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3394573755
Short name T2039
Test name
Test status
Simulation time 170122280 ps
CPU time 0.86 seconds
Started Aug 18 05:38:01 PM PDT 24
Finished Aug 18 05:38:01 PM PDT 24
Peak memory 207492 kb
Host smart-086afff7-5def-4c0a-a3a8-ac218059d1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33945
73755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3394573755
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.213263226
Short name T150
Test name
Test status
Simulation time 175404002 ps
CPU time 0.91 seconds
Started Aug 18 05:38:09 PM PDT 24
Finished Aug 18 05:38:10 PM PDT 24
Peak memory 207460 kb
Host smart-6fbd98b4-3a97-4f77-983d-34296fcacc04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21326
3226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.213263226
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.983591229
Short name T2500
Test name
Test status
Simulation time 170068595 ps
CPU time 0.9 seconds
Started Aug 18 05:38:12 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 207468 kb
Host smart-8c60e278-5aa9-4559-9420-7876214b762e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98359
1229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.983591229
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2788802599
Short name T2663
Test name
Test status
Simulation time 165856114 ps
CPU time 0.92 seconds
Started Aug 18 05:38:11 PM PDT 24
Finished Aug 18 05:38:12 PM PDT 24
Peak memory 207392 kb
Host smart-293d4948-7905-4339-9773-06007842e6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27888
02599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2788802599
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3271646094
Short name T639
Test name
Test status
Simulation time 175875805 ps
CPU time 0.89 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 207520 kb
Host smart-913e317f-a5cd-4003-9b35-4f9e8be89fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32716
46094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3271646094
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1386778021
Short name T1757
Test name
Test status
Simulation time 159428515 ps
CPU time 0.87 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 207568 kb
Host smart-1b9cb58b-cae5-4166-a46d-8fc29bafa989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13867
78021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1386778021
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3965913480
Short name T2190
Test name
Test status
Simulation time 225421987 ps
CPU time 1.06 seconds
Started Aug 18 05:38:00 PM PDT 24
Finished Aug 18 05:38:01 PM PDT 24
Peak memory 207524 kb
Host smart-cd28d9a0-567f-46cc-824b-183d188c0f73
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3965913480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3965913480
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.139915911
Short name T1941
Test name
Test status
Simulation time 190576735 ps
CPU time 0.94 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 207476 kb
Host smart-2feb4ae5-eb90-4b5b-b9c5-a970f01d1516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13991
5911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.139915911
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2795201027
Short name T2235
Test name
Test status
Simulation time 44152006 ps
CPU time 0.73 seconds
Started Aug 18 05:38:11 PM PDT 24
Finished Aug 18 05:38:12 PM PDT 24
Peak memory 207540 kb
Host smart-ab9b4ccf-8db9-4d96-bc67-1c5ffbbb2dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27952
01027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2795201027
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.123836220
Short name T2001
Test name
Test status
Simulation time 15817004889 ps
CPU time 41.86 seconds
Started Aug 18 05:38:10 PM PDT 24
Finished Aug 18 05:38:52 PM PDT 24
Peak memory 215952 kb
Host smart-c2072e12-b182-4f7d-8ed9-314e5892da4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12383
6220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.123836220
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1639246288
Short name T2239
Test name
Test status
Simulation time 228437973 ps
CPU time 0.96 seconds
Started Aug 18 05:38:13 PM PDT 24
Finished Aug 18 05:38:14 PM PDT 24
Peak memory 207468 kb
Host smart-188ee10d-0a6c-425d-b354-938abf91cdc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16392
46288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1639246288
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3089024924
Short name T2531
Test name
Test status
Simulation time 231022956 ps
CPU time 0.97 seconds
Started Aug 18 05:38:10 PM PDT 24
Finished Aug 18 05:38:11 PM PDT 24
Peak memory 207452 kb
Host smart-963ee217-3048-4981-a82c-1a7823248bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30890
24924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3089024924
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.3641366033
Short name T556
Test name
Test status
Simulation time 252289936 ps
CPU time 1.01 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:04 PM PDT 24
Peak memory 207644 kb
Host smart-64857858-f3d9-4cdc-91db-aedc9d275201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36413
66033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.3641366033
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.3312414747
Short name T995
Test name
Test status
Simulation time 208509143 ps
CPU time 0.96 seconds
Started Aug 18 05:38:05 PM PDT 24
Finished Aug 18 05:38:06 PM PDT 24
Peak memory 207644 kb
Host smart-008fd72f-d491-4802-ab03-4613bc7486e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33124
14747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.3312414747
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3463108977
Short name T2122
Test name
Test status
Simulation time 140066386 ps
CPU time 0.79 seconds
Started Aug 18 05:38:12 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 207472 kb
Host smart-34130b8e-d89f-456b-bb87-03e814901818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34631
08977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3463108977
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_rx_full.738476212
Short name T2558
Test name
Test status
Simulation time 265813223 ps
CPU time 1.07 seconds
Started Aug 18 05:38:17 PM PDT 24
Finished Aug 18 05:38:18 PM PDT 24
Peak memory 207420 kb
Host smart-c21eea42-c240-4b87-a790-85887f814b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73847
6212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_full.738476212
Directory /workspace/43.usbdev_rx_full/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.279085222
Short name T1966
Test name
Test status
Simulation time 162818438 ps
CPU time 0.85 seconds
Started Aug 18 05:38:21 PM PDT 24
Finished Aug 18 05:38:22 PM PDT 24
Peak memory 207428 kb
Host smart-049cf7da-d546-4c17-bacf-6b320f8dc862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27908
5222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.279085222
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1522897158
Short name T2270
Test name
Test status
Simulation time 156954487 ps
CPU time 0.84 seconds
Started Aug 18 05:38:08 PM PDT 24
Finished Aug 18 05:38:09 PM PDT 24
Peak memory 207508 kb
Host smart-64ce1f8a-7255-485a-b171-b4ef157b6818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15228
97158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1522897158
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.597978162
Short name T2278
Test name
Test status
Simulation time 231939976 ps
CPU time 1.12 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207504 kb
Host smart-3a861942-6e1f-4bc8-8dd3-b6e2b890bb50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59797
8162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.597978162
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.370872936
Short name T3205
Test name
Test status
Simulation time 2602337136 ps
CPU time 74.69 seconds
Started Aug 18 05:38:10 PM PDT 24
Finished Aug 18 05:39:25 PM PDT 24
Peak memory 217808 kb
Host smart-6282ad80-575e-491b-a855-f3f441e93483
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=370872936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.370872936
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.132556076
Short name T140
Test name
Test status
Simulation time 164100196 ps
CPU time 0.83 seconds
Started Aug 18 05:38:14 PM PDT 24
Finished Aug 18 05:38:15 PM PDT 24
Peak memory 207500 kb
Host smart-ea3f5350-62a3-4f04-91c5-ee42df82a52e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13255
6076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.132556076
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.4092785763
Short name T760
Test name
Test status
Simulation time 200711177 ps
CPU time 0.92 seconds
Started Aug 18 05:38:12 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 207488 kb
Host smart-977157f0-93b0-47e8-886d-d70c2f12648c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40927
85763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.4092785763
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.2000491418
Short name T1613
Test name
Test status
Simulation time 1096910483 ps
CPU time 2.7 seconds
Started Aug 18 05:38:10 PM PDT 24
Finished Aug 18 05:38:12 PM PDT 24
Peak memory 207732 kb
Host smart-49b73822-e78b-4b09-a442-9e471ca957b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20004
91418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.2000491418
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.172623717
Short name T1119
Test name
Test status
Simulation time 2080497084 ps
CPU time 17.6 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:21 PM PDT 24
Peak memory 217424 kb
Host smart-0b2d47d0-4690-47fd-920e-d078f9c3824c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17262
3717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.172623717
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.1219769670
Short name T2316
Test name
Test status
Simulation time 2983487024 ps
CPU time 24.46 seconds
Started Aug 18 05:38:15 PM PDT 24
Finished Aug 18 05:38:40 PM PDT 24
Peak memory 207696 kb
Host smart-7cf0873b-f6d7-4189-b26f-0e4f9156c84f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219769670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.1219769670
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_tx_rx_disruption.2372381856
Short name T1498
Test name
Test status
Simulation time 521051954 ps
CPU time 1.53 seconds
Started Aug 18 05:38:06 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207496 kb
Host smart-6bf6e921-556a-4c3b-b181-f3b5864fdbd6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372381856 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.usbdev_tx_rx_disruption.2372381856
Directory /workspace/43.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/430.usbdev_tx_rx_disruption.3677946902
Short name T225
Test name
Test status
Simulation time 444260367 ps
CPU time 1.41 seconds
Started Aug 18 05:39:58 PM PDT 24
Finished Aug 18 05:39:59 PM PDT 24
Peak memory 207572 kb
Host smart-b857a726-c3b8-4fb3-8074-f31b835748a8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677946902 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 430.usbdev_tx_rx_disruption.3677946902
Directory /workspace/430.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/431.usbdev_tx_rx_disruption.1560838126
Short name T974
Test name
Test status
Simulation time 559766211 ps
CPU time 1.55 seconds
Started Aug 18 05:40:25 PM PDT 24
Finished Aug 18 05:40:27 PM PDT 24
Peak memory 207560 kb
Host smart-d25a0d1c-c805-4366-bd64-14bb93df75b6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560838126 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 431.usbdev_tx_rx_disruption.1560838126
Directory /workspace/431.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/432.usbdev_tx_rx_disruption.4225189025
Short name T1983
Test name
Test status
Simulation time 598251856 ps
CPU time 1.65 seconds
Started Aug 18 05:40:11 PM PDT 24
Finished Aug 18 05:40:13 PM PDT 24
Peak memory 207528 kb
Host smart-59f7ac21-1a47-4a30-b1dd-e18c3f13376b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225189025 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 432.usbdev_tx_rx_disruption.4225189025
Directory /workspace/432.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/433.usbdev_tx_rx_disruption.3744545030
Short name T1886
Test name
Test status
Simulation time 624716897 ps
CPU time 1.74 seconds
Started Aug 18 05:40:08 PM PDT 24
Finished Aug 18 05:40:10 PM PDT 24
Peak memory 207612 kb
Host smart-50a5dbec-26d6-497e-b86a-43240c57cb53
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744545030 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 433.usbdev_tx_rx_disruption.3744545030
Directory /workspace/433.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/434.usbdev_tx_rx_disruption.1948605251
Short name T2643
Test name
Test status
Simulation time 467156153 ps
CPU time 1.52 seconds
Started Aug 18 05:39:57 PM PDT 24
Finished Aug 18 05:39:58 PM PDT 24
Peak memory 207532 kb
Host smart-4d046d5e-b066-4af5-87be-a7b27bece660
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948605251 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 434.usbdev_tx_rx_disruption.1948605251
Directory /workspace/434.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/435.usbdev_tx_rx_disruption.3715121761
Short name T119
Test name
Test status
Simulation time 597502652 ps
CPU time 1.72 seconds
Started Aug 18 05:40:05 PM PDT 24
Finished Aug 18 05:40:07 PM PDT 24
Peak memory 207564 kb
Host smart-b80baa4e-26ee-41cc-a8c5-9a57279bd78a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715121761 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 435.usbdev_tx_rx_disruption.3715121761
Directory /workspace/435.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/436.usbdev_tx_rx_disruption.1504848314
Short name T2102
Test name
Test status
Simulation time 474273888 ps
CPU time 1.44 seconds
Started Aug 18 05:39:58 PM PDT 24
Finished Aug 18 05:40:00 PM PDT 24
Peak memory 207588 kb
Host smart-c9fc487e-7ed9-4bf6-be83-cd8d972c3dbf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504848314 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 436.usbdev_tx_rx_disruption.1504848314
Directory /workspace/436.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/437.usbdev_tx_rx_disruption.1049515978
Short name T118
Test name
Test status
Simulation time 632768320 ps
CPU time 1.76 seconds
Started Aug 18 05:40:16 PM PDT 24
Finished Aug 18 05:40:18 PM PDT 24
Peak memory 207508 kb
Host smart-4b59e086-5e7f-4b43-95cb-bd2019fc838d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049515978 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 437.usbdev_tx_rx_disruption.1049515978
Directory /workspace/437.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/438.usbdev_tx_rx_disruption.1464198312
Short name T2065
Test name
Test status
Simulation time 524741024 ps
CPU time 1.59 seconds
Started Aug 18 05:40:05 PM PDT 24
Finished Aug 18 05:40:07 PM PDT 24
Peak memory 207512 kb
Host smart-9d56c5fa-017e-4377-bff1-676d27042f39
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464198312 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 438.usbdev_tx_rx_disruption.1464198312
Directory /workspace/438.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/439.usbdev_tx_rx_disruption.471916163
Short name T549
Test name
Test status
Simulation time 479043575 ps
CPU time 1.44 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:01 PM PDT 24
Peak memory 207580 kb
Host smart-955a2e33-8bef-4eb3-bf76-bbaf28d29219
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471916163 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 439.usbdev_tx_rx_disruption.471916163
Directory /workspace/439.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.2013169303
Short name T3269
Test name
Test status
Simulation time 37432161 ps
CPU time 0.65 seconds
Started Aug 18 05:38:23 PM PDT 24
Finished Aug 18 05:38:24 PM PDT 24
Peak memory 207408 kb
Host smart-d016960a-bb9f-448f-b14f-a36166b8a308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2013169303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.2013169303
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2635823346
Short name T1463
Test name
Test status
Simulation time 9461447123 ps
CPU time 11.99 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:16 PM PDT 24
Peak memory 207804 kb
Host smart-10b94dd9-6699-4f82-a754-087d1b26b1c8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635823346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.2635823346
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.3229866193
Short name T245
Test name
Test status
Simulation time 19314796301 ps
CPU time 23.74 seconds
Started Aug 18 05:38:05 PM PDT 24
Finished Aug 18 05:38:29 PM PDT 24
Peak memory 207704 kb
Host smart-74e72fa4-c482-4941-bea8-611bbe89ff0f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229866193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.3229866193
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2052441658
Short name T1256
Test name
Test status
Simulation time 30405044636 ps
CPU time 37.28 seconds
Started Aug 18 05:38:05 PM PDT 24
Finished Aug 18 05:38:43 PM PDT 24
Peak memory 207856 kb
Host smart-c3896576-8a66-4233-ad1a-1aec07e825fb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052441658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_resume.2052441658
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.4121453923
Short name T3143
Test name
Test status
Simulation time 170095926 ps
CPU time 0.9 seconds
Started Aug 18 05:38:06 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207460 kb
Host smart-b8c4baf8-ae22-449b-b654-4161fccf5232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41214
53923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.4121453923
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.3948439213
Short name T1500
Test name
Test status
Simulation time 149586552 ps
CPU time 0.82 seconds
Started Aug 18 05:38:24 PM PDT 24
Finished Aug 18 05:38:25 PM PDT 24
Peak memory 207580 kb
Host smart-dda93766-6a05-4b70-adc2-a81184c8bd32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39484
39213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3948439213
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.467127808
Short name T2770
Test name
Test status
Simulation time 550793690 ps
CPU time 1.79 seconds
Started Aug 18 05:38:09 PM PDT 24
Finished Aug 18 05:38:11 PM PDT 24
Peak memory 207548 kb
Host smart-ea73eeb8-6ebe-418c-a1f2-fe250cd5a74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46712
7808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.467127808
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.4215893035
Short name T352
Test name
Test status
Simulation time 1080900418 ps
CPU time 2.67 seconds
Started Aug 18 05:38:10 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 207608 kb
Host smart-cac94a6e-5d0b-4a7b-952a-922c979d973d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4215893035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.4215893035
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1863723249
Short name T1710
Test name
Test status
Simulation time 18238704311 ps
CPU time 30.41 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:34 PM PDT 24
Peak memory 207688 kb
Host smart-05cf757c-cad9-4251-b323-b5ab4699707f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18637
23249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1863723249
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.2699921085
Short name T1676
Test name
Test status
Simulation time 3869627952 ps
CPU time 33.23 seconds
Started Aug 18 05:38:20 PM PDT 24
Finished Aug 18 05:38:54 PM PDT 24
Peak memory 207772 kb
Host smart-f06b37d5-eb84-4f1b-b2b1-083ec5d3e6ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699921085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.2699921085
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2322316031
Short name T1059
Test name
Test status
Simulation time 576339246 ps
CPU time 1.55 seconds
Started Aug 18 05:38:24 PM PDT 24
Finished Aug 18 05:38:26 PM PDT 24
Peak memory 207460 kb
Host smart-a13b861d-56a8-4a87-bad3-426380d31e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23223
16031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2322316031
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.854076327
Short name T2259
Test name
Test status
Simulation time 151168240 ps
CPU time 0.83 seconds
Started Aug 18 05:38:08 PM PDT 24
Finished Aug 18 05:38:09 PM PDT 24
Peak memory 207540 kb
Host smart-e23fb12e-1ffe-4be0-b9d7-d881bac4ad6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85407
6327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.854076327
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2870098948
Short name T2414
Test name
Test status
Simulation time 39299648 ps
CPU time 0.7 seconds
Started Aug 18 05:38:14 PM PDT 24
Finished Aug 18 05:38:15 PM PDT 24
Peak memory 207448 kb
Host smart-b3056abf-6765-4c25-b922-79709a7c7447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28700
98948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2870098948
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2220473468
Short name T2832
Test name
Test status
Simulation time 818944922 ps
CPU time 2.28 seconds
Started Aug 18 05:38:13 PM PDT 24
Finished Aug 18 05:38:15 PM PDT 24
Peak memory 207764 kb
Host smart-bb6892ea-822f-43d5-86f9-a30587b205ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22204
73468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2220473468
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_types.344142118
Short name T415
Test name
Test status
Simulation time 352622907 ps
CPU time 1.17 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:06 PM PDT 24
Peak memory 207452 kb
Host smart-e68ed5da-525a-41fe-8d5f-cf1cc964826d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=344142118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_types.344142118
Directory /workspace/44.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3308495966
Short name T1903
Test name
Test status
Simulation time 285802724 ps
CPU time 2.19 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:06 PM PDT 24
Peak memory 207608 kb
Host smart-5e358289-6b48-4201-9572-b074f5f5629c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33084
95966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3308495966
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.4036010468
Short name T2635
Test name
Test status
Simulation time 213049496 ps
CPU time 1.05 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 216924 kb
Host smart-82342674-6239-4597-825b-c21785403044
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4036010468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.4036010468
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.751546781
Short name T2032
Test name
Test status
Simulation time 140283433 ps
CPU time 0.83 seconds
Started Aug 18 05:38:05 PM PDT 24
Finished Aug 18 05:38:06 PM PDT 24
Peak memory 207412 kb
Host smart-417dcb8d-1415-42ef-887e-c41f2b381e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75154
6781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.751546781
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2237941395
Short name T2404
Test name
Test status
Simulation time 234130170 ps
CPU time 1.06 seconds
Started Aug 18 05:38:02 PM PDT 24
Finished Aug 18 05:38:03 PM PDT 24
Peak memory 207392 kb
Host smart-b1e62d3d-cccb-42b0-8dd4-a98a1284f6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22379
41395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2237941395
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.3235928120
Short name T2061
Test name
Test status
Simulation time 2841371001 ps
CPU time 81.22 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:39:26 PM PDT 24
Peak memory 215976 kb
Host smart-0955a1e4-857e-40ac-a8d6-a3a31b88d61e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3235928120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.3235928120
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.2192624020
Short name T947
Test name
Test status
Simulation time 10470127799 ps
CPU time 67.7 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:39:12 PM PDT 24
Peak memory 207784 kb
Host smart-5c7d1572-6007-4c67-a726-72f46483d452
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2192624020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.2192624020
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.2710168862
Short name T1860
Test name
Test status
Simulation time 182268655 ps
CPU time 0.9 seconds
Started Aug 18 05:37:58 PM PDT 24
Finished Aug 18 05:37:59 PM PDT 24
Peak memory 207504 kb
Host smart-b0a1c590-45f7-4a3b-878e-66750d7a5271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27101
68862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2710168862
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.3920689825
Short name T100
Test name
Test status
Simulation time 7690602863 ps
CPU time 9.94 seconds
Started Aug 18 05:38:05 PM PDT 24
Finished Aug 18 05:38:15 PM PDT 24
Peak memory 216004 kb
Host smart-1ec17b5a-09a5-4936-8ec2-7d060d55df83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39206
89825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.3920689825
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2788594847
Short name T548
Test name
Test status
Simulation time 10390312063 ps
CPU time 13.66 seconds
Started Aug 18 05:38:06 PM PDT 24
Finished Aug 18 05:38:20 PM PDT 24
Peak memory 207784 kb
Host smart-ef9da23d-07e1-4c88-aa1f-88f07c0214e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27885
94847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2788594847
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.3314514578
Short name T944
Test name
Test status
Simulation time 2862622402 ps
CPU time 29.59 seconds
Started Aug 18 05:38:22 PM PDT 24
Finished Aug 18 05:38:52 PM PDT 24
Peak memory 218736 kb
Host smart-34d95270-c4f2-49d9-ac44-f83e385695b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3314514578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.3314514578
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.3420614813
Short name T2615
Test name
Test status
Simulation time 3037978475 ps
CPU time 88.25 seconds
Started Aug 18 05:38:02 PM PDT 24
Finished Aug 18 05:39:31 PM PDT 24
Peak memory 217380 kb
Host smart-66932429-f626-4d23-a298-49cc79d2dc35
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3420614813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.3420614813
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.4070994938
Short name T985
Test name
Test status
Simulation time 263715628 ps
CPU time 1.04 seconds
Started Aug 18 05:38:06 PM PDT 24
Finished Aug 18 05:38:07 PM PDT 24
Peak memory 207460 kb
Host smart-cba3deb5-1569-4e7d-882b-bb9fe9cefb3f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4070994938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.4070994938
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.734705776
Short name T3232
Test name
Test status
Simulation time 191068135 ps
CPU time 0.92 seconds
Started Aug 18 05:38:02 PM PDT 24
Finished Aug 18 05:38:03 PM PDT 24
Peak memory 207480 kb
Host smart-c84e971e-357d-47fd-9f48-362280ee415b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73470
5776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.734705776
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.412471392
Short name T2816
Test name
Test status
Simulation time 3438397018 ps
CPU time 34.09 seconds
Started Aug 18 05:38:05 PM PDT 24
Finished Aug 18 05:38:39 PM PDT 24
Peak memory 217496 kb
Host smart-d4e1d2be-5f74-46bb-8167-8c177ed45a41
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=412471392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.412471392
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.458675635
Short name T2680
Test name
Test status
Simulation time 151843504 ps
CPU time 0.87 seconds
Started Aug 18 05:38:09 PM PDT 24
Finished Aug 18 05:38:10 PM PDT 24
Peak memory 207500 kb
Host smart-2ab0d24a-4dd0-41fc-ba59-1728775af733
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=458675635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.458675635
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3341745423
Short name T1469
Test name
Test status
Simulation time 172823170 ps
CPU time 0.91 seconds
Started Aug 18 05:38:21 PM PDT 24
Finished Aug 18 05:38:22 PM PDT 24
Peak memory 207488 kb
Host smart-42570d49-d7c3-4b24-b333-a1f424daea62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33417
45423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3341745423
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2095435300
Short name T2378
Test name
Test status
Simulation time 224419080 ps
CPU time 1.04 seconds
Started Aug 18 05:38:06 PM PDT 24
Finished Aug 18 05:38:07 PM PDT 24
Peak memory 207476 kb
Host smart-e89a9d79-bafd-4ef5-a525-6d0a37164bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20954
35300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2095435300
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3559678976
Short name T2244
Test name
Test status
Simulation time 210727548 ps
CPU time 0.94 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:04 PM PDT 24
Peak memory 207384 kb
Host smart-af636b92-7a4a-4738-99fb-710c854dcd02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35596
78976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3559678976
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1010898635
Short name T3310
Test name
Test status
Simulation time 178806949 ps
CPU time 0.88 seconds
Started Aug 18 05:38:10 PM PDT 24
Finished Aug 18 05:38:11 PM PDT 24
Peak memory 207504 kb
Host smart-8b9673d5-e18c-40fd-a81a-e2e62d2b806f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10108
98635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1010898635
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1793410739
Short name T2522
Test name
Test status
Simulation time 222496273 ps
CPU time 0.92 seconds
Started Aug 18 05:38:09 PM PDT 24
Finished Aug 18 05:38:10 PM PDT 24
Peak memory 207608 kb
Host smart-47fe9927-bc4e-46a6-8e40-7631af7c064e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17934
10739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1793410739
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.2780624378
Short name T1525
Test name
Test status
Simulation time 190397273 ps
CPU time 0.91 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 207560 kb
Host smart-8a42c13b-fce6-4bbb-bfb6-d1e0b4948be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27806
24378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.2780624378
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.191996222
Short name T1170
Test name
Test status
Simulation time 214484795 ps
CPU time 1.02 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207500 kb
Host smart-1c30865c-3cdd-4e7f-9520-fd6ca271ecb4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=191996222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.191996222
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.2974479616
Short name T1160
Test name
Test status
Simulation time 140917041 ps
CPU time 0.86 seconds
Started Aug 18 05:38:27 PM PDT 24
Finished Aug 18 05:38:28 PM PDT 24
Peak memory 207484 kb
Host smart-aca80d4d-39ad-4bf5-8396-bf6b5f5957cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29744
79616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.2974479616
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.895199784
Short name T2258
Test name
Test status
Simulation time 59271828 ps
CPU time 0.74 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207540 kb
Host smart-aa49ac50-9b27-48f4-91f3-b8f95131d7f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89519
9784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.895199784
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1973729529
Short name T292
Test name
Test status
Simulation time 7802309406 ps
CPU time 20.59 seconds
Started Aug 18 05:38:04 PM PDT 24
Finished Aug 18 05:38:25 PM PDT 24
Peak memory 215872 kb
Host smart-f209f29d-fe8c-4465-95df-51ac44b8ad5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19737
29529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1973729529
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1421495044
Short name T721
Test name
Test status
Simulation time 167213724 ps
CPU time 0.95 seconds
Started Aug 18 05:38:11 PM PDT 24
Finished Aug 18 05:38:12 PM PDT 24
Peak memory 207488 kb
Host smart-a0da7deb-327f-4450-9909-1769ad8fa0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14214
95044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1421495044
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1864821724
Short name T2923
Test name
Test status
Simulation time 186677288 ps
CPU time 0.89 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:09 PM PDT 24
Peak memory 207460 kb
Host smart-435458ea-55b1-42f1-977e-1e47671252a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18648
21724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1864821724
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.255100076
Short name T1826
Test name
Test status
Simulation time 249640571 ps
CPU time 0.99 seconds
Started Aug 18 05:38:12 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 207492 kb
Host smart-18d384b4-2184-4f34-80d9-ed2c894301e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25510
0076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.255100076
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1997227268
Short name T2395
Test name
Test status
Simulation time 159375694 ps
CPU time 0.87 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207500 kb
Host smart-eb44d1a9-8e86-425b-9362-dce3f7f12a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19972
27268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1997227268
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.2811283665
Short name T2089
Test name
Test status
Simulation time 179328960 ps
CPU time 0.87 seconds
Started Aug 18 05:38:12 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 207392 kb
Host smart-c3dd5998-67e5-444f-a902-91e192cd1603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28112
83665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.2811283665
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3725311771
Short name T3227
Test name
Test status
Simulation time 158903677 ps
CPU time 0.87 seconds
Started Aug 18 05:38:08 PM PDT 24
Finished Aug 18 05:38:09 PM PDT 24
Peak memory 207536 kb
Host smart-1cb64b16-79c9-462c-ac3d-d8b46ef36bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37253
11771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3725311771
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.338657915
Short name T1394
Test name
Test status
Simulation time 153849416 ps
CPU time 0.84 seconds
Started Aug 18 05:38:11 PM PDT 24
Finished Aug 18 05:38:12 PM PDT 24
Peak memory 207576 kb
Host smart-92b5901d-6565-485d-b66c-f43b96d531f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33865
7915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.338657915
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.744840454
Short name T2512
Test name
Test status
Simulation time 237238378 ps
CPU time 1.12 seconds
Started Aug 18 05:38:15 PM PDT 24
Finished Aug 18 05:38:16 PM PDT 24
Peak memory 207484 kb
Host smart-6de37c79-0b13-41a2-9633-76c1b5162459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74484
0454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.744840454
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.4217099650
Short name T1302
Test name
Test status
Simulation time 3065984377 ps
CPU time 25.17 seconds
Started Aug 18 05:38:11 PM PDT 24
Finished Aug 18 05:38:36 PM PDT 24
Peak memory 217940 kb
Host smart-b671507a-80a7-40c6-8760-6bee75c5b604
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4217099650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.4217099650
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2512179998
Short name T3608
Test name
Test status
Simulation time 177101561 ps
CPU time 0.85 seconds
Started Aug 18 05:38:25 PM PDT 24
Finished Aug 18 05:38:26 PM PDT 24
Peak memory 207456 kb
Host smart-547261ad-3308-43a4-aebd-0934a4de864c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25121
79998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2512179998
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3256345461
Short name T2736
Test name
Test status
Simulation time 253372237 ps
CPU time 0.94 seconds
Started Aug 18 05:38:08 PM PDT 24
Finished Aug 18 05:38:09 PM PDT 24
Peak memory 207564 kb
Host smart-348d7547-f68e-4c17-b4ec-159fab13498f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32563
45461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3256345461
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.2412935394
Short name T1922
Test name
Test status
Simulation time 502442792 ps
CPU time 1.5 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:09 PM PDT 24
Peak memory 207536 kb
Host smart-437eccc2-b697-4e6d-b9bf-b6c5bbc78153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24129
35394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2412935394
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.3418439396
Short name T2526
Test name
Test status
Simulation time 2945064996 ps
CPU time 18.46 seconds
Started Aug 18 05:38:02 PM PDT 24
Finished Aug 18 05:38:21 PM PDT 24
Peak memory 207708 kb
Host smart-b23682c1-593f-452c-980a-f92880c8cf66
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418439396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_hos
t_handshake.3418439396
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_tx_rx_disruption.2519624944
Short name T2592
Test name
Test status
Simulation time 564125625 ps
CPU time 1.57 seconds
Started Aug 18 05:38:15 PM PDT 24
Finished Aug 18 05:38:17 PM PDT 24
Peak memory 207552 kb
Host smart-abe4709f-b9ba-4d88-9956-33287eac44ca
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519624944 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.usbdev_tx_rx_disruption.2519624944
Directory /workspace/44.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/440.usbdev_tx_rx_disruption.767674842
Short name T2645
Test name
Test status
Simulation time 606758574 ps
CPU time 1.87 seconds
Started Aug 18 05:40:30 PM PDT 24
Finished Aug 18 05:40:32 PM PDT 24
Peak memory 207580 kb
Host smart-570ebf11-4ade-4726-b8ff-ae22613d86af
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767674842 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 440.usbdev_tx_rx_disruption.767674842
Directory /workspace/440.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/441.usbdev_tx_rx_disruption.3486796484
Short name T2451
Test name
Test status
Simulation time 458793637 ps
CPU time 1.34 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:01 PM PDT 24
Peak memory 207564 kb
Host smart-daebcdcf-b689-480e-9a75-847e746aa594
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486796484 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 441.usbdev_tx_rx_disruption.3486796484
Directory /workspace/441.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/442.usbdev_tx_rx_disruption.3586763893
Short name T3124
Test name
Test status
Simulation time 612666150 ps
CPU time 1.66 seconds
Started Aug 18 05:40:22 PM PDT 24
Finished Aug 18 05:40:24 PM PDT 24
Peak memory 207588 kb
Host smart-763a92c9-46ba-46df-9248-33e3684fa4e2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586763893 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 442.usbdev_tx_rx_disruption.3586763893
Directory /workspace/442.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/443.usbdev_tx_rx_disruption.430045554
Short name T209
Test name
Test status
Simulation time 495676509 ps
CPU time 1.45 seconds
Started Aug 18 05:39:58 PM PDT 24
Finished Aug 18 05:40:00 PM PDT 24
Peak memory 207588 kb
Host smart-ddb9471e-0337-4085-858b-6b18cbcccd08
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430045554 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 443.usbdev_tx_rx_disruption.430045554
Directory /workspace/443.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/444.usbdev_tx_rx_disruption.687611244
Short name T1600
Test name
Test status
Simulation time 620072960 ps
CPU time 1.71 seconds
Started Aug 18 05:40:16 PM PDT 24
Finished Aug 18 05:40:18 PM PDT 24
Peak memory 207588 kb
Host smart-61a3db35-ee36-4d25-9147-c0a344ee284f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687611244 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 444.usbdev_tx_rx_disruption.687611244
Directory /workspace/444.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/445.usbdev_tx_rx_disruption.1730163940
Short name T3376
Test name
Test status
Simulation time 505889058 ps
CPU time 1.58 seconds
Started Aug 18 05:39:58 PM PDT 24
Finished Aug 18 05:39:59 PM PDT 24
Peak memory 207604 kb
Host smart-890e8ba1-aa0e-4f2d-b26c-b7b42a22a362
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730163940 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 445.usbdev_tx_rx_disruption.1730163940
Directory /workspace/445.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/446.usbdev_tx_rx_disruption.1618301743
Short name T215
Test name
Test status
Simulation time 514427450 ps
CPU time 1.64 seconds
Started Aug 18 05:40:00 PM PDT 24
Finished Aug 18 05:40:02 PM PDT 24
Peak memory 207584 kb
Host smart-83e14c85-7e59-4c0d-bcbe-c0b04f2af87b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618301743 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 446.usbdev_tx_rx_disruption.1618301743
Directory /workspace/446.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/447.usbdev_tx_rx_disruption.3856537998
Short name T1216
Test name
Test status
Simulation time 574300876 ps
CPU time 1.77 seconds
Started Aug 18 05:39:56 PM PDT 24
Finished Aug 18 05:39:58 PM PDT 24
Peak memory 207480 kb
Host smart-3ebc6f38-1331-4191-9d61-1fabcd857208
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856537998 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 447.usbdev_tx_rx_disruption.3856537998
Directory /workspace/447.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/448.usbdev_tx_rx_disruption.839887230
Short name T993
Test name
Test status
Simulation time 543230907 ps
CPU time 1.68 seconds
Started Aug 18 05:40:30 PM PDT 24
Finished Aug 18 05:40:32 PM PDT 24
Peak memory 207572 kb
Host smart-ccbbdf93-5b3a-4aba-8fb1-375f46a1e165
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839887230 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 448.usbdev_tx_rx_disruption.839887230
Directory /workspace/448.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/449.usbdev_tx_rx_disruption.2595586895
Short name T2573
Test name
Test status
Simulation time 669015432 ps
CPU time 1.81 seconds
Started Aug 18 05:40:08 PM PDT 24
Finished Aug 18 05:40:10 PM PDT 24
Peak memory 207576 kb
Host smart-7aaec1d1-9a29-4a71-a3f0-92a35e16f41e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595586895 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 449.usbdev_tx_rx_disruption.2595586895
Directory /workspace/449.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.3967962294
Short name T1741
Test name
Test status
Simulation time 42896257 ps
CPU time 0.69 seconds
Started Aug 18 05:38:17 PM PDT 24
Finished Aug 18 05:38:17 PM PDT 24
Peak memory 207428 kb
Host smart-1bdaef35-f8f7-4e6c-bbf5-9ad35c79cde9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3967962294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.3967962294
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.524658592
Short name T2499
Test name
Test status
Simulation time 10687530048 ps
CPU time 13.47 seconds
Started Aug 18 05:38:19 PM PDT 24
Finished Aug 18 05:38:33 PM PDT 24
Peak memory 207820 kb
Host smart-661d5c73-5dd0-4dfa-94db-5a1ce47cf16e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524658592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_ao
n_wake_disconnect.524658592
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.32980100
Short name T3493
Test name
Test status
Simulation time 13361208294 ps
CPU time 16.71 seconds
Started Aug 18 05:38:21 PM PDT 24
Finished Aug 18 05:38:38 PM PDT 24
Peak memory 215904 kb
Host smart-95e11922-ce22-4b96-89b3-f1b0c0fd725c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=32980100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.32980100
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.2406063464
Short name T11
Test name
Test status
Simulation time 29219237158 ps
CPU time 44.09 seconds
Started Aug 18 05:38:08 PM PDT 24
Finished Aug 18 05:38:52 PM PDT 24
Peak memory 207848 kb
Host smart-9dbca220-f62a-4be3-8b7d-16f06d2bd1f2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406063464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.2406063464
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.4141905058
Short name T1232
Test name
Test status
Simulation time 158256137 ps
CPU time 0.85 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207508 kb
Host smart-b35ea23f-5617-43bd-b480-f292c6006cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41419
05058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.4141905058
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3822640868
Short name T2449
Test name
Test status
Simulation time 217297486 ps
CPU time 0.97 seconds
Started Aug 18 05:38:17 PM PDT 24
Finished Aug 18 05:38:18 PM PDT 24
Peak memory 207560 kb
Host smart-f1d15b63-0a54-4454-b767-c525289b25a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38226
40868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3822640868
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.3839528540
Short name T2456
Test name
Test status
Simulation time 454652868 ps
CPU time 1.46 seconds
Started Aug 18 05:38:03 PM PDT 24
Finished Aug 18 05:38:05 PM PDT 24
Peak memory 207584 kb
Host smart-b87b36f0-dcdb-4ec0-9093-79c66bc82592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38395
28540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.3839528540
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.289688120
Short name T2941
Test name
Test status
Simulation time 484966178 ps
CPU time 1.52 seconds
Started Aug 18 05:38:24 PM PDT 24
Finished Aug 18 05:38:25 PM PDT 24
Peak memory 207484 kb
Host smart-7987ee92-0f74-440f-9638-14966fcdb515
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=289688120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.289688120
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.1941659209
Short name T1827
Test name
Test status
Simulation time 2031383924 ps
CPU time 17.56 seconds
Started Aug 18 05:38:09 PM PDT 24
Finished Aug 18 05:38:26 PM PDT 24
Peak memory 207788 kb
Host smart-70aaa7fc-266f-4974-a6f6-fe8ee63dce99
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941659209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.1941659209
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.927207675
Short name T844
Test name
Test status
Simulation time 980824357 ps
CPU time 2.15 seconds
Started Aug 18 05:38:32 PM PDT 24
Finished Aug 18 05:38:34 PM PDT 24
Peak memory 207536 kb
Host smart-6d9c1637-33bf-4dfb-b599-7770b646a746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92720
7675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.927207675
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.1878550006
Short name T2853
Test name
Test status
Simulation time 152204229 ps
CPU time 0.85 seconds
Started Aug 18 05:38:36 PM PDT 24
Finished Aug 18 05:38:37 PM PDT 24
Peak memory 207468 kb
Host smart-a4ed2ce9-0adc-4f2a-8ffd-6212ffa9402a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18785
50006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.1878550006
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.1487227353
Short name T1828
Test name
Test status
Simulation time 64392554 ps
CPU time 0.72 seconds
Started Aug 18 05:38:08 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207388 kb
Host smart-a53be7d9-7f09-4618-ae87-49555cd9bd29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14872
27353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1487227353
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3657043016
Short name T1841
Test name
Test status
Simulation time 795796363 ps
CPU time 2.19 seconds
Started Aug 18 05:38:37 PM PDT 24
Finished Aug 18 05:38:39 PM PDT 24
Peak memory 207796 kb
Host smart-736dbaa9-41bd-482d-a94c-8e3ba84172ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36570
43016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3657043016
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1359819745
Short name T886
Test name
Test status
Simulation time 158765911 ps
CPU time 1.32 seconds
Started Aug 18 05:38:19 PM PDT 24
Finished Aug 18 05:38:21 PM PDT 24
Peak memory 207656 kb
Host smart-90e23951-28da-4744-be03-c340c8aba153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13598
19745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1359819745
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2299840464
Short name T3123
Test name
Test status
Simulation time 192765110 ps
CPU time 0.98 seconds
Started Aug 18 05:38:11 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 215908 kb
Host smart-c7143bff-38d4-4d69-9449-8b3c1941f340
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2299840464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2299840464
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2419582411
Short name T1262
Test name
Test status
Simulation time 186451742 ps
CPU time 0.84 seconds
Started Aug 18 05:38:12 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 207288 kb
Host smart-c8790c47-1b80-489f-9c57-1a68cee2e964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24195
82411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2419582411
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2955275854
Short name T3523
Test name
Test status
Simulation time 236983372 ps
CPU time 1.08 seconds
Started Aug 18 05:38:08 PM PDT 24
Finished Aug 18 05:38:09 PM PDT 24
Peak memory 207496 kb
Host smart-9072a9b2-b708-4bf8-91dd-26bd0f785958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29552
75854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2955275854
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.211931369
Short name T1420
Test name
Test status
Simulation time 3285901343 ps
CPU time 91.87 seconds
Started Aug 18 05:38:42 PM PDT 24
Finished Aug 18 05:40:14 PM PDT 24
Peak memory 216008 kb
Host smart-93d8d8b1-a688-49e8-aa36-5b3d1ac83a21
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=211931369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.211931369
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.287982468
Short name T1065
Test name
Test status
Simulation time 3668201645 ps
CPU time 45.94 seconds
Started Aug 18 05:38:19 PM PDT 24
Finished Aug 18 05:39:10 PM PDT 24
Peak memory 207784 kb
Host smart-1da3a980-504a-4c57-99df-97e99237fc9b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=287982468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.287982468
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.3200614784
Short name T1141
Test name
Test status
Simulation time 193037732 ps
CPU time 0.95 seconds
Started Aug 18 05:38:37 PM PDT 24
Finished Aug 18 05:38:38 PM PDT 24
Peak memory 207536 kb
Host smart-3b3ff019-3f37-4ffe-bb1f-b5de06b1ce51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32006
14784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3200614784
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.3207274140
Short name T3462
Test name
Test status
Simulation time 14065286480 ps
CPU time 20.82 seconds
Started Aug 18 05:38:24 PM PDT 24
Finished Aug 18 05:38:45 PM PDT 24
Peak memory 207812 kb
Host smart-2a9bb76a-ea06-4037-90f1-b7420059bf20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32072
74140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.3207274140
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3504908271
Short name T2795
Test name
Test status
Simulation time 5403246264 ps
CPU time 7.42 seconds
Started Aug 18 05:38:09 PM PDT 24
Finished Aug 18 05:38:16 PM PDT 24
Peak memory 207788 kb
Host smart-7037ec72-e733-4cd2-95cb-98f6c0741e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35049
08271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3504908271
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1542216146
Short name T1816
Test name
Test status
Simulation time 4518671379 ps
CPU time 37.47 seconds
Started Aug 18 05:38:22 PM PDT 24
Finished Aug 18 05:38:59 PM PDT 24
Peak memory 219284 kb
Host smart-0b2f5636-8c6d-48a5-b7ed-2397888d6f81
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1542216146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1542216146
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.4050999108
Short name T1956
Test name
Test status
Simulation time 2278578478 ps
CPU time 67.65 seconds
Started Aug 18 05:38:20 PM PDT 24
Finished Aug 18 05:39:33 PM PDT 24
Peak memory 216948 kb
Host smart-75f14c9f-a0a8-4660-83ad-749ac9c960e0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4050999108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.4050999108
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.4179049832
Short name T1070
Test name
Test status
Simulation time 248255284 ps
CPU time 1.12 seconds
Started Aug 18 05:38:06 PM PDT 24
Finished Aug 18 05:38:07 PM PDT 24
Peak memory 207480 kb
Host smart-c94c9a70-b262-488c-9eb8-06f42b627ee4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4179049832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.4179049832
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.2652952748
Short name T3221
Test name
Test status
Simulation time 207312414 ps
CPU time 0.98 seconds
Started Aug 18 05:38:29 PM PDT 24
Finished Aug 18 05:38:30 PM PDT 24
Peak memory 207464 kb
Host smart-f35c3c86-4f16-47f1-bc65-cad2466519e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26529
52748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.2652952748
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.1577619900
Short name T1567
Test name
Test status
Simulation time 2758553665 ps
CPU time 76.69 seconds
Started Aug 18 05:38:18 PM PDT 24
Finished Aug 18 05:39:35 PM PDT 24
Peak memory 217548 kb
Host smart-6d39422f-aaaf-4c23-88ce-bd44225a5101
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1577619900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.1577619900
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.1543426367
Short name T712
Test name
Test status
Simulation time 166094803 ps
CPU time 0.86 seconds
Started Aug 18 05:38:11 PM PDT 24
Finished Aug 18 05:38:12 PM PDT 24
Peak memory 207412 kb
Host smart-9e0ce5b8-d293-44ba-9351-b227fbc6c95e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1543426367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.1543426367
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.36252881
Short name T1019
Test name
Test status
Simulation time 203657023 ps
CPU time 0.87 seconds
Started Aug 18 05:38:15 PM PDT 24
Finished Aug 18 05:38:16 PM PDT 24
Peak memory 207524 kb
Host smart-53b03881-0106-484d-8da0-9d3d536e7f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36252
881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.36252881
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2114119835
Short name T175
Test name
Test status
Simulation time 215062695 ps
CPU time 0.96 seconds
Started Aug 18 05:38:25 PM PDT 24
Finished Aug 18 05:38:26 PM PDT 24
Peak memory 207444 kb
Host smart-dcf18e85-00fd-442f-8265-731fcd2a96e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21141
19835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2114119835
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.1733037808
Short name T1719
Test name
Test status
Simulation time 196584463 ps
CPU time 0.93 seconds
Started Aug 18 05:38:20 PM PDT 24
Finished Aug 18 05:38:21 PM PDT 24
Peak memory 207432 kb
Host smart-80d92870-a252-41b7-9df5-4925115d3653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17330
37808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.1733037808
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2860813782
Short name T1185
Test name
Test status
Simulation time 173207837 ps
CPU time 0.84 seconds
Started Aug 18 05:38:07 PM PDT 24
Finished Aug 18 05:38:08 PM PDT 24
Peak memory 207472 kb
Host smart-b46c45c3-2181-45a7-941b-1b2f9e471cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28608
13782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2860813782
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.457290017
Short name T1362
Test name
Test status
Simulation time 183820844 ps
CPU time 0.85 seconds
Started Aug 18 05:38:12 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 207520 kb
Host smart-74769549-3966-453e-9b20-5c1740683e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45729
0017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.457290017
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2349906495
Short name T3472
Test name
Test status
Simulation time 160608332 ps
CPU time 0.91 seconds
Started Aug 18 05:38:24 PM PDT 24
Finished Aug 18 05:38:25 PM PDT 24
Peak memory 207544 kb
Host smart-803461f7-ff97-469e-a7dd-4855b8308840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23499
06495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2349906495
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3902541029
Short name T933
Test name
Test status
Simulation time 246537455 ps
CPU time 1.04 seconds
Started Aug 18 05:38:17 PM PDT 24
Finished Aug 18 05:38:18 PM PDT 24
Peak memory 207576 kb
Host smart-a8531521-8893-4705-af56-22a16f5fb9bf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3902541029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3902541029
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1759013274
Short name T3152
Test name
Test status
Simulation time 160556967 ps
CPU time 0.89 seconds
Started Aug 18 05:38:14 PM PDT 24
Finished Aug 18 05:38:20 PM PDT 24
Peak memory 207456 kb
Host smart-9ec3f1ec-5fd6-4272-9c62-37e5e9583798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17590
13274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1759013274
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.238817277
Short name T26
Test name
Test status
Simulation time 32964788 ps
CPU time 0.68 seconds
Started Aug 18 05:38:22 PM PDT 24
Finished Aug 18 05:38:23 PM PDT 24
Peak memory 207532 kb
Host smart-00f0c775-ef46-437a-9911-fe7caf86b3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23881
7277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.238817277
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2676974921
Short name T1857
Test name
Test status
Simulation time 7089867180 ps
CPU time 17.42 seconds
Started Aug 18 05:38:25 PM PDT 24
Finished Aug 18 05:38:42 PM PDT 24
Peak memory 216012 kb
Host smart-4284c078-8c84-4fb8-8ebd-832db3a3122d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26769
74921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2676974921
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1157660365
Short name T3186
Test name
Test status
Simulation time 183311202 ps
CPU time 0.97 seconds
Started Aug 18 05:38:14 PM PDT 24
Finished Aug 18 05:38:15 PM PDT 24
Peak memory 207600 kb
Host smart-149c219d-c567-4120-8646-bd80a2c78420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11576
60365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1157660365
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2768587845
Short name T1068
Test name
Test status
Simulation time 194370938 ps
CPU time 0.94 seconds
Started Aug 18 05:38:14 PM PDT 24
Finished Aug 18 05:38:15 PM PDT 24
Peak memory 207460 kb
Host smart-bc0426b9-c737-4cbf-ba11-bd0358ff3761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27685
87845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2768587845
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.1177208847
Short name T1246
Test name
Test status
Simulation time 226329234 ps
CPU time 1.08 seconds
Started Aug 18 05:38:14 PM PDT 24
Finished Aug 18 05:38:15 PM PDT 24
Peak memory 207452 kb
Host smart-5d1196cf-bf8e-48d6-9cf3-3fbbea61d6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11772
08847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.1177208847
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.945529950
Short name T2914
Test name
Test status
Simulation time 161752087 ps
CPU time 0.93 seconds
Started Aug 18 05:38:43 PM PDT 24
Finished Aug 18 05:38:44 PM PDT 24
Peak memory 207424 kb
Host smart-8f2ee54e-dda2-43dd-9d1a-2434c8a02725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94552
9950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.945529950
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.495001587
Short name T1099
Test name
Test status
Simulation time 179027824 ps
CPU time 0.86 seconds
Started Aug 18 05:38:21 PM PDT 24
Finished Aug 18 05:38:22 PM PDT 24
Peak memory 207452 kb
Host smart-a01529ec-aabf-40e6-9cdf-1c9c8096e902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49500
1587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.495001587
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_rx_full.724832802
Short name T3243
Test name
Test status
Simulation time 257618400 ps
CPU time 1.11 seconds
Started Aug 18 05:38:29 PM PDT 24
Finished Aug 18 05:38:30 PM PDT 24
Peak memory 207484 kb
Host smart-d02f3402-c194-4e84-9110-66f7706f632a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72483
2802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_full.724832802
Directory /workspace/45.usbdev_rx_full/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1190170695
Short name T1462
Test name
Test status
Simulation time 146496364 ps
CPU time 0.8 seconds
Started Aug 18 05:38:15 PM PDT 24
Finished Aug 18 05:38:16 PM PDT 24
Peak memory 207540 kb
Host smart-15115790-51c4-4668-804e-9f081d62a34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11901
70695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1190170695
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3837855518
Short name T3528
Test name
Test status
Simulation time 144769894 ps
CPU time 0.83 seconds
Started Aug 18 05:38:16 PM PDT 24
Finished Aug 18 05:38:17 PM PDT 24
Peak memory 207496 kb
Host smart-7302b4bf-4ca6-401f-9941-41291701df1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38378
55518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3837855518
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.4197562975
Short name T2468
Test name
Test status
Simulation time 238378958 ps
CPU time 0.99 seconds
Started Aug 18 05:38:24 PM PDT 24
Finished Aug 18 05:38:26 PM PDT 24
Peak memory 207436 kb
Host smart-5f4a06fc-5ece-428f-8339-fd846561dea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41975
62975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.4197562975
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.1576854133
Short name T1040
Test name
Test status
Simulation time 2504469021 ps
CPU time 19.75 seconds
Started Aug 18 05:38:43 PM PDT 24
Finished Aug 18 05:39:03 PM PDT 24
Peak memory 217920 kb
Host smart-b7304f6c-3980-4e42-8d60-875e34f8f848
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1576854133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.1576854133
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.855810565
Short name T2147
Test name
Test status
Simulation time 196195041 ps
CPU time 0.89 seconds
Started Aug 18 05:38:12 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 207516 kb
Host smart-306c7cb5-d88c-4494-9f61-cbb3945f53b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85581
0565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.855810565
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1057934513
Short name T2597
Test name
Test status
Simulation time 159580946 ps
CPU time 0.86 seconds
Started Aug 18 05:38:39 PM PDT 24
Finished Aug 18 05:38:40 PM PDT 24
Peak memory 207544 kb
Host smart-e5d46697-6a55-451e-baf4-7bd9761ab875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10579
34513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1057934513
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.827219539
Short name T638
Test name
Test status
Simulation time 965262505 ps
CPU time 2.43 seconds
Started Aug 18 05:38:16 PM PDT 24
Finished Aug 18 05:38:18 PM PDT 24
Peak memory 207660 kb
Host smart-1c021ead-a1a6-4247-b7a0-54da12f55f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82721
9539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.827219539
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.3656625633
Short name T929
Test name
Test status
Simulation time 1918390536 ps
CPU time 54.46 seconds
Started Aug 18 05:38:12 PM PDT 24
Finished Aug 18 05:39:06 PM PDT 24
Peak memory 215828 kb
Host smart-47a6c946-fa08-41f4-a228-b7812ba92277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36566
25633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.3656625633
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.2633234707
Short name T3517
Test name
Test status
Simulation time 446997702 ps
CPU time 8.14 seconds
Started Aug 18 05:38:37 PM PDT 24
Finished Aug 18 05:38:45 PM PDT 24
Peak memory 207672 kb
Host smart-bedc16a9-da46-4d4d-9ca8-175e6df4f989
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633234707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_hos
t_handshake.2633234707
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_tx_rx_disruption.2047023971
Short name T2984
Test name
Test status
Simulation time 550848368 ps
CPU time 1.48 seconds
Started Aug 18 05:38:17 PM PDT 24
Finished Aug 18 05:38:19 PM PDT 24
Peak memory 207464 kb
Host smart-01ecc10c-d3d3-42c1-bfde-ce044b806d64
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047023971 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.usbdev_tx_rx_disruption.2047023971
Directory /workspace/45.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/450.usbdev_tx_rx_disruption.854710931
Short name T3161
Test name
Test status
Simulation time 524942116 ps
CPU time 1.63 seconds
Started Aug 18 05:40:05 PM PDT 24
Finished Aug 18 05:40:07 PM PDT 24
Peak memory 207592 kb
Host smart-7bcc345c-a0d4-40a0-8fbc-a46fe62d5a97
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854710931 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 450.usbdev_tx_rx_disruption.854710931
Directory /workspace/450.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/451.usbdev_tx_rx_disruption.1075020387
Short name T2233
Test name
Test status
Simulation time 558587143 ps
CPU time 1.75 seconds
Started Aug 18 05:40:26 PM PDT 24
Finished Aug 18 05:40:28 PM PDT 24
Peak memory 207604 kb
Host smart-374a9f4d-6910-4ebb-8cee-6abc01f2bfe7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075020387 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 451.usbdev_tx_rx_disruption.1075020387
Directory /workspace/451.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/452.usbdev_tx_rx_disruption.1835080650
Short name T211
Test name
Test status
Simulation time 519420335 ps
CPU time 1.56 seconds
Started Aug 18 05:40:27 PM PDT 24
Finished Aug 18 05:40:39 PM PDT 24
Peak memory 207552 kb
Host smart-c6e9a615-910e-43d5-a9c5-f83714541f6d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835080650 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 452.usbdev_tx_rx_disruption.1835080650
Directory /workspace/452.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/453.usbdev_tx_rx_disruption.4125554189
Short name T3285
Test name
Test status
Simulation time 572507328 ps
CPU time 1.56 seconds
Started Aug 18 05:40:13 PM PDT 24
Finished Aug 18 05:40:15 PM PDT 24
Peak memory 207560 kb
Host smart-72d9ab94-b748-4b02-ab29-64442e19f385
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125554189 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 453.usbdev_tx_rx_disruption.4125554189
Directory /workspace/453.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/454.usbdev_tx_rx_disruption.1925455495
Short name T2021
Test name
Test status
Simulation time 632475986 ps
CPU time 1.64 seconds
Started Aug 18 05:40:09 PM PDT 24
Finished Aug 18 05:40:11 PM PDT 24
Peak memory 207532 kb
Host smart-008e34ab-eaf4-4e97-aa83-d517c5d51a20
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925455495 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 454.usbdev_tx_rx_disruption.1925455495
Directory /workspace/454.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/455.usbdev_tx_rx_disruption.3981494425
Short name T1625
Test name
Test status
Simulation time 562203588 ps
CPU time 1.51 seconds
Started Aug 18 05:40:01 PM PDT 24
Finished Aug 18 05:40:03 PM PDT 24
Peak memory 207568 kb
Host smart-b5e8d770-5477-4eb7-9780-54c617d1056e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981494425 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 455.usbdev_tx_rx_disruption.3981494425
Directory /workspace/455.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/456.usbdev_tx_rx_disruption.2105047071
Short name T1095
Test name
Test status
Simulation time 551730067 ps
CPU time 1.79 seconds
Started Aug 18 05:40:08 PM PDT 24
Finished Aug 18 05:40:10 PM PDT 24
Peak memory 207524 kb
Host smart-dc2300be-91cd-410c-aa92-bd04fcfc4ff1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105047071 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 456.usbdev_tx_rx_disruption.2105047071
Directory /workspace/456.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/457.usbdev_tx_rx_disruption.3638137042
Short name T1294
Test name
Test status
Simulation time 429359154 ps
CPU time 1.46 seconds
Started Aug 18 05:40:18 PM PDT 24
Finished Aug 18 05:40:19 PM PDT 24
Peak memory 207520 kb
Host smart-d18d3297-3813-4a22-aa93-beb8f8798dc1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638137042 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 457.usbdev_tx_rx_disruption.3638137042
Directory /workspace/457.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/458.usbdev_tx_rx_disruption.2414257081
Short name T2996
Test name
Test status
Simulation time 472583124 ps
CPU time 1.5 seconds
Started Aug 18 05:40:10 PM PDT 24
Finished Aug 18 05:40:12 PM PDT 24
Peak memory 207580 kb
Host smart-88a8069f-c3df-4da1-9d64-9c42ee1c7452
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414257081 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 458.usbdev_tx_rx_disruption.2414257081
Directory /workspace/458.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/459.usbdev_tx_rx_disruption.2059013459
Short name T827
Test name
Test status
Simulation time 501791448 ps
CPU time 1.46 seconds
Started Aug 18 05:40:15 PM PDT 24
Finished Aug 18 05:40:17 PM PDT 24
Peak memory 207548 kb
Host smart-d11adbd5-51cf-4f8f-9c8d-cf74f9fb6928
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059013459 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 459.usbdev_tx_rx_disruption.2059013459
Directory /workspace/459.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.1885707229
Short name T233
Test name
Test status
Simulation time 38746506 ps
CPU time 0.65 seconds
Started Aug 18 05:38:18 PM PDT 24
Finished Aug 18 05:38:19 PM PDT 24
Peak memory 207432 kb
Host smart-4377b90b-aa65-4600-813d-ddf512407749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1885707229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1885707229
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.2698597592
Short name T3492
Test name
Test status
Simulation time 10142628865 ps
CPU time 12.49 seconds
Started Aug 18 05:38:20 PM PDT 24
Finished Aug 18 05:38:33 PM PDT 24
Peak memory 207792 kb
Host smart-e92fe369-cbd4-485d-950d-b033423a6b28
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698597592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.2698597592
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.3764866090
Short name T2978
Test name
Test status
Simulation time 20561953334 ps
CPU time 25.43 seconds
Started Aug 18 05:38:29 PM PDT 24
Finished Aug 18 05:38:54 PM PDT 24
Peak memory 207812 kb
Host smart-e17dd2bc-bf50-4bad-9c6b-673453fd1518
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764866090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.3764866090
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.642349652
Short name T2617
Test name
Test status
Simulation time 23977309358 ps
CPU time 29.21 seconds
Started Aug 18 05:38:13 PM PDT 24
Finished Aug 18 05:38:42 PM PDT 24
Peak memory 216004 kb
Host smart-f2cdbd5f-1b21-4ac1-9bf7-d0afe45208bc
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642349652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_ao
n_wake_resume.642349652
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.524421301
Short name T2236
Test name
Test status
Simulation time 150468136 ps
CPU time 0.84 seconds
Started Aug 18 05:38:24 PM PDT 24
Finished Aug 18 05:38:24 PM PDT 24
Peak memory 207492 kb
Host smart-f530135e-3ab0-4f95-8bb6-589658b30020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52442
1301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.524421301
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.9635053
Short name T3494
Test name
Test status
Simulation time 141913100 ps
CPU time 0.84 seconds
Started Aug 18 05:38:12 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 207380 kb
Host smart-9bc995d7-670d-499b-b5bd-dc7c40e4d7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96350
53 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.9635053
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3631470936
Short name T1165
Test name
Test status
Simulation time 266482534 ps
CPU time 1.09 seconds
Started Aug 18 05:38:23 PM PDT 24
Finished Aug 18 05:38:24 PM PDT 24
Peak memory 207528 kb
Host smart-a018fab5-ce1f-4824-ad56-ae89d01a533f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36314
70936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3631470936
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.696667403
Short name T2964
Test name
Test status
Simulation time 778917773 ps
CPU time 2.04 seconds
Started Aug 18 05:38:15 PM PDT 24
Finished Aug 18 05:38:17 PM PDT 24
Peak memory 207800 kb
Host smart-f6619fa9-f0b3-445b-b5b0-2911b4977a1c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=696667403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.696667403
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.3593680859
Short name T213
Test name
Test status
Simulation time 22167473149 ps
CPU time 38.31 seconds
Started Aug 18 05:38:42 PM PDT 24
Finished Aug 18 05:39:20 PM PDT 24
Peak memory 207804 kb
Host smart-dba4b64e-bc16-486c-b6a8-5a6f27bd974d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35936
80859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.3593680859
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.3236322866
Short name T1077
Test name
Test status
Simulation time 3869069523 ps
CPU time 32.89 seconds
Started Aug 18 05:38:34 PM PDT 24
Finished Aug 18 05:39:07 PM PDT 24
Peak memory 207812 kb
Host smart-6508676c-cbd3-478d-ad0e-fbfc47673d1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236322866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.3236322866
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.3961782407
Short name T3432
Test name
Test status
Simulation time 767482331 ps
CPU time 1.83 seconds
Started Aug 18 05:38:33 PM PDT 24
Finished Aug 18 05:38:35 PM PDT 24
Peak memory 207516 kb
Host smart-249c8901-4cb0-4113-8b90-1b54019fcbd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39617
82407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3961782407
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.2772892211
Short name T2949
Test name
Test status
Simulation time 136154655 ps
CPU time 0.79 seconds
Started Aug 18 05:38:21 PM PDT 24
Finished Aug 18 05:38:22 PM PDT 24
Peak memory 207548 kb
Host smart-70c41216-a4ce-4719-b91f-f2da87f4eb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27728
92211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.2772892211
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.202207000
Short name T2627
Test name
Test status
Simulation time 38348315 ps
CPU time 0.71 seconds
Started Aug 18 05:38:27 PM PDT 24
Finished Aug 18 05:38:28 PM PDT 24
Peak memory 207444 kb
Host smart-7a4527b3-76da-4865-84e8-10843f69da53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20220
7000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.202207000
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.2929960619
Short name T572
Test name
Test status
Simulation time 972554008 ps
CPU time 2.45 seconds
Started Aug 18 05:38:14 PM PDT 24
Finished Aug 18 05:38:16 PM PDT 24
Peak memory 207712 kb
Host smart-6ff60fc1-3ea2-4e89-8142-6e01af49e43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29299
60619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.2929960619
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_types.276677601
Short name T471
Test name
Test status
Simulation time 234427857 ps
CPU time 1.02 seconds
Started Aug 18 05:38:21 PM PDT 24
Finished Aug 18 05:38:22 PM PDT 24
Peak memory 207532 kb
Host smart-6030533c-ff80-494f-938e-0fd8b490dc55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=276677601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_types.276677601
Directory /workspace/46.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2600124276
Short name T2491
Test name
Test status
Simulation time 288230376 ps
CPU time 2.14 seconds
Started Aug 18 05:38:40 PM PDT 24
Finished Aug 18 05:38:42 PM PDT 24
Peak memory 207688 kb
Host smart-9844015e-32e4-4534-9efb-715c6c2640b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26001
24276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2600124276
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1266273397
Short name T1815
Test name
Test status
Simulation time 186989670 ps
CPU time 0.99 seconds
Started Aug 18 05:38:24 PM PDT 24
Finished Aug 18 05:38:25 PM PDT 24
Peak memory 207444 kb
Host smart-74ddd7e9-2e52-4975-8748-3df51ca4613b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1266273397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1266273397
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.2705100039
Short name T2523
Test name
Test status
Simulation time 149861054 ps
CPU time 0.84 seconds
Started Aug 18 05:38:18 PM PDT 24
Finished Aug 18 05:38:18 PM PDT 24
Peak memory 207428 kb
Host smart-c28634a2-6d6d-4bdc-9e28-616209b67e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27051
00039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2705100039
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3872442832
Short name T3429
Test name
Test status
Simulation time 254665057 ps
CPU time 1.05 seconds
Started Aug 18 05:38:47 PM PDT 24
Finished Aug 18 05:38:48 PM PDT 24
Peak memory 207504 kb
Host smart-6ed81fa7-d02f-41c4-9235-e222cf062932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38724
42832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3872442832
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.1184875047
Short name T1588
Test name
Test status
Simulation time 2424337958 ps
CPU time 22.94 seconds
Started Aug 18 05:38:20 PM PDT 24
Finished Aug 18 05:38:43 PM PDT 24
Peak memory 215988 kb
Host smart-d962507a-931b-4ab6-a789-49be677f7887
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1184875047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.1184875047
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.1996578551
Short name T1000
Test name
Test status
Simulation time 13278890187 ps
CPU time 92.54 seconds
Started Aug 18 05:38:34 PM PDT 24
Finished Aug 18 05:40:07 PM PDT 24
Peak memory 207804 kb
Host smart-08b64a01-56c7-4fee-9d78-1517a9c78da0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1996578551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.1996578551
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.205274516
Short name T1076
Test name
Test status
Simulation time 177103454 ps
CPU time 0.9 seconds
Started Aug 18 05:38:36 PM PDT 24
Finished Aug 18 05:38:37 PM PDT 24
Peak memory 207488 kb
Host smart-7642ca88-9c48-4335-a368-f0b7c6db001b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20527
4516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.205274516
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.4276622234
Short name T2399
Test name
Test status
Simulation time 29941215128 ps
CPU time 45.15 seconds
Started Aug 18 05:38:22 PM PDT 24
Finished Aug 18 05:39:07 PM PDT 24
Peak memory 207804 kb
Host smart-c369bb3f-047a-48be-837e-ad4e79815004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42766
22234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.4276622234
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.1946358390
Short name T2687
Test name
Test status
Simulation time 3690078838 ps
CPU time 5.5 seconds
Started Aug 18 05:38:30 PM PDT 24
Finished Aug 18 05:38:36 PM PDT 24
Peak memory 216200 kb
Host smart-574a13d1-73b7-42e8-be0b-d2eae3116a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19463
58390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1946358390
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.1019528035
Short name T1248
Test name
Test status
Simulation time 3222366314 ps
CPU time 25.65 seconds
Started Aug 18 05:38:44 PM PDT 24
Finished Aug 18 05:39:10 PM PDT 24
Peak memory 219304 kb
Host smart-f0e75b72-4637-4119-8230-cd377eb98533
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1019528035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.1019528035
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.2859684691
Short name T2889
Test name
Test status
Simulation time 2067261401 ps
CPU time 21.06 seconds
Started Aug 18 05:38:20 PM PDT 24
Finished Aug 18 05:38:41 PM PDT 24
Peak memory 217140 kb
Host smart-5e9aee44-627a-4b63-bbf5-1eb66afa6c1d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2859684691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.2859684691
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.2841869802
Short name T2641
Test name
Test status
Simulation time 249883656 ps
CPU time 1 seconds
Started Aug 18 05:38:25 PM PDT 24
Finished Aug 18 05:38:26 PM PDT 24
Peak memory 207504 kb
Host smart-c53249a5-67f1-4489-98b1-315ac4e326f8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2841869802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.2841869802
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1243604127
Short name T582
Test name
Test status
Simulation time 190436116 ps
CPU time 0.92 seconds
Started Aug 18 05:38:29 PM PDT 24
Finished Aug 18 05:38:30 PM PDT 24
Peak memory 207476 kb
Host smart-6a54e50c-df2d-41b0-9ec1-0958484bc854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12436
04127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1243604127
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.2573664376
Short name T1377
Test name
Test status
Simulation time 3946676310 ps
CPU time 111.18 seconds
Started Aug 18 05:38:24 PM PDT 24
Finished Aug 18 05:40:15 PM PDT 24
Peak memory 217272 kb
Host smart-8d7cd25e-f07c-4086-8de0-e767f105861a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2573664376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.2573664376
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.976774354
Short name T3131
Test name
Test status
Simulation time 150479592 ps
CPU time 0.87 seconds
Started Aug 18 05:38:34 PM PDT 24
Finished Aug 18 05:38:35 PM PDT 24
Peak memory 207496 kb
Host smart-41e3230e-7cf9-4096-b2f9-bdadd621a17c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=976774354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.976774354
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.4020655382
Short name T3098
Test name
Test status
Simulation time 141764633 ps
CPU time 0.89 seconds
Started Aug 18 05:38:27 PM PDT 24
Finished Aug 18 05:38:28 PM PDT 24
Peak memory 207500 kb
Host smart-f0cdf2f9-7322-4a84-a62b-3d8051ea9444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40206
55382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.4020655382
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.174674762
Short name T3385
Test name
Test status
Simulation time 239974994 ps
CPU time 0.95 seconds
Started Aug 18 05:38:24 PM PDT 24
Finished Aug 18 05:38:26 PM PDT 24
Peak memory 207436 kb
Host smart-8807c0f9-c29e-440b-8810-9a413e652134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17467
4762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.174674762
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3810067441
Short name T2891
Test name
Test status
Simulation time 183828787 ps
CPU time 0.96 seconds
Started Aug 18 05:38:31 PM PDT 24
Finished Aug 18 05:38:32 PM PDT 24
Peak memory 207388 kb
Host smart-961fb274-ee05-4b73-a607-4ba315eaf0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38100
67441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3810067441
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3936357967
Short name T1747
Test name
Test status
Simulation time 158531408 ps
CPU time 0.97 seconds
Started Aug 18 05:38:29 PM PDT 24
Finished Aug 18 05:38:30 PM PDT 24
Peak memory 207448 kb
Host smart-0261eff6-117b-4310-8760-dff5952bb142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39363
57967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3936357967
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2219559014
Short name T1755
Test name
Test status
Simulation time 183800911 ps
CPU time 0.88 seconds
Started Aug 18 05:38:29 PM PDT 24
Finished Aug 18 05:38:30 PM PDT 24
Peak memory 207552 kb
Host smart-7ba985f6-9ad7-4554-9595-f7e73efb99f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22195
59014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2219559014
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1860387121
Short name T217
Test name
Test status
Simulation time 163605713 ps
CPU time 0.85 seconds
Started Aug 18 05:38:22 PM PDT 24
Finished Aug 18 05:38:23 PM PDT 24
Peak memory 207552 kb
Host smart-1d3985e5-1ab3-4160-a475-0467e15f65c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18603
87121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1860387121
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.1672071493
Short name T1703
Test name
Test status
Simulation time 215135523 ps
CPU time 1.04 seconds
Started Aug 18 05:38:19 PM PDT 24
Finished Aug 18 05:38:20 PM PDT 24
Peak memory 207532 kb
Host smart-4761544f-45b9-4036-9b88-2fafd5b7bde6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1672071493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.1672071493
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.454281001
Short name T2605
Test name
Test status
Simulation time 151370086 ps
CPU time 0.84 seconds
Started Aug 18 05:38:41 PM PDT 24
Finished Aug 18 05:38:42 PM PDT 24
Peak memory 207440 kb
Host smart-0f2795d0-40b3-4f17-a8e8-385c84f4a57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45428
1001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.454281001
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1068023486
Short name T3356
Test name
Test status
Simulation time 29955581 ps
CPU time 0.69 seconds
Started Aug 18 05:38:25 PM PDT 24
Finished Aug 18 05:38:25 PM PDT 24
Peak memory 207444 kb
Host smart-62239df6-0b13-4bde-8008-efc72a6356f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10680
23486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1068023486
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2046122083
Short name T2995
Test name
Test status
Simulation time 22305897333 ps
CPU time 55.33 seconds
Started Aug 18 05:38:27 PM PDT 24
Finished Aug 18 05:39:22 PM PDT 24
Peak memory 215940 kb
Host smart-b91afeb1-2d53-4d18-97ce-f11bfb86cde0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20461
22083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2046122083
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.728343503
Short name T1661
Test name
Test status
Simulation time 147870218 ps
CPU time 0.85 seconds
Started Aug 18 05:38:31 PM PDT 24
Finished Aug 18 05:38:32 PM PDT 24
Peak memory 207536 kb
Host smart-5fc2d4a4-8717-4a78-b0e3-d8f36929e0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72834
3503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.728343503
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3336527438
Short name T2092
Test name
Test status
Simulation time 191721969 ps
CPU time 0.9 seconds
Started Aug 18 05:38:25 PM PDT 24
Finished Aug 18 05:38:26 PM PDT 24
Peak memory 207480 kb
Host smart-f30b7017-50c6-419c-8263-0b2a986865aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33365
27438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3336527438
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.298044853
Short name T1357
Test name
Test status
Simulation time 213499990 ps
CPU time 0.92 seconds
Started Aug 18 05:38:22 PM PDT 24
Finished Aug 18 05:38:23 PM PDT 24
Peak memory 207468 kb
Host smart-a63812ee-2fec-4cad-92ef-98213e2df35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29804
4853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.298044853
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1720053778
Short name T1229
Test name
Test status
Simulation time 180584162 ps
CPU time 0.92 seconds
Started Aug 18 05:38:42 PM PDT 24
Finished Aug 18 05:38:43 PM PDT 24
Peak memory 207464 kb
Host smart-87e151ba-074d-4cfc-b100-3d9603a2f0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17200
53778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1720053778
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3261901809
Short name T688
Test name
Test status
Simulation time 218956937 ps
CPU time 0.96 seconds
Started Aug 18 05:38:49 PM PDT 24
Finished Aug 18 05:38:51 PM PDT 24
Peak memory 207636 kb
Host smart-8881af07-1beb-4d38-89da-2981f8d6412b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32619
01809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3261901809
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_rx_full.1253735566
Short name T344
Test name
Test status
Simulation time 352113446 ps
CPU time 1.36 seconds
Started Aug 18 05:38:32 PM PDT 24
Finished Aug 18 05:38:33 PM PDT 24
Peak memory 207464 kb
Host smart-5f5e32ff-b2ce-43f3-822b-83062e3cd206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12537
35566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_full.1253735566
Directory /workspace/46.usbdev_rx_full/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2800518487
Short name T1854
Test name
Test status
Simulation time 155378254 ps
CPU time 0.9 seconds
Started Aug 18 05:38:29 PM PDT 24
Finished Aug 18 05:38:30 PM PDT 24
Peak memory 207496 kb
Host smart-2dd4432e-58e8-4826-b321-9175e7a5df95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28005
18487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2800518487
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2455788680
Short name T2815
Test name
Test status
Simulation time 152683728 ps
CPU time 0.93 seconds
Started Aug 18 05:38:23 PM PDT 24
Finished Aug 18 05:38:24 PM PDT 24
Peak memory 207452 kb
Host smart-9d9fbcfc-b07b-4c49-947a-dc5d670bac80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24557
88680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2455788680
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3328305081
Short name T2644
Test name
Test status
Simulation time 257377353 ps
CPU time 1.06 seconds
Started Aug 18 05:38:42 PM PDT 24
Finished Aug 18 05:38:43 PM PDT 24
Peak memory 207440 kb
Host smart-64c88adc-d3b2-4450-b72b-1f47b7c1b680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33283
05081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3328305081
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.333761637
Short name T2511
Test name
Test status
Simulation time 2855439638 ps
CPU time 21.82 seconds
Started Aug 18 05:38:48 PM PDT 24
Finished Aug 18 05:39:10 PM PDT 24
Peak memory 207740 kb
Host smart-1c557d2c-7d00-4984-856d-960ffacc84fd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=333761637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.333761637
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.886953891
Short name T2454
Test name
Test status
Simulation time 182174641 ps
CPU time 0.91 seconds
Started Aug 18 05:38:39 PM PDT 24
Finished Aug 18 05:38:40 PM PDT 24
Peak memory 207504 kb
Host smart-e59fd23f-7e58-4f30-963a-3243fa4eae36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88695
3891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.886953891
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.4290417222
Short name T3465
Test name
Test status
Simulation time 142179860 ps
CPU time 0.83 seconds
Started Aug 18 05:38:24 PM PDT 24
Finished Aug 18 05:38:25 PM PDT 24
Peak memory 207568 kb
Host smart-eaace1c5-f3ff-46ab-9542-b6602b836878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42904
17222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.4290417222
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.2874120421
Short name T1031
Test name
Test status
Simulation time 859307459 ps
CPU time 2.1 seconds
Started Aug 18 05:38:37 PM PDT 24
Finished Aug 18 05:38:39 PM PDT 24
Peak memory 207720 kb
Host smart-85d7e045-9ce4-47b9-b9de-9a3322414e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28741
20421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.2874120421
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.1700801126
Short name T701
Test name
Test status
Simulation time 1618615300 ps
CPU time 45.99 seconds
Started Aug 18 05:38:27 PM PDT 24
Finished Aug 18 05:39:14 PM PDT 24
Peak memory 224052 kb
Host smart-4b1a3f68-cb80-4227-97e8-52d73b92d35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17008
01126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.1700801126
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.1282913544
Short name T920
Test name
Test status
Simulation time 4981916292 ps
CPU time 32.62 seconds
Started Aug 18 05:38:11 PM PDT 24
Finished Aug 18 05:38:44 PM PDT 24
Peak memory 207740 kb
Host smart-1749cfae-348c-4e0e-af45-2ae69e8b45de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282913544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_hos
t_handshake.1282913544
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_tx_rx_disruption.1267279771
Short name T3522
Test name
Test status
Simulation time 587277269 ps
CPU time 1.58 seconds
Started Aug 18 05:38:30 PM PDT 24
Finished Aug 18 05:38:32 PM PDT 24
Peak memory 207592 kb
Host smart-336d75fc-5364-42ba-b16a-11e79512596f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267279771 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.usbdev_tx_rx_disruption.1267279771
Directory /workspace/46.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/460.usbdev_tx_rx_disruption.1055658834
Short name T2722
Test name
Test status
Simulation time 540175855 ps
CPU time 1.55 seconds
Started Aug 18 05:40:04 PM PDT 24
Finished Aug 18 05:40:06 PM PDT 24
Peak memory 207520 kb
Host smart-5dc923a1-8444-4d67-af77-b19638b1c9e6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055658834 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 460.usbdev_tx_rx_disruption.1055658834
Directory /workspace/460.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/461.usbdev_tx_rx_disruption.257427410
Short name T3217
Test name
Test status
Simulation time 435462091 ps
CPU time 1.34 seconds
Started Aug 18 05:40:07 PM PDT 24
Finished Aug 18 05:40:09 PM PDT 24
Peak memory 207492 kb
Host smart-dadbd9c8-ba49-4139-bee2-7fb43d3889a8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257427410 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 461.usbdev_tx_rx_disruption.257427410
Directory /workspace/461.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/462.usbdev_tx_rx_disruption.1134838186
Short name T2798
Test name
Test status
Simulation time 506790154 ps
CPU time 1.51 seconds
Started Aug 18 05:40:20 PM PDT 24
Finished Aug 18 05:40:22 PM PDT 24
Peak memory 207472 kb
Host smart-81fb4d62-6c46-404e-b1f5-35dd44f051ad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134838186 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 462.usbdev_tx_rx_disruption.1134838186
Directory /workspace/462.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/463.usbdev_tx_rx_disruption.1776086124
Short name T2866
Test name
Test status
Simulation time 455529114 ps
CPU time 1.6 seconds
Started Aug 18 05:40:23 PM PDT 24
Finished Aug 18 05:40:25 PM PDT 24
Peak memory 207604 kb
Host smart-e7f2de68-d203-4d6a-91d6-95850dd894e5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776086124 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 463.usbdev_tx_rx_disruption.1776086124
Directory /workspace/463.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/464.usbdev_tx_rx_disruption.1874954376
Short name T2470
Test name
Test status
Simulation time 458774039 ps
CPU time 1.46 seconds
Started Aug 18 05:40:30 PM PDT 24
Finished Aug 18 05:40:32 PM PDT 24
Peak memory 207580 kb
Host smart-7b00ce6c-8b60-4cbf-8b6c-88ca672e6ad8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874954376 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 464.usbdev_tx_rx_disruption.1874954376
Directory /workspace/464.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/465.usbdev_tx_rx_disruption.115994226
Short name T3319
Test name
Test status
Simulation time 446313574 ps
CPU time 1.37 seconds
Started Aug 18 05:40:09 PM PDT 24
Finished Aug 18 05:40:11 PM PDT 24
Peak memory 207304 kb
Host smart-6f187e04-e97e-4908-8dd1-9ac41b25e238
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115994226 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 465.usbdev_tx_rx_disruption.115994226
Directory /workspace/465.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/466.usbdev_tx_rx_disruption.1232342791
Short name T3106
Test name
Test status
Simulation time 457203045 ps
CPU time 1.37 seconds
Started Aug 18 05:40:09 PM PDT 24
Finished Aug 18 05:40:11 PM PDT 24
Peak memory 207540 kb
Host smart-a03835aa-f33a-4730-a495-2ed8abe4cad5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232342791 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 466.usbdev_tx_rx_disruption.1232342791
Directory /workspace/466.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/467.usbdev_tx_rx_disruption.351558516
Short name T3414
Test name
Test status
Simulation time 537982178 ps
CPU time 1.68 seconds
Started Aug 18 05:40:11 PM PDT 24
Finished Aug 18 05:40:13 PM PDT 24
Peak memory 207492 kb
Host smart-2fb66ae8-747d-4fa4-9865-91ecac8f5958
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351558516 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 467.usbdev_tx_rx_disruption.351558516
Directory /workspace/467.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/468.usbdev_tx_rx_disruption.2873956446
Short name T2056
Test name
Test status
Simulation time 553260508 ps
CPU time 1.59 seconds
Started Aug 18 05:40:04 PM PDT 24
Finished Aug 18 05:40:05 PM PDT 24
Peak memory 207540 kb
Host smart-d7082fdf-3d65-4435-88d4-7865d1acb068
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873956446 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 468.usbdev_tx_rx_disruption.2873956446
Directory /workspace/468.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/469.usbdev_tx_rx_disruption.1619644235
Short name T2396
Test name
Test status
Simulation time 522383174 ps
CPU time 1.62 seconds
Started Aug 18 05:40:09 PM PDT 24
Finished Aug 18 05:40:11 PM PDT 24
Peak memory 207356 kb
Host smart-1393246f-be90-4aaa-86e3-b9ca9515ef03
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619644235 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 469.usbdev_tx_rx_disruption.1619644235
Directory /workspace/469.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.280089875
Short name T1697
Test name
Test status
Simulation time 73200361 ps
CPU time 0.67 seconds
Started Aug 18 05:38:53 PM PDT 24
Finished Aug 18 05:38:54 PM PDT 24
Peak memory 207248 kb
Host smart-9acb418f-d327-4bf6-b2c7-1cc0f2764bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=280089875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.280089875
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.346317056
Short name T2359
Test name
Test status
Simulation time 5142076103 ps
CPU time 7.63 seconds
Started Aug 18 05:38:46 PM PDT 24
Finished Aug 18 05:38:54 PM PDT 24
Peak memory 216004 kb
Host smart-52710e6c-976f-4e37-a280-1f6b30e08443
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346317056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_ao
n_wake_disconnect.346317056
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.273995354
Short name T955
Test name
Test status
Simulation time 14070984299 ps
CPU time 15.57 seconds
Started Aug 18 05:38:26 PM PDT 24
Finished Aug 18 05:38:42 PM PDT 24
Peak memory 215964 kb
Host smart-5c83d65d-d8e4-409f-9142-532b7fadcdf8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=273995354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.273995354
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1163247336
Short name T2859
Test name
Test status
Simulation time 30985722855 ps
CPU time 43.35 seconds
Started Aug 18 05:38:39 PM PDT 24
Finished Aug 18 05:39:22 PM PDT 24
Peak memory 207764 kb
Host smart-9a2efed3-460f-45b0-a5b1-7a2afe8e5123
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163247336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.1163247336
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1726831244
Short name T1176
Test name
Test status
Simulation time 179934971 ps
CPU time 0.91 seconds
Started Aug 18 05:38:41 PM PDT 24
Finished Aug 18 05:38:42 PM PDT 24
Peak memory 207472 kb
Host smart-37834d07-eb92-4062-87a5-2f8873c159ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17268
31244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1726831244
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.1915410330
Short name T1990
Test name
Test status
Simulation time 145922193 ps
CPU time 0.84 seconds
Started Aug 18 05:38:37 PM PDT 24
Finished Aug 18 05:38:38 PM PDT 24
Peak memory 207564 kb
Host smart-a6c143f2-79f5-416f-b7be-33b535675abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19154
10330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.1915410330
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.2004793184
Short name T1649
Test name
Test status
Simulation time 152997336 ps
CPU time 0.83 seconds
Started Aug 18 05:38:17 PM PDT 24
Finished Aug 18 05:38:18 PM PDT 24
Peak memory 207568 kb
Host smart-9c090fb8-7ff5-4183-90a5-d1a8293081e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20047
93184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.2004793184
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.4005539680
Short name T346
Test name
Test status
Simulation time 1026053737 ps
CPU time 2.75 seconds
Started Aug 18 05:38:41 PM PDT 24
Finished Aug 18 05:38:44 PM PDT 24
Peak memory 207616 kb
Host smart-3d2e9846-9fc4-44a1-bbd1-4503df74b735
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4005539680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.4005539680
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.231910599
Short name T3591
Test name
Test status
Simulation time 33480505567 ps
CPU time 54.69 seconds
Started Aug 18 05:38:43 PM PDT 24
Finished Aug 18 05:39:38 PM PDT 24
Peak memory 207812 kb
Host smart-9d28f6f8-6950-4769-83b0-76fb43f32b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23191
0599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.231910599
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.574607191
Short name T707
Test name
Test status
Simulation time 1061596210 ps
CPU time 22.06 seconds
Started Aug 18 05:38:26 PM PDT 24
Finished Aug 18 05:38:48 PM PDT 24
Peak memory 207756 kb
Host smart-4917f549-52c5-4a70-8210-1d6a67afe553
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574607191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.574607191
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.810401720
Short name T363
Test name
Test status
Simulation time 869947539 ps
CPU time 1.97 seconds
Started Aug 18 05:38:47 PM PDT 24
Finished Aug 18 05:38:49 PM PDT 24
Peak memory 207548 kb
Host smart-77ff6490-12ac-4e1d-bcc7-5c8bb24300b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81040
1720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.810401720
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.1275144776
Short name T3188
Test name
Test status
Simulation time 132406951 ps
CPU time 0.83 seconds
Started Aug 18 05:38:47 PM PDT 24
Finished Aug 18 05:38:48 PM PDT 24
Peak memory 207552 kb
Host smart-72226a41-5aaf-4f99-b23f-399a4c800299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12751
44776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.1275144776
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.823967670
Short name T2863
Test name
Test status
Simulation time 60380350 ps
CPU time 0.72 seconds
Started Aug 18 05:38:36 PM PDT 24
Finished Aug 18 05:38:37 PM PDT 24
Peak memory 207336 kb
Host smart-1f30ba29-c164-48d1-b36f-bbd76f4c575d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82396
7670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.823967670
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.968034881
Short name T694
Test name
Test status
Simulation time 873456160 ps
CPU time 2.47 seconds
Started Aug 18 05:38:35 PM PDT 24
Finished Aug 18 05:38:37 PM PDT 24
Peak memory 207672 kb
Host smart-f533850e-1cec-481c-b401-ca6ee654f0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96803
4881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.968034881
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_types.695657401
Short name T505
Test name
Test status
Simulation time 440865613 ps
CPU time 1.31 seconds
Started Aug 18 05:38:43 PM PDT 24
Finished Aug 18 05:38:44 PM PDT 24
Peak memory 207544 kb
Host smart-de84d43d-0d96-4e67-8620-e5d664038547
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=695657401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_types.695657401
Directory /workspace/47.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3753983993
Short name T3259
Test name
Test status
Simulation time 345665465 ps
CPU time 2.28 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:38:56 PM PDT 24
Peak memory 207588 kb
Host smart-dd982537-1dac-49cf-bd4a-ecc1382c7479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37539
83993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3753983993
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.188722996
Short name T1712
Test name
Test status
Simulation time 212120061 ps
CPU time 1.02 seconds
Started Aug 18 05:38:28 PM PDT 24
Finished Aug 18 05:38:29 PM PDT 24
Peak memory 215892 kb
Host smart-bf58cc32-1586-427a-a0d1-dd2c1ba487f8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=188722996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.188722996
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1215575998
Short name T624
Test name
Test status
Simulation time 140911542 ps
CPU time 0.79 seconds
Started Aug 18 05:38:36 PM PDT 24
Finished Aug 18 05:38:37 PM PDT 24
Peak memory 207392 kb
Host smart-8a37bee6-20aa-4614-af19-77f7b0bbc3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12155
75998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1215575998
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1433207331
Short name T2781
Test name
Test status
Simulation time 224114724 ps
CPU time 1.01 seconds
Started Aug 18 05:38:37 PM PDT 24
Finished Aug 18 05:38:38 PM PDT 24
Peak memory 207500 kb
Host smart-7b2fc7e3-fc7c-47fc-afb2-cf10ab55e9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14332
07331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1433207331
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.3276970577
Short name T1985
Test name
Test status
Simulation time 5250137694 ps
CPU time 40.15 seconds
Started Aug 18 05:38:30 PM PDT 24
Finished Aug 18 05:39:10 PM PDT 24
Peak memory 215964 kb
Host smart-c8c19231-2fe1-404e-9e8e-48be11152692
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3276970577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.3276970577
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.3897155723
Short name T766
Test name
Test status
Simulation time 6092284705 ps
CPU time 74.14 seconds
Started Aug 18 05:38:46 PM PDT 24
Finished Aug 18 05:40:00 PM PDT 24
Peak memory 207668 kb
Host smart-cf5daa56-be25-4faa-8e73-e773012dcce6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3897155723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.3897155723
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3689485525
Short name T3583
Test name
Test status
Simulation time 245667866 ps
CPU time 1.02 seconds
Started Aug 18 05:38:23 PM PDT 24
Finished Aug 18 05:38:24 PM PDT 24
Peak memory 207568 kb
Host smart-6133b24a-4e79-4dd7-8384-e31b40268735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36894
85525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3689485525
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.450370750
Short name T3427
Test name
Test status
Simulation time 14154630665 ps
CPU time 22.02 seconds
Started Aug 18 05:38:22 PM PDT 24
Finished Aug 18 05:38:44 PM PDT 24
Peak memory 207720 kb
Host smart-0cbdc0ea-fd9d-4002-b8f4-1ed527945024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45037
0750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.450370750
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1133887278
Short name T1945
Test name
Test status
Simulation time 10457737678 ps
CPU time 13.44 seconds
Started Aug 18 05:38:24 PM PDT 24
Finished Aug 18 05:38:38 PM PDT 24
Peak memory 207800 kb
Host smart-29c60444-6cef-4cd7-a162-b6547bec8a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11338
87278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1133887278
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.3043677310
Short name T3045
Test name
Test status
Simulation time 4332274279 ps
CPU time 32.34 seconds
Started Aug 18 05:38:42 PM PDT 24
Finished Aug 18 05:39:14 PM PDT 24
Peak memory 224068 kb
Host smart-73790f9b-f387-43f9-8204-8462401aa150
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3043677310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.3043677310
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.3905265155
Short name T1105
Test name
Test status
Simulation time 2800142999 ps
CPU time 76.23 seconds
Started Aug 18 05:38:38 PM PDT 24
Finished Aug 18 05:39:54 PM PDT 24
Peak memory 215708 kb
Host smart-fb8163d7-725f-4086-9ebb-01a69e90c4d5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3905265155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.3905265155
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.680398047
Short name T631
Test name
Test status
Simulation time 249589356 ps
CPU time 1.04 seconds
Started Aug 18 05:38:29 PM PDT 24
Finished Aug 18 05:38:30 PM PDT 24
Peak memory 207480 kb
Host smart-f8eb8e72-d01c-48a3-91a3-9e1d2d2b862a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=680398047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.680398047
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2931906135
Short name T3539
Test name
Test status
Simulation time 194609976 ps
CPU time 0.91 seconds
Started Aug 18 05:38:34 PM PDT 24
Finished Aug 18 05:38:35 PM PDT 24
Peak memory 206468 kb
Host smart-174ddde3-adc0-43e2-a3f2-7bde7bd7f6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29319
06135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2931906135
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.856655849
Short name T1088
Test name
Test status
Simulation time 1780913691 ps
CPU time 16.64 seconds
Started Aug 18 05:38:43 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 224056 kb
Host smart-07eb871e-5803-4967-97dd-b9554f0e0b1e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=856655849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.856655849
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.31197399
Short name T3315
Test name
Test status
Simulation time 208225668 ps
CPU time 0.9 seconds
Started Aug 18 05:38:28 PM PDT 24
Finished Aug 18 05:38:29 PM PDT 24
Peak memory 207296 kb
Host smart-49ecf3d6-97b4-43cb-94d5-e48fe5edaa0e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=31197399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.31197399
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3798494757
Short name T2660
Test name
Test status
Simulation time 152656070 ps
CPU time 0.83 seconds
Started Aug 18 05:38:30 PM PDT 24
Finished Aug 18 05:38:36 PM PDT 24
Peak memory 206468 kb
Host smart-aeb04816-9b14-4300-baf1-8ecb82225f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37984
94757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3798494757
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.4278742862
Short name T160
Test name
Test status
Simulation time 223301838 ps
CPU time 0.95 seconds
Started Aug 18 05:38:32 PM PDT 24
Finished Aug 18 05:38:33 PM PDT 24
Peak memory 207372 kb
Host smart-16e9af77-bb43-4e15-ab7c-48170585bc69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42787
42862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.4278742862
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.1845944562
Short name T2756
Test name
Test status
Simulation time 143992650 ps
CPU time 0.84 seconds
Started Aug 18 05:38:33 PM PDT 24
Finished Aug 18 05:38:34 PM PDT 24
Peak memory 207404 kb
Host smart-319fdcb0-61e5-441e-be1f-d7b67d102016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18459
44562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.1845944562
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1622279547
Short name T976
Test name
Test status
Simulation time 209715210 ps
CPU time 0.97 seconds
Started Aug 18 05:38:28 PM PDT 24
Finished Aug 18 05:38:29 PM PDT 24
Peak memory 207480 kb
Host smart-cba55e2f-6033-4c5d-ae3b-1d271ecba6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16222
79547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1622279547
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1713175960
Short name T3374
Test name
Test status
Simulation time 174735582 ps
CPU time 0.89 seconds
Started Aug 18 05:38:49 PM PDT 24
Finished Aug 18 05:38:50 PM PDT 24
Peak memory 206548 kb
Host smart-ba675f40-a1aa-4dd3-ad1f-22c8d3ae2ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17131
75960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1713175960
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3274542332
Short name T202
Test name
Test status
Simulation time 165514389 ps
CPU time 0.89 seconds
Started Aug 18 05:38:44 PM PDT 24
Finished Aug 18 05:38:45 PM PDT 24
Peak memory 207576 kb
Host smart-b6f8c408-8c46-4bc4-afcf-76fe52ca5b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32745
42332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3274542332
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.1835102333
Short name T1007
Test name
Test status
Simulation time 188184631 ps
CPU time 0.92 seconds
Started Aug 18 05:38:46 PM PDT 24
Finished Aug 18 05:38:47 PM PDT 24
Peak memory 207440 kb
Host smart-a4d2c001-0f9a-40f7-8a1e-026a2e4c2987
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1835102333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.1835102333
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2731398092
Short name T2225
Test name
Test status
Simulation time 156005450 ps
CPU time 0.86 seconds
Started Aug 18 05:38:45 PM PDT 24
Finished Aug 18 05:38:47 PM PDT 24
Peak memory 206436 kb
Host smart-9045acf1-7ee7-4550-bc35-f08e838496df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27313
98092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2731398092
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1834748668
Short name T1094
Test name
Test status
Simulation time 90279989 ps
CPU time 0.7 seconds
Started Aug 18 05:38:33 PM PDT 24
Finished Aug 18 05:38:33 PM PDT 24
Peak memory 207320 kb
Host smart-3e4cde7e-8b9d-4172-8f9d-f7eb3e9bfc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18347
48668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1834748668
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3435184167
Short name T2704
Test name
Test status
Simulation time 8124391847 ps
CPU time 20.46 seconds
Started Aug 18 05:38:53 PM PDT 24
Finished Aug 18 05:39:14 PM PDT 24
Peak memory 215752 kb
Host smart-faa05f49-e2f1-493c-974b-8994d5bf7b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34351
84167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3435184167
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2795426809
Short name T1949
Test name
Test status
Simulation time 165350583 ps
CPU time 0.86 seconds
Started Aug 18 05:38:28 PM PDT 24
Finished Aug 18 05:38:29 PM PDT 24
Peak memory 207544 kb
Host smart-89cdd130-26f3-494b-b6b6-2c841a28d8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27954
26809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2795426809
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1694012653
Short name T3326
Test name
Test status
Simulation time 201965458 ps
CPU time 1 seconds
Started Aug 18 05:38:37 PM PDT 24
Finished Aug 18 05:38:38 PM PDT 24
Peak memory 207372 kb
Host smart-a73e6aa0-89d4-4bab-8015-10da8c7dbb7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16940
12653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1694012653
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.2160295426
Short name T911
Test name
Test status
Simulation time 206918383 ps
CPU time 0.88 seconds
Started Aug 18 05:38:28 PM PDT 24
Finished Aug 18 05:38:29 PM PDT 24
Peak memory 207300 kb
Host smart-e63c2a95-7dba-410f-a54f-6a2ea24f319a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21602
95426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.2160295426
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.4074866237
Short name T1339
Test name
Test status
Simulation time 212195348 ps
CPU time 0.89 seconds
Started Aug 18 05:38:38 PM PDT 24
Finished Aug 18 05:38:39 PM PDT 24
Peak memory 207300 kb
Host smart-85b3286f-aae1-48a5-92ee-67be8812fd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40748
66237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.4074866237
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1018212393
Short name T1023
Test name
Test status
Simulation time 163692670 ps
CPU time 0.85 seconds
Started Aug 18 05:38:44 PM PDT 24
Finished Aug 18 05:38:45 PM PDT 24
Peak memory 206476 kb
Host smart-6f2e2483-17a6-412d-8efd-2c8aaffa73a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10182
12393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1018212393
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_rx_full.3077677292
Short name T340
Test name
Test status
Simulation time 270014021 ps
CPU time 1.06 seconds
Started Aug 18 05:38:31 PM PDT 24
Finished Aug 18 05:38:32 PM PDT 24
Peak memory 207480 kb
Host smart-d43363d1-0575-4f53-b2ae-9f867bbdff87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30776
77292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_full.3077677292
Directory /workspace/47.usbdev_rx_full/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.49377588
Short name T1052
Test name
Test status
Simulation time 147743495 ps
CPU time 0.84 seconds
Started Aug 18 05:38:24 PM PDT 24
Finished Aug 18 05:38:25 PM PDT 24
Peak memory 207452 kb
Host smart-a560876f-836c-415f-9ba1-95f7be7d6bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49377
588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.49377588
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3771657276
Short name T1731
Test name
Test status
Simulation time 168406485 ps
CPU time 0.82 seconds
Started Aug 18 05:38:49 PM PDT 24
Finished Aug 18 05:38:50 PM PDT 24
Peak memory 207424 kb
Host smart-0017c235-4699-44ad-8663-43a9c35bc1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37716
57276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3771657276
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2486047170
Short name T1240
Test name
Test status
Simulation time 242275227 ps
CPU time 1 seconds
Started Aug 18 05:38:32 PM PDT 24
Finished Aug 18 05:38:34 PM PDT 24
Peak memory 207288 kb
Host smart-9ee1e88a-536f-4bdc-8ae0-2adaf72256df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24860
47170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2486047170
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.280982
Short name T1213
Test name
Test status
Simulation time 1759069785 ps
CPU time 13.41 seconds
Started Aug 18 05:38:40 PM PDT 24
Finished Aug 18 05:38:54 PM PDT 24
Peak memory 217580 kb
Host smart-7bc4609c-99a1-41b6-b3c6-4cc6c799ad80
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=280982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.280982
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4216377676
Short name T2951
Test name
Test status
Simulation time 195128673 ps
CPU time 0.97 seconds
Started Aug 18 05:38:46 PM PDT 24
Finished Aug 18 05:38:47 PM PDT 24
Peak memory 207472 kb
Host smart-07579770-7f67-4687-a0ee-0985e8cefaae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42163
77676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4216377676
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2060880389
Short name T500
Test name
Test status
Simulation time 194994379 ps
CPU time 0.92 seconds
Started Aug 18 05:38:38 PM PDT 24
Finished Aug 18 05:38:39 PM PDT 24
Peak memory 207496 kb
Host smart-1c01fcc6-be6e-4637-8652-44f260046646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20608
80389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2060880389
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.834181861
Short name T564
Test name
Test status
Simulation time 1394071902 ps
CPU time 3.27 seconds
Started Aug 18 05:38:45 PM PDT 24
Finished Aug 18 05:38:49 PM PDT 24
Peak memory 207880 kb
Host smart-ca3be88a-51c7-4980-9ec5-b4e8bed88972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83418
1861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.834181861
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.403066742
Short name T1894
Test name
Test status
Simulation time 3965807497 ps
CPU time 29.8 seconds
Started Aug 18 05:38:47 PM PDT 24
Finished Aug 18 05:39:17 PM PDT 24
Peak memory 207796 kb
Host smart-79280e56-fd85-45e3-840f-5c2e1394d332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40306
6742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.403066742
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.814440139
Short name T824
Test name
Test status
Simulation time 6084837926 ps
CPU time 43.99 seconds
Started Aug 18 05:38:45 PM PDT 24
Finished Aug 18 05:39:30 PM PDT 24
Peak memory 207760 kb
Host smart-c51e14c7-2183-49d6-b9cf-65b8686f18f7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814440139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_host
_handshake.814440139
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_tx_rx_disruption.540018351
Short name T1405
Test name
Test status
Simulation time 598631106 ps
CPU time 1.57 seconds
Started Aug 18 05:38:49 PM PDT 24
Finished Aug 18 05:38:50 PM PDT 24
Peak memory 207504 kb
Host smart-dfb97b3a-4245-4021-bd3a-f30889a016da
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540018351 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.usbdev_tx_rx_disruption.540018351
Directory /workspace/47.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/470.usbdev_tx_rx_disruption.2660122642
Short name T2948
Test name
Test status
Simulation time 557088259 ps
CPU time 1.62 seconds
Started Aug 18 05:40:06 PM PDT 24
Finished Aug 18 05:40:07 PM PDT 24
Peak memory 207560 kb
Host smart-ecd55f66-8c46-48df-84cb-82e95b28b9eb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660122642 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 470.usbdev_tx_rx_disruption.2660122642
Directory /workspace/470.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/471.usbdev_tx_rx_disruption.3031397365
Short name T216
Test name
Test status
Simulation time 596434057 ps
CPU time 1.61 seconds
Started Aug 18 05:40:03 PM PDT 24
Finished Aug 18 05:40:04 PM PDT 24
Peak memory 207568 kb
Host smart-ebcccd2f-fe5b-4994-a35c-ff449dcf894e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031397365 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 471.usbdev_tx_rx_disruption.3031397365
Directory /workspace/471.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/472.usbdev_tx_rx_disruption.2611028590
Short name T1159
Test name
Test status
Simulation time 629375060 ps
CPU time 1.8 seconds
Started Aug 18 05:39:57 PM PDT 24
Finished Aug 18 05:40:04 PM PDT 24
Peak memory 207472 kb
Host smart-639dbd2b-47f3-477d-9262-de197836b2ac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611028590 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 472.usbdev_tx_rx_disruption.2611028590
Directory /workspace/472.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/473.usbdev_tx_rx_disruption.2436755802
Short name T2289
Test name
Test status
Simulation time 533520037 ps
CPU time 1.73 seconds
Started Aug 18 05:40:39 PM PDT 24
Finished Aug 18 05:40:40 PM PDT 24
Peak memory 207568 kb
Host smart-06234269-096b-4002-8631-0ed4bb49cf99
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436755802 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 473.usbdev_tx_rx_disruption.2436755802
Directory /workspace/473.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/474.usbdev_tx_rx_disruption.352556655
Short name T2411
Test name
Test status
Simulation time 567573045 ps
CPU time 1.61 seconds
Started Aug 18 05:40:10 PM PDT 24
Finished Aug 18 05:40:12 PM PDT 24
Peak memory 207556 kb
Host smart-744b86d5-8ee5-4425-9897-3899a1c2c421
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352556655 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 474.usbdev_tx_rx_disruption.352556655
Directory /workspace/474.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/475.usbdev_tx_rx_disruption.2095980119
Short name T1552
Test name
Test status
Simulation time 560988381 ps
CPU time 1.62 seconds
Started Aug 18 05:40:21 PM PDT 24
Finished Aug 18 05:40:23 PM PDT 24
Peak memory 207612 kb
Host smart-f518cdbc-1013-4542-bf36-8e8c52ea0711
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095980119 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 475.usbdev_tx_rx_disruption.2095980119
Directory /workspace/475.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/476.usbdev_tx_rx_disruption.944501243
Short name T1611
Test name
Test status
Simulation time 502765708 ps
CPU time 1.44 seconds
Started Aug 18 05:40:05 PM PDT 24
Finished Aug 18 05:40:06 PM PDT 24
Peak memory 207552 kb
Host smart-4ae222b6-8172-432a-a56e-294244ece9eb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944501243 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 476.usbdev_tx_rx_disruption.944501243
Directory /workspace/476.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/477.usbdev_tx_rx_disruption.1094589869
Short name T2022
Test name
Test status
Simulation time 507795763 ps
CPU time 1.46 seconds
Started Aug 18 05:40:25 PM PDT 24
Finished Aug 18 05:40:27 PM PDT 24
Peak memory 207540 kb
Host smart-2416a2b9-34a3-48af-bc19-f810e30fcee8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094589869 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 477.usbdev_tx_rx_disruption.1094589869
Directory /workspace/477.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/478.usbdev_tx_rx_disruption.555519123
Short name T1223
Test name
Test status
Simulation time 459532209 ps
CPU time 1.52 seconds
Started Aug 18 05:39:59 PM PDT 24
Finished Aug 18 05:40:01 PM PDT 24
Peak memory 207500 kb
Host smart-5fa1eeb7-ed59-493a-8fb2-1133db939497
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555519123 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 478.usbdev_tx_rx_disruption.555519123
Directory /workspace/478.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/479.usbdev_tx_rx_disruption.1281791691
Short name T3307
Test name
Test status
Simulation time 606110105 ps
CPU time 1.66 seconds
Started Aug 18 05:40:03 PM PDT 24
Finished Aug 18 05:40:04 PM PDT 24
Peak memory 207588 kb
Host smart-a3680ac0-8743-460c-b067-9c8e5c695dfc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281791691 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 479.usbdev_tx_rx_disruption.1281791691
Directory /workspace/479.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.1854901150
Short name T232
Test name
Test status
Simulation time 36941038 ps
CPU time 0.67 seconds
Started Aug 18 05:39:02 PM PDT 24
Finished Aug 18 05:39:03 PM PDT 24
Peak memory 207480 kb
Host smart-a0366fbb-3b47-4583-86ad-524643263cfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1854901150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.1854901150
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.734250902
Short name T3377
Test name
Test status
Simulation time 9657073571 ps
CPU time 12.89 seconds
Started Aug 18 05:38:25 PM PDT 24
Finished Aug 18 05:38:38 PM PDT 24
Peak memory 207828 kb
Host smart-72be8e90-21cc-4e1b-83c7-044429be8e15
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734250902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_ao
n_wake_disconnect.734250902
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.1176955799
Short name T831
Test name
Test status
Simulation time 19047931912 ps
CPU time 22.41 seconds
Started Aug 18 05:38:51 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207796 kb
Host smart-fc31e487-b89b-4070-9017-bdf9f1c2232d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176955799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.1176955799
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.554081252
Short name T2023
Test name
Test status
Simulation time 25832314391 ps
CPU time 32.35 seconds
Started Aug 18 05:38:46 PM PDT 24
Finished Aug 18 05:39:18 PM PDT 24
Peak memory 215968 kb
Host smart-ac88378d-6e4f-4fe8-8bbb-b17239686a44
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554081252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_ao
n_wake_resume.554081252
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.294437371
Short name T1909
Test name
Test status
Simulation time 194222797 ps
CPU time 0.93 seconds
Started Aug 18 05:38:49 PM PDT 24
Finished Aug 18 05:38:50 PM PDT 24
Peak memory 207460 kb
Host smart-26ea96c0-a7ee-4861-9014-3c585cfb54e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29443
7371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.294437371
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.1972788102
Short name T2906
Test name
Test status
Simulation time 147153866 ps
CPU time 0.83 seconds
Started Aug 18 05:38:47 PM PDT 24
Finished Aug 18 05:38:48 PM PDT 24
Peak memory 207500 kb
Host smart-a31a6e4f-f899-4b55-bed6-36b47c50d3c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19727
88102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.1972788102
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.3092761996
Short name T2549
Test name
Test status
Simulation time 483884696 ps
CPU time 1.67 seconds
Started Aug 18 05:38:49 PM PDT 24
Finished Aug 18 05:38:51 PM PDT 24
Peak memory 207572 kb
Host smart-9d9242ff-5236-4ec2-b698-ef5500de0fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30927
61996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.3092761996
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2621198907
Short name T1012
Test name
Test status
Simulation time 882577326 ps
CPU time 2.47 seconds
Started Aug 18 05:38:46 PM PDT 24
Finished Aug 18 05:38:49 PM PDT 24
Peak memory 207736 kb
Host smart-6c5260ac-d7aa-46f3-a221-72389d25c81d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2621198907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2621198907
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.782212929
Short name T2300
Test name
Test status
Simulation time 19147097206 ps
CPU time 29.06 seconds
Started Aug 18 05:38:31 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207792 kb
Host smart-544d0736-4458-4c25-bcc2-ccb01fcf893f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78221
2929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.782212929
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.4069961191
Short name T789
Test name
Test status
Simulation time 1181801495 ps
CPU time 24.96 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:39:19 PM PDT 24
Peak memory 207752 kb
Host smart-e6350a4c-1d98-4fb2-bbb7-0b94fc980824
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069961191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.4069961191
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.4011466239
Short name T2207
Test name
Test status
Simulation time 551924445 ps
CPU time 1.52 seconds
Started Aug 18 05:38:50 PM PDT 24
Finished Aug 18 05:38:52 PM PDT 24
Peak memory 207536 kb
Host smart-7d4db425-e54a-499d-8c8c-1e3200f2d6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40114
66239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.4011466239
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.3865719356
Short name T1817
Test name
Test status
Simulation time 136517103 ps
CPU time 0.83 seconds
Started Aug 18 05:38:57 PM PDT 24
Finished Aug 18 05:38:58 PM PDT 24
Peak memory 207520 kb
Host smart-f0a2d271-e5dc-4315-a109-1f67bde3f001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38657
19356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3865719356
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.434391450
Short name T2870
Test name
Test status
Simulation time 46027496 ps
CPU time 0.68 seconds
Started Aug 18 05:38:53 PM PDT 24
Finished Aug 18 05:38:54 PM PDT 24
Peak memory 207388 kb
Host smart-db652d12-971b-4885-a0d5-5e45c24d8e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43439
1450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.434391450
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3260778451
Short name T2630
Test name
Test status
Simulation time 1049384652 ps
CPU time 3.02 seconds
Started Aug 18 05:38:48 PM PDT 24
Finished Aug 18 05:38:51 PM PDT 24
Peak memory 207784 kb
Host smart-2dd391cc-fdbd-414c-b6da-82c6b608b5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32607
78451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3260778451
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_types.1230219572
Short name T431
Test name
Test status
Simulation time 307714128 ps
CPU time 1.23 seconds
Started Aug 18 05:38:38 PM PDT 24
Finished Aug 18 05:38:39 PM PDT 24
Peak memory 207460 kb
Host smart-9c41b323-81d0-4fd4-842d-32750d9e10c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1230219572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_types.1230219572
Directory /workspace/48.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2189222821
Short name T3375
Test name
Test status
Simulation time 318387593 ps
CPU time 2.16 seconds
Started Aug 18 05:38:51 PM PDT 24
Finished Aug 18 05:38:54 PM PDT 24
Peak memory 207664 kb
Host smart-4b716e69-e074-4f3f-8281-efece06ced72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21892
22821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2189222821
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.194371522
Short name T3490
Test name
Test status
Simulation time 174668071 ps
CPU time 0.97 seconds
Started Aug 18 05:38:38 PM PDT 24
Finished Aug 18 05:38:39 PM PDT 24
Peak memory 207448 kb
Host smart-9e5f495a-f3eb-4b35-88d3-311250fd4dfa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=194371522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.194371522
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2250531865
Short name T969
Test name
Test status
Simulation time 141516795 ps
CPU time 0.86 seconds
Started Aug 18 05:38:39 PM PDT 24
Finished Aug 18 05:38:40 PM PDT 24
Peak memory 207476 kb
Host smart-e8a61fec-2c4e-40cd-ab8b-16886d222d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22505
31865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2250531865
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.513847345
Short name T1632
Test name
Test status
Simulation time 198823011 ps
CPU time 0.95 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207424 kb
Host smart-6e2ca95d-957c-438d-aabf-1a93d228b367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51384
7345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.513847345
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.4015351457
Short name T658
Test name
Test status
Simulation time 3235380696 ps
CPU time 30.85 seconds
Started Aug 18 05:38:53 PM PDT 24
Finished Aug 18 05:39:24 PM PDT 24
Peak memory 224204 kb
Host smart-76a842e3-75cf-4b31-b06a-043765e78095
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4015351457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.4015351457
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.1641197709
Short name T112
Test name
Test status
Simulation time 3652988245 ps
CPU time 45.37 seconds
Started Aug 18 05:38:40 PM PDT 24
Finished Aug 18 05:39:31 PM PDT 24
Peak memory 207780 kb
Host smart-7aa46799-701a-4f5f-8ed1-a122ed29cd3a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1641197709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.1641197709
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.2147912035
Short name T615
Test name
Test status
Simulation time 211610843 ps
CPU time 0.97 seconds
Started Aug 18 05:38:50 PM PDT 24
Finished Aug 18 05:38:51 PM PDT 24
Peak memory 207448 kb
Host smart-fc216410-9e80-4a3c-b70b-1b0ac2a182bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21479
12035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2147912035
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.2762080110
Short name T2741
Test name
Test status
Simulation time 32038688367 ps
CPU time 47.2 seconds
Started Aug 18 05:38:32 PM PDT 24
Finished Aug 18 05:39:20 PM PDT 24
Peak memory 207816 kb
Host smart-8df1c533-d13c-4e05-9bb1-3000ef4ccc6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27620
80110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2762080110
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.2702660728
Short name T3191
Test name
Test status
Simulation time 10126841575 ps
CPU time 13.09 seconds
Started Aug 18 05:38:47 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207860 kb
Host smart-827cc969-93b6-40a4-a728-b1fb6fa8555c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27026
60728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.2702660728
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.2482239503
Short name T3362
Test name
Test status
Simulation time 3588837976 ps
CPU time 27.78 seconds
Started Aug 18 05:38:37 PM PDT 24
Finished Aug 18 05:39:05 PM PDT 24
Peak memory 216004 kb
Host smart-f248bc31-a01f-4986-a07b-18ca60a7f80f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2482239503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.2482239503
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2751896214
Short name T790
Test name
Test status
Simulation time 2504756635 ps
CPU time 27.18 seconds
Started Aug 18 05:38:48 PM PDT 24
Finished Aug 18 05:39:15 PM PDT 24
Peak memory 217592 kb
Host smart-1c1498a8-a380-41fb-bb92-f4d1beb728cd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2751896214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2751896214
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.2440544047
Short name T2074
Test name
Test status
Simulation time 268693637 ps
CPU time 1.04 seconds
Started Aug 18 05:38:47 PM PDT 24
Finished Aug 18 05:38:48 PM PDT 24
Peak memory 207496 kb
Host smart-a80f3b22-3040-4a9f-bb98-330af17d5c59
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2440544047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.2440544047
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3562374266
Short name T587
Test name
Test status
Simulation time 196641702 ps
CPU time 0.9 seconds
Started Aug 18 05:38:50 PM PDT 24
Finished Aug 18 05:38:51 PM PDT 24
Peak memory 207392 kb
Host smart-ad65142d-ce72-4b6c-9e67-73f4925d7977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35623
74266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3562374266
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.2908283654
Short name T2983
Test name
Test status
Simulation time 2764819769 ps
CPU time 20.15 seconds
Started Aug 18 05:38:47 PM PDT 24
Finished Aug 18 05:39:07 PM PDT 24
Peak memory 217564 kb
Host smart-146d5649-2928-45a4-b6ac-68be3f4f51ad
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2908283654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.2908283654
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.2332447597
Short name T1202
Test name
Test status
Simulation time 156995105 ps
CPU time 0.85 seconds
Started Aug 18 05:38:48 PM PDT 24
Finished Aug 18 05:38:49 PM PDT 24
Peak memory 207496 kb
Host smart-a7e3dd76-0df5-42a2-b6da-e0b7146af802
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2332447597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2332447597
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.4048206835
Short name T2288
Test name
Test status
Simulation time 142345350 ps
CPU time 0.86 seconds
Started Aug 18 05:38:46 PM PDT 24
Finished Aug 18 05:38:47 PM PDT 24
Peak memory 207500 kb
Host smart-53e4768d-7aff-483d-be72-d71abd5d19c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40482
06835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.4048206835
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1444451832
Short name T168
Test name
Test status
Simulation time 224363761 ps
CPU time 0.97 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:38:55 PM PDT 24
Peak memory 207636 kb
Host smart-dd10f658-6ecf-41af-aa5a-6d4c04a46491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14444
51832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1444451832
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2286489940
Short name T1282
Test name
Test status
Simulation time 182219405 ps
CPU time 0.9 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207468 kb
Host smart-3e31810f-ac1b-4e9c-b34d-dbe104aafc6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22864
89940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2286489940
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.513410658
Short name T3544
Test name
Test status
Simulation time 176242705 ps
CPU time 0.92 seconds
Started Aug 18 05:38:46 PM PDT 24
Finished Aug 18 05:38:47 PM PDT 24
Peak memory 207456 kb
Host smart-fee8a0d6-38db-4244-a7ba-54897dc09c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51341
0658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.513410658
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2111088150
Short name T880
Test name
Test status
Simulation time 176746386 ps
CPU time 0.87 seconds
Started Aug 18 05:38:47 PM PDT 24
Finished Aug 18 05:38:48 PM PDT 24
Peak memory 207536 kb
Host smart-329da732-0d16-4bd4-91b2-21bab72f0e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21110
88150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2111088150
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.3486585476
Short name T1445
Test name
Test status
Simulation time 161993956 ps
CPU time 0.9 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:38:55 PM PDT 24
Peak memory 207580 kb
Host smart-991bdb53-6397-4a62-bb48-f8f122505510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34865
85476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.3486585476
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.2906392505
Short name T2353
Test name
Test status
Simulation time 235163916 ps
CPU time 1.03 seconds
Started Aug 18 05:38:49 PM PDT 24
Finished Aug 18 05:38:50 PM PDT 24
Peak memory 207572 kb
Host smart-1cf7cc96-ab6d-4280-a553-738f74da2f51
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2906392505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.2906392505
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.4165609293
Short name T2779
Test name
Test status
Simulation time 149496389 ps
CPU time 0.78 seconds
Started Aug 18 05:38:49 PM PDT 24
Finished Aug 18 05:38:50 PM PDT 24
Peak memory 207388 kb
Host smart-4f5380d7-695b-4a20-aaaf-92448599133c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41656
09293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.4165609293
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.194292823
Short name T1021
Test name
Test status
Simulation time 54324643 ps
CPU time 0.72 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:38:55 PM PDT 24
Peak memory 207496 kb
Host smart-1c777531-2d8b-4088-a56a-ae1f105557f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19429
2823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.194292823
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2445257380
Short name T1856
Test name
Test status
Simulation time 20141962947 ps
CPU time 50.84 seconds
Started Aug 18 05:38:52 PM PDT 24
Finished Aug 18 05:39:43 PM PDT 24
Peak memory 216128 kb
Host smart-1ebfaa9c-cd4a-46eb-b8bb-0eab12e9e69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24452
57380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2445257380
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.1388692159
Short name T950
Test name
Test status
Simulation time 167468123 ps
CPU time 0.86 seconds
Started Aug 18 05:38:57 PM PDT 24
Finished Aug 18 05:38:58 PM PDT 24
Peak memory 207500 kb
Host smart-ae3b386d-4237-4b5f-9518-b5b36e71a13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13886
92159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.1388692159
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1947880777
Short name T962
Test name
Test status
Simulation time 279718394 ps
CPU time 1.06 seconds
Started Aug 18 05:38:52 PM PDT 24
Finished Aug 18 05:38:53 PM PDT 24
Peak memory 207444 kb
Host smart-16e7dd2e-68af-42b2-906a-b5528c8e1627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19478
80777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1947880777
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2351930309
Short name T1265
Test name
Test status
Simulation time 237334151 ps
CPU time 0.95 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:38:55 PM PDT 24
Peak memory 207468 kb
Host smart-7ceb2fc2-ae41-49a6-849f-44758189d7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23519
30309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2351930309
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.771559346
Short name T1424
Test name
Test status
Simulation time 174272744 ps
CPU time 0.93 seconds
Started Aug 18 05:39:02 PM PDT 24
Finished Aug 18 05:39:03 PM PDT 24
Peak memory 207508 kb
Host smart-fa8983ef-6568-466a-b48b-a4de31ea3394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77155
9346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.771559346
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1278879399
Short name T2141
Test name
Test status
Simulation time 177451746 ps
CPU time 0.9 seconds
Started Aug 18 05:38:48 PM PDT 24
Finished Aug 18 05:38:49 PM PDT 24
Peak memory 207468 kb
Host smart-9ebf2959-2db1-4660-a31a-f1381b81f582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12788
79399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1278879399
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1635807612
Short name T3612
Test name
Test status
Simulation time 166091098 ps
CPU time 0.84 seconds
Started Aug 18 05:38:50 PM PDT 24
Finished Aug 18 05:38:51 PM PDT 24
Peak memory 207508 kb
Host smart-af6bce4b-7e2b-47aa-a83a-4076d37975ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16358
07612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1635807612
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.737202030
Short name T1501
Test name
Test status
Simulation time 169011698 ps
CPU time 0.91 seconds
Started Aug 18 05:38:45 PM PDT 24
Finished Aug 18 05:38:47 PM PDT 24
Peak memory 207524 kb
Host smart-438b426d-f314-41cf-b14d-9bae5dc8d1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73720
2030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.737202030
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.3643481848
Short name T3342
Test name
Test status
Simulation time 228815748 ps
CPU time 1.09 seconds
Started Aug 18 05:38:57 PM PDT 24
Finished Aug 18 05:38:58 PM PDT 24
Peak memory 207504 kb
Host smart-fd7c2b5f-4eee-451c-9d85-f888ebf265e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36434
81848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3643481848
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2236417249
Short name T189
Test name
Test status
Simulation time 2575552474 ps
CPU time 25.85 seconds
Started Aug 18 05:38:57 PM PDT 24
Finished Aug 18 05:39:23 PM PDT 24
Peak memory 217888 kb
Host smart-92647260-8233-4326-9aa9-fc6529e4249e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2236417249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2236417249
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.4186009726
Short name T3409
Test name
Test status
Simulation time 195890477 ps
CPU time 0.89 seconds
Started Aug 18 05:38:38 PM PDT 24
Finished Aug 18 05:38:39 PM PDT 24
Peak memory 207456 kb
Host smart-26174b0e-5950-4174-bba1-b5883d147465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41860
09726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.4186009726
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.585684016
Short name T1797
Test name
Test status
Simulation time 169563273 ps
CPU time 0.95 seconds
Started Aug 18 05:38:45 PM PDT 24
Finished Aug 18 05:38:47 PM PDT 24
Peak memory 207416 kb
Host smart-cab31dba-4199-4d30-ac84-9276942204ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58568
4016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.585684016
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.1053275136
Short name T797
Test name
Test status
Simulation time 1104891776 ps
CPU time 2.72 seconds
Started Aug 18 05:38:53 PM PDT 24
Finished Aug 18 05:38:56 PM PDT 24
Peak memory 207724 kb
Host smart-301ac431-d4b2-4047-b070-3252363df85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10532
75136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.1053275136
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.564931462
Short name T2570
Test name
Test status
Simulation time 2106350459 ps
CPU time 16.04 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:39:11 PM PDT 24
Peak memory 224100 kb
Host smart-13e94134-3f6d-4c6f-b03b-cf3a2e855bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56493
1462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.564931462
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.3023938246
Short name T2445
Test name
Test status
Simulation time 988579927 ps
CPU time 23.14 seconds
Started Aug 18 05:38:56 PM PDT 24
Finished Aug 18 05:39:19 PM PDT 24
Peak memory 207664 kb
Host smart-3fd6e81a-d90e-4406-a4d5-730af0ebdfc0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023938246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.3023938246
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_tx_rx_disruption.2876304379
Short name T616
Test name
Test status
Simulation time 508414969 ps
CPU time 1.67 seconds
Started Aug 18 05:38:48 PM PDT 24
Finished Aug 18 05:38:50 PM PDT 24
Peak memory 207568 kb
Host smart-fb81d01e-a548-41d9-9779-17e89c5a51b9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876304379 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.usbdev_tx_rx_disruption.2876304379
Directory /workspace/48.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/480.usbdev_tx_rx_disruption.2788633279
Short name T3016
Test name
Test status
Simulation time 487094321 ps
CPU time 1.37 seconds
Started Aug 18 05:40:17 PM PDT 24
Finished Aug 18 05:40:18 PM PDT 24
Peak memory 207560 kb
Host smart-dd601070-73c1-4bb7-ae48-5076b06feb5c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788633279 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 480.usbdev_tx_rx_disruption.2788633279
Directory /workspace/480.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/481.usbdev_tx_rx_disruption.245538019
Short name T700
Test name
Test status
Simulation time 468082065 ps
CPU time 1.53 seconds
Started Aug 18 05:40:17 PM PDT 24
Finished Aug 18 05:40:18 PM PDT 24
Peak memory 207560 kb
Host smart-a4650be8-5309-4572-997f-567b9812e73c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245538019 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 481.usbdev_tx_rx_disruption.245538019
Directory /workspace/481.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/482.usbdev_tx_rx_disruption.1313463110
Short name T643
Test name
Test status
Simulation time 467074791 ps
CPU time 1.48 seconds
Started Aug 18 05:40:11 PM PDT 24
Finished Aug 18 05:40:13 PM PDT 24
Peak memory 207568 kb
Host smart-446f6a3a-c7fe-4374-8f50-c998a61e03f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313463110 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 482.usbdev_tx_rx_disruption.1313463110
Directory /workspace/482.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/483.usbdev_tx_rx_disruption.3294225624
Short name T2820
Test name
Test status
Simulation time 564573612 ps
CPU time 1.5 seconds
Started Aug 18 05:40:12 PM PDT 24
Finished Aug 18 05:40:13 PM PDT 24
Peak memory 207560 kb
Host smart-5975d1d3-7101-4626-ac79-b02b693f560e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294225624 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 483.usbdev_tx_rx_disruption.3294225624
Directory /workspace/483.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/484.usbdev_tx_rx_disruption.1817243386
Short name T2482
Test name
Test status
Simulation time 547581405 ps
CPU time 1.51 seconds
Started Aug 18 05:40:14 PM PDT 24
Finished Aug 18 05:40:16 PM PDT 24
Peak memory 207532 kb
Host smart-bba41789-6e10-4d3a-8440-028ee61cee70
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817243386 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 484.usbdev_tx_rx_disruption.1817243386
Directory /workspace/484.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/485.usbdev_tx_rx_disruption.3126927718
Short name T1072
Test name
Test status
Simulation time 456538861 ps
CPU time 1.62 seconds
Started Aug 18 05:40:21 PM PDT 24
Finished Aug 18 05:40:23 PM PDT 24
Peak memory 207480 kb
Host smart-9041f96d-358c-4020-a037-1d75000b190d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126927718 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 485.usbdev_tx_rx_disruption.3126927718
Directory /workspace/485.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/486.usbdev_tx_rx_disruption.2264711387
Short name T1871
Test name
Test status
Simulation time 518473238 ps
CPU time 1.69 seconds
Started Aug 18 05:40:04 PM PDT 24
Finished Aug 18 05:40:06 PM PDT 24
Peak memory 207564 kb
Host smart-67deeef1-64e4-4453-81bd-0634cd783c70
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264711387 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 486.usbdev_tx_rx_disruption.2264711387
Directory /workspace/486.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/487.usbdev_tx_rx_disruption.4102186467
Short name T2477
Test name
Test status
Simulation time 522665653 ps
CPU time 1.65 seconds
Started Aug 18 05:40:09 PM PDT 24
Finished Aug 18 05:40:11 PM PDT 24
Peak memory 207568 kb
Host smart-e0b3e794-4422-4d61-8952-8cc2adad5d07
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102186467 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 487.usbdev_tx_rx_disruption.4102186467
Directory /workspace/487.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/488.usbdev_tx_rx_disruption.72586377
Short name T190
Test name
Test status
Simulation time 493287361 ps
CPU time 1.56 seconds
Started Aug 18 05:40:08 PM PDT 24
Finished Aug 18 05:40:10 PM PDT 24
Peak memory 207540 kb
Host smart-6126c31e-1c32-41b1-aa8b-a37aacf5ddf3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72586377 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 488.usbdev_tx_rx_disruption.72586377
Directory /workspace/488.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/489.usbdev_tx_rx_disruption.1964997216
Short name T3027
Test name
Test status
Simulation time 461513718 ps
CPU time 1.48 seconds
Started Aug 18 05:40:19 PM PDT 24
Finished Aug 18 05:40:20 PM PDT 24
Peak memory 207532 kb
Host smart-f6a3517d-12f1-45ec-9609-91bc29e6220f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964997216 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 489.usbdev_tx_rx_disruption.1964997216
Directory /workspace/489.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.3065203061
Short name T3192
Test name
Test status
Simulation time 46324910 ps
CPU time 0.66 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:38:54 PM PDT 24
Peak memory 207456 kb
Host smart-79770762-609a-4915-a598-2d6344b58083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3065203061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.3065203061
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.993032401
Short name T3062
Test name
Test status
Simulation time 6478789001 ps
CPU time 9.04 seconds
Started Aug 18 05:39:03 PM PDT 24
Finished Aug 18 05:39:12 PM PDT 24
Peak memory 216000 kb
Host smart-cced82bd-56ca-41a3-957e-701392acfa29
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993032401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_ao
n_wake_disconnect.993032401
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.140619006
Short name T3635
Test name
Test status
Simulation time 19743518082 ps
CPU time 23.97 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:39:19 PM PDT 24
Peak memory 207824 kb
Host smart-5e56cb95-8520-4c0c-a1e4-db76dc6d7d45
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=140619006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.140619006
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.3881591600
Short name T2817
Test name
Test status
Simulation time 30517039818 ps
CPU time 37.47 seconds
Started Aug 18 05:38:58 PM PDT 24
Finished Aug 18 05:39:36 PM PDT 24
Peak memory 207848 kb
Host smart-bd3ade4f-8cfa-4cbb-8058-6d88f630afaf
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881591600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.3881591600
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.127336173
Short name T2447
Test name
Test status
Simulation time 169359717 ps
CPU time 0.87 seconds
Started Aug 18 05:38:51 PM PDT 24
Finished Aug 18 05:38:52 PM PDT 24
Peak memory 207488 kb
Host smart-27f0661b-0dc2-4634-9d72-170b0b53fe25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12733
6173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.127336173
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2830591766
Short name T2540
Test name
Test status
Simulation time 151560459 ps
CPU time 0.84 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207544 kb
Host smart-abbbf24c-e0e6-435e-9b16-836bd2fe130c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28305
91766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2830591766
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.2457641557
Short name T997
Test name
Test status
Simulation time 257461555 ps
CPU time 1.06 seconds
Started Aug 18 05:38:49 PM PDT 24
Finished Aug 18 05:38:50 PM PDT 24
Peak memory 207540 kb
Host smart-1541f905-6686-4e54-83e4-f5a67452e69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24576
41557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.2457641557
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.4082799206
Short name T951
Test name
Test status
Simulation time 724622177 ps
CPU time 2.06 seconds
Started Aug 18 05:38:43 PM PDT 24
Finished Aug 18 05:38:45 PM PDT 24
Peak memory 207448 kb
Host smart-5ad5cbe3-5e45-4ef7-87c7-d72e5dd57fa4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4082799206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.4082799206
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.945525675
Short name T1901
Test name
Test status
Simulation time 31669401041 ps
CPU time 51.26 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:39:46 PM PDT 24
Peak memory 207716 kb
Host smart-eb31bda1-2f39-4914-90d0-1c239274f177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94552
5675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.945525675
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.2508243549
Short name T737
Test name
Test status
Simulation time 3744738556 ps
CPU time 26.45 seconds
Started Aug 18 05:38:50 PM PDT 24
Finished Aug 18 05:39:17 PM PDT 24
Peak memory 207780 kb
Host smart-9a338d34-6f64-4de7-8be3-b83de5f2152e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508243549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.2508243549
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.448260681
Short name T795
Test name
Test status
Simulation time 507189004 ps
CPU time 1.53 seconds
Started Aug 18 05:38:53 PM PDT 24
Finished Aug 18 05:38:55 PM PDT 24
Peak memory 207528 kb
Host smart-13199288-3e49-47d8-b935-2b314669fcd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44826
0681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.448260681
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1741758275
Short name T3390
Test name
Test status
Simulation time 173090057 ps
CPU time 0.9 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:38:56 PM PDT 24
Peak memory 207520 kb
Host smart-dcad1fbc-1421-440e-beba-9430cb6bb830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17417
58275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1741758275
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2572667993
Short name T2851
Test name
Test status
Simulation time 31198376 ps
CPU time 0.68 seconds
Started Aug 18 05:39:07 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207460 kb
Host smart-753c020d-ac79-46b3-93ff-df3be6e9a770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25726
67993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2572667993
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.389001480
Short name T1269
Test name
Test status
Simulation time 953552219 ps
CPU time 2.56 seconds
Started Aug 18 05:38:58 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207816 kb
Host smart-5f86fb1b-2359-4d83-a161-8445e30a373c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38900
1480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.389001480
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_types.1442296413
Short name T2963
Test name
Test status
Simulation time 574172498 ps
CPU time 1.56 seconds
Started Aug 18 05:38:56 PM PDT 24
Finished Aug 18 05:38:58 PM PDT 24
Peak memory 207548 kb
Host smart-3a162d69-edcb-413e-bfe3-ffd23dea682e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1442296413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_types.1442296413
Directory /workspace/49.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2902450547
Short name T1787
Test name
Test status
Simulation time 232137320 ps
CPU time 1.85 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207652 kb
Host smart-29ea132e-15c3-45d8-bf75-2429327c70bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29024
50547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2902450547
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1565143099
Short name T1314
Test name
Test status
Simulation time 191687949 ps
CPU time 0.99 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 215896 kb
Host smart-fb86bab1-4010-499c-b1ce-768209b2fed5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1565143099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1565143099
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2562991955
Short name T885
Test name
Test status
Simulation time 146582278 ps
CPU time 0.82 seconds
Started Aug 18 05:38:46 PM PDT 24
Finished Aug 18 05:38:47 PM PDT 24
Peak memory 207428 kb
Host smart-24f03f14-8539-44be-a8a1-8d4a31ca8dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25629
91955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2562991955
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.4131601966
Short name T3584
Test name
Test status
Simulation time 228479851 ps
CPU time 1.01 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207372 kb
Host smart-be8ac89f-e1b4-48f5-bc42-eb3dc01a3855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41316
01966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.4131601966
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.2039106076
Short name T1442
Test name
Test status
Simulation time 3956547804 ps
CPU time 116.24 seconds
Started Aug 18 05:38:50 PM PDT 24
Finished Aug 18 05:40:47 PM PDT 24
Peak memory 217600 kb
Host smart-5faf48b0-fa8b-48c2-9569-d978ca195ad5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2039106076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.2039106076
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.3447981965
Short name T812
Test name
Test status
Simulation time 10024957353 ps
CPU time 118.7 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:40:53 PM PDT 24
Peak memory 207712 kb
Host smart-046e8a59-d603-418a-aa44-0b41dd4ea294
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3447981965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.3447981965
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.56327027
Short name T2306
Test name
Test status
Simulation time 249828306 ps
CPU time 0.99 seconds
Started Aug 18 05:38:51 PM PDT 24
Finished Aug 18 05:38:53 PM PDT 24
Peak memory 207460 kb
Host smart-fbe87662-0a08-4fcd-b1fa-beb13013ac05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56327
027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.56327027
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.342165089
Short name T3130
Test name
Test status
Simulation time 11252871648 ps
CPU time 18.39 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207764 kb
Host smart-d7a6616c-86fc-4395-bc5f-fa443684a0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34216
5089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.342165089
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.497907979
Short name T2182
Test name
Test status
Simulation time 4342889378 ps
CPU time 5.74 seconds
Started Aug 18 05:38:52 PM PDT 24
Finished Aug 18 05:38:58 PM PDT 24
Peak memory 207760 kb
Host smart-d380a102-f98f-4d09-924f-1b87b03f8121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49790
7979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.497907979
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.1239312361
Short name T3529
Test name
Test status
Simulation time 2808425919 ps
CPU time 26.61 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:26 PM PDT 24
Peak memory 219112 kb
Host smart-6dc491e3-b173-4e18-b18e-92e6d0aa3822
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1239312361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.1239312361
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.2475500266
Short name T913
Test name
Test status
Simulation time 3787446316 ps
CPU time 30.15 seconds
Started Aug 18 05:39:18 PM PDT 24
Finished Aug 18 05:39:48 PM PDT 24
Peak memory 217776 kb
Host smart-416832a1-cc02-444a-bc78-1a5ec7ddb8c8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2475500266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.2475500266
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.331563655
Short name T3496
Test name
Test status
Simulation time 242235915 ps
CPU time 1.02 seconds
Started Aug 18 05:38:47 PM PDT 24
Finished Aug 18 05:38:48 PM PDT 24
Peak memory 207484 kb
Host smart-241284a5-e4fa-42bc-a8f8-0434fab79938
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=331563655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.331563655
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2521683586
Short name T2871
Test name
Test status
Simulation time 200579930 ps
CPU time 0.94 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:38:55 PM PDT 24
Peak memory 207496 kb
Host smart-4df26223-e66f-49e3-81b0-9c251db567a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25216
83586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2521683586
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.495963448
Short name T3142
Test name
Test status
Simulation time 2666269437 ps
CPU time 74.17 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:40:14 PM PDT 24
Peak memory 223940 kb
Host smart-a5ac26ff-fe23-4acf-9e1b-1dbff18d334d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=495963448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.495963448
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1945666478
Short name T3341
Test name
Test status
Simulation time 156920275 ps
CPU time 0.88 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207468 kb
Host smart-ef98136d-2d0d-4d4e-9060-de4b31b25f6e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1945666478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1945666478
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.763985412
Short name T1132
Test name
Test status
Simulation time 141279637 ps
CPU time 0.82 seconds
Started Aug 18 05:38:56 PM PDT 24
Finished Aug 18 05:38:57 PM PDT 24
Peak memory 207440 kb
Host smart-2e0098ee-9459-4c04-bfbf-9b5521eb8a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76398
5412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.763985412
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2382848720
Short name T3009
Test name
Test status
Simulation time 162503677 ps
CPU time 0.91 seconds
Started Aug 18 05:38:58 PM PDT 24
Finished Aug 18 05:38:59 PM PDT 24
Peak memory 207484 kb
Host smart-5badb3f3-8830-4d15-a318-65522be3f174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23828
48720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2382848720
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.996792875
Short name T2068
Test name
Test status
Simulation time 191238509 ps
CPU time 0.9 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:38:55 PM PDT 24
Peak memory 207476 kb
Host smart-f95060c4-0296-4380-8248-9ed1a4dfce9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99679
2875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.996792875
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2403944629
Short name T1268
Test name
Test status
Simulation time 160705809 ps
CPU time 0.82 seconds
Started Aug 18 05:38:58 PM PDT 24
Finished Aug 18 05:38:59 PM PDT 24
Peak memory 207508 kb
Host smart-ee940e88-b2b5-44b0-831f-66a04410d690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24039
44629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2403944629
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1897722816
Short name T143
Test name
Test status
Simulation time 170710095 ps
CPU time 0.86 seconds
Started Aug 18 05:38:48 PM PDT 24
Finished Aug 18 05:38:49 PM PDT 24
Peak memory 207596 kb
Host smart-05670651-6e82-44f3-b1e5-523b27b86e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18977
22816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1897722816
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3426788253
Short name T1680
Test name
Test status
Simulation time 144325222 ps
CPU time 0.9 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:38:56 PM PDT 24
Peak memory 207448 kb
Host smart-ddba4f42-be6b-4e9f-8184-fe87627eff00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34267
88253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3426788253
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.2021221320
Short name T2874
Test name
Test status
Simulation time 206722645 ps
CPU time 1 seconds
Started Aug 18 05:38:49 PM PDT 24
Finished Aug 18 05:38:50 PM PDT 24
Peak memory 207508 kb
Host smart-1f07f379-c714-489d-938c-f25d5b0eb2da
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2021221320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.2021221320
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2300782070
Short name T748
Test name
Test status
Simulation time 168297952 ps
CPU time 0.92 seconds
Started Aug 18 05:39:01 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207452 kb
Host smart-18e02198-eada-44e3-a258-9e2316c936ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23007
82070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2300782070
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.727931155
Short name T3318
Test name
Test status
Simulation time 39258454 ps
CPU time 0.69 seconds
Started Aug 18 05:38:45 PM PDT 24
Finished Aug 18 05:38:46 PM PDT 24
Peak memory 207492 kb
Host smart-4e870c77-dedb-405a-9378-8177029276ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72793
1155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.727931155
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.782851493
Short name T2792
Test name
Test status
Simulation time 16003979919 ps
CPU time 39.84 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:39:35 PM PDT 24
Peak memory 215996 kb
Host smart-b32f1369-f6d6-4439-8e9d-8b3c822b5c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78285
1493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.782851493
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2124550195
Short name T2847
Test name
Test status
Simulation time 151394627 ps
CPU time 0.83 seconds
Started Aug 18 05:38:45 PM PDT 24
Finished Aug 18 05:38:47 PM PDT 24
Peak memory 207564 kb
Host smart-19d496c8-b816-4be3-9cbd-53146aa8568a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21245
50195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2124550195
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2040698303
Short name T2429
Test name
Test status
Simulation time 268761438 ps
CPU time 1.01 seconds
Started Aug 18 05:38:49 PM PDT 24
Finished Aug 18 05:38:50 PM PDT 24
Peak memory 207432 kb
Host smart-38d8e12b-7fc4-458e-9bd2-8f5f84781b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20406
98303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2040698303
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.939845416
Short name T598
Test name
Test status
Simulation time 225273441 ps
CPU time 1.03 seconds
Started Aug 18 05:38:51 PM PDT 24
Finished Aug 18 05:38:52 PM PDT 24
Peak memory 207492 kb
Host smart-5ea7321e-9fdb-4a6e-af86-b135401653f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93984
5416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.939845416
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.2549593087
Short name T2093
Test name
Test status
Simulation time 177401961 ps
CPU time 0.91 seconds
Started Aug 18 05:38:53 PM PDT 24
Finished Aug 18 05:38:54 PM PDT 24
Peak memory 207444 kb
Host smart-7cb5d268-29eb-4012-a025-f9bb84b31e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25495
93087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.2549593087
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2882217016
Short name T1596
Test name
Test status
Simulation time 152887042 ps
CPU time 0.82 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207464 kb
Host smart-518cdcbb-ca85-40ab-a764-d01135362dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28822
17016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2882217016
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_rx_full.802761712
Short name T702
Test name
Test status
Simulation time 395211938 ps
CPU time 1.48 seconds
Started Aug 18 05:38:57 PM PDT 24
Finished Aug 18 05:38:59 PM PDT 24
Peak memory 207508 kb
Host smart-3c420525-3728-4c49-b450-9ff2e306d9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80276
1712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_full.802761712
Directory /workspace/49.usbdev_rx_full/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.3030183178
Short name T1542
Test name
Test status
Simulation time 158518967 ps
CPU time 0.86 seconds
Started Aug 18 05:38:56 PM PDT 24
Finished Aug 18 05:38:57 PM PDT 24
Peak memory 207500 kb
Host smart-972cf928-2251-45f1-91f5-0f06329f104f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30301
83178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.3030183178
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2794930495
Short name T3079
Test name
Test status
Simulation time 181336626 ps
CPU time 0.92 seconds
Started Aug 18 05:38:57 PM PDT 24
Finished Aug 18 05:38:58 PM PDT 24
Peak memory 207460 kb
Host smart-b55bcbe9-4ca1-41c1-8230-b234ae06f417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27949
30495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2794930495
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.4275559717
Short name T994
Test name
Test status
Simulation time 229142643 ps
CPU time 1.08 seconds
Started Aug 18 05:39:01 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207500 kb
Host smart-ec75d4e3-06ec-4549-9748-35db721ff343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42755
59717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.4275559717
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.511654536
Short name T2389
Test name
Test status
Simulation time 2726129950 ps
CPU time 79.3 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:40:18 PM PDT 24
Peak memory 215956 kb
Host smart-34f779b2-a3a2-49b8-95aa-124e57d8cbc8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=511654536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.511654536
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2949933591
Short name T2607
Test name
Test status
Simulation time 188207501 ps
CPU time 0.88 seconds
Started Aug 18 05:39:17 PM PDT 24
Finished Aug 18 05:39:18 PM PDT 24
Peak memory 207452 kb
Host smart-4379db06-7714-4d32-82f7-b4dcc276d898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29499
33591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2949933591
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.2329809458
Short name T1051
Test name
Test status
Simulation time 196194545 ps
CPU time 0.92 seconds
Started Aug 18 05:39:01 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207708 kb
Host smart-3dfdf7c3-1d4a-4a61-b4fa-29a226e4da91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23298
09458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.2329809458
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.1862829287
Short name T2881
Test name
Test status
Simulation time 832968367 ps
CPU time 2.03 seconds
Started Aug 18 05:39:04 PM PDT 24
Finished Aug 18 05:39:11 PM PDT 24
Peak memory 207748 kb
Host smart-b30e0086-0e9e-42a7-bf46-8def91d778b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18628
29287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.1862829287
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.3818635425
Short name T2777
Test name
Test status
Simulation time 2490009472 ps
CPU time 69.28 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:40:08 PM PDT 24
Peak memory 216012 kb
Host smart-aff5d596-b47b-4f82-aa84-fcee2ec142a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38186
35425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.3818635425
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.2593741333
Short name T2134
Test name
Test status
Simulation time 1186026793 ps
CPU time 25.4 seconds
Started Aug 18 05:38:46 PM PDT 24
Finished Aug 18 05:39:11 PM PDT 24
Peak memory 207624 kb
Host smart-33d8adcd-5cff-47c8-8e37-0dda04edcc74
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593741333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_hos
t_handshake.2593741333
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_tx_rx_disruption.2920706800
Short name T2131
Test name
Test status
Simulation time 598302647 ps
CPU time 1.58 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207528 kb
Host smart-b716f900-fc1c-4aa4-95f7-194cf0b35ddd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920706800 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.usbdev_tx_rx_disruption.2920706800
Directory /workspace/49.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/490.usbdev_tx_rx_disruption.653762961
Short name T905
Test name
Test status
Simulation time 530389868 ps
CPU time 1.49 seconds
Started Aug 18 05:40:19 PM PDT 24
Finished Aug 18 05:40:20 PM PDT 24
Peak memory 207488 kb
Host smart-71d17311-6f1a-49e7-aacc-6d002ea8c3ba
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653762961 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 490.usbdev_tx_rx_disruption.653762961
Directory /workspace/490.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/491.usbdev_tx_rx_disruption.3652337308
Short name T3029
Test name
Test status
Simulation time 646706268 ps
CPU time 1.74 seconds
Started Aug 18 05:40:05 PM PDT 24
Finished Aug 18 05:40:07 PM PDT 24
Peak memory 207596 kb
Host smart-749c0f7f-c3b3-49d5-83a5-6ad06f8180a7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652337308 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 491.usbdev_tx_rx_disruption.3652337308
Directory /workspace/491.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/493.usbdev_tx_rx_disruption.3901270173
Short name T3396
Test name
Test status
Simulation time 668160671 ps
CPU time 1.8 seconds
Started Aug 18 05:40:16 PM PDT 24
Finished Aug 18 05:40:18 PM PDT 24
Peak memory 207500 kb
Host smart-772a3c60-6f16-4143-a001-8b56dcb49373
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901270173 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 493.usbdev_tx_rx_disruption.3901270173
Directory /workspace/493.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/494.usbdev_tx_rx_disruption.841786180
Short name T590
Test name
Test status
Simulation time 461179902 ps
CPU time 1.53 seconds
Started Aug 18 05:40:27 PM PDT 24
Finished Aug 18 05:40:29 PM PDT 24
Peak memory 207564 kb
Host smart-9f6e0cf7-bc8c-4691-9f1f-679b05fa855e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841786180 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 494.usbdev_tx_rx_disruption.841786180
Directory /workspace/494.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/495.usbdev_tx_rx_disruption.4076350513
Short name T3149
Test name
Test status
Simulation time 417781261 ps
CPU time 1.5 seconds
Started Aug 18 05:40:18 PM PDT 24
Finished Aug 18 05:40:19 PM PDT 24
Peak memory 207532 kb
Host smart-bb235dd8-f832-42e7-b58a-239cd3a125e4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076350513 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 495.usbdev_tx_rx_disruption.4076350513
Directory /workspace/495.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/496.usbdev_tx_rx_disruption.29725826
Short name T2805
Test name
Test status
Simulation time 567129322 ps
CPU time 1.61 seconds
Started Aug 18 05:40:25 PM PDT 24
Finished Aug 18 05:40:27 PM PDT 24
Peak memory 207572 kb
Host smart-5e4d1f4c-552e-4e6c-888a-75466f8d8b6a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29725826 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 496.usbdev_tx_rx_disruption.29725826
Directory /workspace/496.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/497.usbdev_tx_rx_disruption.4251723771
Short name T1846
Test name
Test status
Simulation time 470896102 ps
CPU time 1.48 seconds
Started Aug 18 05:40:21 PM PDT 24
Finished Aug 18 05:40:23 PM PDT 24
Peak memory 207584 kb
Host smart-0bf2d0bc-4354-45c9-924f-c7e871c43c24
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251723771 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 497.usbdev_tx_rx_disruption.4251723771
Directory /workspace/497.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/498.usbdev_tx_rx_disruption.406055662
Short name T2575
Test name
Test status
Simulation time 502776323 ps
CPU time 1.39 seconds
Started Aug 18 05:40:15 PM PDT 24
Finished Aug 18 05:40:17 PM PDT 24
Peak memory 207532 kb
Host smart-da56811f-a634-47df-a37c-99557d3761a6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406055662 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 498.usbdev_tx_rx_disruption.406055662
Directory /workspace/498.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/499.usbdev_tx_rx_disruption.3185976659
Short name T2988
Test name
Test status
Simulation time 491352986 ps
CPU time 1.5 seconds
Started Aug 18 05:40:11 PM PDT 24
Finished Aug 18 05:40:13 PM PDT 24
Peak memory 207560 kb
Host smart-d44b4830-238d-4eec-8aee-06937d52f07d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185976659 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 499.usbdev_tx_rx_disruption.3185976659
Directory /workspace/499.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.2555763448
Short name T2932
Test name
Test status
Simulation time 62680054 ps
CPU time 0.69 seconds
Started Aug 18 05:32:43 PM PDT 24
Finished Aug 18 05:32:44 PM PDT 24
Peak memory 207364 kb
Host smart-6477ad5b-0fa1-4a9e-809a-d5bf22ee4010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2555763448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.2555763448
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.288649349
Short name T887
Test name
Test status
Simulation time 10209186649 ps
CPU time 14.88 seconds
Started Aug 18 05:32:35 PM PDT 24
Finished Aug 18 05:32:50 PM PDT 24
Peak memory 207752 kb
Host smart-5391bd02-13b5-4dd8-b5f3-76fd8a6a3dc6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288649349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon
_wake_disconnect.288649349
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3568984845
Short name T2458
Test name
Test status
Simulation time 15964505793 ps
CPU time 18.85 seconds
Started Aug 18 05:32:34 PM PDT 24
Finished Aug 18 05:32:53 PM PDT 24
Peak memory 215896 kb
Host smart-8eb47dae-bfcc-4b93-9475-eaae599fbe63
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568984845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3568984845
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.1768841426
Short name T7
Test name
Test status
Simulation time 23478595322 ps
CPU time 29.25 seconds
Started Aug 18 05:32:40 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 215996 kb
Host smart-e65966df-e80b-45e3-8769-c7546de9f5e2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768841426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.1768841426
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2798510075
Short name T3001
Test name
Test status
Simulation time 175348894 ps
CPU time 0.85 seconds
Started Aug 18 05:32:37 PM PDT 24
Finished Aug 18 05:32:38 PM PDT 24
Peak memory 207476 kb
Host smart-469a495a-31d1-4b18-a892-49ce53d8ca77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27985
10075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2798510075
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.4087339989
Short name T3138
Test name
Test status
Simulation time 163128620 ps
CPU time 0.89 seconds
Started Aug 18 05:32:39 PM PDT 24
Finished Aug 18 05:32:40 PM PDT 24
Peak memory 207560 kb
Host smart-5779cb95-d77b-4c02-b381-b4d85d49a1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40873
39989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.4087339989
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.206587981
Short name T2886
Test name
Test status
Simulation time 400656448 ps
CPU time 1.48 seconds
Started Aug 18 05:32:28 PM PDT 24
Finished Aug 18 05:32:29 PM PDT 24
Peak memory 207568 kb
Host smart-5fbe8ece-bd41-4e0d-9cb9-f2c264120943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20658
7981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.206587981
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1708407264
Short name T1255
Test name
Test status
Simulation time 770574334 ps
CPU time 2.19 seconds
Started Aug 18 05:32:46 PM PDT 24
Finished Aug 18 05:32:48 PM PDT 24
Peak memory 207760 kb
Host smart-96a74a02-b196-4c22-bb94-e02edeaab92d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1708407264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1708407264
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.1225333135
Short name T2012
Test name
Test status
Simulation time 47011177670 ps
CPU time 84.01 seconds
Started Aug 18 05:32:37 PM PDT 24
Finished Aug 18 05:34:02 PM PDT 24
Peak memory 207836 kb
Host smart-23778bd6-8fd8-423d-aa05-73e15587ee26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12253
33135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.1225333135
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.3156763743
Short name T2810
Test name
Test status
Simulation time 861268918 ps
CPU time 5.22 seconds
Started Aug 18 05:32:44 PM PDT 24
Finished Aug 18 05:32:50 PM PDT 24
Peak memory 207704 kb
Host smart-46d43e49-403e-411e-b451-cf6c8098e71a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156763743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.3156763743
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3431299755
Short name T2568
Test name
Test status
Simulation time 736860159 ps
CPU time 1.83 seconds
Started Aug 18 05:32:38 PM PDT 24
Finished Aug 18 05:32:39 PM PDT 24
Peak memory 207508 kb
Host smart-160f8f05-bc3c-44a0-936e-7f746e85a0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34312
99755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3431299755
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3515983912
Short name T2347
Test name
Test status
Simulation time 138999647 ps
CPU time 0.84 seconds
Started Aug 18 05:32:45 PM PDT 24
Finished Aug 18 05:32:46 PM PDT 24
Peak memory 207468 kb
Host smart-4039d39b-5fb9-4df3-aa4e-59b6b2a22d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35159
83912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3515983912
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2421467999
Short name T1487
Test name
Test status
Simulation time 34530481 ps
CPU time 0.72 seconds
Started Aug 18 05:32:37 PM PDT 24
Finished Aug 18 05:32:38 PM PDT 24
Peak memory 207384 kb
Host smart-24202ad2-f75e-407d-a752-1c81c1769c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24214
67999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2421467999
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.3344528112
Short name T2738
Test name
Test status
Simulation time 950208472 ps
CPU time 2.56 seconds
Started Aug 18 05:32:44 PM PDT 24
Finished Aug 18 05:32:47 PM PDT 24
Peak memory 207776 kb
Host smart-7662743c-b08f-4bea-a6a8-88deda3c591d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33445
28112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3344528112
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_types.1172720175
Short name T464
Test name
Test status
Simulation time 380264672 ps
CPU time 1.27 seconds
Started Aug 18 05:32:43 PM PDT 24
Finished Aug 18 05:32:45 PM PDT 24
Peak memory 207536 kb
Host smart-104dc244-94b0-4ef4-b6ed-bfb56adeedcb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1172720175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_types.1172720175
Directory /workspace/5.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.702119085
Short name T3264
Test name
Test status
Simulation time 262820470 ps
CPU time 1.87 seconds
Started Aug 18 05:32:31 PM PDT 24
Finished Aug 18 05:32:33 PM PDT 24
Peak memory 207668 kb
Host smart-53c24dee-5b10-465a-833f-edd48296dd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70211
9085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.702119085
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.1118675384
Short name T3187
Test name
Test status
Simulation time 210182858 ps
CPU time 1.08 seconds
Started Aug 18 05:32:42 PM PDT 24
Finished Aug 18 05:32:43 PM PDT 24
Peak memory 216032 kb
Host smart-c8858e61-40e4-4e27-b5c9-e162cac5cf72
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1118675384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.1118675384
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2377214182
Short name T2388
Test name
Test status
Simulation time 141748966 ps
CPU time 0.84 seconds
Started Aug 18 05:32:42 PM PDT 24
Finished Aug 18 05:32:43 PM PDT 24
Peak memory 207360 kb
Host smart-429191e3-edc1-4f2b-99f6-926797c8cd34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23772
14182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2377214182
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.784004389
Short name T1664
Test name
Test status
Simulation time 242761983 ps
CPU time 1.02 seconds
Started Aug 18 05:32:42 PM PDT 24
Finished Aug 18 05:32:43 PM PDT 24
Peak memory 207480 kb
Host smart-357ddeee-15c4-498d-9924-7259c1155d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78400
4389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.784004389
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.2627008767
Short name T2510
Test name
Test status
Simulation time 4056589583 ps
CPU time 40.93 seconds
Started Aug 18 05:32:37 PM PDT 24
Finished Aug 18 05:33:18 PM PDT 24
Peak memory 217112 kb
Host smart-3032af1d-8bf1-4fcf-82f2-b6cfe8c7dd3f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2627008767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.2627008767
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.1495094029
Short name T2177
Test name
Test status
Simulation time 12348849609 ps
CPU time 148.61 seconds
Started Aug 18 05:32:30 PM PDT 24
Finished Aug 18 05:34:59 PM PDT 24
Peak memory 207708 kb
Host smart-048c05d8-076d-42f6-a8bf-009e3166fc9e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1495094029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.1495094029
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.3256319332
Short name T1608
Test name
Test status
Simulation time 190769073 ps
CPU time 0.9 seconds
Started Aug 18 05:32:46 PM PDT 24
Finished Aug 18 05:32:47 PM PDT 24
Peak memory 207464 kb
Host smart-7980ca79-d8bc-4032-a8e1-40da7e4da0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32563
19332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.3256319332
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.3070658516
Short name T1830
Test name
Test status
Simulation time 11878957843 ps
CPU time 14.95 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:33:03 PM PDT 24
Peak memory 207764 kb
Host smart-b494d1da-0298-4ec8-ac72-b3419b59312b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30706
58516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.3070658516
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.2376109304
Short name T2083
Test name
Test status
Simulation time 4999552914 ps
CPU time 7.23 seconds
Started Aug 18 05:32:44 PM PDT 24
Finished Aug 18 05:32:51 PM PDT 24
Peak memory 216916 kb
Host smart-80876e60-b330-4ccc-9e50-1e285e83f006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23761
09304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2376109304
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.3268134177
Short name T2953
Test name
Test status
Simulation time 2427826827 ps
CPU time 22.65 seconds
Started Aug 18 05:32:42 PM PDT 24
Finished Aug 18 05:33:05 PM PDT 24
Peak memory 215896 kb
Host smart-94aa4999-e101-44e5-8639-8022101627de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3268134177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.3268134177
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.3079673761
Short name T741
Test name
Test status
Simulation time 2339069775 ps
CPU time 65.93 seconds
Started Aug 18 05:32:35 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 216016 kb
Host smart-87391176-8b5c-4cbe-9f2d-2c9cd1062661
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3079673761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3079673761
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.691329114
Short name T1103
Test name
Test status
Simulation time 233573469 ps
CPU time 1.04 seconds
Started Aug 18 05:32:40 PM PDT 24
Finished Aug 18 05:32:41 PM PDT 24
Peak memory 207492 kb
Host smart-ee89e777-54a5-421d-9a82-42cf93da0f65
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=691329114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.691329114
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2315101817
Short name T3426
Test name
Test status
Simulation time 202670584 ps
CPU time 0.97 seconds
Started Aug 18 05:32:49 PM PDT 24
Finished Aug 18 05:32:50 PM PDT 24
Peak memory 207520 kb
Host smart-6cfa5ff5-85a5-4726-8dbc-6c277faa61c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23151
01817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2315101817
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_non_iso_usb_traffic.1893733882
Short name T814
Test name
Test status
Simulation time 2071610176 ps
CPU time 58.04 seconds
Started Aug 18 05:32:45 PM PDT 24
Finished Aug 18 05:33:43 PM PDT 24
Peak memory 215844 kb
Host smart-20486446-b5b6-4958-b6d3-1c11980e9f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18937
33882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_non_iso_usb_traffic.1893733882
Directory /workspace/5.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.4245887008
Short name T1722
Test name
Test status
Simulation time 2056635804 ps
CPU time 18.84 seconds
Started Aug 18 05:32:40 PM PDT 24
Finished Aug 18 05:32:59 PM PDT 24
Peak memory 217396 kb
Host smart-871f3b41-c47c-4a5e-97e8-0d339b80886b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4245887008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.4245887008
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.1342974135
Short name T3147
Test name
Test status
Simulation time 3058344027 ps
CPU time 23.87 seconds
Started Aug 18 05:32:30 PM PDT 24
Finished Aug 18 05:32:54 PM PDT 24
Peak memory 224088 kb
Host smart-65842f4e-b7ec-482c-822e-9db5174f5ec2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1342974135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.1342974135
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.1120544030
Short name T1126
Test name
Test status
Simulation time 162280633 ps
CPU time 0.93 seconds
Started Aug 18 05:32:47 PM PDT 24
Finished Aug 18 05:32:48 PM PDT 24
Peak memory 207508 kb
Host smart-ebc00a33-396b-47e4-990c-27961fea663f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1120544030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.1120544030
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1396683279
Short name T2216
Test name
Test status
Simulation time 146076488 ps
CPU time 0.83 seconds
Started Aug 18 05:32:46 PM PDT 24
Finished Aug 18 05:32:47 PM PDT 24
Peak memory 207364 kb
Host smart-c5c0f258-2901-421a-aad3-c91d0f81e889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13966
83279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1396683279
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.4083578667
Short name T172
Test name
Test status
Simulation time 227007083 ps
CPU time 0.99 seconds
Started Aug 18 05:32:40 PM PDT 24
Finished Aug 18 05:32:41 PM PDT 24
Peak memory 207440 kb
Host smart-ae945101-430d-4b91-b562-6ed379dcdc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40835
78667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.4083578667
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.4084597280
Short name T2088
Test name
Test status
Simulation time 177477173 ps
CPU time 0.91 seconds
Started Aug 18 05:32:39 PM PDT 24
Finished Aug 18 05:32:40 PM PDT 24
Peak memory 207512 kb
Host smart-a84e677e-cf9a-4f2d-86c4-e59badfc9bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40845
97280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.4084597280
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.4190818379
Short name T936
Test name
Test status
Simulation time 168031269 ps
CPU time 0.87 seconds
Started Aug 18 05:32:43 PM PDT 24
Finished Aug 18 05:32:44 PM PDT 24
Peak memory 207444 kb
Host smart-8a2c3b99-8a69-4707-9087-bb94b564d078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41908
18379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.4190818379
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3617460636
Short name T3619
Test name
Test status
Simulation time 189496262 ps
CPU time 0.85 seconds
Started Aug 18 05:32:37 PM PDT 24
Finished Aug 18 05:32:38 PM PDT 24
Peak memory 207492 kb
Host smart-85120b3d-986c-4043-8fca-7d8515a44f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36174
60636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3617460636
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1334780651
Short name T1508
Test name
Test status
Simulation time 157502860 ps
CPU time 0.88 seconds
Started Aug 18 05:32:41 PM PDT 24
Finished Aug 18 05:32:42 PM PDT 24
Peak memory 207488 kb
Host smart-f0a71544-d9aa-4f9a-8973-d6dfa1516900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13347
80651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1334780651
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2807245755
Short name T1134
Test name
Test status
Simulation time 214650999 ps
CPU time 1.03 seconds
Started Aug 18 05:32:47 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207532 kb
Host smart-aabfb295-51e3-4d63-8215-97d860cc6637
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2807245755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2807245755
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2386778567
Short name T1751
Test name
Test status
Simulation time 231592984 ps
CPU time 0.92 seconds
Started Aug 18 05:32:38 PM PDT 24
Finished Aug 18 05:32:39 PM PDT 24
Peak memory 207404 kb
Host smart-679c2190-d92d-49c7-9488-a6659f7f1533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23867
78567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2386778567
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3521208398
Short name T2304
Test name
Test status
Simulation time 38501714 ps
CPU time 0.68 seconds
Started Aug 18 05:32:42 PM PDT 24
Finished Aug 18 05:32:42 PM PDT 24
Peak memory 207528 kb
Host smart-118620f2-f74e-46d4-b226-b1973ebd219f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35212
08398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3521208398
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3954975915
Short name T2075
Test name
Test status
Simulation time 8570340930 ps
CPU time 21.36 seconds
Started Aug 18 05:32:33 PM PDT 24
Finished Aug 18 05:32:55 PM PDT 24
Peak memory 224096 kb
Host smart-9db5f133-a50f-4579-88dc-77a66c6bcd05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39549
75915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3954975915
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.418374060
Short name T3198
Test name
Test status
Simulation time 175995239 ps
CPU time 0.9 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207488 kb
Host smart-0467e44b-ad1e-43b2-bb22-5d362308e12a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41837
4060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.418374060
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.332870690
Short name T609
Test name
Test status
Simulation time 203691488 ps
CPU time 1.02 seconds
Started Aug 18 05:32:33 PM PDT 24
Finished Aug 18 05:32:34 PM PDT 24
Peak memory 207456 kb
Host smart-b0d8170f-614b-4102-b9e1-39938597966c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33287
0690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.332870690
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.581553288
Short name T2838
Test name
Test status
Simulation time 2561427078 ps
CPU time 17.1 seconds
Started Aug 18 05:32:37 PM PDT 24
Finished Aug 18 05:32:55 PM PDT 24
Peak memory 218368 kb
Host smart-f3d314e6-9c5e-47d4-90b7-e2a559b00a41
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=581553288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.581553288
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.1473318671
Short name T3480
Test name
Test status
Simulation time 6432056889 ps
CPU time 92.99 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:34:25 PM PDT 24
Peak memory 219272 kb
Host smart-185be4e0-30b0-47fc-93f9-0fd123b1c7ca
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1473318671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.1473318671
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.813345764
Short name T2312
Test name
Test status
Simulation time 11434756183 ps
CPU time 226.9 seconds
Started Aug 18 05:32:32 PM PDT 24
Finished Aug 18 05:36:19 PM PDT 24
Peak memory 218480 kb
Host smart-835df466-2ae6-4d39-919b-60ce5bd72a76
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=813345764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.813345764
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.214580696
Short name T526
Test name
Test status
Simulation time 240669320 ps
CPU time 1.02 seconds
Started Aug 18 05:32:45 PM PDT 24
Finished Aug 18 05:32:46 PM PDT 24
Peak memory 207372 kb
Host smart-810f41b2-cb79-4edd-ba66-f91f53c26f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21458
0696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.214580696
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.2106919820
Short name T1292
Test name
Test status
Simulation time 153917869 ps
CPU time 0.87 seconds
Started Aug 18 05:32:45 PM PDT 24
Finished Aug 18 05:32:46 PM PDT 24
Peak memory 207400 kb
Host smart-e72f4d9b-c995-47c7-aab2-4a88d28f9831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21069
19820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.2106919820
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_resume_link_active.3202283598
Short name T2563
Test name
Test status
Simulation time 20162746708 ps
CPU time 25.29 seconds
Started Aug 18 05:32:51 PM PDT 24
Finished Aug 18 05:33:16 PM PDT 24
Peak memory 207472 kb
Host smart-b58ef729-1454-48b5-b350-8b8a48a454c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32022
83598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_resume_link_active.3202283598
Directory /workspace/5.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.578596997
Short name T3606
Test name
Test status
Simulation time 152046144 ps
CPU time 0.81 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207464 kb
Host smart-082f4383-d8c2-44cc-a8ef-250d7a90692a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57859
6997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.578596997
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_rx_full.3218959474
Short name T2711
Test name
Test status
Simulation time 364846262 ps
CPU time 1.29 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:50 PM PDT 24
Peak memory 207496 kb
Host smart-20657aff-8840-4a9d-bf60-0028fca4a138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32189
59474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_full.3218959474
Directory /workspace/5.usbdev_rx_full/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3716456983
Short name T2101
Test name
Test status
Simulation time 148767799 ps
CPU time 0.89 seconds
Started Aug 18 05:32:42 PM PDT 24
Finished Aug 18 05:32:43 PM PDT 24
Peak memory 207340 kb
Host smart-594c78ee-0fb6-456e-8ef5-084ede76b063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37164
56983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3716456983
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3819442454
Short name T2639
Test name
Test status
Simulation time 169549636 ps
CPU time 0.87 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207544 kb
Host smart-a348ab4a-9107-45cc-b554-9cd5ddb43e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38194
42454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3819442454
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2280948443
Short name T2856
Test name
Test status
Simulation time 239701974 ps
CPU time 1.07 seconds
Started Aug 18 05:32:46 PM PDT 24
Finished Aug 18 05:32:47 PM PDT 24
Peak memory 207400 kb
Host smart-448545dd-b548-4a1d-9e4e-2af159744be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22809
48443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2280948443
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.159587760
Short name T2583
Test name
Test status
Simulation time 2093946223 ps
CPU time 58.41 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:33:51 PM PDT 24
Peak memory 217168 kb
Host smart-5a45e644-30ca-4049-8922-4bcd1f98f239
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=159587760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.159587760
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2465058165
Short name T3323
Test name
Test status
Simulation time 161921042 ps
CPU time 0.84 seconds
Started Aug 18 05:32:46 PM PDT 24
Finished Aug 18 05:32:47 PM PDT 24
Peak memory 207408 kb
Host smart-aca8165a-1fae-46e0-bcbe-4249c3f53fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24650
58165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2465058165
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1301459559
Short name T3035
Test name
Test status
Simulation time 177640592 ps
CPU time 0.9 seconds
Started Aug 18 05:32:51 PM PDT 24
Finished Aug 18 05:32:52 PM PDT 24
Peak memory 207408 kb
Host smart-c5948181-53b8-4242-889f-8f3088faa4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13014
59559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1301459559
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.1503146732
Short name T3109
Test name
Test status
Simulation time 792543518 ps
CPU time 2.03 seconds
Started Aug 18 05:32:44 PM PDT 24
Finished Aug 18 05:32:47 PM PDT 24
Peak memory 207728 kb
Host smart-b08e3766-abd9-43d7-8d2f-6defee107c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15031
46732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.1503146732
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2484188705
Short name T759
Test name
Test status
Simulation time 3137783451 ps
CPU time 25.67 seconds
Started Aug 18 05:32:51 PM PDT 24
Finished Aug 18 05:33:17 PM PDT 24
Peak memory 217748 kb
Host smart-a2c5a5a2-b541-4de5-a08b-a04b8f520257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24841
88705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2484188705
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.2624562111
Short name T879
Test name
Test status
Simulation time 1069221070 ps
CPU time 9.43 seconds
Started Aug 18 05:32:51 PM PDT 24
Finished Aug 18 05:33:01 PM PDT 24
Peak memory 207672 kb
Host smart-97abb994-7ce6-4b18-b58a-3da75d03e5ad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624562111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.2624562111
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_tx_rx_disruption.30131393
Short name T1323
Test name
Test status
Simulation time 587188893 ps
CPU time 1.54 seconds
Started Aug 18 05:32:51 PM PDT 24
Finished Aug 18 05:32:52 PM PDT 24
Peak memory 207576 kb
Host smart-f61717a8-b3c6-4767-b94d-eb13f30908e0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30131393 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 5.usbdev_tx_rx_disruption.30131393
Directory /workspace/5.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/50.usbdev_endpoint_types.3490830753
Short name T478
Test name
Test status
Simulation time 196405474 ps
CPU time 0.92 seconds
Started Aug 18 05:38:56 PM PDT 24
Finished Aug 18 05:38:57 PM PDT 24
Peak memory 207548 kb
Host smart-c8f9a890-0826-41b0-a5cc-e775a529c222
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3490830753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_endpoint_types.3490830753
Directory /workspace/50.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/50.usbdev_tx_rx_disruption.3723388547
Short name T3595
Test name
Test status
Simulation time 492640727 ps
CPU time 1.52 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207500 kb
Host smart-62c48552-fb17-447d-a620-902aafd47308
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723388547 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.usbdev_tx_rx_disruption.3723388547
Directory /workspace/50.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/51.usbdev_endpoint_types.4284559389
Short name T3115
Test name
Test status
Simulation time 191048103 ps
CPU time 1.01 seconds
Started Aug 18 05:38:53 PM PDT 24
Finished Aug 18 05:38:55 PM PDT 24
Peak memory 207520 kb
Host smart-ea409525-7a93-49e0-a996-7df89478224c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4284559389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_endpoint_types.4284559389
Directory /workspace/51.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/51.usbdev_tx_rx_disruption.2531152054
Short name T1055
Test name
Test status
Simulation time 491298367 ps
CPU time 1.49 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:38:56 PM PDT 24
Peak memory 207676 kb
Host smart-a07cc828-8932-45c8-ade8-427ce6477ee2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531152054 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 51.usbdev_tx_rx_disruption.2531152054
Directory /workspace/51.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/52.usbdev_endpoint_types.1865734364
Short name T425
Test name
Test status
Simulation time 272574270 ps
CPU time 1.08 seconds
Started Aug 18 05:39:12 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207536 kb
Host smart-a5efc7a5-7443-4366-8c64-379c4dea2dfd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1865734364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_endpoint_types.1865734364
Directory /workspace/52.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/52.usbdev_tx_rx_disruption.3695844246
Short name T2716
Test name
Test status
Simulation time 465528230 ps
CPU time 1.51 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207380 kb
Host smart-bdb44b44-fa04-42bf-bb6d-42c9ecea5bfa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695844246 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.usbdev_tx_rx_disruption.3695844246
Directory /workspace/52.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/53.usbdev_endpoint_types.1690786558
Short name T2898
Test name
Test status
Simulation time 177529923 ps
CPU time 0.93 seconds
Started Aug 18 05:38:56 PM PDT 24
Finished Aug 18 05:38:57 PM PDT 24
Peak memory 207500 kb
Host smart-64315058-d916-44e9-9049-40fb17d4576c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1690786558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_endpoint_types.1690786558
Directory /workspace/53.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/53.usbdev_tx_rx_disruption.964005006
Short name T2990
Test name
Test status
Simulation time 635405162 ps
CPU time 1.57 seconds
Started Aug 18 05:39:11 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207564 kb
Host smart-522f3782-e110-4d1c-bcc7-45cc3668d030
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964005006 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 53.usbdev_tx_rx_disruption.964005006
Directory /workspace/53.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/54.usbdev_endpoint_types.2709607883
Short name T424
Test name
Test status
Simulation time 602447315 ps
CPU time 1.66 seconds
Started Aug 18 05:39:01 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207532 kb
Host smart-c3254aa9-2a91-48f8-8ad2-e0ad266fb2c1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2709607883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_endpoint_types.2709607883
Directory /workspace/54.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/54.usbdev_tx_rx_disruption.1506287893
Short name T3030
Test name
Test status
Simulation time 565446381 ps
CPU time 1.7 seconds
Started Aug 18 05:38:51 PM PDT 24
Finished Aug 18 05:38:53 PM PDT 24
Peak memory 207496 kb
Host smart-6920b731-f580-4c09-95bb-3c47c7f15cf9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506287893 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 54.usbdev_tx_rx_disruption.1506287893
Directory /workspace/54.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/55.usbdev_endpoint_types.1820820144
Short name T3466
Test name
Test status
Simulation time 443144812 ps
CPU time 1.42 seconds
Started Aug 18 05:38:58 PM PDT 24
Finished Aug 18 05:38:59 PM PDT 24
Peak memory 207532 kb
Host smart-b03c38c0-0218-44b7-95e3-280578526ba6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1820820144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_endpoint_types.1820820144
Directory /workspace/55.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/55.usbdev_tx_rx_disruption.1053235447
Short name T1546
Test name
Test status
Simulation time 593325654 ps
CPU time 1.62 seconds
Started Aug 18 05:39:04 PM PDT 24
Finished Aug 18 05:39:06 PM PDT 24
Peak memory 207588 kb
Host smart-7ea11575-a9e3-48af-b24d-73d3174298a1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053235447 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 55.usbdev_tx_rx_disruption.1053235447
Directory /workspace/55.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/56.usbdev_endpoint_types.3921913547
Short name T375
Test name
Test status
Simulation time 597591457 ps
CPU time 1.45 seconds
Started Aug 18 05:39:02 PM PDT 24
Finished Aug 18 05:39:04 PM PDT 24
Peak memory 207552 kb
Host smart-14181d5f-219b-4975-93e2-bf2a001656f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3921913547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_endpoint_types.3921913547
Directory /workspace/56.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/56.usbdev_tx_rx_disruption.2865438063
Short name T2574
Test name
Test status
Simulation time 616320179 ps
CPU time 1.62 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:38:56 PM PDT 24
Peak memory 207544 kb
Host smart-1c21d9fa-2f6c-4e44-8a95-eb5c3226a1d9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865438063 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.usbdev_tx_rx_disruption.2865438063
Directory /workspace/56.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/57.usbdev_endpoint_types.3456694912
Short name T475
Test name
Test status
Simulation time 852774980 ps
CPU time 1.95 seconds
Started Aug 18 05:38:50 PM PDT 24
Finished Aug 18 05:38:52 PM PDT 24
Peak memory 207464 kb
Host smart-937e5ae0-46cd-4256-b986-85dbfe2e91b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3456694912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_endpoint_types.3456694912
Directory /workspace/57.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/57.usbdev_tx_rx_disruption.944813102
Short name T1080
Test name
Test status
Simulation time 612553380 ps
CPU time 1.54 seconds
Started Aug 18 05:39:04 PM PDT 24
Finished Aug 18 05:39:06 PM PDT 24
Peak memory 207592 kb
Host smart-c01bc6e5-a82a-470e-a83e-20223e5f7d0b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944813102 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 57.usbdev_tx_rx_disruption.944813102
Directory /workspace/57.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/58.usbdev_endpoint_types.2538268967
Short name T503
Test name
Test status
Simulation time 262463477 ps
CPU time 1.01 seconds
Started Aug 18 05:38:56 PM PDT 24
Finished Aug 18 05:38:57 PM PDT 24
Peak memory 207456 kb
Host smart-e1781735-cf1d-4aa2-b65a-81e194793745
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2538268967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_endpoint_types.2538268967
Directory /workspace/58.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/58.usbdev_tx_rx_disruption.671327569
Short name T2349
Test name
Test status
Simulation time 568143964 ps
CPU time 1.73 seconds
Started Aug 18 05:39:06 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207532 kb
Host smart-cddf5b09-a89c-4eab-a1dd-b51885778d6e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671327569 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 58.usbdev_tx_rx_disruption.671327569
Directory /workspace/58.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/59.usbdev_endpoint_types.3302157171
Short name T482
Test name
Test status
Simulation time 442752830 ps
CPU time 1.35 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:38:57 PM PDT 24
Peak memory 207404 kb
Host smart-a0357c98-1f52-46f4-b791-6052ce55d5f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3302157171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_endpoint_types.3302157171
Directory /workspace/59.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/59.usbdev_tx_rx_disruption.1866689532
Short name T1155
Test name
Test status
Simulation time 592124832 ps
CPU time 1.62 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207588 kb
Host smart-934b9d6c-e765-4d94-a69b-e97569450b91
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866689532 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 59.usbdev_tx_rx_disruption.1866689532
Directory /workspace/59.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.3183136852
Short name T1419
Test name
Test status
Simulation time 39616739 ps
CPU time 0.69 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207464 kb
Host smart-531da2c7-472a-4a61-a7a1-280e902bf182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3183136852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.3183136852
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3258431042
Short name T1388
Test name
Test status
Simulation time 10042665483 ps
CPU time 12.68 seconds
Started Aug 18 05:32:41 PM PDT 24
Finished Aug 18 05:32:53 PM PDT 24
Peak memory 207804 kb
Host smart-817692cf-d0d4-44a2-aba1-8e864f713c2e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258431042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.3258431042
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.525675890
Short name T1340
Test name
Test status
Simulation time 14647814784 ps
CPU time 20.57 seconds
Started Aug 18 05:33:04 PM PDT 24
Finished Aug 18 05:33:25 PM PDT 24
Peak memory 215956 kb
Host smart-ae02858d-5ba3-4cce-bd8d-ba289d2d0e3d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=525675890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.525675890
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3069703807
Short name T1145
Test name
Test status
Simulation time 25262575059 ps
CPU time 31.14 seconds
Started Aug 18 05:32:46 PM PDT 24
Finished Aug 18 05:33:17 PM PDT 24
Peak memory 215980 kb
Host smart-97d06397-17e2-464f-9aaf-4a277d3b1bb2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069703807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.3069703807
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.394729212
Short name T569
Test name
Test status
Simulation time 198891961 ps
CPU time 0.93 seconds
Started Aug 18 05:32:49 PM PDT 24
Finished Aug 18 05:32:50 PM PDT 24
Peak memory 207416 kb
Host smart-45a4cff7-1c03-4308-9932-b4b603f9c99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39472
9212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.394729212
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1232360738
Short name T1986
Test name
Test status
Simulation time 149995945 ps
CPU time 0.85 seconds
Started Aug 18 05:32:46 PM PDT 24
Finished Aug 18 05:32:47 PM PDT 24
Peak memory 207512 kb
Host smart-e2abd9d2-519c-44ee-8945-0e6063b05851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12323
60738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1232360738
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.443155597
Short name T3103
Test name
Test status
Simulation time 442152679 ps
CPU time 1.48 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:50 PM PDT 24
Peak memory 207492 kb
Host smart-3eaf9045-3bc6-4042-9749-89662cac5a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44315
5597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.443155597
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.4211893879
Short name T354
Test name
Test status
Simulation time 449420896 ps
CPU time 1.45 seconds
Started Aug 18 05:32:45 PM PDT 24
Finished Aug 18 05:32:47 PM PDT 24
Peak memory 207484 kb
Host smart-2673ef4c-61c8-43c3-8676-b17cf1a89fa4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4211893879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.4211893879
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.888580540
Short name T528
Test name
Test status
Simulation time 39406528432 ps
CPU time 63.66 seconds
Started Aug 18 05:32:56 PM PDT 24
Finished Aug 18 05:33:59 PM PDT 24
Peak memory 207768 kb
Host smart-ac5f398b-36fa-4186-be4f-97fab8674a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88858
0540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.888580540
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.288265956
Short name T2380
Test name
Test status
Simulation time 1055893802 ps
CPU time 9.1 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:33:01 PM PDT 24
Peak memory 207732 kb
Host smart-437ed82c-e6af-4e0c-b03f-1917d62f8fbe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288265956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.288265956
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.786174592
Short name T3202
Test name
Test status
Simulation time 507180677 ps
CPU time 1.42 seconds
Started Aug 18 05:32:50 PM PDT 24
Finished Aug 18 05:32:57 PM PDT 24
Peak memory 207500 kb
Host smart-8e2d91f0-c148-4d6f-ab9c-5cdabe4254aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78617
4592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.786174592
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2074195564
Short name T1763
Test name
Test status
Simulation time 148391408 ps
CPU time 0.82 seconds
Started Aug 18 05:32:43 PM PDT 24
Finished Aug 18 05:32:44 PM PDT 24
Peak memory 207556 kb
Host smart-72e570c7-6135-4317-b512-2e691a4cfb8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20741
95564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2074195564
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.1472875880
Short name T3533
Test name
Test status
Simulation time 54970187 ps
CPU time 0.72 seconds
Started Aug 18 05:32:47 PM PDT 24
Finished Aug 18 05:32:53 PM PDT 24
Peak memory 207412 kb
Host smart-56a48ffb-e531-46d0-84f5-e5a8d25efff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14728
75880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1472875880
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.799015837
Short name T1474
Test name
Test status
Simulation time 900606271 ps
CPU time 2.63 seconds
Started Aug 18 05:33:00 PM PDT 24
Finished Aug 18 05:33:02 PM PDT 24
Peak memory 207800 kb
Host smart-a1384d21-3002-456e-af8a-8175b037b9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79901
5837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.799015837
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_types.2740546079
Short name T1779
Test name
Test status
Simulation time 198625266 ps
CPU time 0.91 seconds
Started Aug 18 05:32:46 PM PDT 24
Finished Aug 18 05:32:47 PM PDT 24
Peak memory 207544 kb
Host smart-68dca192-b85e-4e06-968a-69fc83f95f97
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2740546079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_types.2740546079
Directory /workspace/6.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2312912360
Short name T2794
Test name
Test status
Simulation time 228995236 ps
CPU time 1.9 seconds
Started Aug 18 05:32:47 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207668 kb
Host smart-0db3b1b7-d72d-4b80-9097-8175a5c8d771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23129
12360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2312912360
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2656672639
Short name T121
Test name
Test status
Simulation time 190604928 ps
CPU time 0.93 seconds
Started Aug 18 05:32:50 PM PDT 24
Finished Aug 18 05:32:51 PM PDT 24
Peak memory 207464 kb
Host smart-317bc055-9e8e-4f5b-b4d5-0a123aa37ca3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2656672639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2656672639
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2941163074
Short name T942
Test name
Test status
Simulation time 140640119 ps
CPU time 0.84 seconds
Started Aug 18 05:32:54 PM PDT 24
Finished Aug 18 05:32:55 PM PDT 24
Peak memory 207448 kb
Host smart-cc30f9c7-89bd-44f5-a7e4-5b7a4f02f9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29411
63074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2941163074
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2938819578
Short name T934
Test name
Test status
Simulation time 201037469 ps
CPU time 0.94 seconds
Started Aug 18 05:32:50 PM PDT 24
Finished Aug 18 05:32:51 PM PDT 24
Peak memory 207504 kb
Host smart-60afe08d-cb32-4be6-b01d-95385a07e208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29388
19578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2938819578
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.1976397726
Short name T3183
Test name
Test status
Simulation time 4358842200 ps
CPU time 34.06 seconds
Started Aug 18 05:32:47 PM PDT 24
Finished Aug 18 05:33:21 PM PDT 24
Peak memory 217332 kb
Host smart-c89594cd-448a-4b7c-b64f-0b38742d1c60
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1976397726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.1976397726
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.4187765482
Short name T1034
Test name
Test status
Simulation time 9353842367 ps
CPU time 67.79 seconds
Started Aug 18 05:32:53 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 207812 kb
Host smart-9d8e459a-5562-488c-ac27-a4f34fb86c87
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4187765482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.4187765482
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.2634978913
Short name T1013
Test name
Test status
Simulation time 216263743 ps
CPU time 0.95 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207500 kb
Host smart-75c9c34b-c5c2-460c-b8e6-768b4217783f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26349
78913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2634978913
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.987674238
Short name T1962
Test name
Test status
Simulation time 24551531468 ps
CPU time 46.76 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:33:39 PM PDT 24
Peak memory 216016 kb
Host smart-4f9ab4fc-1e5e-4249-b9eb-b31582e3fa12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98767
4238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.987674238
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.4281040774
Short name T1607
Test name
Test status
Simulation time 3572811320 ps
CPU time 6.36 seconds
Started Aug 18 05:32:59 PM PDT 24
Finished Aug 18 05:33:05 PM PDT 24
Peak memory 216036 kb
Host smart-7b39e952-e155-4af9-ada0-e07597cd39d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42810
40774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.4281040774
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.4226721609
Short name T2608
Test name
Test status
Simulation time 5595030533 ps
CPU time 48.93 seconds
Started Aug 18 05:32:55 PM PDT 24
Finished Aug 18 05:33:44 PM PDT 24
Peak memory 224156 kb
Host smart-183f3a31-da7d-41f3-a759-5f57f9a8b90b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4226721609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.4226721609
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.1861184850
Short name T808
Test name
Test status
Simulation time 2701649306 ps
CPU time 78.48 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:34:07 PM PDT 24
Peak memory 217376 kb
Host smart-9e940d9d-6454-438c-82ca-38d750f25876
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1861184850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.1861184850
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.3748044902
Short name T1318
Test name
Test status
Simulation time 296745187 ps
CPU time 1.18 seconds
Started Aug 18 05:33:04 PM PDT 24
Finished Aug 18 05:33:05 PM PDT 24
Peak memory 207488 kb
Host smart-de392d92-e4da-492a-b565-1467c0b3b9f4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3748044902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.3748044902
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3466303351
Short name T1952
Test name
Test status
Simulation time 192986879 ps
CPU time 0.96 seconds
Started Aug 18 05:32:46 PM PDT 24
Finished Aug 18 05:32:47 PM PDT 24
Peak memory 207412 kb
Host smart-d6fcf15f-30d3-4309-a5b7-5714ff40ffa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34663
03351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3466303351
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_non_iso_usb_traffic.1170010196
Short name T811
Test name
Test status
Simulation time 2231953790 ps
CPU time 16.91 seconds
Started Aug 18 05:32:50 PM PDT 24
Finished Aug 18 05:33:12 PM PDT 24
Peak memory 217724 kb
Host smart-c228ca0a-b6c6-4221-8305-6f48828a95c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11700
10196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_non_iso_usb_traffic.1170010196
Directory /workspace/6.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3919034120
Short name T2135
Test name
Test status
Simulation time 1514939307 ps
CPU time 11.48 seconds
Started Aug 18 05:32:49 PM PDT 24
Finished Aug 18 05:33:00 PM PDT 24
Peak memory 224104 kb
Host smart-71710ae8-b88e-44b6-b8cd-7a9f18e3f82f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3919034120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3919034120
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.827972469
Short name T2515
Test name
Test status
Simulation time 1781113024 ps
CPU time 18.01 seconds
Started Aug 18 05:32:55 PM PDT 24
Finished Aug 18 05:33:13 PM PDT 24
Peak memory 216388 kb
Host smart-1b04a430-386e-4ceb-9423-fd7bcaeb4aa8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=827972469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.827972469
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.3207178732
Short name T2671
Test name
Test status
Simulation time 153939022 ps
CPU time 0.89 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:32:53 PM PDT 24
Peak memory 207460 kb
Host smart-bfd878a6-e1d8-4b24-8270-e31122ac8cd2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3207178732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.3207178732
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.972375453
Short name T2981
Test name
Test status
Simulation time 179920039 ps
CPU time 0.89 seconds
Started Aug 18 05:33:00 PM PDT 24
Finished Aug 18 05:33:01 PM PDT 24
Peak memory 207628 kb
Host smart-da0f68a4-4b36-4170-baa3-823ca732c074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97237
5453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.972375453
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2149148173
Short name T155
Test name
Test status
Simulation time 191906240 ps
CPU time 0.89 seconds
Started Aug 18 05:32:50 PM PDT 24
Finished Aug 18 05:32:51 PM PDT 24
Peak memory 207508 kb
Host smart-2dfa44b4-14aa-4a61-8715-9e0e88069f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21491
48173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2149148173
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1917609161
Short name T906
Test name
Test status
Simulation time 183333355 ps
CPU time 0.9 seconds
Started Aug 18 05:32:49 PM PDT 24
Finished Aug 18 05:32:50 PM PDT 24
Peak memory 207496 kb
Host smart-5b1a1d34-fbde-4cb3-85e0-02809dfeb1a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19176
09161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1917609161
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3123724969
Short name T2681
Test name
Test status
Simulation time 153986789 ps
CPU time 0.88 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:48 PM PDT 24
Peak memory 207444 kb
Host smart-9766c80e-e0ad-4961-81c2-e7c63c7c9c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31237
24969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3123724969
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.4175815156
Short name T2069
Test name
Test status
Simulation time 219837272 ps
CPU time 0.92 seconds
Started Aug 18 05:32:56 PM PDT 24
Finished Aug 18 05:32:57 PM PDT 24
Peak memory 207524 kb
Host smart-15be90c9-6449-4089-8814-ab80dca94ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41758
15156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.4175815156
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.1112388079
Short name T223
Test name
Test status
Simulation time 182746195 ps
CPU time 0.87 seconds
Started Aug 18 05:32:45 PM PDT 24
Finished Aug 18 05:32:46 PM PDT 24
Peak memory 207560 kb
Host smart-8e7bce66-ddc3-4a65-af72-ba32c8fa6587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11123
88079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.1112388079
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.4137424320
Short name T1124
Test name
Test status
Simulation time 295134542 ps
CPU time 1.12 seconds
Started Aug 18 05:32:45 PM PDT 24
Finished Aug 18 05:32:46 PM PDT 24
Peak memory 207528 kb
Host smart-84c55811-a36f-410e-89bb-f3b9e3bea239
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4137424320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.4137424320
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2388309495
Short name T839
Test name
Test status
Simulation time 142575677 ps
CPU time 0.82 seconds
Started Aug 18 05:32:51 PM PDT 24
Finished Aug 18 05:32:51 PM PDT 24
Peak memory 207492 kb
Host smart-098e8636-3c10-41d8-ae12-c5641d18b3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23883
09495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2388309495
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3928250265
Short name T2166
Test name
Test status
Simulation time 75323014 ps
CPU time 0.75 seconds
Started Aug 18 05:32:47 PM PDT 24
Finished Aug 18 05:32:48 PM PDT 24
Peak memory 207440 kb
Host smart-f250dece-02a4-4ca6-b6cf-3602ae553aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39282
50265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3928250265
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1838215305
Short name T295
Test name
Test status
Simulation time 14338396278 ps
CPU time 37.08 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:33:29 PM PDT 24
Peak memory 224088 kb
Host smart-1e97fdbd-b879-4261-ac80-94e13b994589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18382
15305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1838215305
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.172865560
Short name T983
Test name
Test status
Simulation time 191503150 ps
CPU time 0.96 seconds
Started Aug 18 05:32:49 PM PDT 24
Finished Aug 18 05:32:50 PM PDT 24
Peak memory 207640 kb
Host smart-72ba868e-5f13-4fa7-a64c-a2e2b3e4b605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17286
5560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.172865560
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.583807121
Short name T2203
Test name
Test status
Simulation time 202736244 ps
CPU time 0.88 seconds
Started Aug 18 05:32:50 PM PDT 24
Finished Aug 18 05:32:51 PM PDT 24
Peak memory 207456 kb
Host smart-cd1e57de-0f75-4c17-8f9e-65fb4d4e4f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58380
7121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.583807121
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.607667400
Short name T1298
Test name
Test status
Simulation time 2408805935 ps
CPU time 17.48 seconds
Started Aug 18 05:32:53 PM PDT 24
Finished Aug 18 05:33:11 PM PDT 24
Peak memory 219044 kb
Host smart-ceb9f69e-9a45-40a7-9cee-19e2ff0324f5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=607667400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.607667400
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.1251711036
Short name T186
Test name
Test status
Simulation time 6821793126 ps
CPU time 39.72 seconds
Started Aug 18 05:33:06 PM PDT 24
Finished Aug 18 05:33:46 PM PDT 24
Peak memory 218700 kb
Host smart-89a88e62-9961-4cb5-bc11-11616565428d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1251711036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.1251711036
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.411612314
Short name T1691
Test name
Test status
Simulation time 6398028889 ps
CPU time 77.4 seconds
Started Aug 18 05:32:55 PM PDT 24
Finished Aug 18 05:34:12 PM PDT 24
Peak memory 216012 kb
Host smart-ca5e9015-c9ce-41b9-86fc-aba42fbd3858
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=411612314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.411612314
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.1496397211
Short name T1316
Test name
Test status
Simulation time 184492389 ps
CPU time 0.9 seconds
Started Aug 18 05:32:49 PM PDT 24
Finished Aug 18 05:32:50 PM PDT 24
Peak memory 207508 kb
Host smart-b86c7ec2-6e0e-4f66-b9da-d81b9b60189b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14963
97211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.1496397211
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1280308442
Short name T1392
Test name
Test status
Simulation time 166589266 ps
CPU time 0.86 seconds
Started Aug 18 05:33:08 PM PDT 24
Finished Aug 18 05:33:09 PM PDT 24
Peak memory 207412 kb
Host smart-2ae8d9c8-e6dd-4d23-9fce-e9f4afc7c96c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12803
08442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1280308442
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_resume_link_active.250781197
Short name T1079
Test name
Test status
Simulation time 20166272720 ps
CPU time 26.28 seconds
Started Aug 18 05:32:50 PM PDT 24
Finished Aug 18 05:33:16 PM PDT 24
Peak memory 207600 kb
Host smart-fb3144da-149c-4b91-8349-53a51da0b4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25078
1197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_resume_link_active.250781197
Directory /workspace/6.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.1829816060
Short name T2595
Test name
Test status
Simulation time 159937555 ps
CPU time 0.89 seconds
Started Aug 18 05:33:05 PM PDT 24
Finished Aug 18 05:33:06 PM PDT 24
Peak memory 207400 kb
Host smart-aa03223f-e7ce-46dc-8527-52b471c1bcfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18298
16060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1829816060
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_rx_full.133639641
Short name T342
Test name
Test status
Simulation time 248142793 ps
CPU time 1.04 seconds
Started Aug 18 05:32:44 PM PDT 24
Finished Aug 18 05:32:46 PM PDT 24
Peak memory 207424 kb
Host smart-37a1edda-2cd7-4f09-8ce6-69adba2bae9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13363
9641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_full.133639641
Directory /workspace/6.usbdev_rx_full/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.456731668
Short name T3000
Test name
Test status
Simulation time 148782743 ps
CPU time 0.89 seconds
Started Aug 18 05:32:47 PM PDT 24
Finished Aug 18 05:32:48 PM PDT 24
Peak memory 207428 kb
Host smart-69fb612a-43e4-4c5d-9577-4eb9a5371749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45673
1668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.456731668
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1080547383
Short name T1199
Test name
Test status
Simulation time 158206455 ps
CPU time 0.86 seconds
Started Aug 18 05:32:49 PM PDT 24
Finished Aug 18 05:32:50 PM PDT 24
Peak memory 207464 kb
Host smart-193554eb-5ff5-4320-aa5c-f9e28e1d1fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10805
47383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1080547383
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.58686859
Short name T788
Test name
Test status
Simulation time 248548881 ps
CPU time 1.05 seconds
Started Aug 18 05:32:47 PM PDT 24
Finished Aug 18 05:32:48 PM PDT 24
Peak memory 207500 kb
Host smart-9717ddd5-efaf-4c5e-9c3a-bb7c3b17bfbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58686
859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.58686859
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.4157686433
Short name T1907
Test name
Test status
Simulation time 2781724037 ps
CPU time 26.37 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:33:18 PM PDT 24
Peak memory 215956 kb
Host smart-5162a5de-31e8-4f73-a1a7-f50fde09e561
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4157686433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.4157686433
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.1908395126
Short name T2603
Test name
Test status
Simulation time 169627674 ps
CPU time 0.93 seconds
Started Aug 18 05:32:46 PM PDT 24
Finished Aug 18 05:32:47 PM PDT 24
Peak memory 207464 kb
Host smart-c7c9a39d-7f70-4316-b2fc-d6d8d2bd66b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19083
95126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.1908395126
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2303495454
Short name T715
Test name
Test status
Simulation time 206566636 ps
CPU time 0.89 seconds
Started Aug 18 05:32:54 PM PDT 24
Finished Aug 18 05:32:55 PM PDT 24
Peak memory 207512 kb
Host smart-0046c6fe-54d2-40b6-a03a-06c2214d23d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23034
95454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2303495454
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.1834875471
Short name T82
Test name
Test status
Simulation time 1383330988 ps
CPU time 3.37 seconds
Started Aug 18 05:32:51 PM PDT 24
Finished Aug 18 05:32:55 PM PDT 24
Peak memory 207792 kb
Host smart-b5934479-c144-42d9-8b9d-556137bf5df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18348
75471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.1834875471
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3057127622
Short name T550
Test name
Test status
Simulation time 3083193524 ps
CPU time 25.25 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:33:13 PM PDT 24
Peak memory 217748 kb
Host smart-be3b5218-beed-4a66-8a3c-95a350248647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30571
27622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3057127622
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.4136949628
Short name T1589
Test name
Test status
Simulation time 4320296537 ps
CPU time 37.69 seconds
Started Aug 18 05:32:51 PM PDT 24
Finished Aug 18 05:33:29 PM PDT 24
Peak memory 207672 kb
Host smart-dafacf98-810f-493a-9c2b-33253c062c82
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136949628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host
_handshake.4136949628
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/6.usbdev_tx_rx_disruption.3965816019
Short name T2416
Test name
Test status
Simulation time 646656553 ps
CPU time 1.83 seconds
Started Aug 18 05:32:55 PM PDT 24
Finished Aug 18 05:32:57 PM PDT 24
Peak memory 207576 kb
Host smart-98548c76-efb9-4d16-9441-630d88457832
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965816019 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.usbdev_tx_rx_disruption.3965816019
Directory /workspace/6.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/60.usbdev_tx_rx_disruption.343400979
Short name T2734
Test name
Test status
Simulation time 524347015 ps
CPU time 1.47 seconds
Started Aug 18 05:39:10 PM PDT 24
Finished Aug 18 05:39:27 PM PDT 24
Peak memory 207896 kb
Host smart-29ebc967-ab5d-4cb5-898b-778e0dfd042a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343400979 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 60.usbdev_tx_rx_disruption.343400979
Directory /workspace/60.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/61.usbdev_endpoint_types.1971627037
Short name T453
Test name
Test status
Simulation time 610866374 ps
CPU time 1.59 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207520 kb
Host smart-35349e89-6ac8-4498-ab1d-aa4ac38384bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1971627037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_endpoint_types.1971627037
Directory /workspace/61.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/61.usbdev_tx_rx_disruption.1014886073
Short name T1024
Test name
Test status
Simulation time 483248739 ps
CPU time 1.49 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:38:56 PM PDT 24
Peak memory 207548 kb
Host smart-0e0fcd27-1cff-44d4-9fc4-c22712970896
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014886073 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.usbdev_tx_rx_disruption.1014886073
Directory /workspace/61.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/62.usbdev_endpoint_types.4141313314
Short name T436
Test name
Test status
Simulation time 405435391 ps
CPU time 1.21 seconds
Started Aug 18 05:39:08 PM PDT 24
Finished Aug 18 05:39:09 PM PDT 24
Peak memory 207452 kb
Host smart-c93b656e-bd9d-4aeb-b26e-e7783e1c1e7e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4141313314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_endpoint_types.4141313314
Directory /workspace/62.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/62.usbdev_tx_rx_disruption.149933993
Short name T1461
Test name
Test status
Simulation time 534871752 ps
CPU time 1.59 seconds
Started Aug 18 05:38:56 PM PDT 24
Finished Aug 18 05:38:58 PM PDT 24
Peak memory 207488 kb
Host smart-e36cd665-0b70-4c0b-941b-378f5acb9eed
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149933993 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 62.usbdev_tx_rx_disruption.149933993
Directory /workspace/62.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/63.usbdev_endpoint_types.3181209850
Short name T109
Test name
Test status
Simulation time 195236008 ps
CPU time 1 seconds
Started Aug 18 05:38:52 PM PDT 24
Finished Aug 18 05:38:53 PM PDT 24
Peak memory 207504 kb
Host smart-d4479b10-5a7f-4fcc-87e5-6c17c733581e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3181209850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_endpoint_types.3181209850
Directory /workspace/63.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/63.usbdev_tx_rx_disruption.3588321343
Short name T2264
Test name
Test status
Simulation time 505571204 ps
CPU time 1.44 seconds
Started Aug 18 05:38:58 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207460 kb
Host smart-deb98806-0541-48eb-b40e-d20c5109d2e6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588321343 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.usbdev_tx_rx_disruption.3588321343
Directory /workspace/63.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/64.usbdev_endpoint_types.3329838831
Short name T506
Test name
Test status
Simulation time 165480626 ps
CPU time 0.88 seconds
Started Aug 18 05:39:08 PM PDT 24
Finished Aug 18 05:39:09 PM PDT 24
Peak memory 207512 kb
Host smart-67b5275e-f8cd-4695-9d6f-d80525006e84
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3329838831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_endpoint_types.3329838831
Directory /workspace/64.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/64.usbdev_tx_rx_disruption.2117057192
Short name T3515
Test name
Test status
Simulation time 545791985 ps
CPU time 1.56 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207492 kb
Host smart-d476ae83-dea9-472e-a506-dc8ddf8b11f8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117057192 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 64.usbdev_tx_rx_disruption.2117057192
Directory /workspace/64.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/65.usbdev_tx_rx_disruption.2242431147
Short name T3346
Test name
Test status
Simulation time 481726328 ps
CPU time 1.58 seconds
Started Aug 18 05:38:58 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207540 kb
Host smart-49716946-3ced-4306-835c-642f0849c123
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242431147 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 65.usbdev_tx_rx_disruption.2242431147
Directory /workspace/65.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/66.usbdev_endpoint_types.141425627
Short name T449
Test name
Test status
Simulation time 504780454 ps
CPU time 1.37 seconds
Started Aug 18 05:38:57 PM PDT 24
Finished Aug 18 05:38:59 PM PDT 24
Peak memory 207540 kb
Host smart-bbb5b9cf-efbd-4617-8795-afe5338645fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=141425627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_endpoint_types.141425627
Directory /workspace/66.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/66.usbdev_tx_rx_disruption.1944079308
Short name T2780
Test name
Test status
Simulation time 465000307 ps
CPU time 1.56 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:38:57 PM PDT 24
Peak memory 207496 kb
Host smart-1714cb9e-7ce2-40a9-93ef-9e262b91c496
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944079308 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 66.usbdev_tx_rx_disruption.1944079308
Directory /workspace/66.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/67.usbdev_endpoint_types.3989833967
Short name T2807
Test name
Test status
Simulation time 225230603 ps
CPU time 1.01 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207668 kb
Host smart-1fbd2cea-42e2-455c-923f-2448c1c82e4b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3989833967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_endpoint_types.3989833967
Directory /workspace/67.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/67.usbdev_tx_rx_disruption.1402121572
Short name T2250
Test name
Test status
Simulation time 569674415 ps
CPU time 1.68 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207608 kb
Host smart-76537b16-66cd-44e4-aea1-a03f51780ccb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402121572 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.usbdev_tx_rx_disruption.1402121572
Directory /workspace/67.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/68.usbdev_endpoint_types.597135430
Short name T462
Test name
Test status
Simulation time 605478670 ps
CPU time 1.57 seconds
Started Aug 18 05:39:10 PM PDT 24
Finished Aug 18 05:39:12 PM PDT 24
Peak memory 207544 kb
Host smart-6835d03d-f185-4817-9d19-78d8e46f8f3a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=597135430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_endpoint_types.597135430
Directory /workspace/68.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/68.usbdev_tx_rx_disruption.306412
Short name T588
Test name
Test status
Simulation time 701716062 ps
CPU time 1.75 seconds
Started Aug 18 05:39:03 PM PDT 24
Finished Aug 18 05:39:05 PM PDT 24
Peak memory 207604 kb
Host smart-2fb693fc-d897-4e13-9a2b-79004d9cef7d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306412 -assert nopostproc +UVM_TESTNA
ME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.usbdev_tx_rx_disruption.306412
Directory /workspace/68.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/69.usbdev_endpoint_types.2218324036
Short name T452
Test name
Test status
Simulation time 474171342 ps
CPU time 1.31 seconds
Started Aug 18 05:39:15 PM PDT 24
Finished Aug 18 05:39:16 PM PDT 24
Peak memory 207524 kb
Host smart-e1af88ba-5137-4131-aaf5-f4ab796ac678
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2218324036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_endpoint_types.2218324036
Directory /workspace/69.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/69.usbdev_tx_rx_disruption.3143063930
Short name T2455
Test name
Test status
Simulation time 530144637 ps
CPU time 1.75 seconds
Started Aug 18 05:39:08 PM PDT 24
Finished Aug 18 05:39:10 PM PDT 24
Peak memory 207492 kb
Host smart-4102fc04-7b8b-47f4-b319-5a677315aa7a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143063930 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.usbdev_tx_rx_disruption.3143063930
Directory /workspace/69.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.459263290
Short name T3199
Test name
Test status
Simulation time 28947121 ps
CPU time 0.64 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207456 kb
Host smart-c58aa4fe-5011-43b3-879f-1e1f183cd2ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=459263290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.459263290
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1072324084
Short name T1193
Test name
Test status
Simulation time 10829088406 ps
CPU time 13.17 seconds
Started Aug 18 05:32:44 PM PDT 24
Finished Aug 18 05:32:57 PM PDT 24
Peak memory 207804 kb
Host smart-f87f45d4-15d3-48b4-b989-a379354ba883
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072324084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.1072324084
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.954950386
Short name T1565
Test name
Test status
Simulation time 13548105243 ps
CPU time 15 seconds
Started Aug 18 05:32:55 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 215980 kb
Host smart-1b706c5a-ca64-4bc3-b842-494ac5842bd7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=954950386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.954950386
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.1176437290
Short name T1684
Test name
Test status
Simulation time 28748053996 ps
CPU time 35.48 seconds
Started Aug 18 05:33:00 PM PDT 24
Finished Aug 18 05:33:35 PM PDT 24
Peak memory 207812 kb
Host smart-cd72e0dc-1b6f-4ded-872f-3d7a02b41d4e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176437290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_resume.1176437290
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.4162574851
Short name T1527
Test name
Test status
Simulation time 156438480 ps
CPU time 0.85 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:32:53 PM PDT 24
Peak memory 207504 kb
Host smart-bbaf3971-a4f9-47e1-a863-ac05f1f670b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41625
74851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.4162574851
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.596363385
Short name T1764
Test name
Test status
Simulation time 144893052 ps
CPU time 0.84 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207356 kb
Host smart-41d123a7-e97d-44a0-bca6-3391be62fe5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59636
3385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.596363385
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.1951629030
Short name T2692
Test name
Test status
Simulation time 219571687 ps
CPU time 1.08 seconds
Started Aug 18 05:32:51 PM PDT 24
Finished Aug 18 05:32:52 PM PDT 24
Peak memory 207572 kb
Host smart-09e2d582-043c-4cba-97a0-57e06da2e4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19516
29030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.1951629030
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3831671582
Short name T1650
Test name
Test status
Simulation time 507798461 ps
CPU time 1.47 seconds
Started Aug 18 05:32:50 PM PDT 24
Finished Aug 18 05:32:51 PM PDT 24
Peak memory 207548 kb
Host smart-be3aaac2-1bd4-412e-8ec8-ef40a2194ae6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3831671582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3831671582
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.1116169265
Short name T522
Test name
Test status
Simulation time 22526322214 ps
CPU time 38.86 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:33:31 PM PDT 24
Peak memory 207812 kb
Host smart-34c644d6-695d-4456-bb29-ad6c54fdf487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11161
69265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.1116169265
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.2005875751
Short name T868
Test name
Test status
Simulation time 1190120607 ps
CPU time 25.6 seconds
Started Aug 18 05:32:49 PM PDT 24
Finished Aug 18 05:33:15 PM PDT 24
Peak memory 207672 kb
Host smart-e771efb4-0001-4b77-ad00-df6537c859b4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005875751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.2005875751
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.2001437617
Short name T1407
Test name
Test status
Simulation time 646680752 ps
CPU time 1.71 seconds
Started Aug 18 05:32:56 PM PDT 24
Finished Aug 18 05:32:58 PM PDT 24
Peak memory 207536 kb
Host smart-b18537c8-707b-4ad2-9837-3967f9c5579c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20014
37617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.2001437617
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.516638148
Short name T2761
Test name
Test status
Simulation time 139046131 ps
CPU time 0.8 seconds
Started Aug 18 05:33:03 PM PDT 24
Finished Aug 18 05:33:04 PM PDT 24
Peak memory 207472 kb
Host smart-172af791-8dd4-4819-bfbe-1d0114e23fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51663
8148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.516638148
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.1475880422
Short name T1310
Test name
Test status
Simulation time 36427687 ps
CPU time 0.7 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207460 kb
Host smart-77a0975c-94f0-4c43-9769-c8137a828498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14758
80422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1475880422
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.3818013141
Short name T3070
Test name
Test status
Simulation time 988114621 ps
CPU time 2.63 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:33:13 PM PDT 24
Peak memory 207760 kb
Host smart-fa3ca864-5464-4c7f-a576-4d8847869c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38180
13141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.3818013141
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1381397696
Short name T1780
Test name
Test status
Simulation time 164723082 ps
CPU time 1.55 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:50 PM PDT 24
Peak memory 207644 kb
Host smart-06f1c7a9-d31e-4ce9-98d5-181731a80bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13813
97696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1381397696
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2107849783
Short name T793
Test name
Test status
Simulation time 198135524 ps
CPU time 1.08 seconds
Started Aug 18 05:32:47 PM PDT 24
Finished Aug 18 05:32:48 PM PDT 24
Peak memory 215800 kb
Host smart-e272885b-c872-4c94-b4a1-4e355a351d85
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2107849783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2107849783
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.716959426
Short name T3168
Test name
Test status
Simulation time 135767256 ps
CPU time 0.81 seconds
Started Aug 18 05:32:51 PM PDT 24
Finished Aug 18 05:32:52 PM PDT 24
Peak memory 207472 kb
Host smart-2cc0f1ac-f446-44f9-94a5-4911837575f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71695
9426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.716959426
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3253936124
Short name T3451
Test name
Test status
Simulation time 188674526 ps
CPU time 1 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207484 kb
Host smart-b398606d-fa2a-433b-82ba-012003668ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32539
36124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3253936124
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.3246010420
Short name T1041
Test name
Test status
Simulation time 4848765608 ps
CPU time 138.6 seconds
Started Aug 18 05:32:47 PM PDT 24
Finished Aug 18 05:35:06 PM PDT 24
Peak memory 224096 kb
Host smart-7d0fe1c0-b3d5-4647-80be-c8f2c169cd23
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3246010420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.3246010420
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.2770358141
Short name T636
Test name
Test status
Simulation time 10543782352 ps
CPU time 68.42 seconds
Started Aug 18 05:32:59 PM PDT 24
Finished Aug 18 05:34:07 PM PDT 24
Peak memory 207768 kb
Host smart-867b8d61-2c84-4199-93b5-c24991027797
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2770358141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.2770358141
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.4112255661
Short name T2006
Test name
Test status
Simulation time 228871959 ps
CPU time 0.97 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207504 kb
Host smart-998025b0-1f4e-4d54-be45-b9c684f4742e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41122
55661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.4112255661
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.3506667476
Short name T1142
Test name
Test status
Simulation time 12631339118 ps
CPU time 17.6 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:33:28 PM PDT 24
Peak memory 207764 kb
Host smart-86e36a71-4d42-4c27-b94a-2f249cf4351a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35066
67476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.3506667476
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.3545227724
Short name T1657
Test name
Test status
Simulation time 4836466376 ps
CPU time 6.52 seconds
Started Aug 18 05:33:00 PM PDT 24
Finished Aug 18 05:33:07 PM PDT 24
Peak memory 216100 kb
Host smart-95763486-6adc-4692-a608-89a09f4bac09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35452
27724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.3545227724
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.209573055
Short name T2740
Test name
Test status
Simulation time 2963371844 ps
CPU time 82.58 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:34:32 PM PDT 24
Peak memory 218512 kb
Host smart-9aed62a2-6381-41c9-ab27-138e3a7808fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=209573055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.209573055
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.3711332130
Short name T2768
Test name
Test status
Simulation time 2897281740 ps
CPU time 28.81 seconds
Started Aug 18 05:32:57 PM PDT 24
Finished Aug 18 05:33:26 PM PDT 24
Peak memory 217180 kb
Host smart-71ea1f22-b747-46b8-88dc-c0929c965c1f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3711332130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3711332130
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.3403900566
Short name T2342
Test name
Test status
Simulation time 242801852 ps
CPU time 1.05 seconds
Started Aug 18 05:32:51 PM PDT 24
Finished Aug 18 05:32:52 PM PDT 24
Peak memory 207508 kb
Host smart-2e51e87a-de45-4cc6-add4-6b6d4b8c75af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3403900566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.3403900566
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1259030745
Short name T2702
Test name
Test status
Simulation time 203594917 ps
CPU time 0.96 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:32:53 PM PDT 24
Peak memory 207504 kb
Host smart-5edde132-add6-4f2f-adf3-70d15c525f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12590
30745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1259030745
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_non_iso_usb_traffic.1899749153
Short name T1917
Test name
Test status
Simulation time 1797727397 ps
CPU time 17.29 seconds
Started Aug 18 05:32:59 PM PDT 24
Finished Aug 18 05:33:16 PM PDT 24
Peak memory 217452 kb
Host smart-15fc2cc0-27c9-4853-966f-8b1cb8191efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18997
49153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_non_iso_usb_traffic.1899749153
Directory /workspace/7.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.39805486
Short name T1960
Test name
Test status
Simulation time 3155302686 ps
CPU time 28.51 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:33:21 PM PDT 24
Peak memory 223804 kb
Host smart-8fc45a41-aad6-41a0-ba9f-51b2e3f58030
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=39805486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.39805486
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1003212726
Short name T3379
Test name
Test status
Simulation time 2844236986 ps
CPU time 79.1 seconds
Started Aug 18 05:33:03 PM PDT 24
Finished Aug 18 05:34:22 PM PDT 24
Peak memory 217336 kb
Host smart-24de2193-1db4-4cd2-8d4c-502d4fc18436
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1003212726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1003212726
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.915985000
Short name T3422
Test name
Test status
Simulation time 155400072 ps
CPU time 0.87 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 207484 kb
Host smart-2efc2785-9559-4aae-ab89-01ba3569ffa9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=915985000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.915985000
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.133163842
Short name T3405
Test name
Test status
Simulation time 170555226 ps
CPU time 0.85 seconds
Started Aug 18 05:32:56 PM PDT 24
Finished Aug 18 05:32:57 PM PDT 24
Peak memory 207440 kb
Host smart-3ee95767-37fc-4213-984e-9da71f548f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13316
3842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.133163842
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3646016412
Short name T2441
Test name
Test status
Simulation time 212709458 ps
CPU time 0.95 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:32:49 PM PDT 24
Peak memory 207528 kb
Host smart-fd2b10c0-734d-4128-9550-20b6356fbb1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36460
16412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3646016412
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.3919096363
Short name T867
Test name
Test status
Simulation time 154728986 ps
CPU time 0.83 seconds
Started Aug 18 05:32:54 PM PDT 24
Finished Aug 18 05:32:54 PM PDT 24
Peak memory 207524 kb
Host smart-49edc723-8c88-4742-8eab-b444fafcf244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39190
96363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.3919096363
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3543771345
Short name T3189
Test name
Test status
Simulation time 180990618 ps
CPU time 0.85 seconds
Started Aug 18 05:32:58 PM PDT 24
Finished Aug 18 05:32:59 PM PDT 24
Peak memory 207372 kb
Host smart-e69da73d-cd9b-4e12-afd9-0417a51c72a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35437
71345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3543771345
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.546436757
Short name T860
Test name
Test status
Simulation time 179143982 ps
CPU time 0.95 seconds
Started Aug 18 05:33:02 PM PDT 24
Finished Aug 18 05:33:03 PM PDT 24
Peak memory 207552 kb
Host smart-1b7eefa8-395b-43d1-9ea1-b1b89cd44cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54643
6757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.546436757
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.4095843975
Short name T3382
Test name
Test status
Simulation time 202062816 ps
CPU time 0.89 seconds
Started Aug 18 05:32:55 PM PDT 24
Finished Aug 18 05:32:56 PM PDT 24
Peak memory 207448 kb
Host smart-7ad450e3-707a-4339-9d54-38521db2f1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40958
43975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.4095843975
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1943086306
Short name T3204
Test name
Test status
Simulation time 212193973 ps
CPU time 0.97 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:32:53 PM PDT 24
Peak memory 207592 kb
Host smart-2d1be21b-0f15-4c17-ac0e-2cadea9ccd69
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1943086306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1943086306
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.3320490597
Short name T3082
Test name
Test status
Simulation time 172372011 ps
CPU time 0.84 seconds
Started Aug 18 05:32:55 PM PDT 24
Finished Aug 18 05:32:56 PM PDT 24
Peak memory 207336 kb
Host smart-a66526f9-1909-4d83-8c21-28cbaab85766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33204
90597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.3320490597
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1790098664
Short name T3381
Test name
Test status
Simulation time 47536354 ps
CPU time 0.7 seconds
Started Aug 18 05:33:02 PM PDT 24
Finished Aug 18 05:33:03 PM PDT 24
Peak memory 207436 kb
Host smart-534b3ab2-20b6-4e8f-bd88-89ddfa914dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17900
98664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1790098664
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.741212431
Short name T1201
Test name
Test status
Simulation time 14542634522 ps
CPU time 36.35 seconds
Started Aug 18 05:32:51 PM PDT 24
Finished Aug 18 05:33:28 PM PDT 24
Peak memory 215904 kb
Host smart-b59a2afc-a739-48b9-8a62-d72f429b95a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74121
2431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.741212431
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2400635461
Short name T1824
Test name
Test status
Simulation time 184652268 ps
CPU time 0.9 seconds
Started Aug 18 05:32:50 PM PDT 24
Finished Aug 18 05:32:51 PM PDT 24
Peak memory 207556 kb
Host smart-7512b13e-d02f-489e-81d2-66ad5bb9e6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24006
35461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2400635461
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3218397957
Short name T3420
Test name
Test status
Simulation time 223398214 ps
CPU time 0.98 seconds
Started Aug 18 05:32:53 PM PDT 24
Finished Aug 18 05:32:54 PM PDT 24
Peak memory 207504 kb
Host smart-ffda6405-6ab7-4844-a23a-dd556ab92b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32183
97957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3218397957
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3697231128
Short name T3141
Test name
Test status
Simulation time 5256410759 ps
CPU time 21.99 seconds
Started Aug 18 05:33:12 PM PDT 24
Finished Aug 18 05:33:34 PM PDT 24
Peak memory 219108 kb
Host smart-8e5af510-3580-4ab5-899d-074df169c030
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697231128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3697231128
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.292896346
Short name T3579
Test name
Test status
Simulation time 2115376238 ps
CPU time 16.38 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:33:09 PM PDT 24
Peak memory 218664 kb
Host smart-3d54471e-445c-46b7-b38f-cf6a2e3f6f63
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=292896346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.292896346
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.728289469
Short name T580
Test name
Test status
Simulation time 5334792777 ps
CPU time 25.14 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:33:18 PM PDT 24
Peak memory 219368 kb
Host smart-1705943f-24be-4bf2-a78a-10d52aa31086
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=728289469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.728289469
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.295326694
Short name T1208
Test name
Test status
Simulation time 198919290 ps
CPU time 1.03 seconds
Started Aug 18 05:32:58 PM PDT 24
Finished Aug 18 05:32:59 PM PDT 24
Peak memory 207452 kb
Host smart-acbe6b20-1612-4738-b620-30da256c9456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29532
6694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.295326694
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.3178259051
Short name T2471
Test name
Test status
Simulation time 184217373 ps
CPU time 0.94 seconds
Started Aug 18 05:32:57 PM PDT 24
Finished Aug 18 05:32:58 PM PDT 24
Peak memory 207512 kb
Host smart-7248bd49-28e4-4604-951a-e89ffe18cd68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31782
59051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.3178259051
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_resume_link_active.324064070
Short name T2686
Test name
Test status
Simulation time 20158446022 ps
CPU time 26.32 seconds
Started Aug 18 05:32:48 PM PDT 24
Finished Aug 18 05:33:14 PM PDT 24
Peak memory 207492 kb
Host smart-a4a5bab9-9ec6-40da-8350-ecb497e8b439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32406
4070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_resume_link_active.324064070
Directory /workspace/7.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1624138171
Short name T3483
Test name
Test status
Simulation time 186776137 ps
CPU time 0.88 seconds
Started Aug 18 05:33:05 PM PDT 24
Finished Aug 18 05:33:06 PM PDT 24
Peak memory 207224 kb
Host smart-5affdf26-1f0f-4b14-baa2-194f42b840d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16241
38171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1624138171
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_rx_full.2537066612
Short name T753
Test name
Test status
Simulation time 326370819 ps
CPU time 1.14 seconds
Started Aug 18 05:33:07 PM PDT 24
Finished Aug 18 05:33:08 PM PDT 24
Peak memory 207388 kb
Host smart-127e69e9-141e-4ac0-bc36-8cb6f47f7de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25370
66612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_full.2537066612
Directory /workspace/7.usbdev_rx_full/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1723558907
Short name T1892
Test name
Test status
Simulation time 147826900 ps
CPU time 0.86 seconds
Started Aug 18 05:33:06 PM PDT 24
Finished Aug 18 05:33:08 PM PDT 24
Peak memory 207208 kb
Host smart-9e08c420-4c3a-4ad9-9788-c345af3d6c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17235
58907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1723558907
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.853871411
Short name T1606
Test name
Test status
Simulation time 146179195 ps
CPU time 0.78 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:14 PM PDT 24
Peak memory 207320 kb
Host smart-0c4effdb-e890-449b-b11f-aac2366e87c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85387
1411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.853871411
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.3007074319
Short name T927
Test name
Test status
Simulation time 294028044 ps
CPU time 1.11 seconds
Started Aug 18 05:32:53 PM PDT 24
Finished Aug 18 05:32:55 PM PDT 24
Peak memory 207516 kb
Host smart-8d8d954a-bdca-45d0-88c4-8fb8ee407eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30070
74319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3007074319
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.3458762473
Short name T2749
Test name
Test status
Simulation time 1916280801 ps
CPU time 52.65 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:33:45 PM PDT 24
Peak memory 217380 kb
Host smart-d910a188-7bfc-4069-9175-4a3b540d08e3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3458762473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3458762473
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2601129049
Short name T1078
Test name
Test status
Simulation time 195911058 ps
CPU time 0.92 seconds
Started Aug 18 05:32:49 PM PDT 24
Finished Aug 18 05:32:50 PM PDT 24
Peak memory 207496 kb
Host smart-eb6d3eda-d04a-43c9-ae69-411ea0f621ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26011
29049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2601129049
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2463404833
Short name T1451
Test name
Test status
Simulation time 185294755 ps
CPU time 0.88 seconds
Started Aug 18 05:33:15 PM PDT 24
Finished Aug 18 05:33:16 PM PDT 24
Peak memory 207164 kb
Host smart-67ba14de-e21d-45c3-a937-96c6c68c42af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24634
04833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2463404833
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.3189723841
Short name T1598
Test name
Test status
Simulation time 690459944 ps
CPU time 1.69 seconds
Started Aug 18 05:33:04 PM PDT 24
Finished Aug 18 05:33:05 PM PDT 24
Peak memory 207536 kb
Host smart-3e66d1cc-21f8-4591-83b5-b3d953a47563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31897
23841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.3189723841
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.2653437921
Short name T1658
Test name
Test status
Simulation time 1699291956 ps
CPU time 45.9 seconds
Started Aug 18 05:33:15 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 215620 kb
Host smart-94494d73-4562-4898-b817-3daef7d1943e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26534
37921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.2653437921
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.2047336974
Short name T1439
Test name
Test status
Simulation time 722539037 ps
CPU time 14.4 seconds
Started Aug 18 05:32:50 PM PDT 24
Finished Aug 18 05:33:05 PM PDT 24
Peak memory 207556 kb
Host smart-d48a4a8c-9dd7-4825-b8a6-08110e389d41
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047336974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host
_handshake.2047336974
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/7.usbdev_tx_rx_disruption.3523275701
Short name T1818
Test name
Test status
Simulation time 553332849 ps
CPU time 1.47 seconds
Started Aug 18 05:33:05 PM PDT 24
Finished Aug 18 05:33:06 PM PDT 24
Peak memory 207316 kb
Host smart-0c252b2e-7aa2-4226-abff-caad201cb908
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523275701 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.usbdev_tx_rx_disruption.3523275701
Directory /workspace/7.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/70.usbdev_endpoint_types.2435062342
Short name T115
Test name
Test status
Simulation time 269705184 ps
CPU time 1.06 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207540 kb
Host smart-6ec172f5-f325-48d7-9870-3bede143a8ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2435062342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_endpoint_types.2435062342
Directory /workspace/70.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/70.usbdev_tx_rx_disruption.3555477577
Short name T263
Test name
Test status
Simulation time 531415303 ps
CPU time 1.57 seconds
Started Aug 18 05:38:58 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207552 kb
Host smart-f2eb36fd-92e6-4466-a708-aa1b7b7c64f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555477577 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.usbdev_tx_rx_disruption.3555477577
Directory /workspace/70.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/71.usbdev_endpoint_types.3421171513
Short name T393
Test name
Test status
Simulation time 642130241 ps
CPU time 1.83 seconds
Started Aug 18 05:39:08 PM PDT 24
Finished Aug 18 05:39:10 PM PDT 24
Peak memory 207544 kb
Host smart-87c162c3-5529-418e-9e90-20c58f33a169
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3421171513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_endpoint_types.3421171513
Directory /workspace/71.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/71.usbdev_tx_rx_disruption.974804771
Short name T2942
Test name
Test status
Simulation time 659394308 ps
CPU time 1.86 seconds
Started Aug 18 05:39:11 PM PDT 24
Finished Aug 18 05:39:12 PM PDT 24
Peak memory 207576 kb
Host smart-eec6842d-6706-48e6-864d-b55500a39a53
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974804771 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 71.usbdev_tx_rx_disruption.974804771
Directory /workspace/71.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/72.usbdev_endpoint_types.2974493987
Short name T387
Test name
Test status
Simulation time 717874927 ps
CPU time 1.7 seconds
Started Aug 18 05:39:27 PM PDT 24
Finished Aug 18 05:39:29 PM PDT 24
Peak memory 207536 kb
Host smart-0e1f8339-7cfd-459e-b917-77515353cb21
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2974493987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_endpoint_types.2974493987
Directory /workspace/72.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/72.usbdev_tx_rx_disruption.3984680525
Short name T2804
Test name
Test status
Simulation time 471490752 ps
CPU time 1.53 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:38:56 PM PDT 24
Peak memory 207552 kb
Host smart-292b371c-dac3-484f-8d24-2e53b2e87321
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984680525 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 72.usbdev_tx_rx_disruption.3984680525
Directory /workspace/72.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/73.usbdev_endpoint_types.4266539878
Short name T406
Test name
Test status
Simulation time 238539439 ps
CPU time 0.99 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207500 kb
Host smart-222a4ae5-ed2d-4d66-875a-436aeded0c44
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4266539878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_endpoint_types.4266539878
Directory /workspace/73.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/73.usbdev_tx_rx_disruption.938085119
Short name T529
Test name
Test status
Simulation time 457287265 ps
CPU time 1.39 seconds
Started Aug 18 05:38:58 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207544 kb
Host smart-d551b3c4-6fbd-40eb-a44c-259c469df87e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938085119 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 73.usbdev_tx_rx_disruption.938085119
Directory /workspace/73.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/74.usbdev_endpoint_types.2879579128
Short name T380
Test name
Test status
Simulation time 236126658 ps
CPU time 0.97 seconds
Started Aug 18 05:38:53 PM PDT 24
Finished Aug 18 05:38:55 PM PDT 24
Peak memory 207544 kb
Host smart-9c4666f8-0e0f-4ed6-a468-b3f34132f184
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2879579128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_endpoint_types.2879579128
Directory /workspace/74.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/74.usbdev_tx_rx_disruption.3465863659
Short name T1206
Test name
Test status
Simulation time 573547684 ps
CPU time 1.56 seconds
Started Aug 18 05:39:09 PM PDT 24
Finished Aug 18 05:39:11 PM PDT 24
Peak memory 207584 kb
Host smart-4bc01545-2253-4797-9dc9-34828fba712a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465863659 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.usbdev_tx_rx_disruption.3465863659
Directory /workspace/74.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/75.usbdev_endpoint_types.2460476425
Short name T390
Test name
Test status
Simulation time 331197944 ps
CPU time 1.05 seconds
Started Aug 18 05:38:58 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207340 kb
Host smart-966c91a3-6cdc-4c9c-90e5-555ac87e09e9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2460476425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_endpoint_types.2460476425
Directory /workspace/75.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/75.usbdev_tx_rx_disruption.1366573044
Short name T2913
Test name
Test status
Simulation time 508333422 ps
CPU time 1.65 seconds
Started Aug 18 05:39:04 PM PDT 24
Finished Aug 18 05:39:06 PM PDT 24
Peak memory 207588 kb
Host smart-05b68006-44cc-40a8-b79d-79dd496a9882
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366573044 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.usbdev_tx_rx_disruption.1366573044
Directory /workspace/75.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/76.usbdev_tx_rx_disruption.2000586664
Short name T926
Test name
Test status
Simulation time 593876924 ps
CPU time 1.73 seconds
Started Aug 18 05:38:56 PM PDT 24
Finished Aug 18 05:38:58 PM PDT 24
Peak memory 207588 kb
Host smart-41bad598-46f9-44b0-b9ff-27b71a818bf1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000586664 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.usbdev_tx_rx_disruption.2000586664
Directory /workspace/76.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/77.usbdev_endpoint_types.2648153721
Short name T409
Test name
Test status
Simulation time 406860878 ps
CPU time 1.3 seconds
Started Aug 18 05:39:03 PM PDT 24
Finished Aug 18 05:39:04 PM PDT 24
Peak memory 207544 kb
Host smart-03f1d708-ad97-4246-9afb-c94c4ea72a31
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2648153721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_endpoint_types.2648153721
Directory /workspace/77.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/77.usbdev_tx_rx_disruption.25242098
Short name T941
Test name
Test status
Simulation time 545698974 ps
CPU time 1.51 seconds
Started Aug 18 05:38:57 PM PDT 24
Finished Aug 18 05:38:59 PM PDT 24
Peak memory 207584 kb
Host smart-4ddfb22f-a4f7-4d44-acbb-c5445d6e149d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25242098 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 77.usbdev_tx_rx_disruption.25242098
Directory /workspace/77.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/78.usbdev_endpoint_types.3094579565
Short name T372
Test name
Test status
Simulation time 776448035 ps
CPU time 1.77 seconds
Started Aug 18 05:39:04 PM PDT 24
Finished Aug 18 05:39:06 PM PDT 24
Peak memory 207496 kb
Host smart-e98b11ca-df85-419c-b07a-42fb9ab628a7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3094579565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_endpoint_types.3094579565
Directory /workspace/78.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/78.usbdev_tx_rx_disruption.1339928576
Short name T3328
Test name
Test status
Simulation time 539865206 ps
CPU time 1.58 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207548 kb
Host smart-d3c06772-0b1b-4092-860d-5bcea685c36d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339928576 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 78.usbdev_tx_rx_disruption.1339928576
Directory /workspace/78.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/79.usbdev_endpoint_types.3671917858
Short name T2298
Test name
Test status
Simulation time 497911523 ps
CPU time 1.48 seconds
Started Aug 18 05:39:07 PM PDT 24
Finished Aug 18 05:39:08 PM PDT 24
Peak memory 207544 kb
Host smart-68c5db3d-c2d4-4dd1-896e-07ae23456a03
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3671917858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_endpoint_types.3671917858
Directory /workspace/79.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/79.usbdev_tx_rx_disruption.1793304782
Short name T2606
Test name
Test status
Simulation time 599142212 ps
CPU time 1.61 seconds
Started Aug 18 05:38:54 PM PDT 24
Finished Aug 18 05:38:56 PM PDT 24
Peak memory 207572 kb
Host smart-e8733b95-c792-4e8d-8130-369dec2e34f2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793304782 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 79.usbdev_tx_rx_disruption.1793304782
Directory /workspace/79.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.3207234324
Short name T2902
Test name
Test status
Simulation time 43294920 ps
CPU time 0.66 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 207464 kb
Host smart-ff71e3f9-8a50-4f42-8c43-7b1175a43808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3207234324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.3207234324
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.104887624
Short name T1234
Test name
Test status
Simulation time 6282148224 ps
CPU time 9.66 seconds
Started Aug 18 05:32:47 PM PDT 24
Finished Aug 18 05:32:57 PM PDT 24
Peak memory 215940 kb
Host smart-852add85-3904-40c8-9d10-dbe1f8843178
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104887624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon
_wake_disconnect.104887624
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1740913258
Short name T2053
Test name
Test status
Simulation time 14322107526 ps
CPU time 17.48 seconds
Started Aug 18 05:32:52 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 215916 kb
Host smart-c0d1577a-c6a8-4f22-8d9b-6d413b14921e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740913258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1740913258
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.1650040982
Short name T1655
Test name
Test status
Simulation time 23551303132 ps
CPU time 32.14 seconds
Started Aug 18 05:32:56 PM PDT 24
Finished Aug 18 05:33:28 PM PDT 24
Peak memory 215972 kb
Host smart-cee541ff-13a7-4e6d-b90e-96ec3cea2ba7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650040982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_resume.1650040982
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1124424105
Short name T1821
Test name
Test status
Simulation time 166526518 ps
CPU time 0.88 seconds
Started Aug 18 05:33:14 PM PDT 24
Finished Aug 18 05:33:15 PM PDT 24
Peak memory 207224 kb
Host smart-b127e94e-a275-4ebd-9de8-aa68d43ffc09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11244
24105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1124424105
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.4076708217
Short name T1073
Test name
Test status
Simulation time 187643503 ps
CPU time 0.87 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:14 PM PDT 24
Peak memory 207288 kb
Host smart-940f05b1-0fe8-473a-81b0-3f90d4242c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40767
08217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.4076708217
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.3567857947
Short name T2938
Test name
Test status
Simulation time 464495268 ps
CPU time 1.56 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:15 PM PDT 24
Peak memory 206996 kb
Host smart-924a356e-ebb1-468e-a561-09e90ab0bb80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35678
57947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.3567857947
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.1489243277
Short name T3459
Test name
Test status
Simulation time 431324468 ps
CPU time 1.35 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:15 PM PDT 24
Peak memory 207304 kb
Host smart-e819e298-7718-4f09-8a8b-fbf6a8b3bdd1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1489243277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.1489243277
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.3305572023
Short name T527
Test name
Test status
Simulation time 44571622900 ps
CPU time 71.5 seconds
Started Aug 18 05:33:05 PM PDT 24
Finished Aug 18 05:34:16 PM PDT 24
Peak memory 207804 kb
Host smart-d4dbaa9f-7fc9-462f-af40-66a1226f3c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33055
72023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.3305572023
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.2132369505
Short name T2367
Test name
Test status
Simulation time 756263710 ps
CPU time 5.08 seconds
Started Aug 18 05:32:53 PM PDT 24
Finished Aug 18 05:32:58 PM PDT 24
Peak memory 207756 kb
Host smart-d6300b0e-9f87-48cb-9fbb-2ae9204a3ce1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132369505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.2132369505
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.1525503537
Short name T3172
Test name
Test status
Simulation time 526296497 ps
CPU time 1.62 seconds
Started Aug 18 05:32:58 PM PDT 24
Finished Aug 18 05:33:00 PM PDT 24
Peak memory 207436 kb
Host smart-70558e40-9431-4d4d-939c-625958913709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15255
03537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.1525503537
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2159755696
Short name T3273
Test name
Test status
Simulation time 143949813 ps
CPU time 0.81 seconds
Started Aug 18 05:33:05 PM PDT 24
Finished Aug 18 05:33:06 PM PDT 24
Peak memory 207460 kb
Host smart-8c210e2d-1f79-46f8-8836-2a71f4b9d75d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21597
55696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2159755696
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3047546023
Short name T2070
Test name
Test status
Simulation time 72999464 ps
CPU time 0.71 seconds
Started Aug 18 05:32:54 PM PDT 24
Finished Aug 18 05:32:55 PM PDT 24
Peak memory 207436 kb
Host smart-039aac81-bbff-4cab-84d7-a6002e2f652e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30475
46023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3047546023
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.2255632255
Short name T3196
Test name
Test status
Simulation time 987491767 ps
CPU time 2.41 seconds
Started Aug 18 05:32:49 PM PDT 24
Finished Aug 18 05:32:51 PM PDT 24
Peak memory 207776 kb
Host smart-b8c67087-a430-4098-beb0-ae6247f37b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22556
32255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.2255632255
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_types.1785200329
Short name T397
Test name
Test status
Simulation time 719504562 ps
CPU time 1.76 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:11 PM PDT 24
Peak memory 207528 kb
Host smart-13d3d2ab-77d8-48c5-8719-df76428c2230
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1785200329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_types.1785200329
Directory /workspace/8.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.888146627
Short name T1865
Test name
Test status
Simulation time 231335151 ps
CPU time 1.51 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:11 PM PDT 24
Peak memory 207664 kb
Host smart-0e1af299-9b7a-4e72-8ba4-aa09d18fc40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88814
6627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.888146627
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.2222441666
Short name T1002
Test name
Test status
Simulation time 234016073 ps
CPU time 1.31 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 215808 kb
Host smart-a9f64be5-368b-44f2-8d18-fb1abaaf5928
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2222441666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2222441666
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3919759878
Short name T2200
Test name
Test status
Simulation time 144913664 ps
CPU time 0.86 seconds
Started Aug 18 05:33:11 PM PDT 24
Finished Aug 18 05:33:12 PM PDT 24
Peak memory 207448 kb
Host smart-06943b67-91f3-444c-9221-7f4fe1c33482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39197
59878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3919759878
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1726644541
Short name T1687
Test name
Test status
Simulation time 187790422 ps
CPU time 0.92 seconds
Started Aug 18 05:33:00 PM PDT 24
Finished Aug 18 05:33:01 PM PDT 24
Peak memory 207408 kb
Host smart-d59e1f35-e8b5-485c-b338-9db6be10a8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17266
44541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1726644541
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.179756901
Short name T3305
Test name
Test status
Simulation time 3023365522 ps
CPU time 28.68 seconds
Started Aug 18 05:33:06 PM PDT 24
Finished Aug 18 05:33:35 PM PDT 24
Peak memory 215960 kb
Host smart-090aa7c1-bba1-49f3-8435-3d8fbc6a0fbd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=179756901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.179756901
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.2083777713
Short name T1200
Test name
Test status
Simulation time 4257330512 ps
CPU time 48.82 seconds
Started Aug 18 05:33:04 PM PDT 24
Finished Aug 18 05:33:53 PM PDT 24
Peak memory 207712 kb
Host smart-f4b1b9a0-dac5-4159-9943-06e3b999da4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2083777713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.2083777713
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.2904420942
Short name T3553
Test name
Test status
Simulation time 230304163 ps
CPU time 0.96 seconds
Started Aug 18 05:33:00 PM PDT 24
Finished Aug 18 05:33:01 PM PDT 24
Peak memory 207528 kb
Host smart-88fbddc5-bd21-45ee-a59e-32edb92b8d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29044
20942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.2904420942
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.358969297
Short name T3588
Test name
Test status
Simulation time 29163343428 ps
CPU time 48.29 seconds
Started Aug 18 05:32:56 PM PDT 24
Finished Aug 18 05:33:44 PM PDT 24
Peak memory 216088 kb
Host smart-808d2668-12d0-40f0-9ee4-96b9cda5d575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35896
9297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.358969297
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.525302067
Short name T89
Test name
Test status
Simulation time 6066471066 ps
CPU time 10.11 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:33:20 PM PDT 24
Peak memory 215936 kb
Host smart-3a04e445-0357-4deb-9b86-cf523a3dbdc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52530
2067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.525302067
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.261517043
Short name T3078
Test name
Test status
Simulation time 4818127438 ps
CPU time 37.35 seconds
Started Aug 18 05:33:00 PM PDT 24
Finished Aug 18 05:33:37 PM PDT 24
Peak memory 224068 kb
Host smart-cd4f6206-1718-44e2-a40f-4e4b572b6ede
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=261517043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.261517043
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.2465331436
Short name T1400
Test name
Test status
Simulation time 2569004822 ps
CPU time 18.71 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:33:29 PM PDT 24
Peak memory 207704 kb
Host smart-c772b98a-b408-4030-a314-889cec5dc19b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2465331436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.2465331436
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1018938156
Short name T1355
Test name
Test status
Simulation time 243342955 ps
CPU time 1.07 seconds
Started Aug 18 05:32:55 PM PDT 24
Finished Aug 18 05:32:56 PM PDT 24
Peak memory 207500 kb
Host smart-10428642-dfa5-4156-b5c7-9ef4e28d3426
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1018938156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1018938156
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3400958821
Short name T1440
Test name
Test status
Simulation time 191078643 ps
CPU time 0.93 seconds
Started Aug 18 05:33:08 PM PDT 24
Finished Aug 18 05:33:09 PM PDT 24
Peak memory 207460 kb
Host smart-ba599a64-2e24-4150-9e9e-c30da1b3baf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34009
58821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3400958821
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_non_iso_usb_traffic.2703986054
Short name T2018
Test name
Test status
Simulation time 2204023364 ps
CPU time 21.02 seconds
Started Aug 18 05:33:06 PM PDT 24
Finished Aug 18 05:33:28 PM PDT 24
Peak memory 217596 kb
Host smart-a90017aa-bb3d-4e01-9c37-7c7ed367679c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27039
86054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_non_iso_usb_traffic.2703986054
Directory /workspace/8.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.1477983089
Short name T2050
Test name
Test status
Simulation time 2225313952 ps
CPU time 17.26 seconds
Started Aug 18 05:32:58 PM PDT 24
Finished Aug 18 05:33:16 PM PDT 24
Peak memory 217996 kb
Host smart-680abfc4-3f7e-4400-b637-0156ca29507a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1477983089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.1477983089
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.1040097464
Short name T1728
Test name
Test status
Simulation time 3011366902 ps
CPU time 22.67 seconds
Started Aug 18 05:32:57 PM PDT 24
Finished Aug 18 05:33:20 PM PDT 24
Peak memory 207840 kb
Host smart-34fdde84-7526-4754-8d7b-9e25893eb427
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1040097464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.1040097464
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.495301756
Short name T2800
Test name
Test status
Simulation time 175638405 ps
CPU time 0.86 seconds
Started Aug 18 05:32:59 PM PDT 24
Finished Aug 18 05:33:00 PM PDT 24
Peak memory 207500 kb
Host smart-27102c60-d99d-46f7-8ff9-bc2f4f397545
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=495301756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.495301756
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1632634032
Short name T2623
Test name
Test status
Simulation time 147574952 ps
CPU time 0.86 seconds
Started Aug 18 05:33:06 PM PDT 24
Finished Aug 18 05:33:07 PM PDT 24
Peak memory 207464 kb
Host smart-be111642-2d3f-48e1-b25a-fb91c4d78eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16326
34032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1632634032
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1170700529
Short name T173
Test name
Test status
Simulation time 223652444 ps
CPU time 0.91 seconds
Started Aug 18 05:33:08 PM PDT 24
Finished Aug 18 05:33:09 PM PDT 24
Peak memory 207520 kb
Host smart-3e8468ca-b0a3-45ac-9d08-1eeade7975d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11707
00529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1170700529
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.2177484026
Short name T1329
Test name
Test status
Simulation time 184748657 ps
CPU time 0.99 seconds
Started Aug 18 05:33:00 PM PDT 24
Finished Aug 18 05:33:02 PM PDT 24
Peak memory 207636 kb
Host smart-22fb35a4-4ae6-403c-a2f3-81d120cfce03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21774
84026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.2177484026
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3225021435
Short name T2146
Test name
Test status
Simulation time 169487089 ps
CPU time 0.9 seconds
Started Aug 18 05:33:04 PM PDT 24
Finished Aug 18 05:33:05 PM PDT 24
Peak memory 207484 kb
Host smart-f82c6243-f46a-40c7-b9e1-95073a4ab8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32250
21435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3225021435
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3367373385
Short name T1434
Test name
Test status
Simulation time 198067119 ps
CPU time 0.91 seconds
Started Aug 18 05:32:58 PM PDT 24
Finished Aug 18 05:32:59 PM PDT 24
Peak memory 207524 kb
Host smart-b83c790a-bea2-47e3-bd3a-c5eb0bf0b7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33673
73385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3367373385
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3509761427
Short name T3392
Test name
Test status
Simulation time 171749637 ps
CPU time 0.92 seconds
Started Aug 18 05:33:07 PM PDT 24
Finished Aug 18 05:33:08 PM PDT 24
Peak memory 207488 kb
Host smart-7f6eb35e-0611-4ae0-b2f9-a1e88e7c0e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35097
61427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3509761427
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2079216116
Short name T2372
Test name
Test status
Simulation time 208000596 ps
CPU time 0.94 seconds
Started Aug 18 05:33:07 PM PDT 24
Finished Aug 18 05:33:08 PM PDT 24
Peak memory 207520 kb
Host smart-7ab25f1f-927f-4266-a97a-3297efcd4c6b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2079216116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2079216116
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3676537699
Short name T847
Test name
Test status
Simulation time 142044245 ps
CPU time 0.89 seconds
Started Aug 18 05:32:59 PM PDT 24
Finished Aug 18 05:33:00 PM PDT 24
Peak memory 207492 kb
Host smart-d007ec93-2ed0-4edd-b611-b00226c4f128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36765
37699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3676537699
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1910226126
Short name T32
Test name
Test status
Simulation time 50855374 ps
CPU time 0.76 seconds
Started Aug 18 05:33:06 PM PDT 24
Finished Aug 18 05:33:06 PM PDT 24
Peak memory 207544 kb
Host smart-5f4f1f5f-0340-4d70-8b21-ea290023ccd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19102
26126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1910226126
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2550670481
Short name T2119
Test name
Test status
Simulation time 6770827326 ps
CPU time 17.51 seconds
Started Aug 18 05:33:06 PM PDT 24
Finished Aug 18 05:33:24 PM PDT 24
Peak memory 215904 kb
Host smart-e058979c-2036-4994-a9db-31670199f003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25506
70481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2550670481
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.4083806112
Short name T1572
Test name
Test status
Simulation time 159733897 ps
CPU time 0.84 seconds
Started Aug 18 05:32:57 PM PDT 24
Finished Aug 18 05:32:58 PM PDT 24
Peak memory 207564 kb
Host smart-88a73a3d-5f5d-4a83-8294-a7f36ebbb77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40838
06112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.4083806112
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2549749617
Short name T37
Test name
Test status
Simulation time 237179988 ps
CPU time 0.96 seconds
Started Aug 18 05:32:57 PM PDT 24
Finished Aug 18 05:32:58 PM PDT 24
Peak memory 207424 kb
Host smart-ef0377f2-63b2-43e3-892f-7759e57fb0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25497
49617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2549749617
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.980677369
Short name T2406
Test name
Test status
Simulation time 11377133236 ps
CPU time 309.99 seconds
Started Aug 18 05:33:00 PM PDT 24
Finished Aug 18 05:38:10 PM PDT 24
Peak memory 218508 kb
Host smart-dcffc036-dc42-4413-95b6-b3e63a96a96b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=980677369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.980677369
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.2310334537
Short name T3519
Test name
Test status
Simulation time 7522507962 ps
CPU time 114.51 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:35:07 PM PDT 24
Peak memory 215948 kb
Host smart-b20cce96-3425-419a-90b7-e8a70d51c51f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2310334537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.2310334537
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.789173324
Short name T1127
Test name
Test status
Simulation time 6814786696 ps
CPU time 96.8 seconds
Started Aug 18 05:32:56 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 219192 kb
Host smart-c95d1ba9-3821-4481-af64-4e49b17e355e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=789173324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.789173324
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.2605457124
Short name T3630
Test name
Test status
Simulation time 229504730 ps
CPU time 1.05 seconds
Started Aug 18 05:32:56 PM PDT 24
Finished Aug 18 05:32:57 PM PDT 24
Peak memory 207508 kb
Host smart-25b3aea7-26d0-4260-a728-d0fca4d82868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26054
57124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.2605457124
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.1881526789
Short name T1257
Test name
Test status
Simulation time 160235093 ps
CPU time 0.88 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 207452 kb
Host smart-2b8ed3ce-5760-42b6-8d55-b981cd1345ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18815
26789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.1881526789
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_resume_link_active.2732774760
Short name T97
Test name
Test status
Simulation time 20171159139 ps
CPU time 24.62 seconds
Started Aug 18 05:33:03 PM PDT 24
Finished Aug 18 05:33:27 PM PDT 24
Peak memory 207516 kb
Host smart-39f6568b-e216-4992-b5ee-4d0bbf42f761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27327
74760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_resume_link_active.2732774760
Directory /workspace/8.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2848926456
Short name T1275
Test name
Test status
Simulation time 173390765 ps
CPU time 0.9 seconds
Started Aug 18 05:33:01 PM PDT 24
Finished Aug 18 05:33:02 PM PDT 24
Peak memory 207480 kb
Host smart-de5f07bc-12f4-4dd1-abef-6311db894df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28489
26456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2848926456
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_rx_full.567128338
Short name T43
Test name
Test status
Simulation time 399729452 ps
CPU time 1.3 seconds
Started Aug 18 05:33:11 PM PDT 24
Finished Aug 18 05:33:12 PM PDT 24
Peak memory 207388 kb
Host smart-2d246632-00a9-40ed-988b-9551a2862251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56712
8338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_full.567128338
Directory /workspace/8.usbdev_rx_full/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.4228481943
Short name T3261
Test name
Test status
Simulation time 160838400 ps
CPU time 0.87 seconds
Started Aug 18 05:32:54 PM PDT 24
Finished Aug 18 05:32:55 PM PDT 24
Peak memory 207428 kb
Host smart-9ded0035-0667-4be3-bff8-fa6b851b8500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42284
81943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.4228481943
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.3756226275
Short name T1631
Test name
Test status
Simulation time 152228450 ps
CPU time 0.91 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:14 PM PDT 24
Peak memory 207560 kb
Host smart-cf31b9f6-149a-408e-9f88-c049af32840c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37562
26275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.3756226275
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.824004486
Short name T1344
Test name
Test status
Simulation time 200637903 ps
CPU time 0.95 seconds
Started Aug 18 05:32:58 PM PDT 24
Finished Aug 18 05:33:00 PM PDT 24
Peak memory 207412 kb
Host smart-6cecdbed-30d1-4da1-bc02-1a742c199980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82400
4486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.824004486
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.1020866727
Short name T1075
Test name
Test status
Simulation time 2885985454 ps
CPU time 21.93 seconds
Started Aug 18 05:33:03 PM PDT 24
Finished Aug 18 05:33:25 PM PDT 24
Peak memory 215916 kb
Host smart-5be45274-3002-443b-aac1-f492e1b77cb4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1020866727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.1020866727
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2374161374
Short name T1058
Test name
Test status
Simulation time 189854359 ps
CPU time 0.86 seconds
Started Aug 18 05:33:11 PM PDT 24
Finished Aug 18 05:33:12 PM PDT 24
Peak memory 207504 kb
Host smart-be3bbb6d-2fa2-47ad-977b-62317e258b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23741
61374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2374161374
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2648222105
Short name T1523
Test name
Test status
Simulation time 179922727 ps
CPU time 0.9 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 207508 kb
Host smart-d3966e75-1cbb-4f6f-b8c7-76106bed79bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26482
22105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2648222105
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.2771967662
Short name T2475
Test name
Test status
Simulation time 335636949 ps
CPU time 1.3 seconds
Started Aug 18 05:33:15 PM PDT 24
Finished Aug 18 05:33:16 PM PDT 24
Peak memory 207516 kb
Host smart-48d9a750-9946-498c-aa31-32a8dd9c0a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27719
67662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2771967662
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.1645647866
Short name T3412
Test name
Test status
Simulation time 3116366360 ps
CPU time 90.66 seconds
Started Aug 18 05:33:02 PM PDT 24
Finished Aug 18 05:34:33 PM PDT 24
Peak memory 217296 kb
Host smart-7c4bfabe-ba84-4e6e-a134-f9b83925eee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16456
47866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.1645647866
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.399903619
Short name T3556
Test name
Test status
Simulation time 829821861 ps
CPU time 5.29 seconds
Started Aug 18 05:32:54 PM PDT 24
Finished Aug 18 05:33:00 PM PDT 24
Peak memory 207656 kb
Host smart-d7370ae3-2930-4e5a-b75c-77f5878a3503
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399903619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host_
handshake.399903619
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/8.usbdev_tx_rx_disruption.1828443774
Short name T192
Test name
Test status
Simulation time 401046061 ps
CPU time 1.35 seconds
Started Aug 18 05:33:08 PM PDT 24
Finished Aug 18 05:33:09 PM PDT 24
Peak memory 207548 kb
Host smart-87036ce5-594b-46e7-8ab8-fc9f5136b41b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828443774 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.usbdev_tx_rx_disruption.1828443774
Directory /workspace/8.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/80.usbdev_endpoint_types.430136814
Short name T3566
Test name
Test status
Simulation time 254445246 ps
CPU time 0.96 seconds
Started Aug 18 05:39:16 PM PDT 24
Finished Aug 18 05:39:18 PM PDT 24
Peak memory 207548 kb
Host smart-23c76c90-113e-4684-88f5-34ef3db6749b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=430136814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_endpoint_types.430136814
Directory /workspace/80.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/80.usbdev_tx_rx_disruption.4094455281
Short name T219
Test name
Test status
Simulation time 458161300 ps
CPU time 1.43 seconds
Started Aug 18 05:39:24 PM PDT 24
Finished Aug 18 05:39:26 PM PDT 24
Peak memory 207592 kb
Host smart-adf2d1aa-2b75-4733-8d08-98f76250d571
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094455281 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.usbdev_tx_rx_disruption.4094455281
Directory /workspace/80.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/81.usbdev_endpoint_types.1331260515
Short name T3293
Test name
Test status
Simulation time 487348669 ps
CPU time 1.29 seconds
Started Aug 18 05:39:16 PM PDT 24
Finished Aug 18 05:39:18 PM PDT 24
Peak memory 207544 kb
Host smart-e7c1f975-fbbf-45b7-8c4e-66551a0728dc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1331260515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_endpoint_types.1331260515
Directory /workspace/81.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/81.usbdev_tx_rx_disruption.166974244
Short name T3440
Test name
Test status
Simulation time 575806150 ps
CPU time 1.52 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:38:56 PM PDT 24
Peak memory 207500 kb
Host smart-df566c41-5e83-493c-a19f-6980094a7aa9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166974244 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 81.usbdev_tx_rx_disruption.166974244
Directory /workspace/81.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/82.usbdev_endpoint_types.3634109593
Short name T386
Test name
Test status
Simulation time 852425830 ps
CPU time 1.86 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207672 kb
Host smart-e0f01289-a466-412f-9104-067ea42ecfd4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3634109593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_endpoint_types.3634109593
Directory /workspace/82.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/82.usbdev_tx_rx_disruption.2626335726
Short name T3567
Test name
Test status
Simulation time 520859360 ps
CPU time 1.61 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207588 kb
Host smart-7f581304-71d7-4421-ab4f-e7311902cc96
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626335726 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 82.usbdev_tx_rx_disruption.2626335726
Directory /workspace/82.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/83.usbdev_endpoint_types.2058678947
Short name T444
Test name
Test status
Simulation time 572306234 ps
CPU time 1.55 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207520 kb
Host smart-df1de40e-c298-4429-990d-2c0f546c3204
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2058678947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_endpoint_types.2058678947
Directory /workspace/83.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/83.usbdev_tx_rx_disruption.3329399632
Short name T3127
Test name
Test status
Simulation time 457179394 ps
CPU time 1.41 seconds
Started Aug 18 05:39:29 PM PDT 24
Finished Aug 18 05:39:31 PM PDT 24
Peak memory 207588 kb
Host smart-9a585b2c-2d89-4267-8cb3-da1774af76f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329399632 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 83.usbdev_tx_rx_disruption.3329399632
Directory /workspace/83.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/84.usbdev_endpoint_types.3747101209
Short name T2790
Test name
Test status
Simulation time 207193372 ps
CPU time 0.92 seconds
Started Aug 18 05:39:02 PM PDT 24
Finished Aug 18 05:39:03 PM PDT 24
Peak memory 207496 kb
Host smart-3b6da73a-1d19-4802-a54c-2cb718430e60
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3747101209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_endpoint_types.3747101209
Directory /workspace/84.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/84.usbdev_tx_rx_disruption.4201224964
Short name T3042
Test name
Test status
Simulation time 512992785 ps
CPU time 1.57 seconds
Started Aug 18 05:39:32 PM PDT 24
Finished Aug 18 05:39:34 PM PDT 24
Peak memory 207592 kb
Host smart-43d94b7e-09d4-4c35-bbc2-89066b702bd3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201224964 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 84.usbdev_tx_rx_disruption.4201224964
Directory /workspace/84.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/85.usbdev_endpoint_types.2156669998
Short name T446
Test name
Test status
Simulation time 242904188 ps
CPU time 1.04 seconds
Started Aug 18 05:39:27 PM PDT 24
Finished Aug 18 05:39:28 PM PDT 24
Peak memory 207532 kb
Host smart-2189375a-94f5-4ed4-bd5b-5708810a4ce1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2156669998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_endpoint_types.2156669998
Directory /workspace/85.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/85.usbdev_tx_rx_disruption.1640127040
Short name T623
Test name
Test status
Simulation time 426036034 ps
CPU time 1.35 seconds
Started Aug 18 05:38:55 PM PDT 24
Finished Aug 18 05:38:57 PM PDT 24
Peak memory 207508 kb
Host smart-eb275863-e57e-4add-bc20-3f9edcc88abb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640127040 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.usbdev_tx_rx_disruption.1640127040
Directory /workspace/85.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/86.usbdev_endpoint_types.1292807256
Short name T433
Test name
Test status
Simulation time 350583837 ps
CPU time 1.13 seconds
Started Aug 18 05:38:57 PM PDT 24
Finished Aug 18 05:38:59 PM PDT 24
Peak memory 207500 kb
Host smart-25023b33-c01b-4884-a6a3-582fde5ef435
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1292807256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_endpoint_types.1292807256
Directory /workspace/86.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/86.usbdev_tx_rx_disruption.2631219026
Short name T1678
Test name
Test status
Simulation time 468151142 ps
CPU time 1.53 seconds
Started Aug 18 05:39:09 PM PDT 24
Finished Aug 18 05:39:11 PM PDT 24
Peak memory 207548 kb
Host smart-72a4e846-a2cc-4b04-a1b9-60d4b7408909
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631219026 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 86.usbdev_tx_rx_disruption.2631219026
Directory /workspace/86.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/87.usbdev_endpoint_types.3901114527
Short name T138
Test name
Test status
Simulation time 466099503 ps
CPU time 1.35 seconds
Started Aug 18 05:39:01 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207668 kb
Host smart-3ecf0014-cf91-47cc-a370-90fc6a112817
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3901114527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_endpoint_types.3901114527
Directory /workspace/87.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/87.usbdev_tx_rx_disruption.1371436205
Short name T1618
Test name
Test status
Simulation time 542045938 ps
CPU time 1.63 seconds
Started Aug 18 05:39:08 PM PDT 24
Finished Aug 18 05:39:10 PM PDT 24
Peak memory 207588 kb
Host smart-24412ede-5080-4791-9cb7-da4b06320fc5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371436205 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.usbdev_tx_rx_disruption.1371436205
Directory /workspace/87.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/88.usbdev_endpoint_types.3909866302
Short name T497
Test name
Test status
Simulation time 223919298 ps
CPU time 1.05 seconds
Started Aug 18 05:39:12 PM PDT 24
Finished Aug 18 05:39:14 PM PDT 24
Peak memory 207492 kb
Host smart-ded000f8-cbdc-40f9-8d5f-0c08b4c96f73
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3909866302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_endpoint_types.3909866302
Directory /workspace/88.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/88.usbdev_tx_rx_disruption.4119035338
Short name T1984
Test name
Test status
Simulation time 490529453 ps
CPU time 1.51 seconds
Started Aug 18 05:39:09 PM PDT 24
Finished Aug 18 05:39:11 PM PDT 24
Peak memory 207576 kb
Host smart-065973de-8c50-4568-9ee0-ff788a6ce964
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119035338 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 88.usbdev_tx_rx_disruption.4119035338
Directory /workspace/88.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/89.usbdev_endpoint_types.995858743
Short name T494
Test name
Test status
Simulation time 394424548 ps
CPU time 1.24 seconds
Started Aug 18 05:39:16 PM PDT 24
Finished Aug 18 05:39:18 PM PDT 24
Peak memory 207536 kb
Host smart-b7d188f1-cbf8-44fa-a8e7-806930f7ac3f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=995858743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_endpoint_types.995858743
Directory /workspace/89.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/89.usbdev_tx_rx_disruption.857442889
Short name T181
Test name
Test status
Simulation time 614265097 ps
CPU time 1.56 seconds
Started Aug 18 05:39:13 PM PDT 24
Finished Aug 18 05:39:15 PM PDT 24
Peak memory 207592 kb
Host smart-da10378b-f54c-47c7-bd65-6d48826e6513
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857442889 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 89.usbdev_tx_rx_disruption.857442889
Directory /workspace/89.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.137346808
Short name T1258
Test name
Test status
Simulation time 32411178 ps
CPU time 0.67 seconds
Started Aug 18 05:33:33 PM PDT 24
Finished Aug 18 05:33:34 PM PDT 24
Peak memory 207360 kb
Host smart-d02ed7b5-62e0-4921-a7df-b9454faea985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=137346808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.137346808
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.3043279919
Short name T1963
Test name
Test status
Simulation time 10722763586 ps
CPU time 16.94 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:30 PM PDT 24
Peak memory 207780 kb
Host smart-87fcf29d-b43a-4434-846a-86bfc6a6cc3a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043279919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_disconnect.3043279919
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.2823728133
Short name T3215
Test name
Test status
Simulation time 19685722507 ps
CPU time 25.33 seconds
Started Aug 18 05:33:12 PM PDT 24
Finished Aug 18 05:33:37 PM PDT 24
Peak memory 207724 kb
Host smart-eeb2b467-28b3-42b9-b550-b860d8361ac9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823728133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.2823728133
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.1448000775
Short name T1084
Test name
Test status
Simulation time 30106213195 ps
CPU time 42.08 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:55 PM PDT 24
Peak memory 207812 kb
Host smart-9119c44a-f2bc-4557-86a7-2f46b8e5d44a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448000775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.1448000775
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2191442684
Short name T3430
Test name
Test status
Simulation time 156953518 ps
CPU time 0.92 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 207468 kb
Host smart-bf3616c4-ee11-4d31-82ff-13de011d64a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21914
42684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2191442684
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1995677370
Short name T3314
Test name
Test status
Simulation time 149868313 ps
CPU time 0.87 seconds
Started Aug 18 05:33:07 PM PDT 24
Finished Aug 18 05:33:08 PM PDT 24
Peak memory 207576 kb
Host smart-ae8ebdb7-2bbd-4409-aa5e-fb3553b78427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19956
77370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1995677370
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.3951696112
Short name T826
Test name
Test status
Simulation time 167067820 ps
CPU time 0.92 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:14 PM PDT 24
Peak memory 207540 kb
Host smart-0c39295b-bd31-4a9d-9faa-989e6accbedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39516
96112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.3951696112
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3220098554
Short name T1858
Test name
Test status
Simulation time 542969798 ps
CPU time 1.53 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 207548 kb
Host smart-8cad7fbc-4481-4b5b-8dce-66470f92be7f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3220098554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3220098554
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.753199517
Short name T2662
Test name
Test status
Simulation time 29580122883 ps
CPU time 45.1 seconds
Started Aug 18 05:33:06 PM PDT 24
Finished Aug 18 05:33:51 PM PDT 24
Peak memory 207740 kb
Host smart-4191e70a-4e9d-4d81-a782-d3cc03980319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75319
9517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.753199517
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.1999703324
Short name T1847
Test name
Test status
Simulation time 5696705660 ps
CPU time 35.7 seconds
Started Aug 18 05:33:06 PM PDT 24
Finished Aug 18 05:33:42 PM PDT 24
Peak memory 207728 kb
Host smart-ed2ffac4-3021-4f6f-b83e-e9c5874bc3cb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999703324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.1999703324
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1818715510
Short name T1350
Test name
Test status
Simulation time 777770829 ps
CPU time 1.82 seconds
Started Aug 18 05:33:05 PM PDT 24
Finished Aug 18 05:33:07 PM PDT 24
Peak memory 207540 kb
Host smart-6bea17e9-c568-48b8-a1ff-4c7a646426d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18187
15510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1818715510
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1184643897
Short name T2884
Test name
Test status
Simulation time 142540492 ps
CPU time 0.81 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 207548 kb
Host smart-d901041e-6ab7-49c7-8744-65dddad5f3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11846
43897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1184643897
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2462912624
Short name T3437
Test name
Test status
Simulation time 64528639 ps
CPU time 0.71 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:14 PM PDT 24
Peak memory 207452 kb
Host smart-e7c0d434-8329-45fa-b0c4-27df6acbed6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24629
12624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2462912624
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3072361043
Short name T2920
Test name
Test status
Simulation time 755782773 ps
CPU time 2.06 seconds
Started Aug 18 05:33:12 PM PDT 24
Finished Aug 18 05:33:14 PM PDT 24
Peak memory 207764 kb
Host smart-5c470c24-f9ed-434e-85f8-ff8de2148ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30723
61043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3072361043
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_types.165173346
Short name T495
Test name
Test status
Simulation time 263294469 ps
CPU time 1.02 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 207528 kb
Host smart-94aee6b2-7b15-49f0-b57f-cd1f23ce171f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=165173346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_types.165173346
Directory /workspace/9.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3765032427
Short name T1172
Test name
Test status
Simulation time 169443833 ps
CPU time 1.77 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:15 PM PDT 24
Peak memory 207684 kb
Host smart-a43f4555-08b8-42f8-8d35-ecc7910ed0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37650
32427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3765032427
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.6941181
Short name T1356
Test name
Test status
Simulation time 231593896 ps
CPU time 1.17 seconds
Started Aug 18 05:33:06 PM PDT 24
Finished Aug 18 05:33:07 PM PDT 24
Peak memory 215788 kb
Host smart-f641e35b-e657-4b50-93ea-86147823cd82
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=6941181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.6941181
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.525415912
Short name T2646
Test name
Test status
Simulation time 142346275 ps
CPU time 0.83 seconds
Started Aug 18 05:33:12 PM PDT 24
Finished Aug 18 05:33:13 PM PDT 24
Peak memory 207364 kb
Host smart-94cd49bb-8eee-46bc-a632-71642bf5b583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52541
5912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.525415912
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.617194592
Short name T3352
Test name
Test status
Simulation time 224683862 ps
CPU time 1.04 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:33:13 PM PDT 24
Peak memory 207508 kb
Host smart-37b23b19-aca9-4b39-a840-81e3afdbaa80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61719
4592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.617194592
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.1015068905
Short name T1266
Test name
Test status
Simulation time 3355407094 ps
CPU time 25.37 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:39 PM PDT 24
Peak memory 218112 kb
Host smart-9b84e80f-0154-45ba-af3a-ef355d200b28
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1015068905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.1015068905
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.238508698
Short name T2376
Test name
Test status
Simulation time 5407453487 ps
CPU time 32.76 seconds
Started Aug 18 05:33:12 PM PDT 24
Finished Aug 18 05:33:45 PM PDT 24
Peak memory 207796 kb
Host smart-d3be6f28-0701-4c00-a065-c5fe4e861bf7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=238508698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.238508698
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.166456910
Short name T2210
Test name
Test status
Simulation time 234616983 ps
CPU time 0.97 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:33:11 PM PDT 24
Peak memory 207396 kb
Host smart-1be997d6-19b9-49d9-b679-d91de444995b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16645
6910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.166456910
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3280620826
Short name T862
Test name
Test status
Simulation time 26198304658 ps
CPU time 41.64 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:33:52 PM PDT 24
Peak memory 216028 kb
Host smart-edb12944-0959-4d69-a5cb-4fcdbc0bf7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32806
20826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3280620826
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.3269268279
Short name T1381
Test name
Test status
Simulation time 5804779965 ps
CPU time 7.31 seconds
Started Aug 18 05:33:06 PM PDT 24
Finished Aug 18 05:33:14 PM PDT 24
Peak memory 216732 kb
Host smart-1e9f5f75-933f-49f4-816a-9ad36d3943c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32692
68279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3269268279
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.3152496424
Short name T863
Test name
Test status
Simulation time 2468135537 ps
CPU time 17.41 seconds
Started Aug 18 05:33:16 PM PDT 24
Finished Aug 18 05:33:33 PM PDT 24
Peak memory 224084 kb
Host smart-2d80dc7c-1dd5-4332-be2d-4500e4f3d98c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3152496424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.3152496424
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.4184489299
Short name T2972
Test name
Test status
Simulation time 1889146196 ps
CPU time 14.01 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:23 PM PDT 24
Peak memory 216872 kb
Host smart-200510db-2546-41f9-98bf-9652e3f71533
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4184489299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.4184489299
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3215987556
Short name T3433
Test name
Test status
Simulation time 239724202 ps
CPU time 1.14 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:11 PM PDT 24
Peak memory 207452 kb
Host smart-84103727-c6e0-4e2e-9465-bdae9ba17e2d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3215987556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3215987556
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3322029135
Short name T3260
Test name
Test status
Simulation time 206938236 ps
CPU time 1.06 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:33:11 PM PDT 24
Peak memory 207508 kb
Host smart-6d3cf098-8d4d-44e4-8cb1-70e407a919fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33220
29135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3322029135
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_non_iso_usb_traffic.551159637
Short name T2915
Test name
Test status
Simulation time 3600265803 ps
CPU time 29.33 seconds
Started Aug 18 05:33:15 PM PDT 24
Finished Aug 18 05:33:44 PM PDT 24
Peak memory 215956 kb
Host smart-fdc32873-0a6b-4bf2-84de-57d6c48b6d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55115
9637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_non_iso_usb_traffic.551159637
Directory /workspace/9.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.2134396514
Short name T1288
Test name
Test status
Simulation time 1862339372 ps
CPU time 51.52 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:34:01 PM PDT 24
Peak memory 215940 kb
Host smart-81c97d21-7cd1-445a-90b8-d50e02faea43
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2134396514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.2134396514
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.2021718916
Short name T2919
Test name
Test status
Simulation time 3633621962 ps
CPU time 36.52 seconds
Started Aug 18 05:33:15 PM PDT 24
Finished Aug 18 05:33:51 PM PDT 24
Peak memory 217532 kb
Host smart-17a3c9f0-3842-434f-9014-254c3217e4e3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2021718916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.2021718916
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.2342733182
Short name T2260
Test name
Test status
Simulation time 163411455 ps
CPU time 0.88 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:33:16 PM PDT 24
Peak memory 207460 kb
Host smart-8a33e666-9351-4219-ab49-123b3bac1fd8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2342733182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.2342733182
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3951562808
Short name T1725
Test name
Test status
Simulation time 145976507 ps
CPU time 0.83 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 207448 kb
Host smart-ffa9c6e4-e944-4923-abe0-4c0a58130da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39515
62808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3951562808
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.3745457625
Short name T169
Test name
Test status
Simulation time 237796683 ps
CPU time 0.97 seconds
Started Aug 18 05:33:13 PM PDT 24
Finished Aug 18 05:33:14 PM PDT 24
Peak memory 207460 kb
Host smart-e625715c-5838-4602-8a12-43bccfa8c7cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37454
57625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3745457625
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2639249135
Short name T2211
Test name
Test status
Simulation time 236125145 ps
CPU time 0.98 seconds
Started Aug 18 05:33:07 PM PDT 24
Finished Aug 18 05:33:08 PM PDT 24
Peak memory 207456 kb
Host smart-b9c24e47-a789-47e3-85d5-6aa471af4eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26392
49135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2639249135
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.942024097
Short name T3237
Test name
Test status
Simulation time 190564868 ps
CPU time 0.95 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:33:11 PM PDT 24
Peak memory 207660 kb
Host smart-3b72f5f4-b7a9-4789-a418-4ee9f48516cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94202
4097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.942024097
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.760793175
Short name T1113
Test name
Test status
Simulation time 168719118 ps
CPU time 0.93 seconds
Started Aug 18 05:33:12 PM PDT 24
Finished Aug 18 05:33:13 PM PDT 24
Peak memory 207536 kb
Host smart-9b8d95b0-9ee9-4ea3-b274-be2e8001d4e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76079
3175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.760793175
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2030260441
Short name T2173
Test name
Test status
Simulation time 154169338 ps
CPU time 0.85 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 207564 kb
Host smart-727c9ff6-df67-4f6b-9275-d19e776cd085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20302
60441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2030260441
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.3740598742
Short name T1784
Test name
Test status
Simulation time 231716846 ps
CPU time 0.99 seconds
Started Aug 18 05:33:09 PM PDT 24
Finished Aug 18 05:33:10 PM PDT 24
Peak memory 207532 kb
Host smart-9b9ec246-3597-4918-b6ec-390f8847c41a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3740598742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.3740598742
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2522392430
Short name T1289
Test name
Test status
Simulation time 137550826 ps
CPU time 0.77 seconds
Started Aug 18 05:33:11 PM PDT 24
Finished Aug 18 05:33:12 PM PDT 24
Peak memory 207456 kb
Host smart-80df5212-319c-4ae4-9675-0615586210c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25223
92430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2522392430
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2298996068
Short name T2293
Test name
Test status
Simulation time 74638052 ps
CPU time 0.74 seconds
Started Aug 18 05:33:12 PM PDT 24
Finished Aug 18 05:33:13 PM PDT 24
Peak memory 207560 kb
Host smart-de24153a-7755-47a0-83b3-89a1fbd90aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22989
96068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2298996068
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.1503635308
Short name T294
Test name
Test status
Simulation time 20960744313 ps
CPU time 50.29 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:34:00 PM PDT 24
Peak memory 224136 kb
Host smart-9770bdbf-231e-4c9c-946e-b9b1cf2eb897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15036
35308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.1503635308
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1232163440
Short name T1385
Test name
Test status
Simulation time 188774119 ps
CPU time 0.93 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:33:11 PM PDT 24
Peak memory 207536 kb
Host smart-c824b4eb-4fd4-4bad-b6be-7a5691966287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12321
63440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1232163440
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1992921156
Short name T2599
Test name
Test status
Simulation time 229188992 ps
CPU time 1.07 seconds
Started Aug 18 05:33:11 PM PDT 24
Finished Aug 18 05:33:12 PM PDT 24
Peak memory 207484 kb
Host smart-4310fdcd-03d9-4531-95e8-3d11d9673f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19929
21156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1992921156
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.86018129
Short name T2308
Test name
Test status
Simulation time 5929712068 ps
CPU time 61.9 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:34:17 PM PDT 24
Peak memory 219140 kb
Host smart-588b2708-4651-4826-9c97-77c61ba6a2d0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=86018129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.86018129
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.2627248713
Short name T50
Test name
Test status
Simulation time 10124901059 ps
CPU time 48.35 seconds
Started Aug 18 05:33:11 PM PDT 24
Finished Aug 18 05:34:00 PM PDT 24
Peak memory 218676 kb
Host smart-e6740118-b7fb-44dc-a78b-9f29af0af7fe
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627248713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.2627248713
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.3774254821
Short name T675
Test name
Test status
Simulation time 212829808 ps
CPU time 0.96 seconds
Started Aug 18 05:33:11 PM PDT 24
Finished Aug 18 05:33:12 PM PDT 24
Peak memory 207512 kb
Host smart-5dc58035-8aa8-4920-b66f-1b2d4a108474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37742
54821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.3774254821
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.2606514281
Short name T2133
Test name
Test status
Simulation time 156008016 ps
CPU time 0.86 seconds
Started Aug 18 05:33:11 PM PDT 24
Finished Aug 18 05:33:12 PM PDT 24
Peak memory 207448 kb
Host smart-86e67a09-196a-476f-8807-9bc53254049b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26065
14281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.2606514281
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_resume_link_active.712082181
Short name T2120
Test name
Test status
Simulation time 20154475775 ps
CPU time 26.75 seconds
Started Aug 18 05:33:10 PM PDT 24
Finished Aug 18 05:33:37 PM PDT 24
Peak memory 207596 kb
Host smart-a25dc709-b982-42ae-987b-07a5f9da9005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71208
2181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_resume_link_active.712082181
Directory /workspace/9.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1355230285
Short name T2299
Test name
Test status
Simulation time 158966849 ps
CPU time 0.88 seconds
Started Aug 18 05:33:19 PM PDT 24
Finished Aug 18 05:33:20 PM PDT 24
Peak memory 207508 kb
Host smart-35051e0e-ebd9-44af-93b3-acf3e36f94d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13552
30285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1355230285
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_rx_full.2712611325
Short name T3535
Test name
Test status
Simulation time 289961828 ps
CPU time 1.19 seconds
Started Aug 18 05:33:12 PM PDT 24
Finished Aug 18 05:33:13 PM PDT 24
Peak memory 207440 kb
Host smart-4b07f00e-6be0-4e56-bf38-216d308f7456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27126
11325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_full.2712611325
Directory /workspace/9.usbdev_rx_full/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2555629200
Short name T1378
Test name
Test status
Simulation time 230946498 ps
CPU time 0.96 seconds
Started Aug 18 05:33:22 PM PDT 24
Finished Aug 18 05:33:24 PM PDT 24
Peak memory 207460 kb
Host smart-5325b5e0-c185-4ec0-ae66-3293ded71796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25556
29200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2555629200
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2963889881
Short name T2169
Test name
Test status
Simulation time 165980079 ps
CPU time 0.85 seconds
Started Aug 18 05:33:20 PM PDT 24
Finished Aug 18 05:33:21 PM PDT 24
Peak memory 207580 kb
Host smart-19d1142c-a751-494e-9f6c-e86d182e5cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29638
89881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2963889881
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2628822221
Short name T177
Test name
Test status
Simulation time 207747633 ps
CPU time 0.99 seconds
Started Aug 18 05:33:40 PM PDT 24
Finished Aug 18 05:33:41 PM PDT 24
Peak memory 207464 kb
Host smart-79934241-1cfb-4e40-9616-3cba73a8be7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26288
22221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2628822221
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.1516670338
Short name T2309
Test name
Test status
Simulation time 1877216348 ps
CPU time 14.73 seconds
Started Aug 18 05:33:23 PM PDT 24
Finished Aug 18 05:33:37 PM PDT 24
Peak memory 224020 kb
Host smart-61ba2c6f-9bdb-4977-95d0-dc9b8efeda0b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1516670338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.1516670338
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.301123588
Short name T3521
Test name
Test status
Simulation time 191487607 ps
CPU time 0.92 seconds
Started Aug 18 05:33:19 PM PDT 24
Finished Aug 18 05:33:20 PM PDT 24
Peak memory 207484 kb
Host smart-1b49c43e-a2eb-4739-9972-5c841d9d6c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30112
3588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.301123588
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1683549110
Short name T139
Test name
Test status
Simulation time 194212317 ps
CPU time 0.92 seconds
Started Aug 18 05:33:37 PM PDT 24
Finished Aug 18 05:33:38 PM PDT 24
Peak memory 207456 kb
Host smart-64428a6d-a014-4902-9215-f3ac69e7d19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16835
49110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1683549110
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.3516600644
Short name T3491
Test name
Test status
Simulation time 262540555 ps
CPU time 1.09 seconds
Started Aug 18 05:33:34 PM PDT 24
Finished Aug 18 05:33:36 PM PDT 24
Peak memory 207552 kb
Host smart-e4cacc17-d6db-4b42-b423-f1bedd5772af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35166
00644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3516600644
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.118019015
Short name T1413
Test name
Test status
Simulation time 1934905676 ps
CPU time 53.4 seconds
Started Aug 18 05:33:26 PM PDT 24
Finished Aug 18 05:34:20 PM PDT 24
Peak memory 215848 kb
Host smart-abe2358d-c9e4-4b03-ac23-b7fe9735982d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11801
9015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.118019015
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.2648575731
Short name T3245
Test name
Test status
Simulation time 590144700 ps
CPU time 11.52 seconds
Started Aug 18 05:33:11 PM PDT 24
Finished Aug 18 05:33:23 PM PDT 24
Peak memory 207672 kb
Host smart-8f681b51-c16b-40e5-bdc7-d66a9826aa4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648575731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host
_handshake.2648575731
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/9.usbdev_tx_rx_disruption.4041142410
Short name T1925
Test name
Test status
Simulation time 441378698 ps
CPU time 1.46 seconds
Started Aug 18 05:33:16 PM PDT 24
Finished Aug 18 05:33:17 PM PDT 24
Peak memory 207496 kb
Host smart-09dc57f8-4f02-4f49-bc2d-cf1fa688207a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041142410 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.usbdev_tx_rx_disruption.4041142410
Directory /workspace/9.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/90.usbdev_endpoint_types.4255368292
Short name T392
Test name
Test status
Simulation time 258364311 ps
CPU time 1.03 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 207452 kb
Host smart-bdbb53eb-35be-4c2a-b1fa-22cebadc2260
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4255368292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_endpoint_types.4255368292
Directory /workspace/90.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/90.usbdev_tx_rx_disruption.196404104
Short name T120
Test name
Test status
Simulation time 625355299 ps
CPU time 1.71 seconds
Started Aug 18 05:38:59 PM PDT 24
Finished Aug 18 05:39:01 PM PDT 24
Peak memory 207536 kb
Host smart-d7f322f3-71e3-49dc-8ccf-972ef72e757d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196404104 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 90.usbdev_tx_rx_disruption.196404104
Directory /workspace/90.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/91.usbdev_endpoint_types.3958402296
Short name T3481
Test name
Test status
Simulation time 452485816 ps
CPU time 1.31 seconds
Started Aug 18 05:39:04 PM PDT 24
Finished Aug 18 05:39:06 PM PDT 24
Peak memory 207524 kb
Host smart-704042d0-5b7c-47e4-8613-3b9a05e896d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3958402296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_endpoint_types.3958402296
Directory /workspace/91.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/92.usbdev_endpoint_types.3736616533
Short name T394
Test name
Test status
Simulation time 271555412 ps
CPU time 1.03 seconds
Started Aug 18 05:39:05 PM PDT 24
Finished Aug 18 05:39:07 PM PDT 24
Peak memory 207508 kb
Host smart-05ef5745-c43a-4ff9-a1af-1488199a7b74
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3736616533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_endpoint_types.3736616533
Directory /workspace/92.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/92.usbdev_tx_rx_disruption.3977034544
Short name T2564
Test name
Test status
Simulation time 562854333 ps
CPU time 1.53 seconds
Started Aug 18 05:39:28 PM PDT 24
Finished Aug 18 05:39:30 PM PDT 24
Peak memory 207592 kb
Host smart-94e5c465-ce22-495b-a3c9-45807cd77969
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977034544 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.usbdev_tx_rx_disruption.3977034544
Directory /workspace/92.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/93.usbdev_endpoint_types.2919664978
Short name T470
Test name
Test status
Simulation time 165074444 ps
CPU time 0.88 seconds
Started Aug 18 05:39:12 PM PDT 24
Finished Aug 18 05:39:13 PM PDT 24
Peak memory 207532 kb
Host smart-71c8759f-0a2d-4dfa-bf48-f3a45656f993
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2919664978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_endpoint_types.2919664978
Directory /workspace/93.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/93.usbdev_tx_rx_disruption.735303005
Short name T921
Test name
Test status
Simulation time 478639505 ps
CPU time 1.57 seconds
Started Aug 18 05:39:06 PM PDT 24
Finished Aug 18 05:39:08 PM PDT 24
Peak memory 207496 kb
Host smart-408dc1bd-6ebc-4538-a326-848eabcb4aeb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735303005 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 93.usbdev_tx_rx_disruption.735303005
Directory /workspace/93.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/94.usbdev_tx_rx_disruption.2386155303
Short name T945
Test name
Test status
Simulation time 433958347 ps
CPU time 1.37 seconds
Started Aug 18 05:39:29 PM PDT 24
Finished Aug 18 05:39:30 PM PDT 24
Peak memory 207592 kb
Host smart-896e58cf-b842-425d-bc1b-e50c983d5fc3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386155303 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.usbdev_tx_rx_disruption.2386155303
Directory /workspace/94.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/95.usbdev_endpoint_types.1731086718
Short name T3538
Test name
Test status
Simulation time 425540022 ps
CPU time 1.32 seconds
Started Aug 18 05:39:07 PM PDT 24
Finished Aug 18 05:39:14 PM PDT 24
Peak memory 207448 kb
Host smart-09254f9f-0ab5-4715-ae0c-c0feb2cfef98
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1731086718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_endpoint_types.1731086718
Directory /workspace/95.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/95.usbdev_tx_rx_disruption.171728149
Short name T2253
Test name
Test status
Simulation time 459554265 ps
CPU time 1.4 seconds
Started Aug 18 05:38:57 PM PDT 24
Finished Aug 18 05:38:58 PM PDT 24
Peak memory 207580 kb
Host smart-e632d3e5-b83e-45d3-a7cb-543b960698d0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171728149 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 95.usbdev_tx_rx_disruption.171728149
Directory /workspace/95.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/96.usbdev_endpoint_types.2966110611
Short name T458
Test name
Test status
Simulation time 293971059 ps
CPU time 1.12 seconds
Started Aug 18 05:39:19 PM PDT 24
Finished Aug 18 05:39:20 PM PDT 24
Peak memory 207532 kb
Host smart-12152915-3637-4b6a-b0a7-681cefde4833
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2966110611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_endpoint_types.2966110611
Directory /workspace/96.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/96.usbdev_tx_rx_disruption.790790874
Short name T1063
Test name
Test status
Simulation time 498487470 ps
CPU time 1.51 seconds
Started Aug 18 05:39:01 PM PDT 24
Finished Aug 18 05:39:03 PM PDT 24
Peak memory 207552 kb
Host smart-06d243de-3c26-47bb-8ef4-7c06583059d7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790790874 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 96.usbdev_tx_rx_disruption.790790874
Directory /workspace/96.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/97.usbdev_endpoint_types.3858886955
Short name T402
Test name
Test status
Simulation time 347965245 ps
CPU time 1.08 seconds
Started Aug 18 05:39:05 PM PDT 24
Finished Aug 18 05:39:06 PM PDT 24
Peak memory 207508 kb
Host smart-dd04d6c1-f56c-4991-8b4c-ef539f2355f9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3858886955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_endpoint_types.3858886955
Directory /workspace/97.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/97.usbdev_tx_rx_disruption.471775909
Short name T208
Test name
Test status
Simulation time 600807437 ps
CPU time 1.74 seconds
Started Aug 18 05:39:08 PM PDT 24
Finished Aug 18 05:39:10 PM PDT 24
Peak memory 207552 kb
Host smart-d215da33-c895-4a59-aaf1-1263b6c5292f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471775909 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 97.usbdev_tx_rx_disruption.471775909
Directory /workspace/97.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/98.usbdev_endpoint_types.1790502024
Short name T1273
Test name
Test status
Simulation time 230429074 ps
CPU time 1.15 seconds
Started Aug 18 05:39:00 PM PDT 24
Finished Aug 18 05:39:02 PM PDT 24
Peak memory 207524 kb
Host smart-91eaa3f2-159b-429a-8608-2e1079b9b1a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1790502024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_endpoint_types.1790502024
Directory /workspace/98.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/98.usbdev_tx_rx_disruption.64430107
Short name T1237
Test name
Test status
Simulation time 644036294 ps
CPU time 1.66 seconds
Started Aug 18 05:39:08 PM PDT 24
Finished Aug 18 05:39:10 PM PDT 24
Peak memory 207596 kb
Host smart-e072bb45-186c-4c7a-a5df-cbb73aebf354
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64430107 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 98.usbdev_tx_rx_disruption.64430107
Directory /workspace/98.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/99.usbdev_endpoint_types.3567385694
Short name T490
Test name
Test status
Simulation time 324241911 ps
CPU time 1.18 seconds
Started Aug 18 05:39:11 PM PDT 24
Finished Aug 18 05:39:12 PM PDT 24
Peak memory 207460 kb
Host smart-554ec8d6-4dba-4948-946f-d85fc7e84072
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3567385694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_endpoint_types.3567385694
Directory /workspace/99.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/99.usbdev_tx_rx_disruption.1267837954
Short name T1479
Test name
Test status
Simulation time 541673608 ps
CPU time 1.57 seconds
Started Aug 18 05:39:05 PM PDT 24
Finished Aug 18 05:39:07 PM PDT 24
Peak memory 207772 kb
Host smart-9a5e124f-6cd7-4dd4-9d0a-417927cb97bc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267837954 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 99.usbdev_tx_rx_disruption.1267837954
Directory /workspace/99.usbdev_tx_rx_disruption/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%