Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	80265	1			T1	5		T2	3		T3	3
all_values[1]	80265	1			T1	5		T2	3		T3	3
all_values[2]	80265	1			T1	5		T2	3		T3	3
all_values[3]	80265	1			T1	5		T2	3		T3	3
all_values[4]	80265	1			T1	5		T2	3		T3	3
all_values[5]	80265	1			T1	5		T2	3		T3	3
all_values[6]	80265	1			T1	5		T2	3		T3	3
all_values[7]	80265	1			T1	5		T2	3		T3	3
all_values[8]	80265	1			T1	5		T2	3		T3	3
all_values[9]	80265	1			T1	5		T2	3		T3	3
all_values[10]	80265	1			T1	5		T2	3		T3	3
all_values[11]	80265	1			T1	5		T2	3		T3	3
all_values[12]	80265	1			T1	5		T2	3		T3	3
all_values[13]	80265	1			T1	5		T2	3		T3	3
all_values[14]	80265	1			T1	5		T2	3		T3	3
all_values[15]	80265	1			T1	5		T2	3		T3	3
all_values[16]	80265	1			T1	5		T2	3		T3	3
all_values[17]	80265	1			T1	5		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2558855

1

T1

158

T2

93

T3

94

auto[1]

9625

1

T1

2

T2

3

T3

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2132130

1

T1

146

T2

83

T3

85

auto[1]

436350

1

T1

14

T2

13

T3

11

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	52361	1			T1	3		T2	3		T3	3
all_values[0]	auto[0]	auto[1]	24658	1			T1	2		T34	3		T36	4
all_values[0]	auto[1]	auto[0]	3152	1			T53	3		T54	3		T55	3
all_values[0]	auto[1]	auto[1]	94	1			T308	1		T340	1		T341	1
all_values[1]	auto[0]	auto[0]	75836	1			T1	5		T3	3		T41	2
all_values[1]	auto[0]	auto[1]	3015	1			T29	2		T30	2		T34	1
all_values[1]	auto[1]	auto[0]	518	1			T2	2		T31	2		T33	2
all_values[1]	auto[1]	auto[1]	896	1			T2	1		T31	12		T33	1
all_values[2]	auto[0]	auto[0]	4228	1			T1	4		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	75780	1			T1	1		T2	2		T3	2
all_values[2]	auto[1]	auto[0]	149	1			T42	1		T68	1		T69	1
all_values[2]	auto[1]	auto[1]	108	1			T42	1		T68	1		T69	1
all_values[3]	auto[0]	auto[0]	78332	1			T1	5		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	293	1			T22	1		T70	1		T71	1
all_values[3]	auto[1]	auto[0]	1567	1			T22	1484		T228	1		T231	2
all_values[3]	auto[1]	auto[1]	73	1			T22	1		T228	3		T231	3
all_values[4]	auto[0]	auto[0]	4187	1			T1	4		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	75900	1			T1	1		T2	2		T3	2
all_values[4]	auto[1]	auto[0]	116	1			T52	1		T228	5		T231	3
all_values[4]	auto[1]	auto[1]	62	1			T52	1		T228	1		T231	1
all_values[5]	auto[0]	auto[0]	79755	1			T1	5		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	358	1			T7	1		T21	1		T8	1
all_values[5]	auto[1]	auto[0]	82	1			T228	3		T229	3		T231	1
all_values[5]	auto[1]	auto[1]	70	1			T228	1		T229	1		T231	3
all_values[6]	auto[0]	auto[0]	79851	1			T1	5		T2	3		T3	3
all_values[6]	auto[0]	auto[1]	212	1			T8	1		T9	1		T10	1
all_values[6]	auto[1]	auto[0]	93	1			T228	3		T229	2		T231	1
all_values[6]	auto[1]	auto[1]	109	1			T72	1		T73	1		T74	1
all_values[7]	auto[0]	auto[0]	24945	1			T3	3		T42	2		T43	2
all_values[7]	auto[0]	auto[1]	55149	1			T1	3		T2	3		T29	2
all_values[7]	auto[1]	auto[0]	113	1			T1	1		T56	1		T57	1
all_values[7]	auto[1]	auto[1]	58	1			T1	1		T56	1		T57	1
all_values[8]	auto[0]	auto[0]	79522	1			T1	5		T2	3		T3	3
all_values[8]	auto[0]	auto[1]	49	1			T228	1		T231	2		T330	2
all_values[8]	auto[1]	auto[0]	611	1			T58	10		T60	10		T61	10
all_values[8]	auto[1]	auto[1]	83	1			T58	1		T61	1		T63	1
all_values[9]	auto[0]	auto[0]	80022	1			T1	5		T2	3		T3	3
all_values[9]	auto[0]	auto[1]	74	1			T228	4		T229	1		T330	5
all_values[9]	auto[1]	auto[0]	98	1			T66	3		T23	3		T67	3
all_values[9]	auto[1]	auto[1]	71	1			T66	2		T23	2		T67	2
all_values[10]	auto[0]	auto[0]	79743	1			T1	5		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	374	1			T30	1		T36	2		T40	1
all_values[10]	auto[1]	auto[0]	98	1			T229	4		T231	2		T330	4
all_values[10]	auto[1]	auto[1]	50	1			T231	3		T332	3		T333	1
all_values[11]	auto[0]	auto[0]	79257	1			T1	5		T2	3		T3	2
all_values[11]	auto[0]	auto[1]	743	1			T3	1		T37	4		T38	4
all_values[11]	auto[1]	auto[0]	151	1			T78	1		T79	1		T80	1
all_values[11]	auto[1]	auto[1]	114	1			T78	1		T79	1		T80	1
all_values[12]	auto[0]	auto[0]	79878	1			T1	5		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	220	1			T83	1		T85	1		T86	1
all_values[12]	auto[1]	auto[0]	105	1			T81	2		T82	2		T84	2
all_values[12]	auto[1]	auto[1]	62	1			T81	1		T82	1		T84	1
all_values[13]	auto[0]	auto[0]	79942	1			T1	5		T2	3		T3	1
all_values[13]	auto[0]	auto[1]	74	1			T83	1		T85	1		T86	1
all_values[13]	auto[1]	auto[0]	135	1			T3	1		T87	1		T88	1
all_values[13]	auto[1]	auto[1]	114	1			T3	1		T87	1		T88	1
all_values[14]	auto[0]	auto[0]	15869	1			T1	5		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	64235	1			T42	1		T65	1		T7	2
all_values[14]	auto[1]	auto[0]	113	1			T228	4		T229	1		T231	3
all_values[14]	auto[1]	auto[1]	48	1			T228	1		T231	1		T330	1
all_values[15]	auto[0]	auto[0]	4256	1			T1	4		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	75850	1			T1	1		T2	2		T3	2
all_values[15]	auto[1]	auto[0]	93	1			T228	3		T229	1		T330	1
all_values[15]	auto[1]	auto[1]	66	1			T228	3		T229	4		T330	2
all_values[16]	auto[0]	auto[0]	79253	1			T1	5		T2	3		T3	3
all_values[16]	auto[0]	auto[1]	809	1			T30	1		T76	1		T77	1
all_values[16]	auto[1]	auto[0]	143	1			T37	4		T38	4		T75	4
all_values[16]	auto[1]	auto[1]	60	1			T37	4		T38	4		T75	4
all_values[17]	auto[0]	auto[0]	23747	1			T43	2		T44	2		T45	2
all_values[17]	auto[0]	auto[1]	56368	1			T1	5		T2	3		T3	3
all_values[17]	auto[1]	auto[0]	99	1			T64	1		T228	1		T231	4
all_values[17]	auto[1]	auto[1]	51	1			T64	1		T228	2		T229	1