Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111586

1

T1

1

T2

1

T3

1

auto[1]

45236

1

T2

1

T29

1

T30

8

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	29123	1			T30	2		T38	1		T90	1
max_len_m1	905	1			T37	1		T18	1		T22	3
max_len_m2	952	1			T77	1		T322	2		T17	1
max_len_m3	818	1			T18	1		T22	2		T4	4
five	1097	1			T38	1		T21	2		T22	1
four	1096	1			T30	2		T22	3		T4	4
three	776	1			T37	1		T113	1		T105	5
one	856	1			T22	2		T168	2		T105	13
zero	11496	1			T3	1		T29	1		T30	4

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23640	1			T30	1		T38	1		T90	1
max_len	auto[1]	5483	1			T30	1		T39	1		T4	3
max_len_m1	auto[0]	592	1			T37	1		T18	1		T22	3
max_len_m1	auto[1]	313	1			T4	1		T5	2		T112	1
max_len_m2	auto[0]	644	1			T77	1		T322	1		T17	1
max_len_m2	auto[1]	308	1			T322	1		T4	2		T70	1
max_len_m3	auto[0]	544	1			T18	1		T22	2		T4	2
max_len_m3	auto[1]	274	1			T4	2		T112	1		T6	2
five	auto[0]	564	1			T38	1		T21	1		T22	1
five	auto[1]	533	1			T21	1		T105	2		T520	1
four	auto[0]	585	1			T30	1		T22	3		T4	2
four	auto[1]	511	1			T30	1		T4	2		T70	2
three	auto[0]	367	1			T37	1		T113	1		T105	3
three	auto[1]	409	1			T105	2		T521	1		T522	1
one	auto[0]	371	1			T22	2		T168	1		T105	5
one	auto[1]	485	1			T168	1		T105	8		T519	2
zero	auto[0]	557	1			T3	1		T31	1		T37	1
zero	auto[1]	10939	1			T29	1		T30	4		T31	1