Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.95	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	24	72	75.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	24	72	75.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69513

1

T1

1

T2

1

T30

8

auto[1]

77223

1

T2

2

T29

2

T30

15

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	11218	1			T30	3		T31	3		T33	3
endpoints[0x1]	10892	1			T2	3		T31	3		T34	1
endpoints[0x2]	15144	1			T1	1		T30	2		T31	3
endpoints[0x3]	12190	1			T29	2		T30	1		T31	3
endpoints[0x4]	13163	1			T30	1		T31	3		T46	1
endpoints[0x5]	12775	1			T31	3		T76	1		T77	2
endpoints[0x6]	9414	1			T30	1		T31	3		T39	3
endpoints[0x7]	13324	1			T30	3		T31	3		T111	21
endpoints[0x8]	11493	1			T30	2		T31	3		T75	11
endpoints[0x9]	12621	1			T31	3		T36	3		T307	1
endpoints[0xa]	12753	1			T30	4		T31	3		T81	1
endpoints[0xb]	11749	1			T30	6		T31	3		T308	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	184	1			T30	4		T112	3		T116	7
ack	38004	1			T2	1		T29	1		T30	3
data1	50265	1			T30	9		T37	5		T38	5
data0	58209	1			T1	1		T2	2		T29	1

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	24	72	75.00	24

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	[auto[0]]	*	--	--	24

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[1]	endpoints[0x0]	14	1			T30	1		T116	1		T309	1
nak	auto[1]	endpoints[0x1]	17	1			T112	1		T116	1		T310	1
nak	auto[1]	endpoints[0x2]	20	1			T112	1		T116	2		T311	1
nak	auto[1]	endpoints[0x3]	12	1			T116	1		T310	1		T312	1
nak	auto[1]	endpoints[0x4]	15	1			T311	1		T310	1		T312	2
nak	auto[1]	endpoints[0x5]	17	1			T313	1		T314	1		T310	1
nak	auto[1]	endpoints[0x6]	20	1			T112	1		T313	1		T315	2
nak	auto[1]	endpoints[0x7]	15	1			T311	1		T310	2		T316	1
nak	auto[1]	endpoints[0x8]	14	1			T316	3		T317	1		T318	1
nak	auto[1]	endpoints[0x9]	15	1			T313	2		T314	1		T319	1
nak	auto[1]	endpoints[0xa]	14	1			T30	1		T116	1		T312	2
nak	auto[1]	endpoints[0xb]	11	1			T30	2		T116	1		T310	1
ack	auto[1]	endpoints[0x0]	3073	1			T31	1		T33	1		T94	1
ack	auto[1]	endpoints[0x1]	3311	1			T2	1		T31	1		T21	1
ack	auto[1]	endpoints[0x2]	3321	1			T30	1		T31	1		T4	13
ack	auto[1]	endpoints[0x3]	2977	1			T29	1		T31	1		T168	1
ack	auto[1]	endpoints[0x4]	3224	1			T31	1		T40	5		T4	13
ack	auto[1]	endpoints[0x5]	3392	1			T31	1		T53	1		T93	1
ack	auto[1]	endpoints[0x6]	2833	1			T31	1		T39	1		T55	1
ack	auto[1]	endpoints[0x7]	3225	1			T30	1		T31	1		T111	8
ack	auto[1]	endpoints[0x8]	2980	1			T30	1		T31	1		T4	13
ack	auto[1]	endpoints[0x9]	2932	1			T31	1		T54	1		T168	1
ack	auto[1]	endpoints[0xa]	3377	1			T31	1		T20	1		T113	5
ack	auto[1]	endpoints[0xb]	3359	1			T31	1		T4	13		T168	1
data1	auto[0]	endpoints[0x0]	2018	1			T106	1		T169	3		T5	1
data1	auto[0]	endpoints[0x1]	1666	1			T18	4		T106	2		T5	1
data1	auto[0]	endpoints[0x2]	3747	1			T38	5		T98	9		T4	5
data1	auto[0]	endpoints[0x3]	2608	1			T5	1		T112	1		T105	13
data1	auto[0]	endpoints[0x4]	2891	1			T37	5		T4	6		T5	1
data1	auto[0]	endpoints[0x5]	2436	1			T77	1		T53	1		T93	1
data1	auto[0]	endpoints[0x6]	1324	1			T30	1		T55	1		T112	1
data1	auto[0]	endpoints[0x7]	2915	1			T30	1		T5	2		T70	4
data1	auto[0]	endpoints[0x8]	2333	1			T75	5		T4	6		T105	10
data1	auto[0]	endpoints[0x9]	2870	1			T54	1		T178	1		T105	9
data1	auto[0]	endpoints[0xa]	2482	1			T30	2		T20	1		T113	2
data1	auto[0]	endpoints[0xb]	2019	1			T4	6		T5	2		T180	1
data1	auto[1]	endpoints[0x0]	1728	1			T30	1		T106	1		T169	5
data1	auto[1]	endpoints[0x1]	1812	1			T106	2		T5	4		T112	1
data1	auto[1]	endpoints[0x2]	1830	1			T4	7		T5	3		T112	1
data1	auto[1]	endpoints[0x3]	1617	1			T30	1		T5	4		T105	7
data1	auto[1]	endpoints[0x4]	1740	1			T40	4		T4	6		T5	3
data1	auto[1]	endpoints[0x5]	1909	1			T53	1		T93	1		T70	4
data1	auto[1]	endpoints[0x6]	1550	1			T55	1		T105	14		T172	31
data1	auto[1]	endpoints[0x7]	1775	1			T30	1		T111	5		T5	3
data1	auto[1]	endpoints[0x8]	1638	1			T4	6		T112	1		T105	9
data1	auto[1]	endpoints[0x9]	1641	1			T54	1		T178	1		T105	6
data1	auto[1]	endpoints[0xa]	1869	1			T30	1		T20	1		T113	1
data1	auto[1]	endpoints[0xb]	1847	1			T30	1		T4	6		T5	2
data0	auto[0]	endpoints[0x0]	2930	1			T30	1		T31	1		T33	1
data0	auto[0]	endpoints[0x1]	2515	1			T2	1		T31	1		T34	1
data0	auto[0]	endpoints[0x2]	4615	1			T1	1		T31	1		T38	6
data0	auto[0]	endpoints[0x3]	3529	1			T31	1		T17	2		T168	1
data0	auto[0]	endpoints[0x4]	3738	1			T30	1		T31	1		T46	1
data0	auto[0]	endpoints[0x5]	3451	1			T31	1		T76	1		T77	1
data0	auto[0]	endpoints[0x6]	2318	1			T31	1		T39	1		T92	1
data0	auto[0]	endpoints[0x7]	3835	1			T31	1		T237	1		T168	1
data0	auto[0]	endpoints[0x8]	3119	1			T31	1		T75	6		T320	1
data0	auto[0]	endpoints[0x9]	3790	1			T31	1		T36	1		T307	1
data0	auto[0]	endpoints[0xa]	3383	1			T31	1		T123	1		T20	1
data0	auto[0]	endpoints[0xb]	2957	1			T30	2		T31	1		T308	1
data0	auto[1]	endpoints[0x0]	1451	1			T31	1		T33	1		T94	1
data0	auto[1]	endpoints[0x1]	1564	1			T2	1		T31	1		T21	1
data0	auto[1]	endpoints[0x2]	1609	1			T30	1		T31	1		T4	6
data0	auto[1]	endpoints[0x3]	1438	1			T29	1		T31	1		T168	1
data0	auto[1]	endpoints[0x4]	1551	1			T31	1		T40	3		T4	7
data0	auto[1]	endpoints[0x5]	1563	1			T31	1		T321	1		T322	1
data0	auto[1]	endpoints[0x6]	1362	1			T31	1		T39	1		T8	1
data0	auto[1]	endpoints[0x7]	1556	1			T31	1		T111	8		T168	1
data0	auto[1]	endpoints[0x8]	1404	1			T30	1		T31	1		T4	7
data0	auto[1]	endpoints[0x9]	1366	1			T31	1		T36	1		T168	1
data0	auto[1]	endpoints[0xa]	1614	1			T31	1		T113	4		T168	1
data0	auto[1]	endpoints[0xb]	1551	1			T30	1		T31	1		T4	7