Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8305 1 T43 4 T45 2 T117 1
auto[1] 53553 1 T2 1 T29 1 T30 8


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 54304 1 T2 1 T29 1 T30 8
auto[1] 7554 1 T45 3 T34 1 T110 1


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 55654 1 T2 1 T29 1 T30 8
auto[1] 6204 1 T43 4 T45 1 T32 1


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4604 1 T45 2 T358 2 T121 81
pkt_types[PidTypeInToken] 57254 1 T2 1 T29 1 T30 8


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1342 1 T121 13 T120 31 T122 40
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 806 1 T121 21 T343 2 T120 41
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 105 1 T45 1 T342 3 T374 2
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 9 1 T464 2 T381 1 T361 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1519 1 T45 1 T358 2 T121 47
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 723 1 T120 28 T122 20 T439 2
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 83 1 T131 1 T407 2 T345 5
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 17 1 T408 1 T360 1 T485 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 3630 1 T117 1 T358 2 T121 32
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 2328 1 T43 4 T121 49 T440 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 38 1 T406 2 T437 1 T383 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 47 1 T45 1 T375 1 T387 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 41724 1 T2 1 T29 1 T30 8
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2232 1 T32 1 T35 1 T17 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7213 1 T45 1 T34 1 T110 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 42 1 T434 1 T485 1 T372 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%