Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	80265	1			T1	5		T2	3		T3	3
all_pins[1]	80265	1			T1	5		T2	3		T3	3
all_pins[2]	80265	1			T1	5		T2	3		T3	3
all_pins[3]	80265	1			T1	5		T2	3		T3	3
all_pins[4]	80265	1			T1	5		T2	3		T3	3
all_pins[5]	80265	1			T1	5		T2	3		T3	3
all_pins[6]	80265	1			T1	5		T2	3		T3	3
all_pins[7]	80265	1			T1	5		T2	3		T3	3
all_pins[8]	80265	1			T1	5		T2	3		T3	3
all_pins[9]	80265	1			T1	5		T2	3		T3	3
all_pins[10]	80265	1			T1	5		T2	3		T3	3
all_pins[11]	80265	1			T1	5		T2	3		T3	3
all_pins[12]	80265	1			T1	5		T2	3		T3	3
all_pins[13]	80265	1			T1	5		T2	3		T3	3
all_pins[14]	80265	1			T1	5		T2	3		T3	3
all_pins[15]	80265	1			T1	5		T2	3		T3	3
all_pins[16]	80265	1			T1	5		T2	3		T3	3
all_pins[17]	80265	1			T1	5		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2566291	1			T1	159		T2	95		T3	95
values[0x1]	2189	1			T1	1		T2	1		T3	1
transitions[0x0=>0x1]	1920	1			T1	1		T2	1		T3	1
transitions[0x1=>0x0]	1920	1			T1	1		T2	1		T3	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	80171	1			T1	5		T2	3		T3	3
all_pins[0]	values[0x1]	94	1			T308	1		T340	1		T341	1
all_pins[0]	transitions[0x0=>0x1]	82	1			T308	1		T340	1		T341	1
all_pins[0]	transitions[0x1=>0x0]	884	1			T2	1		T31	12		T33	1
all_pins[1]	values[0x0]	79369	1			T1	5		T2	2		T3	3
all_pins[1]	values[0x1]	896	1			T2	1		T31	12		T33	1
all_pins[1]	transitions[0x0=>0x1]	879	1			T2	1		T31	12		T33	1
all_pins[1]	transitions[0x1=>0x0]	91	1			T42	1		T68	1		T69	1
all_pins[2]	values[0x0]	80157	1			T1	5		T2	3		T3	3
all_pins[2]	values[0x1]	108	1			T42	1		T68	1		T69	1
all_pins[2]	transitions[0x0=>0x1]	91	1			T42	1		T68	1		T69	1
all_pins[2]	transitions[0x1=>0x0]	56	1			T22	1		T228	2		T231	3
all_pins[3]	values[0x0]	80192	1			T1	5		T2	3		T3	3
all_pins[3]	values[0x1]	73	1			T22	1		T228	3		T231	3
all_pins[3]	transitions[0x0=>0x1]	51	1			T22	1		T228	3		T231	2
all_pins[3]	transitions[0x1=>0x0]	40	1			T52	1		T228	1		T330	1
all_pins[4]	values[0x0]	80203	1			T1	5		T2	3		T3	3
all_pins[4]	values[0x1]	62	1			T52	1		T228	1		T231	1
all_pins[4]	transitions[0x0=>0x1]	43	1			T52	1		T231	1		T332	5
all_pins[4]	transitions[0x1=>0x0]	51	1			T229	1		T231	3		T330	1
all_pins[5]	values[0x0]	80195	1			T1	5		T2	3		T3	3
all_pins[5]	values[0x1]	70	1			T228	1		T229	1		T231	3
all_pins[5]	transitions[0x0=>0x1]	51	1			T228	1		T229	1		T231	1
all_pins[5]	transitions[0x1=>0x0]	90	1			T72	1		T73	1		T74	1
all_pins[6]	values[0x0]	80156	1			T1	5		T2	3		T3	3
all_pins[6]	values[0x1]	109	1			T72	1		T73	1		T74	1
all_pins[6]	transitions[0x0=>0x1]	95	1			T72	1		T73	1		T74	1
all_pins[6]	transitions[0x1=>0x0]	44	1			T1	1		T56	1		T57	1
all_pins[7]	values[0x0]	80207	1			T1	4		T2	3		T3	3
all_pins[7]	values[0x1]	58	1			T1	1		T56	1		T57	1
all_pins[7]	transitions[0x0=>0x1]	39	1			T1	1		T56	1		T57	1
all_pins[7]	transitions[0x1=>0x0]	64	1			T58	1		T61	1		T63	1
all_pins[8]	values[0x0]	80182	1			T1	5		T2	3		T3	3
all_pins[8]	values[0x1]	83	1			T58	1		T61	1		T63	1
all_pins[8]	transitions[0x0=>0x1]	65	1			T58	1		T61	1		T63	1
all_pins[8]	transitions[0x1=>0x0]	53	1			T66	2		T23	2		T67	2
all_pins[9]	values[0x0]	80194	1			T1	5		T2	3		T3	3
all_pins[9]	values[0x1]	71	1			T66	2		T23	2		T67	2
all_pins[9]	transitions[0x0=>0x1]	56	1			T66	2		T23	2		T67	2
all_pins[9]	transitions[0x1=>0x0]	35	1			T231	1		T332	1		T331	3
all_pins[10]	values[0x0]	80215	1			T1	5		T2	3		T3	3
all_pins[10]	values[0x1]	50	1			T231	3		T332	3		T333	1
all_pins[10]	transitions[0x0=>0x1]	34	1			T231	1		T332	1		T333	1
all_pins[10]	transitions[0x1=>0x0]	98	1			T78	1		T79	1		T80	1
all_pins[11]	values[0x0]	80151	1			T1	5		T2	3		T3	3
all_pins[11]	values[0x1]	114	1			T78	1		T79	1		T80	1
all_pins[11]	transitions[0x0=>0x1]	99	1			T78	1		T79	1		T80	1
all_pins[11]	transitions[0x1=>0x0]	47	1			T81	1		T82	1		T84	1
all_pins[12]	values[0x0]	80203	1			T1	5		T2	3		T3	3
all_pins[12]	values[0x1]	62	1			T81	1		T82	1		T84	1
all_pins[12]	transitions[0x0=>0x1]	46	1			T81	1		T82	1		T84	1
all_pins[12]	transitions[0x1=>0x0]	98	1			T3	1		T87	1		T88	1
all_pins[13]	values[0x0]	80151	1			T1	5		T2	3		T3	2
all_pins[13]	values[0x1]	114	1			T3	1		T87	1		T88	1
all_pins[13]	transitions[0x0=>0x1]	102	1			T3	1		T87	1		T88	1
all_pins[13]	transitions[0x1=>0x0]	36	1			T228	1		T332	1		T331	2
all_pins[14]	values[0x0]	80217	1			T1	5		T2	3		T3	3
all_pins[14]	values[0x1]	48	1			T228	1		T231	1		T330	1
all_pins[14]	transitions[0x0=>0x1]	35	1			T228	1		T231	1		T330	1
all_pins[14]	transitions[0x1=>0x0]	53	1			T228	3		T229	4		T330	2
all_pins[15]	values[0x0]	80199	1			T1	5		T2	3		T3	3
all_pins[15]	values[0x1]	66	1			T228	3		T229	4		T330	2
all_pins[15]	transitions[0x0=>0x1]	53	1			T228	3		T229	3		T330	2
all_pins[15]	transitions[0x1=>0x0]	47	1			T37	4		T38	4		T75	4
all_pins[16]	values[0x0]	80205	1			T1	5		T2	3		T3	3
all_pins[16]	values[0x1]	60	1			T37	4		T38	4		T75	4
all_pins[16]	transitions[0x0=>0x1]	48	1			T37	4		T38	4		T75	4
all_pins[16]	transitions[0x1=>0x0]	39	1			T64	1		T228	2		T229	1
all_pins[17]	values[0x0]	80214	1			T1	5		T2	3		T3	3
all_pins[17]	values[0x1]	51	1			T64	1		T228	2		T229	1
all_pins[17]	transitions[0x0=>0x1]	51	1			T64	1		T228	2		T229	1