Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4678	1			T45	2		T117	1		T121	98
invalid_ep[0xd]	4790	1			T45	1		T121	77		T118	15
invalid_ep[0xe]	4732	1			T121	88		T118	11		T83	1
invalid_ep[0xf]	4771	1			T45	2		T121	87		T118	17
endpoints[0x0]	12554	1			T30	2		T43	2		T45	1
endpoints[0x1]	12224	1			T2	2		T43	3		T31	2
endpoints[0x2]	15924	1			T1	1		T30	1		T45	2
endpoints[0x3]	13266	1			T29	1		T30	1		T43	6
endpoints[0x4]	14453	1			T30	1		T45	1		T31	2
endpoints[0x5]	13852	1			T31	2		T76	1		T77	2
endpoints[0x6]	10476	1			T30	1		T43	3		T31	2
endpoints[0x7]	14493	1			T3	1		T30	2		T43	2
endpoints[0x8]	12995	1			T30	1		T31	2		T75	11
endpoints[0x9]	14281	1			T43	1		T45	1		T31	2
endpoints[0xa]	13536	1			T30	3		T45	3		T31	2
endpoints[0xb]	12237	1			T30	4		T43	1		T31	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	23265	1			T43	6		T45	3		T91	1
pkt_types[PidTypeOutToken]	76333	1			T1	1		T2	1		T3	1
pkt_types[PidTypeInToken]	61483	1			T2	1		T29	1		T30	8

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1036	1			T117	1		T121	25		T120	30
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1011	1			T121	24		T406	1		T120	27
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1058	1			T121	23		T120	37		T122	23
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1017	1			T121	25		T120	21		T122	18
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1568	1			T43	1		T18	1		T19	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1611	1			T43	2		T106	2		T117	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1529	1			T45	1		T4	5		T117	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1557	1			T17	1		T358	2		T5	4
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1568	1			T45	1		T91	1		T358	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1775	1			T53	1		T93	1		T121	20
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1550	1			T43	2		T55	1		T172	26
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1575	1			T43	1		T5	3		T121	29
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1577	1			T121	25		T175	24		T176	1
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1580	1			T54	1		T358	1		T178	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1651	1			T45	1		T123	1		T20	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1602	1			T58	8		T117	1		T358	2
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1553	1			T121	22		T118	13		T85	2
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1600	1			T121	15		T118	15		T83	2
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1640	1			T121	22		T118	11		T83	1
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1562	1			T121	21		T118	17		T83	3
pkt_types[PidTypeOutToken]	endpoints[0x0]	5037	1			T30	1		T43	1		T31	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	4274	1			T2	1		T31	1		T34	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	8458	1			T1	1		T31	1		T38	11
pkt_types[PidTypeOutToken]	endpoints[0x3]	6172	1			T43	3		T31	1		T17	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	6783	1			T30	1		T31	1		T46	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	5649	1			T31	1		T76	1		T77	2
pkt_types[PidTypeOutToken]	endpoints[0x6]	3592	1			T30	1		T31	1		T39	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	6991	1			T3	1		T30	1		T43	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	5621	1			T31	1		T75	11		T320	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	6718	1			T31	1		T36	1		T307	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	5809	1			T30	2		T45	1		T31	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	4874	1			T30	2		T31	1		T308	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1015	1			T45	1		T121	23		T406	1
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1092	1			T121	20		T120	35		T122	12
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1020	1			T121	20		T120	30		T122	14
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1102	1			T45	2		T121	20		T406	1
pkt_types[PidTypeInToken]	endpoints[0x0]	4768	1			T30	1		T45	1		T31	1
pkt_types[PidTypeInToken]	endpoints[0x1]	5196	1			T2	1		T31	1		T34	1
pkt_types[PidTypeInToken]	endpoints[0x2]	4774	1			T30	1		T45	1		T31	1
pkt_types[PidTypeInToken]	endpoints[0x3]	4383	1			T29	1		T30	1		T43	3
pkt_types[PidTypeInToken]	endpoints[0x4]	4956	1			T31	1		T40	7		T4	14
pkt_types[PidTypeInToken]	endpoints[0x5]	5316	1			T31	1		T53	1		T93	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4217	1			T43	1		T31	1		T39	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4781	1			T30	1		T31	1		T111	13
pkt_types[PidTypeInToken]	endpoints[0x8]	4618	1			T30	1		T31	1		T4	14
pkt_types[PidTypeInToken]	endpoints[0x9]	4787	1			T31	1		T36	1		T54	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4873	1			T30	1		T31	1		T20	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4585	1			T30	2		T43	1		T31	1