Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1			T228	7		T229	4		T231	4
all_values[1]	263	1			T228	7		T229	4		T231	4
all_values[2]	263	1			T228	7		T229	4		T231	4
all_values[3]	263	1			T228	7		T229	4		T231	4
all_values[4]	263	1			T228	7		T229	4		T231	4
all_values[5]	263	1			T228	7		T229	4		T231	4
all_values[6]	263	1			T228	7		T229	4		T231	4
all_values[7]	263	1			T228	7		T229	4		T231	4
all_values[8]	263	1			T228	7		T229	4		T231	4
all_values[9]	263	1			T228	7		T229	4		T231	4
all_values[10]	263	1			T228	7		T229	4		T231	4
all_values[11]	263	1			T228	7		T229	4		T231	4
all_values[12]	263	1			T228	7		T229	4		T231	4
all_values[13]	263	1			T228	7		T229	4		T231	4
all_values[14]	263	1			T228	7		T229	4		T231	4
all_values[15]	263	1			T228	7		T229	4		T231	4
all_values[16]	263	1			T228	7		T229	4		T231	4
all_values[17]	263	1			T228	7		T229	4		T231	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6291

1

T228

173

T229

88

T231

86

auto[1]

2125

1

T228

51

T229

40

T231

42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5792

1

T228

154

T229

89

T231

93

auto[1]

2624

1

T228

70

T229

39

T231

35

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5055

1

T228

135

T229

84

T231

76

auto[1]

3361

1

T228

89

T229

44

T231

52

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	104	1			T229	2		T231	3		T330	2
all_values[0]	auto[0]	auto[1]	auto[0]	51	1			T228	2		T229	1		T331	1
all_values[0]	auto[1]	auto[0]	auto[1]	67	1			T228	3		T229	1		T231	1
all_values[0]	auto[1]	auto[1]	auto[1]	41	1			T228	2		T330	3		T332	2
all_values[1]	auto[0]	auto[0]	auto[0]	86	1			T228	3		T231	1		T330	2
all_values[1]	auto[0]	auto[1]	auto[0]	65	1			T228	1		T229	3		T231	2
all_values[1]	auto[1]	auto[0]	auto[1]	67	1			T228	2		T229	1		T231	1
all_values[1]	auto[1]	auto[1]	auto[1]	45	1			T228	1		T330	1		T332	1
all_values[2]	auto[0]	auto[0]	auto[0]	54	1			T332	5		T333	2		T331	2
all_values[2]	auto[0]	auto[0]	auto[1]	34	1			T228	4		T229	1		T334	1
all_values[2]	auto[0]	auto[1]	auto[0]	41	1			T231	4		T332	1		T331	2
all_values[2]	auto[0]	auto[1]	auto[1]	34	1			T229	1		T330	2		T334	1
all_values[2]	auto[1]	auto[0]	auto[1]	57	1			T228	2		T330	1		T332	1
all_values[2]	auto[1]	auto[1]	auto[1]	43	1			T228	1		T229	2		T330	4
all_values[3]	auto[0]	auto[0]	auto[0]	57	1			T229	2		T330	1		T333	1
all_values[3]	auto[0]	auto[0]	auto[1]	23	1			T332	1		T334	2		T335	1
all_values[3]	auto[0]	auto[1]	auto[0]	39	1			T330	1		T336	3		T335	1
all_values[3]	auto[0]	auto[1]	auto[1]	29	1			T228	1		T231	1		T330	1
all_values[3]	auto[1]	auto[0]	auto[1]	61	1			T228	4		T229	2		T332	1
all_values[3]	auto[1]	auto[1]	auto[1]	54	1			T228	2		T231	3		T330	4
all_values[4]	auto[0]	auto[0]	auto[0]	53	1			T228	2		T229	1		T330	2
all_values[4]	auto[0]	auto[0]	auto[1]	21	1			T229	1		T330	1		T333	1
all_values[4]	auto[0]	auto[1]	auto[0]	52	1			T228	3		T231	2		T330	2
all_values[4]	auto[0]	auto[1]	auto[1]	29	1			T330	1		T332	2		T333	1
all_values[4]	auto[1]	auto[0]	auto[1]	55	1			T228	1		T229	2		T330	1
all_values[4]	auto[1]	auto[1]	auto[1]	53	1			T228	1		T231	2		T332	3
all_values[5]	auto[0]	auto[0]	auto[0]	59	1			T228	1		T231	1		T330	2
all_values[5]	auto[0]	auto[0]	auto[1]	32	1			T228	2		T330	2		T333	1
all_values[5]	auto[0]	auto[1]	auto[0]	30	1			T228	2		T229	1		T332	2
all_values[5]	auto[0]	auto[1]	auto[1]	32	1			T231	2		T330	1		T331	1
all_values[5]	auto[1]	auto[0]	auto[1]	62	1			T228	1		T229	2		T231	1
all_values[5]	auto[1]	auto[1]	auto[1]	48	1			T228	1		T229	1		T330	1
all_values[6]	auto[0]	auto[0]	auto[0]	53	1			T228	2		T229	1		T332	2
all_values[6]	auto[0]	auto[0]	auto[1]	27	1			T330	1		T337	1		T338	1
all_values[6]	auto[0]	auto[1]	auto[0]	48	1			T228	1		T229	3		T332	1
all_values[6]	auto[0]	auto[1]	auto[1]	29	1			T228	1		T231	2		T330	3
all_values[6]	auto[1]	auto[0]	auto[1]	69	1			T228	1		T231	2		T330	1
all_values[6]	auto[1]	auto[1]	auto[1]	37	1			T228	2		T330	2		T332	1
all_values[7]	auto[0]	auto[0]	auto[0]	81	1			T228	4		T229	1		T330	1
all_values[7]	auto[0]	auto[1]	auto[0]	78	1			T228	1		T231	2		T330	3
all_values[7]	auto[1]	auto[0]	auto[1]	52	1			T228	2		T229	1		T330	1
all_values[7]	auto[1]	auto[1]	auto[1]	52	1			T229	2		T231	2		T330	2
all_values[8]	auto[0]	auto[0]	auto[0]	83	1			T228	1		T229	3		T231	2
all_values[8]	auto[0]	auto[1]	auto[0]	72	1			T228	3		T229	1		T332	1
all_values[8]	auto[1]	auto[0]	auto[1]	51	1			T228	1		T231	2		T332	3
all_values[8]	auto[1]	auto[1]	auto[1]	57	1			T228	2		T330	4		T332	1
all_values[9]	auto[0]	auto[0]	auto[0]	48	1			T231	1		T332	1		T331	1
all_values[9]	auto[0]	auto[0]	auto[1]	37	1			T228	2		T229	1		T330	3
all_values[9]	auto[0]	auto[1]	auto[0]	40	1			T228	1		T229	1		T330	1
all_values[9]	auto[0]	auto[1]	auto[1]	29	1			T228	1		T229	1		T231	1
all_values[9]	auto[1]	auto[0]	auto[1]	65	1			T228	2		T231	1		T330	2
all_values[9]	auto[1]	auto[1]	auto[1]	44	1			T228	1		T229	1		T231	1
all_values[10]	auto[0]	auto[0]	auto[0]	59	1			T228	3		T330	1		T332	1
all_values[10]	auto[0]	auto[0]	auto[1]	31	1			T228	1		T229	1		T330	1
all_values[10]	auto[0]	auto[1]	auto[0]	46	1			T229	2		T231	1		T330	4
all_values[10]	auto[0]	auto[1]	auto[1]	26	1			T231	1		T332	1		T331	3
all_values[10]	auto[1]	auto[0]	auto[1]	56	1			T228	3		T229	1		T332	3
all_values[10]	auto[1]	auto[1]	auto[1]	45	1			T231	2		T330	1		T332	2
all_values[11]	auto[0]	auto[0]	auto[0]	53	1			T231	2		T330	1		T331	1
all_values[11]	auto[0]	auto[0]	auto[1]	24	1			T228	1		T332	2		T333	1
all_values[11]	auto[0]	auto[1]	auto[0]	52	1			T228	1		T330	2		T331	1
all_values[11]	auto[0]	auto[1]	auto[1]	30	1			T228	3		T229	1		T231	1
all_values[11]	auto[1]	auto[0]	auto[1]	60	1			T228	1		T229	1		T332	1
all_values[11]	auto[1]	auto[1]	auto[1]	44	1			T228	1		T229	2		T231	1
all_values[12]	auto[0]	auto[0]	auto[0]	56	1			T228	5		T231	2		T330	1
all_values[12]	auto[0]	auto[0]	auto[1]	28	1			T333	1		T331	1		T334	1
all_values[12]	auto[0]	auto[1]	auto[0]	48	1			T229	3		T231	2		T330	1
all_values[12]	auto[0]	auto[1]	auto[1]	31	1			T330	2		T332	1		T331	1
all_values[12]	auto[1]	auto[0]	auto[1]	60	1			T228	2		T229	1		T330	2
all_values[12]	auto[1]	auto[1]	auto[1]	40	1			T330	1		T332	1		T331	1
all_values[13]	auto[0]	auto[0]	auto[0]	54	1			T228	2		T231	2		T333	1
all_values[13]	auto[0]	auto[0]	auto[1]	33	1			T228	1		T332	1		T331	1
all_values[13]	auto[0]	auto[1]	auto[0]	46	1			T228	1		T229	1		T330	3
all_values[13]	auto[0]	auto[1]	auto[1]	24	1			T231	1		T330	2		T332	1
all_values[13]	auto[1]	auto[0]	auto[1]	56	1			T228	2		T330	1		T332	2
all_values[13]	auto[1]	auto[1]	auto[1]	50	1			T228	1		T229	3		T231	1
all_values[14]	auto[0]	auto[0]	auto[0]	65	1			T228	2		T229	2		T231	1
all_values[14]	auto[0]	auto[0]	auto[1]	26	1			T330	1		T333	2		T339	1
all_values[14]	auto[0]	auto[1]	auto[0]	55	1			T228	2		T229	2		T231	2
all_values[14]	auto[0]	auto[1]	auto[1]	17	1			T332	2		T331	1		T334	1
all_values[14]	auto[1]	auto[0]	auto[1]	60	1			T228	2		T231	1		T330	2
all_values[14]	auto[1]	auto[1]	auto[1]	40	1			T228	1		T330	1		T331	1
all_values[15]	auto[0]	auto[0]	auto[0]	65	1			T228	1		T330	1		T332	3
all_values[15]	auto[0]	auto[0]	auto[1]	28	1			T228	1		T231	2		T330	1
all_values[15]	auto[0]	auto[1]	auto[0]	43	1			T228	1		T332	3		T333	1
all_values[15]	auto[0]	auto[1]	auto[1]	27	1			T228	2		T229	1		T330	1
all_values[15]	auto[1]	auto[0]	auto[1]	58	1			T228	1		T231	2		T330	4
all_values[15]	auto[1]	auto[1]	auto[1]	42	1			T228	1		T229	3		T334	1
all_values[16]	auto[0]	auto[0]	auto[0]	62	1			T228	2		T330	1		T332	3
all_values[16]	auto[0]	auto[0]	auto[1]	19	1			T330	1		T333	1		T339	2
all_values[16]	auto[0]	auto[1]	auto[0]	63	1			T228	4		T229	1		T231	3
all_values[16]	auto[0]	auto[1]	auto[1]	24	1			T229	1		T332	2		T333	2
all_values[16]	auto[1]	auto[0]	auto[1]	48	1			T229	1		T330	1		T332	1
all_values[16]	auto[1]	auto[1]	auto[1]	47	1			T228	1		T229	1		T231	1
all_values[17]	auto[0]	auto[0]	auto[0]	83	1			T228	4		T229	2		T231	2
all_values[17]	auto[0]	auto[1]	auto[0]	66	1			T228	1		T231	2		T330	1
all_values[17]	auto[1]	auto[0]	auto[1]	67	1			T228	1		T229	1		T330	4
all_values[17]	auto[1]	auto[1]	auto[1]	47	1			T228	1		T229	1		T332	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal