| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.30 | 98.11 | 95.91 | 97.44 | 93.22 | 98.30 | 98.17 | 92.94 |
| T3568 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/499.usbdev_tx_rx_disruption.269761197 | Aug 21 08:07:37 AM UTC 24 | Aug 21 08:07:41 AM UTC 24 | 485541228 ps | ||
| T3569 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/449.usbdev_tx_rx_disruption.1865770837 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:41 AM UTC 24 | 469946065 ps | ||
| T3570 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/453.usbdev_tx_rx_disruption.2182199883 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:41 AM UTC 24 | 499162081 ps | ||
| T3571 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/375.usbdev_tx_rx_disruption.3886502585 | Aug 21 08:07:02 AM UTC 24 | Aug 21 08:07:41 AM UTC 24 | 530517931 ps | ||
| T3572 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/447.usbdev_tx_rx_disruption.3425638585 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:41 AM UTC 24 | 591659966 ps | ||
| T3573 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/448.usbdev_tx_rx_disruption.348635479 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:41 AM UTC 24 | 615375557 ps | ||
| T3574 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/425.usbdev_tx_rx_disruption.2017207889 | Aug 21 08:07:18 AM UTC 24 | Aug 21 08:07:41 AM UTC 24 | 511475764 ps | ||
| T3575 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/374.usbdev_tx_rx_disruption.3488122196 | Aug 21 08:07:02 AM UTC 24 | Aug 21 08:07:41 AM UTC 24 | 522390772 ps | ||
| T3576 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/459.usbdev_tx_rx_disruption.3943266789 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:41 AM UTC 24 | 422410911 ps | ||
| T3577 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/458.usbdev_tx_rx_disruption.2366677570 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:41 AM UTC 24 | 508447182 ps | ||
| T3578 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/431.usbdev_tx_rx_disruption.1781156763 | Aug 21 08:07:19 AM UTC 24 | Aug 21 08:07:42 AM UTC 24 | 423584758 ps | ||
| T3579 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/430.usbdev_tx_rx_disruption.2326912066 | Aug 21 08:07:19 AM UTC 24 | Aug 21 08:07:42 AM UTC 24 | 443228237 ps | ||
| T3580 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/428.usbdev_tx_rx_disruption.2536573479 | Aug 21 08:07:19 AM UTC 24 | Aug 21 08:07:42 AM UTC 24 | 567160960 ps | ||
| T3581 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/461.usbdev_tx_rx_disruption.1808921752 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:42 AM UTC 24 | 446179684 ps | ||
| T3582 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/456.usbdev_tx_rx_disruption.2652684939 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:42 AM UTC 24 | 517807790 ps | ||
| T3583 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/451.usbdev_tx_rx_disruption.204959187 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:42 AM UTC 24 | 630270078 ps | ||
| T3584 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/452.usbdev_tx_rx_disruption.1243955726 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:42 AM UTC 24 | 619133807 ps | ||
| T3585 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/454.usbdev_tx_rx_disruption.3344059497 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:42 AM UTC 24 | 515974955 ps | ||
| T3586 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/427.usbdev_tx_rx_disruption.2164720613 | Aug 21 08:07:19 AM UTC 24 | Aug 21 08:07:42 AM UTC 24 | 534369158 ps | ||
| T3587 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/460.usbdev_tx_rx_disruption.2721680655 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:42 AM UTC 24 | 540334142 ps | ||
| T3588 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/457.usbdev_tx_rx_disruption.2416950355 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:42 AM UTC 24 | 640148932 ps | ||
| T3589 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/429.usbdev_tx_rx_disruption.3426220436 | Aug 21 08:07:19 AM UTC 24 | Aug 21 08:07:42 AM UTC 24 | 612333079 ps | ||
| T3590 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/455.usbdev_tx_rx_disruption.2430454812 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:42 AM UTC 24 | 701248732 ps | ||
| T3591 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/486.usbdev_tx_rx_disruption.1314550065 | Aug 21 08:07:33 AM UTC 24 | Aug 21 08:07:45 AM UTC 24 | 494497463 ps | ||
| T3592 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/489.usbdev_tx_rx_disruption.1544720798 | Aug 21 08:07:33 AM UTC 24 | Aug 21 08:07:45 AM UTC 24 | 462346824 ps | ||
| T3593 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/488.usbdev_tx_rx_disruption.2502051833 | Aug 21 08:07:33 AM UTC 24 | Aug 21 08:07:45 AM UTC 24 | 530130977 ps | ||
| T3594 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/490.usbdev_tx_rx_disruption.3125863274 | Aug 21 08:07:33 AM UTC 24 | Aug 21 08:07:45 AM UTC 24 | 485851608 ps | ||
| T3595 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/487.usbdev_tx_rx_disruption.2180696641 | Aug 21 08:07:33 AM UTC 24 | Aug 21 08:07:45 AM UTC 24 | 630051713 ps | ||
| T3596 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/478.usbdev_tx_rx_disruption.894051573 | Aug 21 08:07:32 AM UTC 24 | Aug 21 08:07:46 AM UTC 24 | 475324992 ps | ||
| T3597 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/469.usbdev_tx_rx_disruption.131152688 | Aug 21 08:07:30 AM UTC 24 | Aug 21 08:07:46 AM UTC 24 | 568230281 ps | ||
| T3598 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/474.usbdev_tx_rx_disruption.3110149884 | Aug 21 08:07:32 AM UTC 24 | Aug 21 08:07:46 AM UTC 24 | 539470124 ps | ||
| T3599 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/480.usbdev_tx_rx_disruption.2839897653 | Aug 21 08:07:32 AM UTC 24 | Aug 21 08:07:46 AM UTC 24 | 518259109 ps | ||
| T3600 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/464.usbdev_tx_rx_disruption.3224159300 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:52 AM UTC 24 | 529596458 ps | ||
| T3601 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/462.usbdev_tx_rx_disruption.1842360312 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:52 AM UTC 24 | 554331225 ps | ||
| T3602 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/466.usbdev_tx_rx_disruption.1161158612 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:52 AM UTC 24 | 623139949 ps | ||
| T3603 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/465.usbdev_tx_rx_disruption.4215819369 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:52 AM UTC 24 | 539805166 ps | ||
| T3604 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/467.usbdev_tx_rx_disruption.2940176973 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:52 AM UTC 24 | 506806296 ps | ||
| T3605 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/463.usbdev_tx_rx_disruption.2052294274 | Aug 21 08:07:29 AM UTC 24 | Aug 21 08:07:52 AM UTC 24 | 603908473 ps | ||
| T3606 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/473.usbdev_tx_rx_disruption.3043594793 | Aug 21 08:07:30 AM UTC 24 | Aug 21 08:07:53 AM UTC 24 | 550223442 ps | ||
| T3607 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/477.usbdev_tx_rx_disruption.272035994 | Aug 21 08:07:32 AM UTC 24 | Aug 21 08:07:53 AM UTC 24 | 430157675 ps | ||
| T3608 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/479.usbdev_tx_rx_disruption.1627642178 | Aug 21 08:07:32 AM UTC 24 | Aug 21 08:07:53 AM UTC 24 | 486509278 ps | ||
| T3609 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/481.usbdev_tx_rx_disruption.3196989932 | Aug 21 08:07:32 AM UTC 24 | Aug 21 08:07:53 AM UTC 24 | 501462504 ps | ||
| T3610 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/470.usbdev_tx_rx_disruption.3839591777 | Aug 21 08:07:30 AM UTC 24 | Aug 21 08:07:53 AM UTC 24 | 583907522 ps | ||
| T3611 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/491.usbdev_tx_rx_disruption.3148430318 | Aug 21 08:07:33 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 466434284 ps | ||
| T3612 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/484.usbdev_tx_rx_disruption.80589371 | Aug 21 08:07:32 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 511603614 ps | ||
| T3613 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/493.usbdev_tx_rx_disruption.3909045743 | Aug 21 08:07:33 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 470011237 ps | ||
| T3614 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/495.usbdev_tx_rx_disruption.66272164 | Aug 21 08:07:33 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 464670668 ps | ||
| T3615 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/482.usbdev_tx_rx_disruption.3634862343 | Aug 21 08:07:32 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 554303215 ps | ||
| T3616 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/492.usbdev_tx_rx_disruption.1497963015 | Aug 21 08:07:33 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 565744120 ps | ||
| T3617 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/485.usbdev_tx_rx_disruption.1855456463 | Aug 21 08:07:33 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 568252778 ps | ||
| T3618 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/497.usbdev_tx_rx_disruption.1118794252 | Aug 21 08:07:34 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 466114604 ps | ||
| T3619 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/494.usbdev_tx_rx_disruption.2726580426 | Aug 21 08:07:33 AM UTC 24 | Aug 21 08:07:57 AM UTC 24 | 670956831 ps | ||
| T3620 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/496.usbdev_tx_rx_disruption.2658063805 | Aug 21 08:07:34 AM UTC 24 | Aug 21 08:07:57 AM UTC 24 | 639977919 ps | ||
| T228 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.369509414 | Aug 21 08:07:37 AM UTC 24 | Aug 21 08:07:40 AM UTC 24 | 33253778 ps | ||
| T274 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.3465109775 | Aug 21 08:07:37 AM UTC 24 | Aug 21 08:07:41 AM UTC 24 | 114195481 ps | ||
| T223 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.3386826892 | Aug 21 08:07:37 AM UTC 24 | Aug 21 08:07:41 AM UTC 24 | 154693029 ps | ||
| T3621 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.3695715521 | Aug 21 08:07:37 AM UTC 24 | Aug 21 08:07:41 AM UTC 24 | 270137495 ps | ||
| T224 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.3024208403 | Aug 21 08:07:37 AM UTC 24 | Aug 21 08:07:44 AM UTC 24 | 1267215467 ps | ||
| T229 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.1590101570 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:45 AM UTC 24 | 31938384 ps | ||
| T225 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2331813266 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:45 AM UTC 24 | 93636556 ps | ||
| T264 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.564319927 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:45 AM UTC 24 | 65106283 ps | ||
| T232 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3042277568 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:45 AM UTC 24 | 208379593 ps | ||
| T244 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.3703497014 | Aug 21 08:07:40 AM UTC 24 | Aug 21 08:07:46 AM UTC 24 | 45676501 ps | ||
| T245 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3014505317 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:46 AM UTC 24 | 178438443 ps | ||
| T286 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3877667513 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:46 AM UTC 24 | 125342990 ps | ||
| T242 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.226266860 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:46 AM UTC 24 | 76247379 ps | ||
| T266 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.156903292 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:46 AM UTC 24 | 78375442 ps | ||
| T275 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.3620347729 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:46 AM UTC 24 | 206085772 ps | ||
| T243 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.4104509739 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:47 AM UTC 24 | 725158650 ps | ||
| T250 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_errors.3274727415 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:47 AM UTC 24 | 98782081 ps | ||
| T276 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.3362606121 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:47 AM UTC 24 | 133980187 ps | ||
| T3622 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.1798524176 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:48 AM UTC 24 | 215562902 ps | ||
| T249 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_intg_err.1420587438 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:48 AM UTC 24 | 586093494 ps | ||
| T231 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_intr_test.3782128984 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:50 AM UTC 24 | 29360812 ps | ||
| T277 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_rw.4166035310 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:50 AM UTC 24 | 107588185 ps | ||
| T278 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_rw.3014159708 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:50 AM UTC 24 | 45562036 ps | ||
| T3623 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3458459293 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:50 AM UTC 24 | 148187469 ps | ||
| T230 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_hw_reset.38757789 | Aug 21 08:07:45 AM UTC 24 | Aug 21 08:07:50 AM UTC 24 | 109892901 ps | ||
| T287 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2455611665 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:50 AM UTC 24 | 112077385 ps | ||
| T288 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2289463694 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:50 AM UTC 24 | 94258628 ps | ||
| T330 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_intr_test.3802180837 | Aug 21 08:07:49 AM UTC 24 | Aug 21 08:07:50 AM UTC 24 | 43507273 ps | ||
| T289 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_rw.1285980195 | Aug 21 08:07:49 AM UTC 24 | Aug 21 08:07:50 AM UTC 24 | 77171383 ps | ||
| T3624 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1655156835 | Aug 21 08:07:49 AM UTC 24 | Aug 21 08:07:51 AM UTC 24 | 67161105 ps | ||
| T279 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_partial_access.2399152409 | Aug 21 08:07:45 AM UTC 24 | Aug 21 08:07:51 AM UTC 24 | 82722442 ps | ||
| T259 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1728273785 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:51 AM UTC 24 | 202379633 ps | ||
| T254 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_errors.3617722998 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:51 AM UTC 24 | 98425154 ps | ||
| T3625 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_aliasing.1944648581 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:51 AM UTC 24 | 236981482 ps | ||
| T258 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.123216121 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:51 AM UTC 24 | 211503605 ps | ||
| T262 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1943666493 | Aug 21 08:07:49 AM UTC 24 | Aug 21 08:07:51 AM UTC 24 | 94912970 ps | ||
| T497 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_intg_err.3569610553 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:51 AM UTC 24 | 469192055 ps | ||
| T280 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_partial_access.2854428208 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:51 AM UTC 24 | 193312549 ps | ||
| T281 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_aliasing.975176832 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:51 AM UTC 24 | 197118266 ps | ||
| T257 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_errors.1270928766 | Aug 21 08:07:49 AM UTC 24 | Aug 21 08:07:52 AM UTC 24 | 166429285 ps | ||
| T3626 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_walk.1443940203 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:52 AM UTC 24 | 382394442 ps | ||
| T282 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3775318557 | Aug 21 08:07:42 AM UTC 24 | Aug 21 08:07:52 AM UTC 24 | 1568463405 ps | ||
| T498 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_intg_err.1175773577 | Aug 21 08:07:49 AM UTC 24 | Aug 21 08:07:52 AM UTC 24 | 358695122 ps | ||
| T3627 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2795300666 | Aug 21 08:07:40 AM UTC 24 | Aug 21 08:07:52 AM UTC 24 | 55066775 ps | ||
| T255 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_errors.1713861133 | Aug 21 08:07:49 AM UTC 24 | Aug 21 08:07:53 AM UTC 24 | 297451328 ps | ||
| T283 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3221764269 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:53 AM UTC 24 | 712650669 ps | ||
| T332 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_intr_test.4212294410 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:55 AM UTC 24 | 31481799 ps | ||
| T333 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.2682700605 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:55 AM UTC 24 | 32663699 ps | ||
| T293 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.517303135 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:55 AM UTC 24 | 53193087 ps | ||
| T3628 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_rw.2976688027 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:55 AM UTC 24 | 71416035 ps | ||
| T284 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.3586161858 | Aug 21 08:07:41 AM UTC 24 | Aug 21 08:07:55 AM UTC 24 | 346255989 ps | ||
| T3629 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2221827502 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:55 AM UTC 24 | 129459608 ps | ||
| T331 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.3517954544 | Aug 21 08:07:56 AM UTC 24 | Aug 21 08:08:05 AM UTC 24 | 53551182 ps | ||
| T3630 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1335570304 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:55 AM UTC 24 | 185997756 ps | ||
| T3631 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.221398253 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 120275315 ps | ||
| T256 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_tl_errors.3910724648 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 155492117 ps | ||
| T334 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_intr_test.3880362636 | Aug 21 08:07:44 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 54457695 ps | ||
| T294 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2176853550 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 227842947 ps | ||
| T336 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_intr_test.3403338092 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 44629562 ps | ||
| T3632 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_rw.1441386871 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 55258639 ps | ||
| T263 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.518051928 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 75688196 ps | ||
| T3633 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2292266370 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 555503695 ps | ||
| T3634 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_tl_intg_err.2546624938 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:56 AM UTC 24 | 377587480 ps | ||
| T3635 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1374841948 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:57 AM UTC 24 | 109104818 ps | ||
| T260 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_errors.822284711 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:57 AM UTC 24 | 143876135 ps | ||
| T3636 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2970631354 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:57 AM UTC 24 | 155434993 ps | ||
| T285 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2932443444 | Aug 21 08:07:47 AM UTC 24 | Aug 21 08:07:57 AM UTC 24 | 780577275 ps | ||
| T3637 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_walk.4128045382 | Aug 21 08:07:44 AM UTC 24 | Aug 21 08:07:57 AM UTC 24 | 326855435 ps | ||
| T3638 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_partial_access.1587778309 | Aug 21 08:07:44 AM UTC 24 | Aug 21 08:07:57 AM UTC 24 | 237754077 ps | ||
| T295 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_intg_err.3753282600 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:58 AM UTC 24 | 698890794 ps | ||
| T494 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_intg_err.2488395065 | Aug 21 08:07:53 AM UTC 24 | Aug 21 08:07:58 AM UTC 24 | 857086310 ps | ||
| T296 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1203590672 | Aug 21 08:07:41 AM UTC 24 | Aug 21 08:07:59 AM UTC 24 | 1338323102 ps | ||
| T335 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_intr_test.231042284 | Aug 21 08:07:51 AM UTC 24 | Aug 21 08:08:00 AM UTC 24 | 36609959 ps | ||
| T3639 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_rw.4170872800 | Aug 21 08:07:51 AM UTC 24 | Aug 21 08:08:00 AM UTC 24 | 78678268 ps | ||
| T3640 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2793693927 | Aug 21 08:07:51 AM UTC 24 | Aug 21 08:08:00 AM UTC 24 | 79803189 ps | ||
| T3641 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3062507884 | Aug 21 08:07:44 AM UTC 24 | Aug 21 08:08:01 AM UTC 24 | 268706128 ps | ||
| T261 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.3830396165 | Aug 21 08:07:58 AM UTC 24 | Aug 21 08:08:01 AM UTC 24 | 165496460 ps | ||
| T3642 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_aliasing.3493003207 | Aug 21 08:07:44 AM UTC 24 | Aug 21 08:08:02 AM UTC 24 | 299642673 ps | ||
| T501 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_intg_err.2035425058 | Aug 21 08:07:51 AM UTC 24 | Aug 21 08:08:03 AM UTC 24 | 670280379 ps | ||
| T499 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_intg_err.2444031596 | Aug 21 08:07:58 AM UTC 24 | Aug 21 08:08:03 AM UTC 24 | 797888722 ps | ||
| T3643 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2256818447 | Aug 21 08:08:03 AM UTC 24 | Aug 21 08:08:05 AM UTC 24 | 137356786 ps | ||
| T3644 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.1171129285 | Aug 21 08:07:56 AM UTC 24 | Aug 21 08:08:05 AM UTC 24 | 69288060 ps | ||
| T3645 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.4271466394 | Aug 21 08:08:00 AM UTC 24 | Aug 21 08:08:05 AM UTC 24 | 88972896 ps | ||
| T3646 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.141755849 | Aug 21 08:07:56 AM UTC 24 | Aug 21 08:08:05 AM UTC 24 | 94394512 ps | ||
| T3647 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.4197888034 | Aug 21 08:07:56 AM UTC 24 | Aug 21 08:08:05 AM UTC 24 | 108046714 ps | ||
| T3648 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_rw.107573770 | Aug 21 08:07:44 AM UTC 24 | Aug 21 08:08:06 AM UTC 24 | 63085038 ps | ||
| T3649 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.3698349093 | Aug 21 08:07:56 AM UTC 24 | Aug 21 08:08:06 AM UTC 24 | 173751342 ps | ||
| T3650 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_errors.1182981456 | Aug 21 08:08:00 AM UTC 24 | Aug 21 08:08:06 AM UTC 24 | 117605950 ps | ||
| T502 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_intg_err.817834364 | Aug 21 08:07:56 AM UTC 24 | Aug 21 08:08:07 AM UTC 24 | 441270642 ps | ||
| T3651 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1661940656 | Aug 21 08:08:07 AM UTC 24 | Aug 21 08:08:09 AM UTC 24 | 105525824 ps | ||
| T337 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/24.usbdev_intr_test.2413210396 | Aug 21 08:08:07 AM UTC 24 | Aug 21 08:08:09 AM UTC 24 | 43190040 ps | ||
| T339 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/21.usbdev_intr_test.3630942721 | Aug 21 08:08:07 AM UTC 24 | Aug 21 08:08:09 AM UTC 24 | 83640114 ps | ||
| T3652 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.129761093 | Aug 21 08:07:55 AM UTC 24 | Aug 21 08:08:09 AM UTC 24 | 43628838 ps | ||
| T338 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/46.usbdev_intr_test.1683114455 | Aug 21 08:08:18 AM UTC 24 | Aug 21 08:08:20 AM UTC 24 | 46619386 ps | ||
| T3653 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_rw.1170408104 | Aug 21 08:08:05 AM UTC 24 | Aug 21 08:08:10 AM UTC 24 | 77049174 ps | ||
| T3654 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_intr_test.3941941254 | Aug 21 08:07:58 AM UTC 24 | Aug 21 08:08:10 AM UTC 24 | 29762724 ps | ||
| T3655 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_intr_test.2623129082 | Aug 21 08:07:58 AM UTC 24 | Aug 21 08:08:10 AM UTC 24 | 47420611 ps | ||
| T3656 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_rw.1503477244 | Aug 21 08:07:58 AM UTC 24 | Aug 21 08:08:10 AM UTC 24 | 88348069 ps | ||
| T500 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.1243799064 | Aug 21 08:07:44 AM UTC 24 | Aug 21 08:08:10 AM UTC 24 | 1723956065 ps | ||
| T3657 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3517836249 | Aug 21 08:07:58 AM UTC 24 | Aug 21 08:08:10 AM UTC 24 | 120468721 ps | ||
| T3658 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.2601341206 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:11 AM UTC 24 | 109149000 ps | ||
| T3659 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.2673404009 | Aug 21 08:07:55 AM UTC 24 | Aug 21 08:08:11 AM UTC 24 | 215430489 ps | ||
| T3660 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2679135410 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:11 AM UTC 24 | 128661454 ps | ||
| T3661 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3241387040 | Aug 21 08:07:51 AM UTC 24 | Aug 21 08:08:11 AM UTC 24 | 108255903 ps | ||
| T3662 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3919442359 | Aug 21 08:07:58 AM UTC 24 | Aug 21 08:08:11 AM UTC 24 | 99389525 ps | ||
| T3663 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_intg_err.3882115353 | Aug 21 08:07:55 AM UTC 24 | Aug 21 08:08:12 AM UTC 24 | 790100464 ps | ||
| T3664 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_errors.3034425652 | Aug 21 08:07:51 AM UTC 24 | Aug 21 08:08:12 AM UTC 24 | 286696087 ps | ||
| T503 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_intg_err.3803763880 | Aug 21 08:07:51 AM UTC 24 | Aug 21 08:08:13 AM UTC 24 | 1037872715 ps | ||
| T3665 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/36.usbdev_intr_test.3679119734 | Aug 21 08:08:13 AM UTC 24 | Aug 21 08:08:14 AM UTC 24 | 42765481 ps | ||
| T3666 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1471546670 | Aug 21 08:08:03 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 95262077 ps | ||
| T495 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_intg_err.741630774 | Aug 21 08:08:01 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 2332265640 ps | ||
| T3667 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/33.usbdev_intr_test.3111549522 | Aug 21 08:08:12 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 43859096 ps | ||
| T3668 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/49.usbdev_intr_test.759244433 | Aug 21 08:08:19 AM UTC 24 | Aug 21 08:08:20 AM UTC 24 | 95821067 ps | ||
| T3669 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/34.usbdev_intr_test.2717118434 | Aug 21 08:08:13 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 54425304 ps | ||
| T3670 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.2549284213 | Aug 21 08:07:56 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 43181087 ps | ||
| T3671 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/35.usbdev_intr_test.3315835566 | Aug 21 08:08:13 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 43653641 ps | ||
| T3672 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/38.usbdev_intr_test.1129318873 | Aug 21 08:08:13 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 36033287 ps | ||
| T3673 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/29.usbdev_intr_test.2096832713 | Aug 21 08:08:11 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 40805626 ps | ||
| T3674 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/40.usbdev_intr_test.1126073974 | Aug 21 08:08:13 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 42028166 ps | ||
| T3675 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/37.usbdev_intr_test.1220749328 | Aug 21 08:08:13 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 45373903 ps | ||
| T3676 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/28.usbdev_intr_test.4170479968 | Aug 21 08:08:11 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 33120423 ps | ||
| T3677 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/31.usbdev_intr_test.1298083050 | Aug 21 08:08:11 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 43644516 ps | ||
| T3678 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/30.usbdev_intr_test.3086898509 | Aug 21 08:08:11 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 48482178 ps | ||
| T3679 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/45.usbdev_intr_test.2686009642 | Aug 21 08:08:15 AM UTC 24 | Aug 21 08:08:20 AM UTC 24 | 45743487 ps | ||
| T3680 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/47.usbdev_intr_test.2912659979 | Aug 21 08:08:18 AM UTC 24 | Aug 21 08:08:20 AM UTC 24 | 68792323 ps | ||
| T3681 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.2534604908 | Aug 21 08:07:56 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 47851561 ps | ||
| T3682 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/41.usbdev_intr_test.2197841085 | Aug 21 08:08:13 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 70884744 ps | ||
| T3683 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/39.usbdev_intr_test.3396269887 | Aug 21 08:08:13 AM UTC 24 | Aug 21 08:08:15 AM UTC 24 | 78638521 ps | ||
| T3684 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/48.usbdev_intr_test.2187190192 | Aug 21 08:08:19 AM UTC 24 | Aug 21 08:08:20 AM UTC 24 | 77074587 ps | ||
| T3685 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/32.usbdev_intr_test.2741937119 | Aug 21 08:08:11 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 39870382 ps | ||
| T3686 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/20.usbdev_intr_test.3787658531 | Aug 21 08:08:07 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 39098902 ps | ||
| T3687 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2656809495 | Aug 21 08:07:56 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 134888307 ps | ||
| T3688 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/23.usbdev_intr_test.116959924 | Aug 21 08:08:07 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 49812328 ps | ||
| T3689 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_rw.2979642328 | Aug 21 08:08:01 AM UTC 24 | Aug 21 08:08:20 AM UTC 24 | 69957741 ps | ||
| T3690 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/22.usbdev_intr_test.2482941888 | Aug 21 08:08:07 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 45662328 ps | ||
| T3691 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/42.usbdev_intr_test.207290467 | Aug 21 08:08:14 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 60581255 ps | ||
| T3692 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/43.usbdev_intr_test.1904188554 | Aug 21 08:08:14 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 35067685 ps | ||
| T3693 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/44.usbdev_intr_test.3744495590 | Aug 21 08:08:14 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 54368280 ps | ||
| T3694 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_intr_test.2005720168 | Aug 21 08:08:04 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 44981196 ps | ||
| T3695 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.2386265243 | Aug 21 08:07:44 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 38696883 ps | ||
| T3696 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2672863359 | Aug 21 08:07:56 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 158237808 ps | ||
| T3697 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1827286780 | Aug 21 08:07:44 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 164367387 ps | ||
| T3698 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_intr_test.1520030466 | Aug 21 08:07:51 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 36188068 ps | ||
| T3699 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_errors.603567452 | Aug 21 08:08:04 AM UTC 24 | Aug 21 08:08:16 AM UTC 24 | 124639474 ps | ||
| T3700 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_rw.3740947455 | Aug 21 08:07:51 AM UTC 24 | Aug 21 08:08:17 AM UTC 24 | 96898511 ps | ||
| T3701 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_rw.4176926313 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:21 AM UTC 24 | 57643342 ps | ||
| T3702 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_intr_test.3995613830 | Aug 21 08:07:55 AM UTC 24 | Aug 21 08:08:17 AM UTC 24 | 40488335 ps | ||
| T3703 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1687086653 | Aug 21 08:08:07 AM UTC 24 | Aug 21 08:08:17 AM UTC 24 | 138139934 ps | ||
| T3704 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/25.usbdev_intr_test.662661934 | Aug 21 08:08:08 AM UTC 24 | Aug 21 08:08:17 AM UTC 24 | 49443261 ps | ||
| T3705 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/26.usbdev_intr_test.192687560 | Aug 21 08:08:08 AM UTC 24 | Aug 21 08:08:17 AM UTC 24 | 74718029 ps | ||
| T3706 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3742602004 | Aug 21 08:07:44 AM UTC 24 | Aug 21 08:08:17 AM UTC 24 | 134445501 ps | ||
| T3707 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2912401581 | Aug 21 08:07:51 AM UTC 24 | Aug 21 08:08:17 AM UTC 24 | 341960579 ps | ||
| T3708 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.3939555995 | Aug 21 08:07:55 AM UTC 24 | Aug 21 08:08:17 AM UTC 24 | 133922294 ps | ||
| T3709 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3322577194 | Aug 21 08:07:55 AM UTC 24 | Aug 21 08:08:17 AM UTC 24 | 153632675 ps | ||
| T3710 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_intg_err.3880156422 | Aug 21 08:08:04 AM UTC 24 | Aug 21 08:08:17 AM UTC 24 | 360516360 ps | ||
| T3711 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3256878995 | Aug 21 08:07:55 AM UTC 24 | Aug 21 08:08:18 AM UTC 24 | 87932345 ps | ||
| T3712 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_errors.2545519891 | Aug 21 08:07:44 AM UTC 24 | Aug 21 08:08:18 AM UTC 24 | 286183127 ps | ||
| T3713 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_walk.3152827065 | Aug 21 08:07:44 AM UTC 24 | Aug 21 08:08:19 AM UTC 24 | 166468997 ps | ||
| T496 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.4204055030 | Aug 21 08:07:55 AM UTC 24 | Aug 21 08:08:20 AM UTC 24 | 772936274 ps | ||
| T3714 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_intr_test.3940892841 | Aug 21 08:08:01 AM UTC 24 | Aug 21 08:08:20 AM UTC 24 | 66186314 ps | ||
| T3715 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_intr_test.2149154285 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:20 AM UTC 24 | 58576361 ps | ||
| T3716 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_rw.2350110396 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:21 AM UTC 24 | 45626166 ps | ||
| T3717 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_intr_test.736326674 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:21 AM UTC 24 | 55441078 ps | ||
| T3718 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2396449591 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:21 AM UTC 24 | 96459892 ps | ||
| T3719 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.434050239 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:21 AM UTC 24 | 167184546 ps | ||
| T3720 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1919621581 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:21 AM UTC 24 | 343596333 ps | ||
| T3721 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1409411395 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:22 AM UTC 24 | 266614728 ps | ||
| T3722 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_errors.345189162 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:22 AM UTC 24 | 131734706 ps | ||
| T3723 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_intg_err.1686200832 | Aug 21 08:07:58 AM UTC 24 | Aug 21 08:08:22 AM UTC 24 | 375677460 ps | ||
| T3724 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_errors.1636055210 | Aug 21 08:07:58 AM UTC 24 | Aug 21 08:08:22 AM UTC 24 | 137448558 ps | ||
| T3725 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_errors.3751837386 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:23 AM UTC 24 | 314086753 ps | ||
| T3726 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3178342020 | Aug 21 08:07:44 AM UTC 24 | Aug 21 08:08:23 AM UTC 24 | 2044178673 ps | ||
| T504 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_intg_err.667078526 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:24 AM UTC 24 | 894459114 ps | ||
| T3727 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_intg_err.84938856 | Aug 21 08:07:59 AM UTC 24 | Aug 21 08:08:24 AM UTC 24 | 1175268479 ps | ||
| T3728 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/27.usbdev_intr_test.2807740320 | Aug 21 08:08:09 AM UTC 24 | Aug 21 08:08:31 AM UTC 24 | 79142523 ps |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.3852277743 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 626875092 ps |
| CPU time | 1.89 seconds |
| Started | Aug 21 07:49:26 AM UTC 24 |
| Finished | Aug 21 07:49:33 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3852277743 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3852277743 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_device_timeout.4101509347 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 445100710 ps |
| CPU time | 9.18 seconds |
| Started | Aug 21 07:49:26 AM UTC 24 |
| Finished | Aug 21 07:49:40 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4101509347 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.4101509347 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_disable_endpoint.3782654240 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 482056024 ps |
| CPU time | 2.17 seconds |
| Started | Aug 21 07:49:26 AM UTC 24 |
| Finished | Aug 21 07:49:33 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3782654240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3782654240 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_reset.549933764 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 18772528897 ps |
| CPU time | 24.37 seconds |
| Started | Aug 21 07:49:56 AM UTC 24 |
| Finished | Aug 21 07:50:22 AM UTC 24 |
| Peak memory | 218268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=549933764 -assert nopostp roc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.549933764 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_intr_test.3802180837 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 43507273 ps |
| CPU time | 0.66 seconds |
| Started | Aug 21 08:07:49 AM UTC 24 |
| Finished | Aug 21 08:07:50 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3802180837 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3802180837 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_access.3460826503 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 918519177 ps |
| CPU time | 3.46 seconds |
| Started | Aug 21 07:49:30 AM UTC 24 |
| Finished | Aug 21 07:49:34 AM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3460826503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3460826503 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.869169227 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 32523126508 ps |
| CPU time | 61.65 seconds |
| Started | Aug 21 07:49:26 AM UTC 24 |
| Finished | Aug 21 07:50:33 AM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=869169227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.869169227 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2331813266 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 93636556 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:45 AM UTC 24 |
| Peak memory | 227396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2331813266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.u sbdev_csr_mem_rw_with_rand_reset.2331813266 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.666328896 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2616304943 ps |
| CPU time | 74.52 seconds |
| Started | Aug 21 07:49:35 AM UTC 24 |
| Finished | Aug 21 07:50:52 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=666328896 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.666328896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_disconnect.3083553446 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12335611347 ps |
| CPU time | 18.97 seconds |
| Started | Aug 21 07:49:22 AM UTC 24 |
| Finished | Aug 21 07:49:49 AM UTC 24 |
| Peak memory | 218272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3083553446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbde v_aon_wake_disconnect.3083553446 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_link_resume.2318570551 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 6098830031 ps |
| CPU time | 16.68 seconds |
| Started | Aug 21 07:52:00 AM UTC 24 |
| Finished | Aug 21 07:52:18 AM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2318570551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.2318570551 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.1267290681 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 470866076 ps |
| CPU time | 2.08 seconds |
| Started | Aug 21 07:49:56 AM UTC 24 |
| Finished | Aug 21 07:49:59 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1267290681 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1267290681 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_max_non_iso_usb_traffic.86051904 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3097294768 ps |
| CPU time | 24.28 seconds |
| Started | Aug 21 07:49:37 AM UTC 24 |
| Finished | Aug 21 07:50:02 AM UTC 24 |
| Peak memory | 228488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=86051904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_202 4_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_non_iso_usb_traffic.86051904 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3357180794 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 332312949 ps |
| CPU time | 2.08 seconds |
| Started | Aug 21 07:49:42 AM UTC 24 |
| Finished | Aug 21 07:49:45 AM UTC 24 |
| Peak memory | 218040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3357180794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.3357180794 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_phy_config_tx_osc_test_mode/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/191.usbdev_tx_rx_disruption.2830721424 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 570520366 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:06:46 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2830721424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 191.usbdev_tx_rx_disruption.2830721424 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/191.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_intr_test.4212294410 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 31481799 ps |
| CPU time | 0.62 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:55 AM UTC 24 |
| Peak memory | 216984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4212294410 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.4212294410 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_phy_pins_sense.171586471 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 45501726 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 07:50:15 AM UTC 24 |
| Finished | Aug 21 07:50:18 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=171586471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.171586471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_intg_err.1420587438 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 586093494 ps |
| CPU time | 3.3 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:48 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1420587438 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1420587438 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.2530243049 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 159209285 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 07:49:26 AM UTC 24 |
| Finished | Aug 21 07:49:32 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2530243049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.2530243049 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_pinflip.3964611881 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 189420504 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:49:42 AM UTC 24 |
| Finished | Aug 21 07:49:44 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3964611881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.3964611881 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_stress_usb_traffic.107526877 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 7595875103 ps |
| CPU time | 37.01 seconds |
| Started | Aug 21 07:50:24 AM UTC 24 |
| Finished | Aug 21 07:51:03 AM UTC 24 |
| Peak memory | 235252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_ disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=107526877 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.107526877 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_stress_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_aon_wake_resume.3621157208 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 23779830155 ps |
| CPU time | 33.23 seconds |
| Started | Aug 21 07:54:55 AM UTC 24 |
| Finished | Aug 21 07:55:30 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3621157208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbd ev_aon_wake_resume.3621157208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/123.usbdev_tx_rx_disruption.2456671116 |
| Short name | T3215 |
| Test name | |
| Test status | |
| Simulation time | 517416040 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:56 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2456671116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 123.usbdev_tx_rx_disruption.2456671116 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/123.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_rw.4166035310 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 107588185 ps |
| CPU time | 0.87 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:50 AM UTC 24 |
| Peak memory | 216864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4166035310 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.4166035310 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_errors.1713861133 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 297451328 ps |
| CPU time | 2.94 seconds |
| Started | Aug 21 08:07:49 AM UTC 24 |
| Finished | Aug 21 08:07:53 AM UTC 24 |
| Peak memory | 228524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1713861133 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1713861133 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_types.3794618285 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 450995420 ps |
| CPU time | 1.91 seconds |
| Started | Aug 21 07:50:01 AM UTC 24 |
| Finished | Aug 21 07:50:04 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3794618285 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_types.3794618285 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.829716507 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 12124143163 ps |
| CPU time | 37.78 seconds |
| Started | Aug 21 07:49:43 AM UTC 24 |
| Finished | Aug 21 07:50:22 AM UTC 24 |
| Peak memory | 228512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=829716507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.829716507 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_rx_full.778510101 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 294291660 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 07:50:54 AM UTC 24 |
| Finished | Aug 21 07:50:56 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=778510101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_full.778510101 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/109.usbdev_endpoint_types.596835897 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 828341245 ps |
| CPU time | 1.71 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=596835897 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_endpoint_types.596835897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/109.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_endpoint_types.924689207 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 544362533 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 07:58:21 AM UTC 24 |
| Finished | Aug 21 07:58:24 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=924689207 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_types.924689207 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.3587419069 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 141048783 ps |
| CPU time | 0.73 seconds |
| Started | Aug 21 07:49:25 AM UTC 24 |
| Finished | Aug 21 07:49:30 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3587419069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.3587419069 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_device_address.1609615213 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 21444431776 ps |
| CPU time | 48.23 seconds |
| Started | Aug 21 07:51:04 AM UTC 24 |
| Finished | Aug 21 07:51:54 AM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1609615213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1609615213 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/125.usbdev_endpoint_types.2165814849 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 553885253 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:56 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2165814849 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_endpoint_types.2165814849 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/125.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.1447367603 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 199292760 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 07:49:47 AM UTC 24 |
| Finished | Aug 21 07:49:49 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1447367603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1447367603 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.3852340699 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 439497436 ps |
| CPU time | 2.47 seconds |
| Started | Aug 21 07:49:47 AM UTC 24 |
| Finished | Aug 21 07:49:50 AM UTC 24 |
| Peak memory | 218068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3852340699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.3852340699 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_setup_priority/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/108.usbdev_endpoint_types.4085670887 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 468690245 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4085670887 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_endpoint_types.4085670887 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/108.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/136.usbdev_endpoint_types.2866077230 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 800330059 ps |
| CPU time | 1.72 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:05:57 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2866077230 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_endpoint_types.2866077230 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/136.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/64.usbdev_endpoint_types.3977814724 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 674725937 ps |
| CPU time | 1.95 seconds |
| Started | Aug 21 08:05:24 AM UTC 24 |
| Finished | Aug 21 08:05:27 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3977814724 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_endpoint_types.3977814724 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/64.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/123.usbdev_endpoint_types.2802834821 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 599748056 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:55 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2802834821 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_endpoint_types.2802834821 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/123.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/141.usbdev_endpoint_types.3012577729 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 545730901 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3012577729 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_endpoint_types.3012577729 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/141.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_data_toggle_restore.3246603435 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1045481426 ps |
| CPU time | 2.9 seconds |
| Started | Aug 21 07:59:23 AM UTC 24 |
| Finished | Aug 21 07:59:27 AM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3246603435 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3246603435 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.2585939343 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 44865603152 ps |
| CPU time | 73.02 seconds |
| Started | Aug 21 07:50:00 AM UTC 24 |
| Finished | Aug 21 07:51:15 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2585939343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2585939343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_intg_err.2488395065 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 857086310 ps |
| CPU time | 3.99 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:58 AM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2488395065 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2488395065 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_endpoint_types.105446684 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 648263881 ps |
| CPU time | 2.21 seconds |
| Started | Aug 21 07:55:13 AM UTC 24 |
| Finished | Aug 21 07:55:17 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=105446684 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_types.105446684 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/167.usbdev_endpoint_types.2273062994 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 648113471 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 08:06:04 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2273062994 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_endpoint_types.2273062994 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/167.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/187.usbdev_endpoint_types.576832088 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 480590060 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:06:49 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=576832088 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_endpoint_types.576832088 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/187.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/83.usbdev_endpoint_types.418569778 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 589981718 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 08:05:35 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=418569778 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_endpoint_types.418569778 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/83.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_tx_rx_disruption.2377435940 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 520127504 ps |
| CPU time | 2.03 seconds |
| Started | Aug 21 07:55:31 AM UTC 24 |
| Finished | Aug 21 07:55:34 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2377435940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.usbdev_tx_rx_disruption.2377435940 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.369509414 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 33253778 ps |
| CPU time | 0.58 seconds |
| Started | Aug 21 08:07:37 AM UTC 24 |
| Finished | Aug 21 08:07:40 AM UTC 24 |
| Peak memory | 217372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=369509414 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.369509414 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/194.usbdev_endpoint_types.600756800 |
| Short name | T3478 |
| Test name | |
| Test status | |
| Simulation time | 327990515 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=600756800 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_endpoint_types.600756800 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/194.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_endpoint_types.838003742 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 738341404 ps |
| CPU time | 1.86 seconds |
| Started | Aug 21 08:05:03 AM UTC 24 |
| Finished | Aug 21 08:05:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=838003742 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_types.838003742 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.3057238813 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 50170962 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 07:49:56 AM UTC 24 |
| Finished | Aug 21 07:49:58 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3057238813 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.3057238813 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_resets.2241093669 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5125200216 ps |
| CPU time | 125.22 seconds |
| Started | Aug 21 07:49:45 AM UTC 24 |
| Finished | Aug 21 07:51:53 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2241093669 -assert nopostproc +UVM_TESTNAME=usbdev_ base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2241093669 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.4204055030 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 772936274 ps |
| CPU time | 3.84 seconds |
| Started | Aug 21 08:07:55 AM UTC 24 |
| Finished | Aug 21 08:08:20 AM UTC 24 |
| Peak memory | 217760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4204055030 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.4204055030 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.2996750369 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 153525199 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:49:43 AM UTC 24 |
| Finished | Aug 21 07:49:45 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2996750369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2996750369 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/128.usbdev_endpoint_types.2268100233 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 521421908 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:56 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2268100233 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_endpoint_types.2268100233 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/128.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/133.usbdev_endpoint_types.1445329425 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 410614145 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:05:55 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1445329425 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_endpoint_types.1445329425 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/133.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_endpoint_types.718096236 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 693083618 ps |
| CPU time | 2.79 seconds |
| Started | Aug 21 07:56:31 AM UTC 24 |
| Finished | Aug 21 07:56:34 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=718096236 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_types.718096236 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/156.usbdev_endpoint_types.676758704 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 471325691 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:00 AM UTC 24 |
| Peak memory | 214900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=676758704 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_endpoint_types.676758704 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/156.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_min_inter_pkt_delay.2966946036 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2200035903 ps |
| CPU time | 21.37 seconds |
| Started | Aug 21 07:57:44 AM UTC 24 |
| Finished | Aug 21 07:58:06 AM UTC 24 |
| Peak memory | 230516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2966946036 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2966946036 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_types.497413686 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 365170502 ps |
| CPU time | 2.11 seconds |
| Started | Aug 21 07:50:32 AM UTC 24 |
| Finished | Aug 21 07:50:35 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=497413686 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_types.497413686 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_data_toggle_restore.947510621 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1348254430 ps |
| CPU time | 5.23 seconds |
| Started | Aug 21 07:58:20 AM UTC 24 |
| Finished | Aug 21 07:58:26 AM UTC 24 |
| Peak memory | 218148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=947510621 -assert nopostproc +UVM_TESTNAME=us bdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.947510621 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_endpoint_types.2231663068 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 312714464 ps |
| CPU time | 1.85 seconds |
| Started | Aug 21 08:04:01 AM UTC 24 |
| Finished | Aug 21 08:04:11 AM UTC 24 |
| Peak memory | 216424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2231663068 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_types.2231663068 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_tx_rx_disruption.37686062 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 557389041 ps |
| CPU time | 1.94 seconds |
| Started | Aug 21 07:51:01 AM UTC 24 |
| Finished | Aug 21 07:51:04 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=37686062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.usbdev_tx_rx_disruption.37686062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.176463263 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 160119117 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 07:49:24 AM UTC 24 |
| Finished | Aug 21 07:49:36 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=176463263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.176463263 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_av_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_dpi_config_host.1650824765 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 5130923737 ps |
| CPU time | 37.36 seconds |
| Started | Aug 21 07:49:27 AM UTC 24 |
| Finished | Aug 21 07:50:07 AM UTC 24 |
| Peak memory | 217796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1650824765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1650824765 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_dpi_config_host/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.2347618082 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 527275577 ps |
| CPU time | 2.41 seconds |
| Started | Aug 21 07:49:30 AM UTC 24 |
| Finished | Aug 21 07:49:33 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2347618082 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_types.2347618082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_stall_priority_over_nak.2684057866 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 156387216 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:49:54 AM UTC 24 |
| Finished | Aug 21 07:49:56 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2684057866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2684057866 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/112.usbdev_endpoint_types.1861534505 |
| Short name | T3191 |
| Test name | |
| Test status | |
| Simulation time | 470801649 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1861534505 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_endpoint_types.1861534505 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/112.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/126.usbdev_endpoint_types.1666143069 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 286565953 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:55 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1666143069 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_endpoint_types.1666143069 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/126.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/134.usbdev_endpoint_types.3844478255 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 292294281 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:06 AM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3844478255 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_endpoint_types.3844478255 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/134.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/147.usbdev_endpoint_types.3716059492 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 573135241 ps |
| CPU time | 1.7 seconds |
| Started | Aug 21 08:05:56 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 216300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3716059492 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_endpoint_types.3716059492 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/147.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_data_toggle_restore.1688824140 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 522379546 ps |
| CPU time | 2.11 seconds |
| Started | Aug 21 07:56:52 AM UTC 24 |
| Finished | Aug 21 07:56:55 AM UTC 24 |
| Peak memory | 218008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1688824140 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1688824140 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/171.usbdev_endpoint_types.2099047022 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 747885575 ps |
| CPU time | 1.72 seconds |
| Started | Aug 21 08:06:09 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 215184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2099047022 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_endpoint_types.2099047022 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/171.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_rx_full.3506766353 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 257641773 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:57:34 AM UTC 24 |
| Finished | Aug 21 07:57:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3506766353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_full.3506766353 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_types.3417150245 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 414965891 ps |
| CPU time | 2.07 seconds |
| Started | Aug 21 07:51:06 AM UTC 24 |
| Finished | Aug 21 07:51:09 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3417150245 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_types.3417150245 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_device_address.3370348936 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 42774643258 ps |
| CPU time | 72.3 seconds |
| Started | Aug 21 08:00:25 AM UTC 24 |
| Finished | Aug 21 08:01:39 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3370348936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.3370348936 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_endpoint_types.2792267318 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 578635306 ps |
| CPU time | 1.72 seconds |
| Started | Aug 21 08:03:13 AM UTC 24 |
| Finished | Aug 21 08:03:16 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2792267318 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_types.2792267318 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.226266860 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 76247379 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:46 AM UTC 24 |
| Peak memory | 217164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=226266860 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.226266860 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_av_empty.3591374374 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 161772922 ps |
| CPU time | 0.86 seconds |
| Started | Aug 21 07:49:24 AM UTC 24 |
| Finished | Aug 21 07:49:26 AM UTC 24 |
| Peak memory | 217416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3591374374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3591374374 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_av_empty/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_stress_usb_traffic.242976004 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 11787967003 ps |
| CPU time | 307.97 seconds |
| Started | Aug 21 07:52:20 AM UTC 24 |
| Finished | Aug 21 07:57:32 AM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_ disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=242976004 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.242976004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_stress_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_low_speed_traffic.3013750851 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4553185183 ps |
| CPU time | 118.16 seconds |
| Started | Aug 21 07:50:08 AM UTC 24 |
| Finished | Aug 21 07:52:08 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3013750851 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.3013750851 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_phy_pins_sense.1226736773 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 66727771 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 07:55:05 AM UTC 24 |
| Finished | Aug 21 07:55:08 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1226736773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1226736773 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_rand_bus_disconnects.1371454782 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 7668927974 ps |
| CPU time | 112.55 seconds |
| Started | Aug 21 07:52:13 AM UTC 24 |
| Finished | Aug 21 07:54:08 AM UTC 24 |
| Peak memory | 235248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1371454782 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1371454782 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.2682700605 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 32663699 ps |
| CPU time | 0.59 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:55 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2682700605 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2682700605 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_intg_err.817834364 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 441270642 ps |
| CPU time | 2.54 seconds |
| Started | Aug 21 08:07:56 AM UTC 24 |
| Finished | Aug 21 08:08:07 AM UTC 24 |
| Peak memory | 218144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=817834364 -assert nopostproc +UVM_TESTNA ME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.817834364 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/102.usbdev_endpoint_types.1626576681 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 319737124 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:05:45 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1626576681 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.1626576681 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/102.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/115.usbdev_endpoint_types.2840946657 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 447003895 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2840946657 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_endpoint_types.2840946657 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/115.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/119.usbdev_endpoint_types.255086896 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 359373492 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:54 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=255086896 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_endpoint_types.255086896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/119.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_rx_full.4025729963 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 420745019 ps |
| CPU time | 2.32 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:55:49 AM UTC 24 |
| Peak memory | 218068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4025729963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_full.4025729963 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/124.usbdev_endpoint_types.3594535735 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 646570138 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:56 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3594535735 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_endpoint_types.3594535735 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/124.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/130.usbdev_endpoint_types.228606529 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 416353115 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:06:06 AM UTC 24 |
| Peak memory | 216132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=228606529 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_endpoint_types.228606529 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/130.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/172.usbdev_endpoint_types.1434615130 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 414619256 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 08:06:09 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 215436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1434615130 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_endpoint_types.1434615130 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/172.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/185.usbdev_endpoint_types.1887783550 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 600826414 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:06:49 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1887783550 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_endpoint_types.1887783550 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/185.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_freq_hiclk.2471269853 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 110176859797 ps |
| CPU time | 190.21 seconds |
| Started | Aug 21 07:50:33 AM UTC 24 |
| Finished | Aug 21 07:53:46 AM UTC 24 |
| Peak memory | 217972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2471269853 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.2471269853 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_freq_hiclk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_endpoint_types.3721281674 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 521574075 ps |
| CPU time | 1.97 seconds |
| Started | Aug 21 07:58:09 AM UTC 24 |
| Finished | Aug 21 07:58:12 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3721281674 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_types.3721281674 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_endpoint_types.3901315280 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 289199339 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 07:58:55 AM UTC 24 |
| Finished | Aug 21 07:58:58 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3901315280 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_types.3901315280 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_rx_full.3007085566 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 259449058 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:00:51 AM UTC 24 |
| Finished | Aug 21 08:00:54 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3007085566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_full.3007085566 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_pkt_buffer.3913003599 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 21708441729 ps |
| CPU time | 49.28 seconds |
| Started | Aug 21 08:04:57 AM UTC 24 |
| Finished | Aug 21 08:05:49 AM UTC 24 |
| Peak memory | 228508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3913003599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3913003599 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/58.usbdev_endpoint_types.504976903 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 510519465 ps |
| CPU time | 2.19 seconds |
| Started | Aug 21 08:05:22 AM UTC 24 |
| Finished | Aug 21 08:05:25 AM UTC 24 |
| Peak memory | 218040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=504976903 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_endpoint_types.504976903 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/58.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_usb_ref_disable.3394800661 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 139499030 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 07:49:43 AM UTC 24 |
| Finished | Aug 21 07:49:45 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3394800661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3394800661 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_reset.3872965466 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 20676168006 ps |
| CPU time | 27.94 seconds |
| Started | Aug 21 07:50:29 AM UTC 24 |
| Finished | Aug 21 07:50:58 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3872965466 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.3872965466 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_nak_trans.3628707646 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 278258664 ps |
| CPU time | 1.73 seconds |
| Started | Aug 21 07:49:39 AM UTC 24 |
| Finished | Aug 21 07:49:42 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3628707646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3628707646 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.360709056 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4166189048 ps |
| CPU time | 18.29 seconds |
| Started | Aug 21 07:49:32 AM UTC 24 |
| Finished | Aug 21 07:49:55 AM UTC 24 |
| Peak memory | 218336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=360709056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.360709056 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_host_lost/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2968616582 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 529114582 ps |
| CPU time | 2.61 seconds |
| Started | Aug 21 07:49:32 AM UTC 24 |
| Finished | Aug 21 07:49:39 AM UTC 24 |
| Peak memory | 218008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2968616582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2968616582 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_invalid_data1_data0_toggle_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_link_reset.1405407076 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 165689547 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:49:34 AM UTC 24 |
| Finished | Aug 21 07:49:37 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1405407076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1405407076 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_link_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_rx_pid_err.374536860 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 206613869 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:49:47 AM UTC 24 |
| Finished | Aug 21 07:49:49 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=374536860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.374536860 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_rx_pid_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_av_empty.1864430101 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 162065177 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:51:04 AM UTC 24 |
| Finished | Aug 21 07:51:06 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1864430101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1864430101 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_av_empty/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_rand_bus_resets.2150010263 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3753870698 ps |
| CPU time | 97.59 seconds |
| Started | Aug 21 07:54:21 AM UTC 24 |
| Finished | Aug 21 07:56:00 AM UTC 24 |
| Peak memory | 228076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2150010263 -assert nopostproc +UVM_TESTNAME=usbdev_ base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.2150010263 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_rst.4058563420 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 173301080 ps |
| CPU time | 2.18 seconds |
| Started | Aug 21 07:49:30 AM UTC 24 |
| Finished | Aug 21 07:49:33 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4058563420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.4058563420 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_sync.2589619874 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3525260782 ps |
| CPU time | 93.41 seconds |
| Started | Aug 21 07:49:33 AM UTC 24 |
| Finished | Aug 21 07:51:08 AM UTC 24 |
| Peak memory | 230680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2589619874 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.2589619874 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_nak_trans.2739387408 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 189753860 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:50:11 AM UTC 24 |
| Finished | Aug 21 07:50:13 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2739387408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2739387408 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_iso_retraction.1289899939 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 9561468991 ps |
| CPU time | 108.7 seconds |
| Started | Aug 21 07:54:59 AM UTC 24 |
| Finished | Aug 21 07:56:50 AM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1289899939 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.1289899939 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_nak_trans.716976032 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 200652786 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:55:04 AM UTC 24 |
| Finished | Aug 21 07:55:06 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=716976032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.716976032 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_nak_trans.2975447160 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 189286903 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:55:22 AM UTC 24 |
| Finished | Aug 21 07:55:25 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2975447160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2975447160 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_nak_trans.2659336214 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 176020349 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:55:40 AM UTC 24 |
| Finished | Aug 21 07:55:42 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2659336214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2659336214 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_nak_trans.3973611961 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 222266156 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 07:56:17 AM UTC 24 |
| Finished | Aug 21 07:56:20 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3973611961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3973611961 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/173.usbdev_tx_rx_disruption.4209020361 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 615977973 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:06:09 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4209020361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 173.usbdev_tx_rx_disruption.4209020361 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/173.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_nak_trans.1796400258 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 224175157 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:57:30 AM UTC 24 |
| Finished | Aug 21 07:57:33 AM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1796400258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1796400258 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_nak_trans.1292635336 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 192212921 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:57:59 AM UTC 24 |
| Finished | Aug 21 07:58:02 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1292635336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1292635336 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_nak_trans.1937753187 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 201565172 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 07:58:12 AM UTC 24 |
| Finished | Aug 21 07:58:15 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1937753187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1937753187 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_nak_trans.3519089031 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 225690987 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:59:29 AM UTC 24 |
| Finished | Aug 21 07:59:31 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3519089031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3519089031 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_nak_trans.1836647330 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 187429653 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 08:00:34 AM UTC 24 |
| Finished | Aug 21 08:00:37 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1836647330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1836647330 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_nak_trans.387030592 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 201819258 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:18 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=387030592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.387030592 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.3586161858 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 346255989 ps |
| CPU time | 3.23 seconds |
| Started | Aug 21 08:07:41 AM UTC 24 |
| Finished | Aug 21 08:07:55 AM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3586161858 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3586161858 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1203590672 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1338323102 ps |
| CPU time | 4.39 seconds |
| Started | Aug 21 08:07:41 AM UTC 24 |
| Finished | Aug 21 08:07:59 AM UTC 24 |
| Peak memory | 217972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1203590672 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1203590672 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2795300666 |
| Short name | T3627 |
| Test name | |
| Test status | |
| Simulation time | 55066775 ps |
| CPU time | 0.72 seconds |
| Started | Aug 21 08:07:40 AM UTC 24 |
| Finished | Aug 21 08:07:52 AM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2795300666 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2795300666 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.3703497014 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 45676501 ps |
| CPU time | 0.77 seconds |
| Started | Aug 21 08:07:40 AM UTC 24 |
| Finished | Aug 21 08:07:46 AM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3703497014 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3703497014 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.3465109775 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 114195481 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:07:37 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3465109775 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3465109775 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_mem_partial_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.3695715521 |
| Short name | T3621 |
| Test name | |
| Test status | |
| Simulation time | 270137495 ps |
| CPU time | 2.07 seconds |
| Started | Aug 21 08:07:37 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 218096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3695715521 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3695715521 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_mem_walk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3014505317 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 178438443 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:46 AM UTC 24 |
| Peak memory | 217472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3014505317 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3014505317 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.3386826892 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 154693029 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:07:37 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 217008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3386826892 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3386826892 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.3024208403 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1267215467 ps |
| CPU time | 4.57 seconds |
| Started | Aug 21 08:07:37 AM UTC 24 |
| Finished | Aug 21 08:07:44 AM UTC 24 |
| Peak memory | 218080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3024208403 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3024208403 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.3362606121 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 133980187 ps |
| CPU time | 2.71 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:47 AM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3362606121 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3362606121 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3775318557 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1568463405 ps |
| CPU time | 7.41 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:52 AM UTC 24 |
| Peak memory | 218148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3775318557 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3775318557 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3042277568 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 208379593 ps |
| CPU time | 0.94 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:45 AM UTC 24 |
| Peak memory | 217292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3042277568 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3042277568 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.156903292 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 78375442 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:46 AM UTC 24 |
| Peak memory | 227472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=156903292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.us bdev_csr_mem_rw_with_rand_reset.156903292 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.564319927 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 65106283 ps |
| CPU time | 0.73 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:45 AM UTC 24 |
| Peak memory | 217352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=564319927 -assert nopostproc +UVM_TESTNAME=usbdev _base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.564319927 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.1590101570 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 31938384 ps |
| CPU time | 0.62 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:45 AM UTC 24 |
| Peak memory | 216984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1590101570 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1590101570 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.3620347729 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 206085772 ps |
| CPU time | 1.99 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:46 AM UTC 24 |
| Peak memory | 227464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3620347729 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3620347729 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_mem_partial_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.1798524176 |
| Short name | T3622 |
| Test name | |
| Test status | |
| Simulation time | 215562902 ps |
| CPU time | 3.54 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:48 AM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1798524176 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1798524176 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_mem_walk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3877667513 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 125342990 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:46 AM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3877667513 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3877667513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.4104509739 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 725158650 ps |
| CPU time | 2.55 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:47 AM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4104509739 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.4104509739 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1374841948 |
| Short name | T3635 |
| Test name | |
| Test status | |
| Simulation time | 109104818 ps |
| CPU time | 2.17 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:57 AM UTC 24 |
| Peak memory | 228456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1374841948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. usbdev_csr_mem_rw_with_rand_reset.1374841948 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.517303135 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 53193087 ps |
| CPU time | 0.71 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:55 AM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=517303135 -assert nopostproc +UVM_TESTNAME=usbdev _base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.517303135 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.221398253 |
| Short name | T3631 |
| Test name | |
| Test status | |
| Simulation time | 120275315 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=221398253 -assert nopostproc +U VM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.221398253 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.518051928 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 75688196 ps |
| CPU time | 1.71 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 235048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=518051928 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.518051928 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3256878995 |
| Short name | T3711 |
| Test name | |
| Test status | |
| Simulation time | 87932345 ps |
| CPU time | 1.81 seconds |
| Started | Aug 21 08:07:55 AM UTC 24 |
| Finished | Aug 21 08:08:18 AM UTC 24 |
| Peak memory | 227404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3256878995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. usbdev_csr_mem_rw_with_rand_reset.3256878995 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.129761093 |
| Short name | T3652 |
| Test name | |
| Test status | |
| Simulation time | 43628838 ps |
| CPU time | 0.66 seconds |
| Started | Aug 21 08:07:55 AM UTC 24 |
| Finished | Aug 21 08:08:09 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=129761093 -assert nopostproc +UVM_TESTNAME=usbdev _base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.129761093 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_intr_test.3995613830 |
| Short name | T3702 |
| Test name | |
| Test status | |
| Simulation time | 40488335 ps |
| CPU time | 0.62 seconds |
| Started | Aug 21 08:07:55 AM UTC 24 |
| Finished | Aug 21 08:08:17 AM UTC 24 |
| Peak memory | 217048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3995613830 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3995613830 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3322577194 |
| Short name | T3709 |
| Test name | |
| Test status | |
| Simulation time | 153632675 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:07:55 AM UTC 24 |
| Finished | Aug 21 08:08:17 AM UTC 24 |
| Peak memory | 217184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3322577194 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3322577194 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.3939555995 |
| Short name | T3708 |
| Test name | |
| Test status | |
| Simulation time | 133922294 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:07:55 AM UTC 24 |
| Finished | Aug 21 08:08:17 AM UTC 24 |
| Peak memory | 226780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3939555995 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3939555995 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.141755849 |
| Short name | T3646 |
| Test name | |
| Test status | |
| Simulation time | 94394512 ps |
| CPU time | 0.96 seconds |
| Started | Aug 21 08:07:56 AM UTC 24 |
| Finished | Aug 21 08:08:05 AM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=141755849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.u sbdev_csr_mem_rw_with_rand_reset.141755849 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.1171129285 |
| Short name | T3644 |
| Test name | |
| Test status | |
| Simulation time | 69288060 ps |
| CPU time | 0.71 seconds |
| Started | Aug 21 08:07:56 AM UTC 24 |
| Finished | Aug 21 08:08:05 AM UTC 24 |
| Peak memory | 217132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1171129285 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1171129285 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.3517954544 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 53551182 ps |
| CPU time | 0.63 seconds |
| Started | Aug 21 08:07:56 AM UTC 24 |
| Finished | Aug 21 08:08:05 AM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3517954544 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3517954544 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.4197888034 |
| Short name | T3647 |
| Test name | |
| Test status | |
| Simulation time | 108046714 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:07:56 AM UTC 24 |
| Finished | Aug 21 08:08:05 AM UTC 24 |
| Peak memory | 217224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4197888034 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.4197888034 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.2673404009 |
| Short name | T3659 |
| Test name | |
| Test status | |
| Simulation time | 215430489 ps |
| CPU time | 2.02 seconds |
| Started | Aug 21 08:07:55 AM UTC 24 |
| Finished | Aug 21 08:08:11 AM UTC 24 |
| Peak memory | 218352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2673404009 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2673404009 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_intg_err.3882115353 |
| Short name | T3663 |
| Test name | |
| Test status | |
| Simulation time | 790100464 ps |
| CPU time | 2.91 seconds |
| Started | Aug 21 08:07:55 AM UTC 24 |
| Finished | Aug 21 08:08:12 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3882115353 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3882115353 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2672863359 |
| Short name | T3696 |
| Test name | |
| Test status | |
| Simulation time | 158237808 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:07:56 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 227400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2672863359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. usbdev_csr_mem_rw_with_rand_reset.2672863359 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.2534604908 |
| Short name | T3681 |
| Test name | |
| Test status | |
| Simulation time | 47851561 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 08:07:56 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2534604908 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2534604908 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.2549284213 |
| Short name | T3670 |
| Test name | |
| Test status | |
| Simulation time | 43181087 ps |
| CPU time | 0.64 seconds |
| Started | Aug 21 08:07:56 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2549284213 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2549284213 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2656809495 |
| Short name | T3687 |
| Test name | |
| Test status | |
| Simulation time | 134888307 ps |
| CPU time | 0.92 seconds |
| Started | Aug 21 08:07:56 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 216940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2656809495 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2656809495 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.3698349093 |
| Short name | T3649 |
| Test name | |
| Test status | |
| Simulation time | 173751342 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 08:07:56 AM UTC 24 |
| Finished | Aug 21 08:08:06 AM UTC 24 |
| Peak memory | 217300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3698349093 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3698349093 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3919442359 |
| Short name | T3662 |
| Test name | |
| Test status | |
| Simulation time | 99389525 ps |
| CPU time | 1.89 seconds |
| Started | Aug 21 08:07:58 AM UTC 24 |
| Finished | Aug 21 08:08:11 AM UTC 24 |
| Peak memory | 227400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3919442359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. usbdev_csr_mem_rw_with_rand_reset.3919442359 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_rw.1503477244 |
| Short name | T3656 |
| Test name | |
| Test status | |
| Simulation time | 88348069 ps |
| CPU time | 0.89 seconds |
| Started | Aug 21 08:07:58 AM UTC 24 |
| Finished | Aug 21 08:08:10 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1503477244 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1503477244 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_intr_test.3941941254 |
| Short name | T3654 |
| Test name | |
| Test status | |
| Simulation time | 29762724 ps |
| CPU time | 0.64 seconds |
| Started | Aug 21 08:07:58 AM UTC 24 |
| Finished | Aug 21 08:08:10 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3941941254 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3941941254 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3517836249 |
| Short name | T3657 |
| Test name | |
| Test status | |
| Simulation time | 120468721 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:07:58 AM UTC 24 |
| Finished | Aug 21 08:08:10 AM UTC 24 |
| Peak memory | 217224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3517836249 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3517836249 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.3830396165 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 165496460 ps |
| CPU time | 1.77 seconds |
| Started | Aug 21 08:07:58 AM UTC 24 |
| Finished | Aug 21 08:08:01 AM UTC 24 |
| Peak memory | 217196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3830396165 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3830396165 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_intg_err.2444031596 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 797888722 ps |
| CPU time | 4.06 seconds |
| Started | Aug 21 08:07:58 AM UTC 24 |
| Finished | Aug 21 08:08:03 AM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2444031596 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2444031596 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2396449591 |
| Short name | T3718 |
| Test name | |
| Test status | |
| Simulation time | 96459892 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:21 AM UTC 24 |
| Peak memory | 227404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2396449591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. usbdev_csr_mem_rw_with_rand_reset.2396449591 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.2601341206 |
| Short name | T3658 |
| Test name | |
| Test status | |
| Simulation time | 109149000 ps |
| CPU time | 0.91 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:11 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2601341206 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2601341206 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_intr_test.2623129082 |
| Short name | T3655 |
| Test name | |
| Test status | |
| Simulation time | 47420611 ps |
| CPU time | 0.66 seconds |
| Started | Aug 21 08:07:58 AM UTC 24 |
| Finished | Aug 21 08:08:10 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2623129082 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2623129082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1919621581 |
| Short name | T3720 |
| Test name | |
| Test status | |
| Simulation time | 343596333 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:21 AM UTC 24 |
| Peak memory | 217236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1919621581 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1919621581 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_errors.1636055210 |
| Short name | T3724 |
| Test name | |
| Test status | |
| Simulation time | 137448558 ps |
| CPU time | 2.67 seconds |
| Started | Aug 21 08:07:58 AM UTC 24 |
| Finished | Aug 21 08:08:22 AM UTC 24 |
| Peak memory | 232560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1636055210 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1636055210 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_intg_err.1686200832 |
| Short name | T3723 |
| Test name | |
| Test status | |
| Simulation time | 375677460 ps |
| CPU time | 2.55 seconds |
| Started | Aug 21 08:07:58 AM UTC 24 |
| Finished | Aug 21 08:08:22 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1686200832 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1686200832 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2679135410 |
| Short name | T3660 |
| Test name | |
| Test status | |
| Simulation time | 128661454 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:11 AM UTC 24 |
| Peak memory | 227132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2679135410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. usbdev_csr_mem_rw_with_rand_reset.2679135410 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_rw.4176926313 |
| Short name | T3701 |
| Test name | |
| Test status | |
| Simulation time | 57643342 ps |
| CPU time | 0.75 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:21 AM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4176926313 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.4176926313 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_intr_test.2149154285 |
| Short name | T3715 |
| Test name | |
| Test status | |
| Simulation time | 58576361 ps |
| CPU time | 0.66 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:20 AM UTC 24 |
| Peak memory | 216988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2149154285 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2149154285 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1409411395 |
| Short name | T3721 |
| Test name | |
| Test status | |
| Simulation time | 266614728 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:22 AM UTC 24 |
| Peak memory | 217164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1409411395 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1409411395 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_errors.345189162 |
| Short name | T3722 |
| Test name | |
| Test status | |
| Simulation time | 131734706 ps |
| CPU time | 2.23 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:22 AM UTC 24 |
| Peak memory | 235496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=345189162 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.345189162 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_intg_err.667078526 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 894459114 ps |
| CPU time | 4.15 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:24 AM UTC 24 |
| Peak memory | 218268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=667078526 -assert nopostproc +UVM_TESTNA ME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.667078526 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.4271466394 |
| Short name | T3645 |
| Test name | |
| Test status | |
| Simulation time | 88972896 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 08:08:00 AM UTC 24 |
| Finished | Aug 21 08:08:05 AM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4271466394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. usbdev_csr_mem_rw_with_rand_reset.4271466394 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_rw.2350110396 |
| Short name | T3716 |
| Test name | |
| Test status | |
| Simulation time | 45626166 ps |
| CPU time | 0.73 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:21 AM UTC 24 |
| Peak memory | 217348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2350110396 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2350110396 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_intr_test.736326674 |
| Short name | T3717 |
| Test name | |
| Test status | |
| Simulation time | 55441078 ps |
| CPU time | 0.71 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:21 AM UTC 24 |
| Peak memory | 217164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=736326674 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.736326674 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.434050239 |
| Short name | T3719 |
| Test name | |
| Test status | |
| Simulation time | 167184546 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:21 AM UTC 24 |
| Peak memory | 217224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=434050239 -assert nopostproc +U VM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.434050239 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_errors.3751837386 |
| Short name | T3725 |
| Test name | |
| Test status | |
| Simulation time | 314086753 ps |
| CPU time | 2.58 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:23 AM UTC 24 |
| Peak memory | 235440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3751837386 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3751837386 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_intg_err.84938856 |
| Short name | T3727 |
| Test name | |
| Test status | |
| Simulation time | 1175268479 ps |
| CPU time | 4.05 seconds |
| Started | Aug 21 08:07:59 AM UTC 24 |
| Finished | Aug 21 08:08:24 AM UTC 24 |
| Peak memory | 218336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=84938856 -assert nopostproc +UVM_TESTNAM E=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.84938856 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2256818447 |
| Short name | T3643 |
| Test name | |
| Test status | |
| Simulation time | 137356786 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:08:03 AM UTC 24 |
| Finished | Aug 21 08:08:05 AM UTC 24 |
| Peak memory | 227476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2256818447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. usbdev_csr_mem_rw_with_rand_reset.2256818447 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_rw.2979642328 |
| Short name | T3689 |
| Test name | |
| Test status | |
| Simulation time | 69957741 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 08:08:01 AM UTC 24 |
| Finished | Aug 21 08:08:20 AM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2979642328 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2979642328 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_intr_test.3940892841 |
| Short name | T3714 |
| Test name | |
| Test status | |
| Simulation time | 66186314 ps |
| CPU time | 0.63 seconds |
| Started | Aug 21 08:08:01 AM UTC 24 |
| Finished | Aug 21 08:08:20 AM UTC 24 |
| Peak memory | 216172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3940892841 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3940892841 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1471546670 |
| Short name | T3666 |
| Test name | |
| Test status | |
| Simulation time | 95262077 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:08:03 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 217224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1471546670 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1471546670 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_errors.1182981456 |
| Short name | T3650 |
| Test name | |
| Test status | |
| Simulation time | 117605950 ps |
| CPU time | 2.04 seconds |
| Started | Aug 21 08:08:00 AM UTC 24 |
| Finished | Aug 21 08:08:06 AM UTC 24 |
| Peak memory | 228352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1182981456 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1182981456 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_intg_err.741630774 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2332265640 ps |
| CPU time | 5.39 seconds |
| Started | Aug 21 08:08:01 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=741630774 -assert nopostproc +UVM_TESTNA ME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.741630774 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1687086653 |
| Short name | T3703 |
| Test name | |
| Test status | |
| Simulation time | 138139934 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:08:07 AM UTC 24 |
| Finished | Aug 21 08:08:17 AM UTC 24 |
| Peak memory | 227400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1687086653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. usbdev_csr_mem_rw_with_rand_reset.1687086653 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_rw.1170408104 |
| Short name | T3653 |
| Test name | |
| Test status | |
| Simulation time | 77049174 ps |
| CPU time | 0.71 seconds |
| Started | Aug 21 08:08:05 AM UTC 24 |
| Finished | Aug 21 08:08:10 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1170408104 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1170408104 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_intr_test.2005720168 |
| Short name | T3694 |
| Test name | |
| Test status | |
| Simulation time | 44981196 ps |
| CPU time | 0.65 seconds |
| Started | Aug 21 08:08:04 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2005720168 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2005720168 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1661940656 |
| Short name | T3651 |
| Test name | |
| Test status | |
| Simulation time | 105525824 ps |
| CPU time | 0.92 seconds |
| Started | Aug 21 08:08:07 AM UTC 24 |
| Finished | Aug 21 08:08:09 AM UTC 24 |
| Peak memory | 217352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1661940656 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1661940656 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_errors.603567452 |
| Short name | T3699 |
| Test name | |
| Test status | |
| Simulation time | 124639474 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:08:04 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 217300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=603567452 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.603567452 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_intg_err.3880156422 |
| Short name | T3710 |
| Test name | |
| Test status | |
| Simulation time | 360516360 ps |
| CPU time | 2.29 seconds |
| Started | Aug 21 08:08:04 AM UTC 24 |
| Finished | Aug 21 08:08:17 AM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3880156422 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3880156422 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_aliasing.3493003207 |
| Short name | T3642 |
| Test name | |
| Test status | |
| Simulation time | 299642673 ps |
| CPU time | 2.97 seconds |
| Started | Aug 21 08:07:44 AM UTC 24 |
| Finished | Aug 21 08:08:02 AM UTC 24 |
| Peak memory | 218028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3493003207 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3493003207 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3178342020 |
| Short name | T3726 |
| Test name | |
| Test status | |
| Simulation time | 2044178673 ps |
| CPU time | 7.34 seconds |
| Started | Aug 21 08:07:44 AM UTC 24 |
| Finished | Aug 21 08:08:23 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3178342020 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3178342020 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1827286780 |
| Short name | T3697 |
| Test name | |
| Test status | |
| Simulation time | 164367387 ps |
| CPU time | 0.84 seconds |
| Started | Aug 21 08:07:44 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 219288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1827286780 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1827286780 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3742602004 |
| Short name | T3706 |
| Test name | |
| Test status | |
| Simulation time | 134445501 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:07:44 AM UTC 24 |
| Finished | Aug 21 08:08:17 AM UTC 24 |
| Peak memory | 227092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3742602004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.u sbdev_csr_mem_rw_with_rand_reset.3742602004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_rw.107573770 |
| Short name | T3648 |
| Test name | |
| Test status | |
| Simulation time | 63085038 ps |
| CPU time | 0.77 seconds |
| Started | Aug 21 08:07:44 AM UTC 24 |
| Finished | Aug 21 08:08:06 AM UTC 24 |
| Peak memory | 217288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=107573770 -assert nopostproc +UVM_TESTNAME=usbdev _base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.107573770 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_intr_test.3880362636 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 54457695 ps |
| CPU time | 0.62 seconds |
| Started | Aug 21 08:07:44 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 216984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3880362636 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3880362636 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_partial_access.1587778309 |
| Short name | T3638 |
| Test name | |
| Test status | |
| Simulation time | 237754077 ps |
| CPU time | 2.13 seconds |
| Started | Aug 21 08:07:44 AM UTC 24 |
| Finished | Aug 21 08:07:57 AM UTC 24 |
| Peak memory | 228328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1587778309 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1587778309 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_mem_partial_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_walk.4128045382 |
| Short name | T3637 |
| Test name | |
| Test status | |
| Simulation time | 326855435 ps |
| CPU time | 2.13 seconds |
| Started | Aug 21 08:07:44 AM UTC 24 |
| Finished | Aug 21 08:07:57 AM UTC 24 |
| Peak memory | 218096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4128045382 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.4128045382 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_mem_walk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3062507884 |
| Short name | T3641 |
| Test name | |
| Test status | |
| Simulation time | 268706128 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 08:07:44 AM UTC 24 |
| Finished | Aug 21 08:08:01 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3062507884 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3062507884 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_errors.3274727415 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 98782081 ps |
| CPU time | 2.34 seconds |
| Started | Aug 21 08:07:42 AM UTC 24 |
| Finished | Aug 21 08:07:47 AM UTC 24 |
| Peak memory | 228396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3274727415 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3274727415 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/20.usbdev_intr_test.3787658531 |
| Short name | T3686 |
| Test name | |
| Test status | |
| Simulation time | 39098902 ps |
| CPU time | 0.62 seconds |
| Started | Aug 21 08:08:07 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 216920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3787658531 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3787658531 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/21.usbdev_intr_test.3630942721 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 83640114 ps |
| CPU time | 0.65 seconds |
| Started | Aug 21 08:08:07 AM UTC 24 |
| Finished | Aug 21 08:08:09 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3630942721 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3630942721 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/22.usbdev_intr_test.2482941888 |
| Short name | T3690 |
| Test name | |
| Test status | |
| Simulation time | 45662328 ps |
| CPU time | 0.63 seconds |
| Started | Aug 21 08:08:07 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2482941888 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2482941888 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/23.usbdev_intr_test.116959924 |
| Short name | T3688 |
| Test name | |
| Test status | |
| Simulation time | 49812328 ps |
| CPU time | 0.61 seconds |
| Started | Aug 21 08:08:07 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 217044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=116959924 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.116959924 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/24.usbdev_intr_test.2413210396 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 43190040 ps |
| CPU time | 0.59 seconds |
| Started | Aug 21 08:08:07 AM UTC 24 |
| Finished | Aug 21 08:08:09 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2413210396 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2413210396 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/25.usbdev_intr_test.662661934 |
| Short name | T3704 |
| Test name | |
| Test status | |
| Simulation time | 49443261 ps |
| CPU time | 0.61 seconds |
| Started | Aug 21 08:08:08 AM UTC 24 |
| Finished | Aug 21 08:08:17 AM UTC 24 |
| Peak memory | 217044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=662661934 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.662661934 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/26.usbdev_intr_test.192687560 |
| Short name | T3705 |
| Test name | |
| Test status | |
| Simulation time | 74718029 ps |
| CPU time | 0.65 seconds |
| Started | Aug 21 08:08:08 AM UTC 24 |
| Finished | Aug 21 08:08:17 AM UTC 24 |
| Peak memory | 217044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=192687560 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.192687560 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/27.usbdev_intr_test.2807740320 |
| Short name | T3728 |
| Test name | |
| Test status | |
| Simulation time | 79142523 ps |
| CPU time | 0.65 seconds |
| Started | Aug 21 08:08:09 AM UTC 24 |
| Finished | Aug 21 08:08:31 AM UTC 24 |
| Peak memory | 219044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2807740320 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2807740320 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/28.usbdev_intr_test.4170479968 |
| Short name | T3676 |
| Test name | |
| Test status | |
| Simulation time | 33120423 ps |
| CPU time | 0.62 seconds |
| Started | Aug 21 08:08:11 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4170479968 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.4170479968 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/29.usbdev_intr_test.2096832713 |
| Short name | T3673 |
| Test name | |
| Test status | |
| Simulation time | 40805626 ps |
| CPU time | 0.6 seconds |
| Started | Aug 21 08:08:11 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2096832713 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2096832713 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_aliasing.1944648581 |
| Short name | T3625 |
| Test name | |
| Test status | |
| Simulation time | 236981482 ps |
| CPU time | 1.87 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:51 AM UTC 24 |
| Peak memory | 217240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1944648581 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1944648581 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3221764269 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 712650669 ps |
| CPU time | 4.07 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:53 AM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3221764269 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3221764269 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_hw_reset.38757789 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 109892901 ps |
| CPU time | 0.8 seconds |
| Started | Aug 21 08:07:45 AM UTC 24 |
| Finished | Aug 21 08:07:50 AM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38757789 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.38757789 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1728273785 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 202379633 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:51 AM UTC 24 |
| Peak memory | 231492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1728273785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.u sbdev_csr_mem_rw_with_rand_reset.1728273785 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.2386265243 |
| Short name | T3695 |
| Test name | |
| Test status | |
| Simulation time | 38696883 ps |
| CPU time | 0.62 seconds |
| Started | Aug 21 08:07:44 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 216988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2386265243 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2386265243 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_partial_access.2399152409 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 82722442 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:07:45 AM UTC 24 |
| Finished | Aug 21 08:07:51 AM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2399152409 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2399152409 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_mem_partial_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_walk.3152827065 |
| Short name | T3713 |
| Test name | |
| Test status | |
| Simulation time | 166468997 ps |
| CPU time | 3.26 seconds |
| Started | Aug 21 08:07:44 AM UTC 24 |
| Finished | Aug 21 08:08:19 AM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3152827065 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3152827065 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_mem_walk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2289463694 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 94258628 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:50 AM UTC 24 |
| Peak memory | 217168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2289463694 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2289463694 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_errors.2545519891 |
| Short name | T3712 |
| Test name | |
| Test status | |
| Simulation time | 286183127 ps |
| CPU time | 2.58 seconds |
| Started | Aug 21 08:07:44 AM UTC 24 |
| Finished | Aug 21 08:08:18 AM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2545519891 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2545519891 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.1243799064 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1723956065 ps |
| CPU time | 5.12 seconds |
| Started | Aug 21 08:07:44 AM UTC 24 |
| Finished | Aug 21 08:08:10 AM UTC 24 |
| Peak memory | 218028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1243799064 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1243799064 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/30.usbdev_intr_test.3086898509 |
| Short name | T3678 |
| Test name | |
| Test status | |
| Simulation time | 48482178 ps |
| CPU time | 0.64 seconds |
| Started | Aug 21 08:08:11 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3086898509 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3086898509 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/31.usbdev_intr_test.1298083050 |
| Short name | T3677 |
| Test name | |
| Test status | |
| Simulation time | 43644516 ps |
| CPU time | 0.63 seconds |
| Started | Aug 21 08:08:11 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1298083050 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1298083050 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/32.usbdev_intr_test.2741937119 |
| Short name | T3685 |
| Test name | |
| Test status | |
| Simulation time | 39870382 ps |
| CPU time | 0.62 seconds |
| Started | Aug 21 08:08:11 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2741937119 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2741937119 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/33.usbdev_intr_test.3111549522 |
| Short name | T3667 |
| Test name | |
| Test status | |
| Simulation time | 43859096 ps |
| CPU time | 0.62 seconds |
| Started | Aug 21 08:08:12 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 216980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3111549522 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3111549522 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/34.usbdev_intr_test.2717118434 |
| Short name | T3669 |
| Test name | |
| Test status | |
| Simulation time | 54425304 ps |
| CPU time | 0.66 seconds |
| Started | Aug 21 08:08:13 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2717118434 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2717118434 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/35.usbdev_intr_test.3315835566 |
| Short name | T3671 |
| Test name | |
| Test status | |
| Simulation time | 43653641 ps |
| CPU time | 0.64 seconds |
| Started | Aug 21 08:08:13 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3315835566 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3315835566 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/36.usbdev_intr_test.3679119734 |
| Short name | T3665 |
| Test name | |
| Test status | |
| Simulation time | 42765481 ps |
| CPU time | 0.6 seconds |
| Started | Aug 21 08:08:13 AM UTC 24 |
| Finished | Aug 21 08:08:14 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3679119734 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3679119734 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/37.usbdev_intr_test.1220749328 |
| Short name | T3675 |
| Test name | |
| Test status | |
| Simulation time | 45373903 ps |
| CPU time | 0.66 seconds |
| Started | Aug 21 08:08:13 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1220749328 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1220749328 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/38.usbdev_intr_test.1129318873 |
| Short name | T3672 |
| Test name | |
| Test status | |
| Simulation time | 36033287 ps |
| CPU time | 0.59 seconds |
| Started | Aug 21 08:08:13 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 216980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1129318873 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1129318873 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/39.usbdev_intr_test.3396269887 |
| Short name | T3683 |
| Test name | |
| Test status | |
| Simulation time | 78638521 ps |
| CPU time | 0.68 seconds |
| Started | Aug 21 08:08:13 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3396269887 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3396269887 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_aliasing.975176832 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 197118266 ps |
| CPU time | 1.89 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:51 AM UTC 24 |
| Peak memory | 217364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=975176832 -assert nopostproc +UVM_TESTNAME= usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.975176832 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2932443444 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 780577275 ps |
| CPU time | 7.33 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:57 AM UTC 24 |
| Peak memory | 218004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2932443444 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2932443444 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3458459293 |
| Short name | T3623 |
| Test name | |
| Test status | |
| Simulation time | 148187469 ps |
| CPU time | 0.79 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:50 AM UTC 24 |
| Peak memory | 217292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3458459293 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3458459293 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.123216121 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 211503605 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:51 AM UTC 24 |
| Peak memory | 235596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=123216121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.us bdev_csr_mem_rw_with_rand_reset.123216121 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_rw.3014159708 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 45562036 ps |
| CPU time | 0.69 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:50 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3014159708 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3014159708 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_intr_test.3782128984 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 29360812 ps |
| CPU time | 0.59 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:50 AM UTC 24 |
| Peak memory | 216984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3782128984 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3782128984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_partial_access.2854428208 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 193312549 ps |
| CPU time | 1.99 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:51 AM UTC 24 |
| Peak memory | 227464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2854428208 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2854428208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_mem_partial_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_walk.1443940203 |
| Short name | T3626 |
| Test name | |
| Test status | |
| Simulation time | 382394442 ps |
| CPU time | 2.37 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:52 AM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1443940203 -assert nopostproc +UVM_TESTNAME =usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1443940203 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_mem_walk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2455611665 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 112077385 ps |
| CPU time | 0.92 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:50 AM UTC 24 |
| Peak memory | 217292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2455611665 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2455611665 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_errors.3617722998 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 98425154 ps |
| CPU time | 1.71 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:51 AM UTC 24 |
| Peak memory | 217232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3617722998 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3617722998 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_intg_err.3569610553 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 469192055 ps |
| CPU time | 2.09 seconds |
| Started | Aug 21 08:07:47 AM UTC 24 |
| Finished | Aug 21 08:07:51 AM UTC 24 |
| Peak memory | 218028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3569610553 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3569610553 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/40.usbdev_intr_test.1126073974 |
| Short name | T3674 |
| Test name | |
| Test status | |
| Simulation time | 42028166 ps |
| CPU time | 0.6 seconds |
| Started | Aug 21 08:08:13 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 216972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1126073974 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1126073974 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/41.usbdev_intr_test.2197841085 |
| Short name | T3682 |
| Test name | |
| Test status | |
| Simulation time | 70884744 ps |
| CPU time | 0.62 seconds |
| Started | Aug 21 08:08:13 AM UTC 24 |
| Finished | Aug 21 08:08:15 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2197841085 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2197841085 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/42.usbdev_intr_test.207290467 |
| Short name | T3691 |
| Test name | |
| Test status | |
| Simulation time | 60581255 ps |
| CPU time | 0.64 seconds |
| Started | Aug 21 08:08:14 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 217044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=207290467 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.207290467 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/43.usbdev_intr_test.1904188554 |
| Short name | T3692 |
| Test name | |
| Test status | |
| Simulation time | 35067685 ps |
| CPU time | 0.6 seconds |
| Started | Aug 21 08:08:14 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 216980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1904188554 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1904188554 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/44.usbdev_intr_test.3744495590 |
| Short name | T3693 |
| Test name | |
| Test status | |
| Simulation time | 54368280 ps |
| CPU time | 0.65 seconds |
| Started | Aug 21 08:08:14 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3744495590 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3744495590 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/45.usbdev_intr_test.2686009642 |
| Short name | T3679 |
| Test name | |
| Test status | |
| Simulation time | 45743487 ps |
| CPU time | 0.61 seconds |
| Started | Aug 21 08:08:15 AM UTC 24 |
| Finished | Aug 21 08:08:20 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2686009642 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2686009642 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/46.usbdev_intr_test.1683114455 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 46619386 ps |
| CPU time | 0.62 seconds |
| Started | Aug 21 08:08:18 AM UTC 24 |
| Finished | Aug 21 08:08:20 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683114455 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1683114455 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/47.usbdev_intr_test.2912659979 |
| Short name | T3680 |
| Test name | |
| Test status | |
| Simulation time | 68792323 ps |
| CPU time | 0.62 seconds |
| Started | Aug 21 08:08:18 AM UTC 24 |
| Finished | Aug 21 08:08:20 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2912659979 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2912659979 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/48.usbdev_intr_test.2187190192 |
| Short name | T3684 |
| Test name | |
| Test status | |
| Simulation time | 77074587 ps |
| CPU time | 0.65 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:20 AM UTC 24 |
| Peak memory | 216980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2187190192 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2187190192 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/49.usbdev_intr_test.759244433 |
| Short name | T3668 |
| Test name | |
| Test status | |
| Simulation time | 95821067 ps |
| CPU time | 0.68 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:20 AM UTC 24 |
| Peak memory | 217044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=759244433 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.759244433 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1943666493 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 94912970 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:07:49 AM UTC 24 |
| Finished | Aug 21 08:07:51 AM UTC 24 |
| Peak memory | 227472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1943666493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.u sbdev_csr_mem_rw_with_rand_reset.1943666493 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_rw.1285980195 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 77171383 ps |
| CPU time | 0.71 seconds |
| Started | Aug 21 08:07:49 AM UTC 24 |
| Finished | Aug 21 08:07:50 AM UTC 24 |
| Peak memory | 217196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1285980195 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1285980195 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1655156835 |
| Short name | T3624 |
| Test name | |
| Test status | |
| Simulation time | 67161105 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 08:07:49 AM UTC 24 |
| Finished | Aug 21 08:07:51 AM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1655156835 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1655156835 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_errors.1270928766 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 166429285 ps |
| CPU time | 1.73 seconds |
| Started | Aug 21 08:07:49 AM UTC 24 |
| Finished | Aug 21 08:07:52 AM UTC 24 |
| Peak memory | 217168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1270928766 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1270928766 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_intg_err.1175773577 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 358695122 ps |
| CPU time | 2.18 seconds |
| Started | Aug 21 08:07:49 AM UTC 24 |
| Finished | Aug 21 08:07:52 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1175773577 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1175773577 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3241387040 |
| Short name | T3661 |
| Test name | |
| Test status | |
| Simulation time | 108255903 ps |
| CPU time | 1.9 seconds |
| Started | Aug 21 08:07:51 AM UTC 24 |
| Finished | Aug 21 08:08:11 AM UTC 24 |
| Peak memory | 227160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3241387040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.u sbdev_csr_mem_rw_with_rand_reset.3241387040 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_rw.4170872800 |
| Short name | T3639 |
| Test name | |
| Test status | |
| Simulation time | 78678268 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 08:07:51 AM UTC 24 |
| Finished | Aug 21 08:08:00 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4170872800 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.4170872800 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_intr_test.231042284 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 36609959 ps |
| CPU time | 0.59 seconds |
| Started | Aug 21 08:07:51 AM UTC 24 |
| Finished | Aug 21 08:08:00 AM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=231042284 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.231042284 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2793693927 |
| Short name | T3640 |
| Test name | |
| Test status | |
| Simulation time | 79803189 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:07:51 AM UTC 24 |
| Finished | Aug 21 08:08:00 AM UTC 24 |
| Peak memory | 217420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2793693927 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2793693927 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_intg_err.2035425058 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 670280379 ps |
| CPU time | 4.01 seconds |
| Started | Aug 21 08:07:51 AM UTC 24 |
| Finished | Aug 21 08:08:03 AM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2035425058 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2035425058 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2970631354 |
| Short name | T3636 |
| Test name | |
| Test status | |
| Simulation time | 155434993 ps |
| CPU time | 1.67 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:57 AM UTC 24 |
| Peak memory | 227448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2970631354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.u sbdev_csr_mem_rw_with_rand_reset.2970631354 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_rw.3740947455 |
| Short name | T3700 |
| Test name | |
| Test status | |
| Simulation time | 96898511 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 08:07:51 AM UTC 24 |
| Finished | Aug 21 08:08:17 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3740947455 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3740947455 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_intr_test.1520030466 |
| Short name | T3698 |
| Test name | |
| Test status | |
| Simulation time | 36188068 ps |
| CPU time | 0.63 seconds |
| Started | Aug 21 08:07:51 AM UTC 24 |
| Finished | Aug 21 08:08:16 AM UTC 24 |
| Peak memory | 216988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1520030466 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1520030466 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2912401581 |
| Short name | T3707 |
| Test name | |
| Test status | |
| Simulation time | 341960579 ps |
| CPU time | 1.76 seconds |
| Started | Aug 21 08:07:51 AM UTC 24 |
| Finished | Aug 21 08:08:17 AM UTC 24 |
| Peak memory | 217292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2912401581 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2912401581 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_errors.3034425652 |
| Short name | T3664 |
| Test name | |
| Test status | |
| Simulation time | 286696087 ps |
| CPU time | 2.68 seconds |
| Started | Aug 21 08:07:51 AM UTC 24 |
| Finished | Aug 21 08:08:12 AM UTC 24 |
| Peak memory | 232556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3034425652 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3034425652 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_intg_err.3803763880 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1037872715 ps |
| CPU time | 3.67 seconds |
| Started | Aug 21 08:07:51 AM UTC 24 |
| Finished | Aug 21 08:08:13 AM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3803763880 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3803763880 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2221827502 |
| Short name | T3629 |
| Test name | |
| Test status | |
| Simulation time | 129459608 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:55 AM UTC 24 |
| Peak memory | 227396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2221827502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.u sbdev_csr_mem_rw_with_rand_reset.2221827502 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_rw.1441386871 |
| Short name | T3632 |
| Test name | |
| Test status | |
| Simulation time | 55258639 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1441386871 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1441386871 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_intr_test.3403338092 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 44629562 ps |
| CPU time | 0.63 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 216984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3403338092 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3403338092 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1335570304 |
| Short name | T3630 |
| Test name | |
| Test status | |
| Simulation time | 185997756 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:55 AM UTC 24 |
| Peak memory | 217240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1335570304 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1335570304 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_errors.822284711 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 143876135 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:57 AM UTC 24 |
| Peak memory | 217228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=822284711 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.822284711 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_intg_err.3753282600 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 698890794 ps |
| CPU time | 2.67 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:58 AM UTC 24 |
| Peak memory | 218300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3753282600 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3753282600 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2176853550 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 227842947 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 227396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns =10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2176853550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.u sbdev_csr_mem_rw_with_rand_reset.2176853550 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_rw.2976688027 |
| Short name | T3628 |
| Test name | |
| Test status | |
| Simulation time | 71416035 ps |
| CPU time | 0.87 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:55 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2976688027 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2976688027 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2292266370 |
| Short name | T3633 |
| Test name | |
| Test status | |
| Simulation time | 555503695 ps |
| CPU time | 2.03 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 218068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2292266370 -assert nopostproc + UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2292266370 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_tl_errors.3910724648 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 155492117 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 217192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3910724648 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3910724648 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_tl_intg_err.2546624938 |
| Short name | T3634 |
| Test name | |
| Test status | |
| Simulation time | 377587480 ps |
| CPU time | 2.21 seconds |
| Started | Aug 21 08:07:53 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2546624938 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2546624938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.1833486545 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 21241602727 ps |
| CPU time | 27.98 seconds |
| Started | Aug 21 07:49:22 AM UTC 24 |
| Finished | Aug 21 07:49:58 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1833486545 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.1833486545 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_resume.3812007967 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 26418377262 ps |
| CPU time | 37.38 seconds |
| Started | Aug 21 07:49:23 AM UTC 24 |
| Finished | Aug 21 07:50:03 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3812007967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbde v_aon_wake_resume.3812007967 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_av_buffer.4164849971 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 210801783 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:49:23 AM UTC 24 |
| Finished | Aug 21 07:49:37 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4164849971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4164849971 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_clear.3258559811 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 181888248 ps |
| CPU time | 0.79 seconds |
| Started | Aug 21 07:49:25 AM UTC 24 |
| Finished | Aug 21 07:49:30 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3258559811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.3258559811 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_enable.68914783 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 34608089 ps |
| CPU time | 0.71 seconds |
| Started | Aug 21 07:49:28 AM UTC 24 |
| Finished | Aug 21 07:49:30 AM UTC 24 |
| Peak memory | 216360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=68914783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.68914783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_freq_hiclk.4145614208 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 87171670276 ps |
| CPU time | 168.73 seconds |
| Started | Aug 21 07:49:31 AM UTC 24 |
| Finished | Aug 21 07:52:22 AM UTC 24 |
| Peak memory | 218240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4145614208 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.4145614208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_freq_hiclk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_freq_hiclk_max.2335032742 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 88307784299 ps |
| CPU time | 154.52 seconds |
| Started | Aug 21 07:49:31 AM UTC 24 |
| Finished | Aug 21 07:52:08 AM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_ freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2335032742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_p hase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2335032742 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_freq_hiclk_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_freq_loclk.3316371316 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 94106509714 ps |
| CPU time | 158.15 seconds |
| Started | Aug 21 07:49:31 AM UTC 24 |
| Finished | Aug 21 07:52:12 AM UTC 24 |
| Peak memory | 218388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3316371316 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.3316371316 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_freq_loclk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_freq_loclk_max.758851736 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 89139609479 ps |
| CPU time | 137.52 seconds |
| Started | Aug 21 07:49:32 AM UTC 24 |
| Finished | Aug 21 07:51:53 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_d rifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=758851736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_ph ase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.758851736 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_freq_loclk_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_freq_phase.2577615752 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 106126876693 ps |
| CPU time | 206.87 seconds |
| Started | Aug 21 07:49:32 AM UTC 24 |
| Finished | Aug 21 07:53:05 AM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2577615752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.2577615752 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_freq_phase/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_in_iso.2227092372 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 210324906 ps |
| CPU time | 1.69 seconds |
| Started | Aug 21 07:49:33 AM UTC 24 |
| Finished | Aug 21 07:49:36 AM UTC 24 |
| Peak memory | 226632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2227092372 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2227092372 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_in_stall.2156260102 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 134245405 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 07:49:33 AM UTC 24 |
| Finished | Aug 21 07:49:35 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2156260102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2156260102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_in_trans.3182063938 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 204786543 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:49:33 AM UTC 24 |
| Finished | Aug 21 07:49:35 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3182063938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3182063938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_iso_retraction.1311412664 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 6669388556 ps |
| CPU time | 38.18 seconds |
| Started | Aug 21 07:49:34 AM UTC 24 |
| Finished | Aug 21 07:50:14 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1311412664 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.1311412664 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_link_in_err.633605325 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 219829653 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:49:34 AM UTC 24 |
| Finished | Aug 21 07:49:37 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=633605325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.633605325 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_link_out_err.1521133371 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 398994802 ps |
| CPU time | 2.47 seconds |
| Started | Aug 21 07:49:34 AM UTC 24 |
| Finished | Aug 21 07:49:38 AM UTC 24 |
| Peak memory | 218072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1521133371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.1521133371 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_link_out_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_link_resume.531165400 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 29789648553 ps |
| CPU time | 58.08 seconds |
| Started | Aug 21 07:49:35 AM UTC 24 |
| Finished | Aug 21 07:50:35 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=531165400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.531165400 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_link_suspend.1436981433 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11077855718 ps |
| CPU time | 16.43 seconds |
| Started | Aug 21 07:49:35 AM UTC 24 |
| Finished | Aug 21 07:49:53 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1436981433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1436981433 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_max_inter_pkt_delay.3299747637 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2059105567 ps |
| CPU time | 52.46 seconds |
| Started | Aug 21 07:49:36 AM UTC 24 |
| Finished | Aug 21 07:50:29 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3299747637 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3299747637 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_in_transaction.3365126170 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 241309626 ps |
| CPU time | 1.69 seconds |
| Started | Aug 21 07:49:37 AM UTC 24 |
| Finished | Aug 21 07:49:39 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3365126170 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3365126170 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_out_transaction.3760173351 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 193633027 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:49:37 AM UTC 24 |
| Finished | Aug 21 07:49:39 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3760173351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3760173351 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_max_usb_traffic.291501274 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2894752666 ps |
| CPU time | 76.57 seconds |
| Started | Aug 21 07:49:38 AM UTC 24 |
| Finished | Aug 21 07:50:56 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=291501274 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.291501274 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_min_inter_pkt_delay.348254966 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2828883453 ps |
| CPU time | 30.96 seconds |
| Started | Aug 21 07:49:38 AM UTC 24 |
| Finished | Aug 21 07:50:10 AM UTC 24 |
| Peak memory | 229668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=348254966 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.348254966 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_in_transaction.2848226471 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 152655078 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:49:38 AM UTC 24 |
| Finished | Aug 21 07:49:40 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2848226471 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.2848226471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_out_transaction.3601477286 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 162093859 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:49:38 AM UTC 24 |
| Finished | Aug 21 07:49:40 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3601477286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3601477286 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3812728432 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 408191380 ps |
| CPU time | 2.29 seconds |
| Started | Aug 21 07:49:38 AM UTC 24 |
| Finished | Aug 21 07:49:41 AM UTC 24 |
| Peak memory | 218140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3812728432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3812728432 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_out_iso.1059202540 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 224926654 ps |
| CPU time | 1.75 seconds |
| Started | Aug 21 07:49:39 AM UTC 24 |
| Finished | Aug 21 07:49:42 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1059202540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.1059202540 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_out_stall.303850096 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 191400520 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 07:49:39 AM UTC 24 |
| Finished | Aug 21 07:49:41 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=303850096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.303850096 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_out_trans_nak.3841010666 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 261531336 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 07:49:40 AM UTC 24 |
| Finished | Aug 21 07:49:43 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3841010666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3841010666 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_pending_in_trans.3834461810 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 153035091 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:49:40 AM UTC 24 |
| Finished | Aug 21 07:49:43 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3834461810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3834461810 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2119712939 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 169251855 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:49:42 AM UTC 24 |
| Finished | Aug 21 07:49:44 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2119712939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2119712939 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_phy_config_eop_single_bit_handling/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rand_bus_type.3649274635 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 206653815 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:49:42 AM UTC 24 |
| Finished | Aug 21 07:49:44 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3649274635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_ 2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.3649274635 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_phy_config_rand_bus_type/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rx_dp_dn.2444632910 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 260941225 ps |
| CPU time | 1.73 seconds |
| Started | Aug 21 07:49:42 AM UTC 24 |
| Finished | Aug 21 07:49:44 AM UTC 24 |
| Peak memory | 216580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2444632910 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_202 4_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.2444632910 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_phy_config_rx_dp_dn/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1286908708 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 186530256 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:49:43 AM UTC 24 |
| Finished | Aug 21 07:49:45 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1286908708 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_202 4_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.1286908708 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_phy_config_tx_use_d_se0/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.3747692493 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 55907000 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 07:49:43 AM UTC 24 |
| Finished | Aug 21 07:49:45 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3747692493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3747692493 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_sent.3914037757 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 194113590 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:49:43 AM UTC 24 |
| Finished | Aug 21 07:49:46 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3914037757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3914037757 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_disconnects.2472411939 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2850439978 ps |
| CPU time | 72.25 seconds |
| Started | Aug 21 07:49:45 AM UTC 24 |
| Finished | Aug 21 07:50:59 AM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2472411939 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2472411939 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_rand_suspends.2030993493 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 6520362710 ps |
| CPU time | 25.31 seconds |
| Started | Aug 21 07:49:45 AM UTC 24 |
| Finished | Aug 21 07:50:12 AM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2030993493 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.2030993493 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_rand_suspends/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_in_transaction.4155725147 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 238554065 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 07:49:44 AM UTC 24 |
| Finished | Aug 21 07:49:47 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4155725147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.4155725147 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_out_transaction.2405033883 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 233516885 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 07:49:45 AM UTC 24 |
| Finished | Aug 21 07:49:48 AM UTC 24 |
| Peak memory | 216592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2405033883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.2405033883 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_resume_link_active.240503264 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 20173108934 ps |
| CPU time | 27.82 seconds |
| Started | Aug 21 07:49:45 AM UTC 24 |
| Finished | Aug 21 07:50:14 AM UTC 24 |
| Peak memory | 218104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=240503264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.240503264 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_rx_full.2526453188 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 248483310 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:49:47 AM UTC 24 |
| Finished | Aug 21 07:49:49 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2526453188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.2526453188 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority_over_stall_response.2701362699 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 209824904 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 07:49:47 AM UTC 24 |
| Finished | Aug 21 07:49:49 AM UTC 24 |
| Peak memory | 216572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2701362699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.2701362699 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_setup_priority_over_stall_response/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_setup_stage.3900425048 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 159517777 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:49:47 AM UTC 24 |
| Finished | Aug 21 07:49:49 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3900425048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3900425048 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_setup_trans_ignored.1965390756 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 181656082 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:49:48 AM UTC 24 |
| Finished | Aug 21 07:49:50 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1965390756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1965390756 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_smoke.1480597635 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 259361237 ps |
| CPU time | 1.75 seconds |
| Started | Aug 21 07:49:48 AM UTC 24 |
| Finished | Aug 21 07:49:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1480597635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1480597635 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_spurious_pids_ignored.2392434538 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1850974342 ps |
| CPU time | 16.88 seconds |
| Started | Aug 21 07:49:49 AM UTC 24 |
| Finished | Aug 21 07:50:07 AM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2392434538 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.2392434538 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_stall_trans.3690825695 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 233318940 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 07:49:54 AM UTC 24 |
| Finished | Aug 21 07:49:57 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3690825695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3690825695 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_stream_len_max.3960281257 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1264204470 ps |
| CPU time | 3.64 seconds |
| Started | Aug 21 07:49:54 AM UTC 24 |
| Finished | Aug 21 07:49:59 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3960281257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.3960281257 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_streaming_out.3608170432 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2623852677 ps |
| CPU time | 21.06 seconds |
| Started | Aug 21 07:49:54 AM UTC 24 |
| Finished | Aug 21 07:50:16 AM UTC 24 |
| Peak memory | 235184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3608170432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.3608170432 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.1387613853 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 9267291748 ps |
| CPU time | 59.55 seconds |
| Started | Aug 21 07:49:54 AM UTC 24 |
| Finished | Aug 21 07:50:56 AM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_ disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1387613853 -assert nopo stproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.1387613853 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_stress_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_timeout_missing_host_handshake.2912904141 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 974017355 ps |
| CPU time | 18.06 seconds |
| Started | Aug 21 07:49:26 AM UTC 24 |
| Finished | Aug 21 07:49:49 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2912904141 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_ host_handshake.2912904141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/0.usbdev_tx_rx_disruption.1148535343 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 684019506 ps |
| CPU time | 1.85 seconds |
| Started | Aug 21 07:49:54 AM UTC 24 |
| Finished | Aug 21 07:49:57 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1148535343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.usbdev_tx_rx_disruption.1148535343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/0.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_alert_test.1912452075 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 32408952 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 07:50:27 AM UTC 24 |
| Finished | Aug 21 07:50:29 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1912452075 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1912452075 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_disconnect.2234346045 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6188428842 ps |
| CPU time | 13.03 seconds |
| Started | Aug 21 07:49:56 AM UTC 24 |
| Finished | Aug 21 07:50:11 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2234346045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbde v_aon_wake_disconnect.2234346045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_resume.2955652210 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 25805276468 ps |
| CPU time | 33.03 seconds |
| Started | Aug 21 07:49:56 AM UTC 24 |
| Finished | Aug 21 07:50:31 AM UTC 24 |
| Peak memory | 228388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2955652210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbde v_aon_wake_resume.2955652210 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_av_buffer.4005802695 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 169311294 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:49:56 AM UTC 24 |
| Finished | Aug 21 07:49:59 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4005802695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.4005802695 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_av_empty.2436883420 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 154625996 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:49:56 AM UTC 24 |
| Finished | Aug 21 07:49:59 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2436883420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.2436883420 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_av_empty/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_av_overflow.167044496 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 153235519 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 07:49:57 AM UTC 24 |
| Finished | Aug 21 07:49:59 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=167044496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.167044496 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_av_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_bitstuff_err.2604495813 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 152016239 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 07:49:57 AM UTC 24 |
| Finished | Aug 21 07:49:59 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2604495813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2604495813 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_clear.2664494120 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 346471172 ps |
| CPU time | 1.89 seconds |
| Started | Aug 21 07:49:57 AM UTC 24 |
| Finished | Aug 21 07:50:00 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2664494120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2664494120 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_restore.3696608860 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1270450984 ps |
| CPU time | 6.22 seconds |
| Started | Aug 21 07:50:00 AM UTC 24 |
| Finished | Aug 21 07:50:08 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3696608860 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.3696608860 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_device_timeout.957877821 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 3188700757 ps |
| CPU time | 25.37 seconds |
| Started | Aug 21 07:50:00 AM UTC 24 |
| Finished | Aug 21 07:50:27 AM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=957877821 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.957877821 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_disable_endpoint.1102057883 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 853811593 ps |
| CPU time | 3.67 seconds |
| Started | Aug 21 07:50:01 AM UTC 24 |
| Finished | Aug 21 07:50:06 AM UTC 24 |
| Peak memory | 218104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1102057883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.1102057883 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_disconnected.2519697424 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 165275023 ps |
| CPU time | 1.16 seconds |
| Started | Aug 21 07:50:01 AM UTC 24 |
| Finished | Aug 21 07:50:04 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2519697424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.2519697424 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_enable.2770935546 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 50377898 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 07:50:01 AM UTC 24 |
| Finished | Aug 21 07:50:03 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2770935546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2770935546 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_access.934191058 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 982791581 ps |
| CPU time | 2.81 seconds |
| Started | Aug 21 07:50:01 AM UTC 24 |
| Finished | Aug 21 07:50:05 AM UTC 24 |
| Peak memory | 218148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=934191058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.934191058 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_rst.161746142 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 322203087 ps |
| CPU time | 3.26 seconds |
| Started | Aug 21 07:50:01 AM UTC 24 |
| Finished | Aug 21 07:50:06 AM UTC 24 |
| Peak memory | 218104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=161746142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.161746142 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_freq_hiclk.3779468211 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 100196873134 ps |
| CPU time | 173.84 seconds |
| Started | Aug 21 07:50:01 AM UTC 24 |
| Finished | Aug 21 07:52:58 AM UTC 24 |
| Peak memory | 218304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3779468211 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.3779468211 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_freq_hiclk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_freq_hiclk_max.1644908821 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 117169766138 ps |
| CPU time | 229.22 seconds |
| Started | Aug 21 07:50:01 AM UTC 24 |
| Finished | Aug 21 07:53:54 AM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_ freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1644908821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_p hase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.1644908821 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_freq_hiclk_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_freq_loclk.1942978857 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 113115723302 ps |
| CPU time | 191.43 seconds |
| Started | Aug 21 07:50:03 AM UTC 24 |
| Finished | Aug 21 07:53:18 AM UTC 24 |
| Peak memory | 218320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1942978857 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.1942978857 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_freq_loclk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_freq_loclk_max.3990472651 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 99121938516 ps |
| CPU time | 177.38 seconds |
| Started | Aug 21 07:50:05 AM UTC 24 |
| Finished | Aug 21 07:53:06 AM UTC 24 |
| Peak memory | 217904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_d rifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3990472651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_p hase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.3990472651 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_freq_loclk_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_freq_phase.136320675 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 100145581133 ps |
| CPU time | 187.72 seconds |
| Started | Aug 21 07:50:05 AM UTC 24 |
| Finished | Aug 21 07:53:16 AM UTC 24 |
| Peak memory | 217904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=136320675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.136320675 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_freq_phase/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_in_iso.1129912785 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 195788970 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 07:50:05 AM UTC 24 |
| Finished | Aug 21 07:50:08 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1129912785 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1129912785 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_in_stall.1801314097 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 139230821 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:50:06 AM UTC 24 |
| Finished | Aug 21 07:50:08 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1801314097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1801314097 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_in_trans.2038248045 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 186901271 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:50:06 AM UTC 24 |
| Finished | Aug 21 07:50:08 AM UTC 24 |
| Peak memory | 216364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2038248045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2038248045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_invalid_sync.2545452491 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 4969919203 ps |
| CPU time | 37.45 seconds |
| Started | Aug 21 07:50:05 AM UTC 24 |
| Finished | Aug 21 07:50:44 AM UTC 24 |
| Peak memory | 235172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2545452491 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2545452491 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_iso_retraction.887053934 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 10897754384 ps |
| CPU time | 127.83 seconds |
| Started | Aug 21 07:50:06 AM UTC 24 |
| Finished | Aug 21 07:52:16 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=887053934 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.887053934 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_link_in_err.3589774618 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 232555443 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 07:50:06 AM UTC 24 |
| Finished | Aug 21 07:50:09 AM UTC 24 |
| Peak memory | 216360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3589774618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3589774618 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_link_resume.1343075434 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 12508666259 ps |
| CPU time | 22.69 seconds |
| Started | Aug 21 07:50:06 AM UTC 24 |
| Finished | Aug 21 07:50:30 AM UTC 24 |
| Peak memory | 218268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1343075434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.1343075434 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_link_suspend.2539502503 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 9519940339 ps |
| CPU time | 18.61 seconds |
| Started | Aug 21 07:50:08 AM UTC 24 |
| Finished | Aug 21 07:50:28 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2539502503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.2539502503 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_max_inter_pkt_delay.2224798460 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 3294710170 ps |
| CPU time | 84.91 seconds |
| Started | Aug 21 07:50:08 AM UTC 24 |
| Finished | Aug 21 07:51:35 AM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2224798460 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.2224798460 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_in_transaction.3352124657 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 262585397 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 07:50:08 AM UTC 24 |
| Finished | Aug 21 07:50:11 AM UTC 24 |
| Peak memory | 216296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3352124657 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3352124657 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_out_transaction.3596365176 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 195859553 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 07:50:08 AM UTC 24 |
| Finished | Aug 21 07:50:11 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3596365176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3596365176 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_max_non_iso_usb_traffic.61004595 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2943711165 ps |
| CPU time | 27.78 seconds |
| Started | Aug 21 07:50:08 AM UTC 24 |
| Finished | Aug 21 07:50:37 AM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=61004595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_202 4_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_non_iso_usb_traffic.61004595 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_max_usb_traffic.3706610541 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2061385888 ps |
| CPU time | 52.05 seconds |
| Started | Aug 21 07:50:10 AM UTC 24 |
| Finished | Aug 21 07:51:04 AM UTC 24 |
| Peak memory | 235124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3706610541 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.3706610541 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_min_inter_pkt_delay.2471131533 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 3348880982 ps |
| CPU time | 106.72 seconds |
| Started | Aug 21 07:50:10 AM UTC 24 |
| Finished | Aug 21 07:51:59 AM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2471131533 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.2471131533 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_in_transaction.1433080862 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 176839474 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:50:11 AM UTC 24 |
| Finished | Aug 21 07:50:13 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1433080862 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1433080862 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_out_transaction.59987993 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 181059204 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 07:50:11 AM UTC 24 |
| Finished | Aug 21 07:50:13 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=59987993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_ 2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.59987993 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_out_iso.1239307034 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 179022893 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 07:50:13 AM UTC 24 |
| Finished | Aug 21 07:50:15 AM UTC 24 |
| Peak memory | 216060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1239307034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1239307034 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_out_stall.2415819975 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 165584601 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:50:13 AM UTC 24 |
| Finished | Aug 21 07:50:15 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2415819975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2415819975 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_out_trans_nak.2431210288 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 158702133 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:50:13 AM UTC 24 |
| Finished | Aug 21 07:50:15 AM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2431210288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2431210288 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_pending_in_trans.2176999978 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 156931864 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:50:13 AM UTC 24 |
| Finished | Aug 21 07:50:15 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2176999978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2176999978 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_pinflip.1416425977 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 176022972 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 07:50:13 AM UTC 24 |
| Finished | Aug 21 07:50:16 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1416425977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.1416425977 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_rand_bus_type.3544050815 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 234284646 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 07:50:15 AM UTC 24 |
| Finished | Aug 21 07:50:18 AM UTC 24 |
| Peak memory | 216308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3544050815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_ 2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3544050815 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_phy_config_rand_bus_type/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_usb_ref_disable.2465413039 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 148033531 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:50:15 AM UTC 24 |
| Finished | Aug 21 07:50:18 AM UTC 24 |
| Peak memory | 216148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2465413039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2465413039 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_buffer.3709272123 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 17447007919 ps |
| CPU time | 45.33 seconds |
| Started | Aug 21 07:50:15 AM UTC 24 |
| Finished | Aug 21 07:51:03 AM UTC 24 |
| Peak memory | 228580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3709272123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3709272123 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_received.3096113371 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 169502435 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:50:15 AM UTC 24 |
| Finished | Aug 21 07:50:18 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3096113371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3096113371 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_sent.887108014 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 196262541 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:50:16 AM UTC 24 |
| Finished | Aug 21 07:50:18 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=887108014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.887108014 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_disconnects.3194779302 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 3072212815 ps |
| CPU time | 21.35 seconds |
| Started | Aug 21 07:50:18 AM UTC 24 |
| Finished | Aug 21 07:50:41 AM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3194779302 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.3194779302 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_resets.822864825 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 7183024917 ps |
| CPU time | 40.66 seconds |
| Started | Aug 21 07:50:18 AM UTC 24 |
| Finished | Aug 21 07:51:00 AM UTC 24 |
| Peak memory | 230560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=822864825 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.822864825 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_rand_suspends.2344547684 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 9712339876 ps |
| CPU time | 168.03 seconds |
| Started | Aug 21 07:50:18 AM UTC 24 |
| Finished | Aug 21 07:53:09 AM UTC 24 |
| Peak memory | 235308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2344547684 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.2344547684 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_rand_suspends/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_in_transaction.4064506663 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 188916666 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:50:18 AM UTC 24 |
| Finished | Aug 21 07:50:20 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4064506663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.4064506663 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_out_transaction.2100359955 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 174575205 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:50:18 AM UTC 24 |
| Finished | Aug 21 07:50:20 AM UTC 24 |
| Peak memory | 216592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2100359955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.2100359955 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_resume_link_active.2362959389 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 20180657358 ps |
| CPU time | 35.29 seconds |
| Started | Aug 21 07:50:18 AM UTC 24 |
| Finished | Aug 21 07:50:55 AM UTC 24 |
| Peak memory | 218096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2362959389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_resume_link_active.2362959389 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_rx_crc_err.2487376494 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 132059097 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:50:20 AM UTC 24 |
| Finished | Aug 21 07:50:23 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2487376494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.2487376494 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_rx_full.2089784184 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 308594412 ps |
| CPU time | 1.96 seconds |
| Started | Aug 21 07:50:20 AM UTC 24 |
| Finished | Aug 21 07:50:23 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2089784184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_full.2089784184 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_rx_pid_err.2287438170 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 151420105 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:50:20 AM UTC 24 |
| Finished | Aug 21 07:50:23 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2287438170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2287438170 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_rx_pid_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_sec_cm.1848894873 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 681282129 ps |
| CPU time | 2.67 seconds |
| Started | Aug 21 07:50:27 AM UTC 24 |
| Finished | Aug 21 07:50:30 AM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1848894873 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1848894873 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority.625434149 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 387963108 ps |
| CPU time | 2.48 seconds |
| Started | Aug 21 07:50:20 AM UTC 24 |
| Finished | Aug 21 07:50:24 AM UTC 24 |
| Peak memory | 218080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=625434149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.625434149 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_setup_priority/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority_over_stall_response.2681979291 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 305553876 ps |
| CPU time | 1.99 seconds |
| Started | Aug 21 07:50:20 AM UTC 24 |
| Finished | Aug 21 07:50:23 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2681979291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.2681979291 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_setup_priority_over_stall_response/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_setup_stage.3265559022 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 154298420 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:50:20 AM UTC 24 |
| Finished | Aug 21 07:50:23 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3265559022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3265559022 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_setup_trans_ignored.3625817809 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 157354796 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:50:22 AM UTC 24 |
| Finished | Aug 21 07:50:25 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3625817809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3625817809 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_smoke.612809451 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 284529253 ps |
| CPU time | 2 seconds |
| Started | Aug 21 07:50:22 AM UTC 24 |
| Finished | Aug 21 07:50:26 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=612809451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.612809451 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_spurious_pids_ignored.3621380985 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 3009804734 ps |
| CPU time | 94.35 seconds |
| Started | Aug 21 07:50:24 AM UTC 24 |
| Finished | Aug 21 07:52:01 AM UTC 24 |
| Peak memory | 235376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3621380985 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.3621380985 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_stall_priority_over_nak.2756145871 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 243521562 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 07:50:24 AM UTC 24 |
| Finished | Aug 21 07:50:27 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2756145871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2756145871 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_stall_trans.2996558977 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 179843887 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:50:24 AM UTC 24 |
| Finished | Aug 21 07:50:27 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2996558977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.2996558977 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_stream_len_max.3068057190 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 458354455 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 07:50:24 AM UTC 24 |
| Finished | Aug 21 07:50:27 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3068057190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.3068057190 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_streaming_out.496945374 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2123222784 ps |
| CPU time | 16.82 seconds |
| Started | Aug 21 07:50:24 AM UTC 24 |
| Finished | Aug 21 07:50:42 AM UTC 24 |
| Peak memory | 230400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=496945374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.496945374 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_timeout_missing_host_handshake.4195710619 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 4317505262 ps |
| CPU time | 37.42 seconds |
| Started | Aug 21 07:50:01 AM UTC 24 |
| Finished | Aug 21 07:50:40 AM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4195710619 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_ host_handshake.4195710619 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/1.usbdev_tx_rx_disruption.2460636719 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 552936355 ps |
| CPU time | 2.69 seconds |
| Started | Aug 21 07:50:26 AM UTC 24 |
| Finished | Aug 21 07:50:30 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2460636719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.usbdev_tx_rx_disruption.2460636719 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/1.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_alert_test.2272321536 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 39082609 ps |
| CPU time | 0.88 seconds |
| Started | Aug 21 07:55:09 AM UTC 24 |
| Finished | Aug 21 07:55:11 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2272321536 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.2272321536 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_aon_wake_disconnect.4130278895 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 5362003021 ps |
| CPU time | 8.53 seconds |
| Started | Aug 21 07:54:55 AM UTC 24 |
| Finished | Aug 21 07:55:05 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4130278895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbd ev_aon_wake_disconnect.4130278895 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_aon_wake_reset.2467283701 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 14529916383 ps |
| CPU time | 22.81 seconds |
| Started | Aug 21 07:54:55 AM UTC 24 |
| Finished | Aug 21 07:55:19 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2467283701 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2467283701 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_av_buffer.33379429 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 181651740 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:54:55 AM UTC 24 |
| Finished | Aug 21 07:54:58 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33379429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.33379429 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_bitstuff_err.3668351210 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 148729971 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 07:54:55 AM UTC 24 |
| Finished | Aug 21 07:54:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3668351210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3668351210 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_data_toggle_clear.830794848 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 146406202 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:54:55 AM UTC 24 |
| Finished | Aug 21 07:54:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=830794848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.830794848 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_data_toggle_restore.2422409959 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 926193439 ps |
| CPU time | 4.22 seconds |
| Started | Aug 21 07:54:56 AM UTC 24 |
| Finished | Aug 21 07:55:01 AM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2422409959 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2422409959 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_device_address.2795832466 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 18123389228 ps |
| CPU time | 36.37 seconds |
| Started | Aug 21 07:54:56 AM UTC 24 |
| Finished | Aug 21 07:55:33 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2795832466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.2795832466 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_device_timeout.76805821 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 5713945753 ps |
| CPU time | 35.6 seconds |
| Started | Aug 21 07:54:56 AM UTC 24 |
| Finished | Aug 21 07:55:33 AM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=76805821 -assert nop ostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.76805821 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_disable_endpoint.3173832072 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 659689455 ps |
| CPU time | 2.31 seconds |
| Started | Aug 21 07:54:57 AM UTC 24 |
| Finished | Aug 21 07:55:00 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3173832072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.3173832072 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_disconnected.3850609321 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 141074911 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:54:57 AM UTC 24 |
| Finished | Aug 21 07:55:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3850609321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3850609321 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_enable.3828697177 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 67549086 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 07:54:57 AM UTC 24 |
| Finished | Aug 21 07:54:59 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3828697177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3828697177 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_endpoint_access.12427961 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 872705482 ps |
| CPU time | 4.25 seconds |
| Started | Aug 21 07:54:57 AM UTC 24 |
| Finished | Aug 21 07:55:03 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=12427961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.12427961 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_endpoint_types.538921847 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 441718467 ps |
| CPU time | 2.17 seconds |
| Started | Aug 21 07:54:57 AM UTC 24 |
| Finished | Aug 21 07:55:01 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=538921847 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_types.538921847 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_fifo_rst.820804915 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 203978146 ps |
| CPU time | 1.78 seconds |
| Started | Aug 21 07:54:57 AM UTC 24 |
| Finished | Aug 21 07:55:00 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=820804915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.820804915 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_in_iso.2077676088 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 174619995 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 07:54:59 AM UTC 24 |
| Finished | Aug 21 07:55:02 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2077676088 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2077676088 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_in_stall.3109115666 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 141704325 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:54:59 AM UTC 24 |
| Finished | Aug 21 07:55:01 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3109115666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3109115666 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_in_trans.2532580170 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 207946689 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:54:59 AM UTC 24 |
| Finished | Aug 21 07:55:02 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2532580170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2532580170 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_invalid_sync.4293660084 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 2227835259 ps |
| CPU time | 54.92 seconds |
| Started | Aug 21 07:54:57 AM UTC 24 |
| Finished | Aug 21 07:55:54 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4293660084 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.4293660084 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_link_in_err.1852871437 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 193183669 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:54:59 AM UTC 24 |
| Finished | Aug 21 07:55:02 AM UTC 24 |
| Peak memory | 216148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1852871437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.1852871437 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_link_resume.2136228101 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 25830503952 ps |
| CPU time | 44.07 seconds |
| Started | Aug 21 07:54:59 AM UTC 24 |
| Finished | Aug 21 07:55:45 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2136228101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.2136228101 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_link_suspend.2490793066 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 9022378765 ps |
| CPU time | 14.64 seconds |
| Started | Aug 21 07:54:59 AM UTC 24 |
| Finished | Aug 21 07:55:15 AM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2490793066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.2490793066 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_low_speed_traffic.1882337653 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 3429316375 ps |
| CPU time | 28.44 seconds |
| Started | Aug 21 07:55:00 AM UTC 24 |
| Finished | Aug 21 07:55:31 AM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1882337653 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.1882337653 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_max_inter_pkt_delay.3823278073 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 4034671452 ps |
| CPU time | 105.35 seconds |
| Started | Aug 21 07:55:00 AM UTC 24 |
| Finished | Aug 21 07:56:48 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3823278073 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.3823278073 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_max_length_in_transaction.2510074715 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 316359669 ps |
| CPU time | 1.72 seconds |
| Started | Aug 21 07:55:02 AM UTC 24 |
| Finished | Aug 21 07:55:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2510074715 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2510074715 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_max_length_out_transaction.2123601062 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 186656169 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 07:55:02 AM UTC 24 |
| Finished | Aug 21 07:55:04 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2123601062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2123601062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_max_non_iso_usb_traffic.3788937354 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 3682184885 ps |
| CPU time | 100.71 seconds |
| Started | Aug 21 07:55:02 AM UTC 24 |
| Finished | Aug 21 07:56:45 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3788937354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_non_iso_usb_traffic.3788937354 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_max_usb_traffic.2451053221 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 2043179113 ps |
| CPU time | 55.34 seconds |
| Started | Aug 21 07:55:02 AM UTC 24 |
| Finished | Aug 21 07:55:59 AM UTC 24 |
| Peak memory | 235056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2451053221 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2451053221 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_min_inter_pkt_delay.3428299471 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 3628860147 ps |
| CPU time | 26.05 seconds |
| Started | Aug 21 07:55:02 AM UTC 24 |
| Finished | Aug 21 07:55:29 AM UTC 24 |
| Peak memory | 230664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3428299471 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.3428299471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_min_length_in_transaction.966678265 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 159622193 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 07:55:02 AM UTC 24 |
| Finished | Aug 21 07:55:04 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=966678265 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.966678265 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_min_length_out_transaction.2227281437 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 161213397 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 07:55:04 AM UTC 24 |
| Finished | Aug 21 07:55:06 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2227281437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2227281437 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_out_iso.300105910 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 193589564 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:55:04 AM UTC 24 |
| Finished | Aug 21 07:55:06 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=300105910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.300105910 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_out_stall.392389206 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 193774457 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:55:04 AM UTC 24 |
| Finished | Aug 21 07:55:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=392389206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.392389206 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_out_trans_nak.1554819888 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 196628724 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 07:55:04 AM UTC 24 |
| Finished | Aug 21 07:55:06 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1554819888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1554819888 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_pending_in_trans.3219459442 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 154756936 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:55:04 AM UTC 24 |
| Finished | Aug 21 07:55:06 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3219459442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3219459442 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_phy_config_pinflip.787138744 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 211738003 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 07:55:05 AM UTC 24 |
| Finished | Aug 21 07:55:09 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=787138744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.787138744 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_phy_config_usb_ref_disable.2115511647 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 147183678 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:55:05 AM UTC 24 |
| Finished | Aug 21 07:55:08 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2115511647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.2115511647 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_pkt_buffer.3948442737 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 22328924292 ps |
| CPU time | 61.38 seconds |
| Started | Aug 21 07:55:05 AM UTC 24 |
| Finished | Aug 21 07:56:09 AM UTC 24 |
| Peak memory | 235184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3948442737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3948442737 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_pkt_received.19736556 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 181535999 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 07:55:05 AM UTC 24 |
| Finished | Aug 21 07:55:08 AM UTC 24 |
| Peak memory | 216312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19736556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.19736556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_pkt_sent.540711547 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 238606961 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 07:55:06 AM UTC 24 |
| Finished | Aug 21 07:55:08 AM UTC 24 |
| Peak memory | 216132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=540711547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.540711547 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_random_length_in_transaction.1975423019 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 166434620 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 07:55:06 AM UTC 24 |
| Finished | Aug 21 07:55:08 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1975423019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.1975423019 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_random_length_out_transaction.3039407196 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 147540695 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 07:55:06 AM UTC 24 |
| Finished | Aug 21 07:55:08 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3039407196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3039407196 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_resume_link_active.4183306079 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 20176461181 ps |
| CPU time | 29.9 seconds |
| Started | Aug 21 07:55:07 AM UTC 24 |
| Finished | Aug 21 07:55:38 AM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4183306079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_resume_link_active.4183306079 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_rx_crc_err.1904590786 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 146035862 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 07:55:07 AM UTC 24 |
| Finished | Aug 21 07:55:10 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1904590786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1904590786 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_rx_full.262528893 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 335994154 ps |
| CPU time | 2.1 seconds |
| Started | Aug 21 07:55:07 AM UTC 24 |
| Finished | Aug 21 07:55:10 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=262528893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_full.262528893 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_setup_stage.635138442 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 159177612 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:55:07 AM UTC 24 |
| Finished | Aug 21 07:55:10 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=635138442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.635138442 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_setup_trans_ignored.329763714 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 154200159 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:55:07 AM UTC 24 |
| Finished | Aug 21 07:55:10 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=329763714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.329763714 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_smoke.501418052 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 198476330 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:55:07 AM UTC 24 |
| Finished | Aug 21 07:55:10 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=501418052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.501418052 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_spurious_pids_ignored.360416 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 3297348660 ps |
| CPU time | 25.96 seconds |
| Started | Aug 21 07:55:07 AM UTC 24 |
| Finished | Aug 21 07:55:35 AM UTC 24 |
| Peak memory | 235200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=360416 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.360416 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_stall_priority_over_nak.3088587119 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 179920913 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 07:55:09 AM UTC 24 |
| Finished | Aug 21 07:55:11 AM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3088587119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3088587119 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_stall_trans.3141990319 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 253903920 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:55:09 AM UTC 24 |
| Finished | Aug 21 07:55:11 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3141990319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3141990319 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_stream_len_max.3647525171 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 549500689 ps |
| CPU time | 2.77 seconds |
| Started | Aug 21 07:55:09 AM UTC 24 |
| Finished | Aug 21 07:55:13 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3647525171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.3647525171 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_streaming_out.2375289965 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 2997401347 ps |
| CPU time | 28.44 seconds |
| Started | Aug 21 07:55:09 AM UTC 24 |
| Finished | Aug 21 07:55:39 AM UTC 24 |
| Peak memory | 230724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2375289965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.2375289965 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_timeout_missing_host_handshake.3378890075 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 842603400 ps |
| CPU time | 5.47 seconds |
| Started | Aug 21 07:54:57 AM UTC 24 |
| Finished | Aug 21 07:55:04 AM UTC 24 |
| Peak memory | 218128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3378890075 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing _host_handshake.3378890075 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/10.usbdev_tx_rx_disruption.1126993508 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 638443601 ps |
| CPU time | 2.04 seconds |
| Started | Aug 21 07:55:09 AM UTC 24 |
| Finished | Aug 21 07:55:12 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1126993508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.usbdev_tx_rx_disruption.1126993508 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/10.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/100.usbdev_endpoint_types.360957525 |
| Short name | T3173 |
| Test name | |
| Test status | |
| Simulation time | 278357304 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 08:05:45 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=360957525 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_endpoint_types.360957525 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/100.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/100.usbdev_tx_rx_disruption.1728998090 |
| Short name | T3181 |
| Test name | |
| Test status | |
| Simulation time | 462960087 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:05:45 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1728998090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 100.usbdev_tx_rx_disruption.1728998090 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/100.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/101.usbdev_endpoint_types.2954157580 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 593383809 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 08:05:45 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2954157580 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_endpoint_types.2954157580 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/101.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/101.usbdev_tx_rx_disruption.1925586078 |
| Short name | T3183 |
| Test name | |
| Test status | |
| Simulation time | 507848026 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:05:45 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1925586078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 101.usbdev_tx_rx_disruption.1925586078 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/101.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/102.usbdev_tx_rx_disruption.1119719824 |
| Short name | T3182 |
| Test name | |
| Test status | |
| Simulation time | 527556296 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:05:45 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1119719824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 102.usbdev_tx_rx_disruption.1119719824 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/102.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/103.usbdev_endpoint_types.3895894541 |
| Short name | T3171 |
| Test name | |
| Test status | |
| Simulation time | 161793826 ps |
| CPU time | 0.79 seconds |
| Started | Aug 21 08:05:45 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3895894541 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_endpoint_types.3895894541 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/103.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/103.usbdev_tx_rx_disruption.2961548432 |
| Short name | T3184 |
| Test name | |
| Test status | |
| Simulation time | 531975288 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 08:05:45 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2961548432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 103.usbdev_tx_rx_disruption.2961548432 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/103.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/104.usbdev_endpoint_types.907556715 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 249443085 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=907556715 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_endpoint_types.907556715 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/104.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/104.usbdev_tx_rx_disruption.429417195 |
| Short name | T3186 |
| Test name | |
| Test status | |
| Simulation time | 488814538 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:49 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=429417195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 104.usbdev_tx_rx_disruption.429417195 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/104.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/105.usbdev_endpoint_types.529978541 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 293020925 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=529978541 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_endpoint_types.529978541 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/105.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/105.usbdev_tx_rx_disruption.3891898956 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 551427933 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3891898956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 105.usbdev_tx_rx_disruption.3891898956 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/105.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/106.usbdev_endpoint_types.2872532160 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 355383012 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:49 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2872532160 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_endpoint_types.2872532160 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/106.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/106.usbdev_tx_rx_disruption.1297358277 |
| Short name | T3187 |
| Test name | |
| Test status | |
| Simulation time | 602588836 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1297358277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 106.usbdev_tx_rx_disruption.1297358277 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/106.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/107.usbdev_endpoint_types.1941146518 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 398685475 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1941146518 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_endpoint_types.1941146518 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/107.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/107.usbdev_tx_rx_disruption.2840165516 |
| Short name | T3195 |
| Test name | |
| Test status | |
| Simulation time | 681136619 ps |
| CPU time | 1.71 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2840165516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 107.usbdev_tx_rx_disruption.2840165516 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/107.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/108.usbdev_tx_rx_disruption.369006521 |
| Short name | T3196 |
| Test name | |
| Test status | |
| Simulation time | 550889780 ps |
| CPU time | 1.69 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=369006521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 108.usbdev_tx_rx_disruption.369006521 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/108.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/109.usbdev_tx_rx_disruption.188574154 |
| Short name | T3189 |
| Test name | |
| Test status | |
| Simulation time | 505625846 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=188574154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 109.usbdev_tx_rx_disruption.188574154 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/109.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_alert_test.2109225229 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 41152751 ps |
| CPU time | 0.92 seconds |
| Started | Aug 21 07:55:31 AM UTC 24 |
| Finished | Aug 21 07:55:33 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2109225229 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.2109225229 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_aon_wake_disconnect.1946092169 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 10433421231 ps |
| CPU time | 15.94 seconds |
| Started | Aug 21 07:55:09 AM UTC 24 |
| Finished | Aug 21 07:55:26 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1946092169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbd ev_aon_wake_disconnect.1946092169 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_aon_wake_reset.445776988 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 14539886004 ps |
| CPU time | 22.96 seconds |
| Started | Aug 21 07:55:10 AM UTC 24 |
| Finished | Aug 21 07:55:35 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=445776988 -assert nopostp roc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.445776988 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_aon_wake_resume.102375077 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 31108352447 ps |
| CPU time | 44.55 seconds |
| Started | Aug 21 07:55:10 AM UTC 24 |
| Finished | Aug 21 07:55:56 AM UTC 24 |
| Peak memory | 218284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=102375077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbde v_aon_wake_resume.102375077 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_av_buffer.1772641201 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 156061955 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:55:10 AM UTC 24 |
| Finished | Aug 21 07:55:13 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1772641201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1772641201 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_bitstuff_err.88284574 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 164442816 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 07:55:10 AM UTC 24 |
| Finished | Aug 21 07:55:13 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=88284574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.88284574 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_data_toggle_clear.2175928620 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 477918755 ps |
| CPU time | 2.41 seconds |
| Started | Aug 21 07:55:12 AM UTC 24 |
| Finished | Aug 21 07:55:15 AM UTC 24 |
| Peak memory | 218012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2175928620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.2175928620 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_data_toggle_restore.1816356962 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1157344777 ps |
| CPU time | 5.18 seconds |
| Started | Aug 21 07:55:12 AM UTC 24 |
| Finished | Aug 21 07:55:18 AM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1816356962 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.1816356962 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_device_address.4235151993 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 36638442828 ps |
| CPU time | 62.26 seconds |
| Started | Aug 21 07:55:12 AM UTC 24 |
| Finished | Aug 21 07:56:16 AM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4235151993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.4235151993 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_device_timeout.4245120352 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 3653239499 ps |
| CPU time | 27.46 seconds |
| Started | Aug 21 07:55:12 AM UTC 24 |
| Finished | Aug 21 07:55:41 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4245120352 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.4245120352 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_disable_endpoint.4064106399 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 534925164 ps |
| CPU time | 2.63 seconds |
| Started | Aug 21 07:55:12 AM UTC 24 |
| Finished | Aug 21 07:55:16 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4064106399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.4064106399 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_disconnected.1519424444 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 147079742 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:55:13 AM UTC 24 |
| Finished | Aug 21 07:55:16 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1519424444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1519424444 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_enable.2599704431 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 68059574 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 07:55:13 AM UTC 24 |
| Finished | Aug 21 07:55:15 AM UTC 24 |
| Peak memory | 216084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2599704431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2599704431 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_endpoint_access.3599985522 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 1003679455 ps |
| CPU time | 4.01 seconds |
| Started | Aug 21 07:55:13 AM UTC 24 |
| Finished | Aug 21 07:55:18 AM UTC 24 |
| Peak memory | 218136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3599985522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3599985522 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_fifo_rst.637407126 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 236687338 ps |
| CPU time | 3.42 seconds |
| Started | Aug 21 07:55:15 AM UTC 24 |
| Finished | Aug 21 07:55:19 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=637407126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.637407126 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_in_iso.3632003610 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 189402054 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 07:55:17 AM UTC 24 |
| Finished | Aug 21 07:55:20 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3632003610 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.3632003610 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_in_stall.3153926984 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 134933833 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 07:55:17 AM UTC 24 |
| Finished | Aug 21 07:55:20 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3153926984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3153926984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_in_trans.3447230807 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 294499439 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 07:55:17 AM UTC 24 |
| Finished | Aug 21 07:55:20 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3447230807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3447230807 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_invalid_sync.2164033342 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 3988259396 ps |
| CPU time | 28.68 seconds |
| Started | Aug 21 07:55:17 AM UTC 24 |
| Finished | Aug 21 07:55:47 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2164033342 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.2164033342 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_iso_retraction.1376362077 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 3665083451 ps |
| CPU time | 43.33 seconds |
| Started | Aug 21 07:55:17 AM UTC 24 |
| Finished | Aug 21 07:56:02 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1376362077 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.1376362077 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_link_in_err.113226974 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 236674824 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 07:55:17 AM UTC 24 |
| Finished | Aug 21 07:55:20 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=113226974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.113226974 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_link_resume.2154961017 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 5757958772 ps |
| CPU time | 11.3 seconds |
| Started | Aug 21 07:55:17 AM UTC 24 |
| Finished | Aug 21 07:55:30 AM UTC 24 |
| Peak memory | 218372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2154961017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.2154961017 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_link_suspend.2573514282 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 4539127269 ps |
| CPU time | 9.66 seconds |
| Started | Aug 21 07:55:17 AM UTC 24 |
| Finished | Aug 21 07:55:28 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2573514282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2573514282 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_low_speed_traffic.1827297194 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 3419599009 ps |
| CPU time | 86.18 seconds |
| Started | Aug 21 07:55:17 AM UTC 24 |
| Finished | Aug 21 07:56:46 AM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1827297194 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.1827297194 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_max_inter_pkt_delay.1606492979 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 2369317092 ps |
| CPU time | 23.88 seconds |
| Started | Aug 21 07:55:19 AM UTC 24 |
| Finished | Aug 21 07:55:44 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1606492979 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.1606492979 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_max_length_in_transaction.218203937 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 242194508 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 07:55:20 AM UTC 24 |
| Finished | Aug 21 07:55:23 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=218203937 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.218203937 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_max_length_out_transaction.399104350 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 219877616 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 07:55:20 AM UTC 24 |
| Finished | Aug 21 07:55:23 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=399104350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.399104350 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_max_non_iso_usb_traffic.2016055315 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 1864444808 ps |
| CPU time | 16.4 seconds |
| Started | Aug 21 07:55:22 AM UTC 24 |
| Finished | Aug 21 07:55:40 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2016055315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_non_iso_usb_traffic.2016055315 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_max_usb_traffic.1550674630 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 1682988453 ps |
| CPU time | 14.36 seconds |
| Started | Aug 21 07:55:22 AM UTC 24 |
| Finished | Aug 21 07:55:38 AM UTC 24 |
| Peak memory | 230480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1550674630 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.1550674630 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_min_inter_pkt_delay.702096759 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 2443343248 ps |
| CPU time | 19.57 seconds |
| Started | Aug 21 07:55:22 AM UTC 24 |
| Finished | Aug 21 07:55:43 AM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=702096759 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.702096759 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_min_length_in_transaction.3374243427 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 154468656 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:55:22 AM UTC 24 |
| Finished | Aug 21 07:55:25 AM UTC 24 |
| Peak memory | 216424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3374243427 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.3374243427 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_min_length_out_transaction.3463736361 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 155065182 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:55:22 AM UTC 24 |
| Finished | Aug 21 07:55:25 AM UTC 24 |
| Peak memory | 216420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3463736361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3463736361 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_out_iso.451370464 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 180519019 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:55:22 AM UTC 24 |
| Finished | Aug 21 07:55:25 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=451370464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.451370464 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_out_stall.75019512 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 187501779 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 07:55:22 AM UTC 24 |
| Finished | Aug 21 07:55:24 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=75019512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.75019512 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_out_trans_nak.3697677250 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 187427561 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:55:25 AM UTC 24 |
| Finished | Aug 21 07:55:28 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3697677250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3697677250 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_pending_in_trans.1727196584 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 146952601 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:55:25 AM UTC 24 |
| Finished | Aug 21 07:55:28 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1727196584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1727196584 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_phy_config_pinflip.1627137229 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 241384427 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 07:55:25 AM UTC 24 |
| Finished | Aug 21 07:55:28 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1627137229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1627137229 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_phy_config_usb_ref_disable.394700047 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 148595815 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:55:25 AM UTC 24 |
| Finished | Aug 21 07:55:28 AM UTC 24 |
| Peak memory | 216368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=394700047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.394700047 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_phy_pins_sense.109299270 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 51553606 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 07:55:25 AM UTC 24 |
| Finished | Aug 21 07:55:27 AM UTC 24 |
| Peak memory | 216444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=109299270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.109299270 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_pkt_buffer.1697249689 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 6084035927 ps |
| CPU time | 17.03 seconds |
| Started | Aug 21 07:55:25 AM UTC 24 |
| Finished | Aug 21 07:55:43 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1697249689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1697249689 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_pkt_received.3633807776 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 191760481 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 07:55:26 AM UTC 24 |
| Finished | Aug 21 07:55:29 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3633807776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3633807776 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_pkt_sent.3612198611 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 189641050 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 07:55:26 AM UTC 24 |
| Finished | Aug 21 07:55:29 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3612198611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3612198611 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_random_length_in_transaction.497605302 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 205748328 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 07:55:26 AM UTC 24 |
| Finished | Aug 21 07:55:29 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=497605302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.497605302 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_random_length_out_transaction.2233696867 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 176537275 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:55:26 AM UTC 24 |
| Finished | Aug 21 07:55:29 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2233696867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.2233696867 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_resume_link_active.3867184595 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 20149581068 ps |
| CPU time | 27.95 seconds |
| Started | Aug 21 07:55:27 AM UTC 24 |
| Finished | Aug 21 07:55:57 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3867184595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_resume_link_active.3867184595 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_rx_crc_err.532951901 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 157428221 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:55:29 AM UTC 24 |
| Finished | Aug 21 07:55:32 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=532951901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.532951901 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_rx_full.2520371856 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 269981121 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 07:55:29 AM UTC 24 |
| Finished | Aug 21 07:55:32 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2520371856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_full.2520371856 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_setup_stage.1216391084 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 151383258 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:55:29 AM UTC 24 |
| Finished | Aug 21 07:55:32 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1216391084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1216391084 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_setup_trans_ignored.1455147200 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 149701051 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:55:29 AM UTC 24 |
| Finished | Aug 21 07:55:32 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1455147200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1455147200 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_smoke.905511943 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 238455669 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 07:55:29 AM UTC 24 |
| Finished | Aug 21 07:55:32 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=905511943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.905511943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_spurious_pids_ignored.3773142951 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 3392009841 ps |
| CPU time | 89.46 seconds |
| Started | Aug 21 07:55:29 AM UTC 24 |
| Finished | Aug 21 07:57:01 AM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3773142951 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.3773142951 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_stall_priority_over_nak.375435863 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 204153036 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 07:55:29 AM UTC 24 |
| Finished | Aug 21 07:55:32 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=375435863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20 24_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.375435863 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_stall_trans.1507143863 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 192434886 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:55:31 AM UTC 24 |
| Finished | Aug 21 07:55:33 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1507143863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.1507143863 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_stream_len_max.3651216862 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 770557763 ps |
| CPU time | 2.88 seconds |
| Started | Aug 21 07:55:31 AM UTC 24 |
| Finished | Aug 21 07:55:35 AM UTC 24 |
| Peak memory | 217536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3651216862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.3651216862 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_streaming_out.835829123 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 2123525601 ps |
| CPU time | 22.58 seconds |
| Started | Aug 21 07:55:31 AM UTC 24 |
| Finished | Aug 21 07:55:55 AM UTC 24 |
| Peak memory | 230000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=835829123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.835829123 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/11.usbdev_timeout_missing_host_handshake.299153002 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 2609386143 ps |
| CPU time | 17.46 seconds |
| Started | Aug 21 07:55:12 AM UTC 24 |
| Finished | Aug 21 07:55:31 AM UTC 24 |
| Peak memory | 218372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=299153002 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_ host_handshake.299153002 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/11.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/110.usbdev_endpoint_types.2294422745 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 348971493 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2294422745 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_endpoint_types.2294422745 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/110.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/110.usbdev_tx_rx_disruption.3556352146 |
| Short name | T3190 |
| Test name | |
| Test status | |
| Simulation time | 551495243 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3556352146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 110.usbdev_tx_rx_disruption.3556352146 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/110.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/111.usbdev_endpoint_types.2503616446 |
| Short name | T3188 |
| Test name | |
| Test status | |
| Simulation time | 411219833 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:05:47 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2503616446 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_endpoint_types.2503616446 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/111.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/111.usbdev_tx_rx_disruption.98260529 |
| Short name | T3197 |
| Test name | |
| Test status | |
| Simulation time | 526141490 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=98260529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 111.usbdev_tx_rx_disruption.98260529 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/111.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/112.usbdev_tx_rx_disruption.3046741897 |
| Short name | T3193 |
| Test name | |
| Test status | |
| Simulation time | 552100710 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3046741897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 112.usbdev_tx_rx_disruption.3046741897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/112.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/113.usbdev_endpoint_types.555681635 |
| Short name | T3185 |
| Test name | |
| Test status | |
| Simulation time | 147386398 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=555681635 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_endpoint_types.555681635 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/113.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/113.usbdev_tx_rx_disruption.3030717085 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 621824855 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3030717085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 113.usbdev_tx_rx_disruption.3030717085 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/113.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/114.usbdev_endpoint_types.1314059197 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 242518358 ps |
| CPU time | 0.86 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1314059197 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_endpoint_types.1314059197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/114.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/114.usbdev_tx_rx_disruption.3966589541 |
| Short name | T3200 |
| Test name | |
| Test status | |
| Simulation time | 578709222 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3966589541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 114.usbdev_tx_rx_disruption.3966589541 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/114.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/115.usbdev_tx_rx_disruption.1529954688 |
| Short name | T3199 |
| Test name | |
| Test status | |
| Simulation time | 530024612 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1529954688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 115.usbdev_tx_rx_disruption.1529954688 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/115.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/116.usbdev_endpoint_types.2243379051 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 386798618 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2243379051 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_endpoint_types.2243379051 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/116.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/116.usbdev_tx_rx_disruption.1370431178 |
| Short name | T3198 |
| Test name | |
| Test status | |
| Simulation time | 554774511 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1370431178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 116.usbdev_tx_rx_disruption.1370431178 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/116.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/117.usbdev_endpoint_types.614910779 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 273881830 ps |
| CPU time | 0.87 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=614910779 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_endpoint_types.614910779 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/117.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/117.usbdev_tx_rx_disruption.981603873 |
| Short name | T3201 |
| Test name | |
| Test status | |
| Simulation time | 599367716 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=981603873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 117.usbdev_tx_rx_disruption.981603873 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/117.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/118.usbdev_endpoint_types.3700762646 |
| Short name | T3194 |
| Test name | |
| Test status | |
| Simulation time | 263063369 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3700762646 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_endpoint_types.3700762646 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/118.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/118.usbdev_tx_rx_disruption.1879763569 |
| Short name | T3202 |
| Test name | |
| Test status | |
| Simulation time | 654454993 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 08:05:48 AM UTC 24 |
| Finished | Aug 21 08:05:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1879763569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 118.usbdev_tx_rx_disruption.1879763569 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/118.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/119.usbdev_tx_rx_disruption.2354715265 |
| Short name | T3208 |
| Test name | |
| Test status | |
| Simulation time | 494104417 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:54 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2354715265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 119.usbdev_tx_rx_disruption.2354715265 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/119.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_alert_test.2861258343 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 82742896 ps |
| CPU time | 0.91 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:55:48 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2861258343 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.2861258343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_aon_wake_disconnect.3224450806 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 6527537915 ps |
| CPU time | 10.08 seconds |
| Started | Aug 21 07:55:31 AM UTC 24 |
| Finished | Aug 21 07:55:42 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3224450806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbd ev_aon_wake_disconnect.3224450806 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_aon_wake_reset.105460380 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 19407087700 ps |
| CPU time | 26.71 seconds |
| Started | Aug 21 07:55:32 AM UTC 24 |
| Finished | Aug 21 07:56:01 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=105460380 -assert nopostp roc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.105460380 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_aon_wake_resume.2547922560 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 25385952904 ps |
| CPU time | 39.97 seconds |
| Started | Aug 21 07:55:33 AM UTC 24 |
| Finished | Aug 21 07:56:14 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2547922560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbd ev_aon_wake_resume.2547922560 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_av_buffer.2225490961 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 155396093 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:55:33 AM UTC 24 |
| Finished | Aug 21 07:55:35 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2225490961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2225490961 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_bitstuff_err.1454689624 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 166084796 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:55:33 AM UTC 24 |
| Finished | Aug 21 07:55:35 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1454689624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1454689624 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_data_toggle_clear.3034030424 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 338672298 ps |
| CPU time | 1.81 seconds |
| Started | Aug 21 07:55:33 AM UTC 24 |
| Finished | Aug 21 07:55:36 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3034030424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3034030424 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_data_toggle_restore.2837912544 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 426304869 ps |
| CPU time | 2.34 seconds |
| Started | Aug 21 07:55:33 AM UTC 24 |
| Finished | Aug 21 07:55:36 AM UTC 24 |
| Peak memory | 218008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2837912544 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2837912544 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_device_address.1837743383 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 45091856320 ps |
| CPU time | 81.81 seconds |
| Started | Aug 21 07:55:33 AM UTC 24 |
| Finished | Aug 21 07:56:57 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1837743383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1837743383 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_device_timeout.95086294 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 1790299274 ps |
| CPU time | 38.71 seconds |
| Started | Aug 21 07:55:33 AM UTC 24 |
| Finished | Aug 21 07:56:13 AM UTC 24 |
| Peak memory | 218192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=95086294 -assert nop ostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.95086294 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_disable_endpoint.4231964790 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 707127325 ps |
| CPU time | 3.39 seconds |
| Started | Aug 21 07:55:34 AM UTC 24 |
| Finished | Aug 21 07:55:39 AM UTC 24 |
| Peak memory | 218080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4231964790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.4231964790 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_disconnected.2092906373 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 142074913 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:55:34 AM UTC 24 |
| Finished | Aug 21 07:55:37 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2092906373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2092906373 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_enable.2295818746 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 41781376 ps |
| CPU time | 1 seconds |
| Started | Aug 21 07:55:35 AM UTC 24 |
| Finished | Aug 21 07:55:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2295818746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2295818746 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_endpoint_access.2155164547 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 879648340 ps |
| CPU time | 4.09 seconds |
| Started | Aug 21 07:55:35 AM UTC 24 |
| Finished | Aug 21 07:55:40 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2155164547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2155164547 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_endpoint_types.3235407117 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 262009572 ps |
| CPU time | 1.74 seconds |
| Started | Aug 21 07:55:36 AM UTC 24 |
| Finished | Aug 21 07:55:39 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3235407117 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_types.3235407117 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_fifo_rst.1152190279 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 341429193 ps |
| CPU time | 2.51 seconds |
| Started | Aug 21 07:55:36 AM UTC 24 |
| Finished | Aug 21 07:55:40 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1152190279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1152190279 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_in_iso.937796396 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 227196522 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:55:36 AM UTC 24 |
| Finished | Aug 21 07:55:39 AM UTC 24 |
| Peak memory | 234072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=937796396 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.937796396 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_in_stall.3625914745 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 171865629 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:55:36 AM UTC 24 |
| Finished | Aug 21 07:55:39 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3625914745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3625914745 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_in_trans.2769055050 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 178898954 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:55:36 AM UTC 24 |
| Finished | Aug 21 07:55:39 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2769055050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2769055050 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_invalid_sync.1093084387 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 5350387368 ps |
| CPU time | 50.22 seconds |
| Started | Aug 21 07:55:36 AM UTC 24 |
| Finished | Aug 21 07:56:28 AM UTC 24 |
| Peak memory | 235116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1093084387 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.1093084387 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_iso_retraction.231791688 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 6292618566 ps |
| CPU time | 72.32 seconds |
| Started | Aug 21 07:55:36 AM UTC 24 |
| Finished | Aug 21 07:56:50 AM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=231791688 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.231791688 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_link_in_err.3410616410 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 186519159 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 07:55:36 AM UTC 24 |
| Finished | Aug 21 07:55:39 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3410616410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3410616410 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_link_resume.2112366538 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 8303383710 ps |
| CPU time | 15.34 seconds |
| Started | Aug 21 07:55:36 AM UTC 24 |
| Finished | Aug 21 07:55:53 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2112366538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2112366538 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_link_suspend.801278891 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 9263654671 ps |
| CPU time | 12.12 seconds |
| Started | Aug 21 07:55:36 AM UTC 24 |
| Finished | Aug 21 07:55:50 AM UTC 24 |
| Peak memory | 218408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=801278891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.801278891 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_low_speed_traffic.2176070372 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 3935100838 ps |
| CPU time | 98.5 seconds |
| Started | Aug 21 07:55:38 AM UTC 24 |
| Finished | Aug 21 07:57:18 AM UTC 24 |
| Peak memory | 235204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2176070372 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2176070372 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_max_inter_pkt_delay.3222267830 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 2560609678 ps |
| CPU time | 69.36 seconds |
| Started | Aug 21 07:55:38 AM UTC 24 |
| Finished | Aug 21 07:56:49 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3222267830 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.3222267830 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_max_length_in_transaction.2046941322 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 247467160 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:55:38 AM UTC 24 |
| Finished | Aug 21 07:55:40 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2046941322 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.2046941322 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_max_length_out_transaction.2608904157 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 206502667 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:55:39 AM UTC 24 |
| Finished | Aug 21 07:55:42 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2608904157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2608904157 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_max_non_iso_usb_traffic.2267008602 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 2765287776 ps |
| CPU time | 69.45 seconds |
| Started | Aug 21 07:55:39 AM UTC 24 |
| Finished | Aug 21 07:56:50 AM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2267008602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_non_iso_usb_traffic.2267008602 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_max_usb_traffic.654695191 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 3131774699 ps |
| CPU time | 84.13 seconds |
| Started | Aug 21 07:55:39 AM UTC 24 |
| Finished | Aug 21 07:57:05 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=654695191 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.654695191 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_min_inter_pkt_delay.2749426757 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 2904887544 ps |
| CPU time | 26.42 seconds |
| Started | Aug 21 07:55:39 AM UTC 24 |
| Finished | Aug 21 07:56:07 AM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2749426757 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.2749426757 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_min_length_in_transaction.4169459436 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 152443415 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:55:39 AM UTC 24 |
| Finished | Aug 21 07:55:42 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4169459436 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.4169459436 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_min_length_out_transaction.2186409651 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 162640421 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 07:55:40 AM UTC 24 |
| Finished | Aug 21 07:55:42 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2186409651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2186409651 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_out_iso.3938237589 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 179903462 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 07:55:41 AM UTC 24 |
| Finished | Aug 21 07:55:44 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3938237589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3938237589 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_out_stall.2627704946 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 213074905 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 07:55:41 AM UTC 24 |
| Finished | Aug 21 07:55:43 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2627704946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2627704946 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_out_trans_nak.2785257150 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 215419416 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 07:55:41 AM UTC 24 |
| Finished | Aug 21 07:55:44 AM UTC 24 |
| Peak memory | 216344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2785257150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2785257150 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_pending_in_trans.1648342590 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 161841552 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:55:41 AM UTC 24 |
| Finished | Aug 21 07:55:44 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1648342590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1648342590 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_phy_config_pinflip.3421751514 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 256787452 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:55:41 AM UTC 24 |
| Finished | Aug 21 07:55:44 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3421751514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.3421751514 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_phy_config_usb_ref_disable.292881855 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 171664547 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:55:41 AM UTC 24 |
| Finished | Aug 21 07:55:44 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=292881855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.292881855 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_phy_pins_sense.3547349299 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 56893021 ps |
| CPU time | 0.88 seconds |
| Started | Aug 21 07:55:41 AM UTC 24 |
| Finished | Aug 21 07:55:43 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3547349299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3547349299 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_pkt_buffer.2348487813 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 14272682276 ps |
| CPU time | 38.97 seconds |
| Started | Aug 21 07:55:43 AM UTC 24 |
| Finished | Aug 21 07:56:23 AM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2348487813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2348487813 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_pkt_received.3206618668 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 230741185 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 07:55:43 AM UTC 24 |
| Finished | Aug 21 07:55:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3206618668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3206618668 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_pkt_sent.1865776375 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 189534620 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 07:55:43 AM UTC 24 |
| Finished | Aug 21 07:55:45 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1865776375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1865776375 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_random_length_in_transaction.2647265058 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 223158260 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:55:43 AM UTC 24 |
| Finished | Aug 21 07:55:45 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2647265058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.2647265058 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_random_length_out_transaction.4185773668 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 173475460 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:55:43 AM UTC 24 |
| Finished | Aug 21 07:55:45 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4185773668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.4185773668 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_resume_link_active.3246106831 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 20210134477 ps |
| CPU time | 33.08 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:56:20 AM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3246106831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_resume_link_active.3246106831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_rx_crc_err.2253502872 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 155811880 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:55:48 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2253502872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2253502872 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_setup_stage.929199281 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 148062820 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:55:48 AM UTC 24 |
| Peak memory | 216316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=929199281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.929199281 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_setup_trans_ignored.907961613 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 152312067 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:55:48 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=907961613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.907961613 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_smoke.1404723167 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 200421849 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:55:48 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1404723167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1404723167 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_spurious_pids_ignored.3652728604 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 3612411995 ps |
| CPU time | 96.26 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:57:24 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3652728604 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3652728604 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_stall_priority_over_nak.4046200465 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 196402749 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:55:48 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4046200465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.4046200465 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_stall_trans.724495997 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 147775297 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:55:48 AM UTC 24 |
| Peak memory | 216176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=724495997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.724495997 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_stream_len_max.2471412004 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 571394932 ps |
| CPU time | 2.23 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:55:49 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2471412004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.2471412004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_streaming_out.409591846 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 2072152204 ps |
| CPU time | 56.25 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:56:44 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=409591846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.409591846 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_timeout_missing_host_handshake.3915868839 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 2896497178 ps |
| CPU time | 18.64 seconds |
| Started | Aug 21 07:55:34 AM UTC 24 |
| Finished | Aug 21 07:55:54 AM UTC 24 |
| Peak memory | 218320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3915868839 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing _host_handshake.3915868839 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/12.usbdev_tx_rx_disruption.4275518154 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 600350248 ps |
| CPU time | 1.98 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:55:49 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4275518154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.usbdev_tx_rx_disruption.4275518154 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/12.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/120.usbdev_endpoint_types.239348722 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 443518227 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:54 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=239348722 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_endpoint_types.239348722 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/120.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/120.usbdev_tx_rx_disruption.1594298174 |
| Short name | T3207 |
| Test name | |
| Test status | |
| Simulation time | 530603242 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:54 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1594298174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 120.usbdev_tx_rx_disruption.1594298174 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/120.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/121.usbdev_endpoint_types.255419857 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 417694424 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:54 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=255419857 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_endpoint_types.255419857 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/121.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/121.usbdev_tx_rx_disruption.1207403521 |
| Short name | T3210 |
| Test name | |
| Test status | |
| Simulation time | 539773814 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:55 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1207403521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 121.usbdev_tx_rx_disruption.1207403521 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/121.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/122.usbdev_endpoint_types.677250085 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 532902358 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:54 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=677250085 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_endpoint_types.677250085 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/122.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/122.usbdev_tx_rx_disruption.780252943 |
| Short name | T3209 |
| Test name | |
| Test status | |
| Simulation time | 465743654 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:54 AM UTC 24 |
| Peak memory | 216152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=780252943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 122.usbdev_tx_rx_disruption.780252943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/122.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/124.usbdev_tx_rx_disruption.286942938 |
| Short name | T3216 |
| Test name | |
| Test status | |
| Simulation time | 479518262 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:56 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=286942938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 124.usbdev_tx_rx_disruption.286942938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/124.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/125.usbdev_tx_rx_disruption.4017406813 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 441378453 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:56 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4017406813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 125.usbdev_tx_rx_disruption.4017406813 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/125.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/126.usbdev_tx_rx_disruption.610054634 |
| Short name | T3218 |
| Test name | |
| Test status | |
| Simulation time | 537070962 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:56 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=610054634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 126.usbdev_tx_rx_disruption.610054634 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/126.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/127.usbdev_endpoint_types.4156066875 |
| Short name | T3214 |
| Test name | |
| Test status | |
| Simulation time | 333490744 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:55 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4156066875 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_endpoint_types.4156066875 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/127.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/127.usbdev_tx_rx_disruption.2071251180 |
| Short name | T3220 |
| Test name | |
| Test status | |
| Simulation time | 615511979 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:56 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2071251180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 127.usbdev_tx_rx_disruption.2071251180 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/127.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/128.usbdev_tx_rx_disruption.3691721382 |
| Short name | T3217 |
| Test name | |
| Test status | |
| Simulation time | 506127615 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:56 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3691721382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 128.usbdev_tx_rx_disruption.3691721382 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/128.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/129.usbdev_endpoint_types.3818167402 |
| Short name | T3219 |
| Test name | |
| Test status | |
| Simulation time | 682872569 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:56 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3818167402 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_endpoint_types.3818167402 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/129.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/129.usbdev_tx_rx_disruption.1761674559 |
| Short name | T3244 |
| Test name | |
| Test status | |
| Simulation time | 655083247 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:06:06 AM UTC 24 |
| Peak memory | 216428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1761674559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 129.usbdev_tx_rx_disruption.1761674559 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/129.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_alert_test.2949635715 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 27910804 ps |
| CPU time | 0.96 seconds |
| Started | Aug 21 07:56:06 AM UTC 24 |
| Finished | Aug 21 07:56:07 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2949635715 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.2949635715 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_aon_wake_disconnect.3035866849 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 9461330385 ps |
| CPU time | 14.94 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:56:02 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3035866849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbd ev_aon_wake_disconnect.3035866849 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_aon_wake_reset.1305923332 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 20290868004 ps |
| CPU time | 25.97 seconds |
| Started | Aug 21 07:55:46 AM UTC 24 |
| Finished | Aug 21 07:56:13 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1305923332 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1305923332 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_aon_wake_resume.2256622430 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 30150656357 ps |
| CPU time | 57.39 seconds |
| Started | Aug 21 07:55:47 AM UTC 24 |
| Finished | Aug 21 07:56:46 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2256622430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbd ev_aon_wake_resume.2256622430 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_av_buffer.549810803 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 162929114 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:55:49 AM UTC 24 |
| Finished | Aug 21 07:55:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=549810803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.549810803 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_bitstuff_err.1983346749 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 164445267 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:55:49 AM UTC 24 |
| Finished | Aug 21 07:55:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1983346749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.1983346749 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_data_toggle_clear.1672013381 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 231364679 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 07:55:49 AM UTC 24 |
| Finished | Aug 21 07:55:51 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1672013381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.1672013381 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_data_toggle_restore.4219155640 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 589304027 ps |
| CPU time | 2.89 seconds |
| Started | Aug 21 07:55:49 AM UTC 24 |
| Finished | Aug 21 07:55:53 AM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4219155640 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.4219155640 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_device_address.886143121 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 17974154379 ps |
| CPU time | 32.98 seconds |
| Started | Aug 21 07:55:49 AM UTC 24 |
| Finished | Aug 21 07:56:23 AM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=886143121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.886143121 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_device_timeout.4107408843 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 476826671 ps |
| CPU time | 8.63 seconds |
| Started | Aug 21 07:55:49 AM UTC 24 |
| Finished | Aug 21 07:55:59 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4107408843 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.4107408843 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_disable_endpoint.1398458199 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 726259472 ps |
| CPU time | 3.3 seconds |
| Started | Aug 21 07:55:49 AM UTC 24 |
| Finished | Aug 21 07:55:53 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1398458199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1398458199 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_disconnected.4043660132 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 140115374 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 07:55:50 AM UTC 24 |
| Finished | Aug 21 07:55:53 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4043660132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.4043660132 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_enable.2729491543 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 47940061 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 07:55:51 AM UTC 24 |
| Finished | Aug 21 07:55:53 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2729491543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2729491543 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_endpoint_access.3728821765 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 1036189115 ps |
| CPU time | 5.12 seconds |
| Started | Aug 21 07:55:51 AM UTC 24 |
| Finished | Aug 21 07:55:57 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3728821765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.3728821765 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_endpoint_types.3481461183 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 536223535 ps |
| CPU time | 1.84 seconds |
| Started | Aug 21 07:55:51 AM UTC 24 |
| Finished | Aug 21 07:55:54 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3481461183 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_types.3481461183 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_fifo_rst.803913000 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 305395321 ps |
| CPU time | 3.05 seconds |
| Started | Aug 21 07:55:51 AM UTC 24 |
| Finished | Aug 21 07:55:55 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=803913000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.803913000 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_in_iso.2355633504 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 275664180 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 07:55:52 AM UTC 24 |
| Finished | Aug 21 07:55:55 AM UTC 24 |
| Peak memory | 226440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2355633504 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2355633504 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_in_stall.2212514904 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 164169685 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 07:55:52 AM UTC 24 |
| Finished | Aug 21 07:55:54 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2212514904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2212514904 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_in_trans.1841823385 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 200627996 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:55:52 AM UTC 24 |
| Finished | Aug 21 07:55:54 AM UTC 24 |
| Peak memory | 216180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1841823385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1841823385 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_invalid_sync.140991510 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 3490384524 ps |
| CPU time | 33.81 seconds |
| Started | Aug 21 07:55:51 AM UTC 24 |
| Finished | Aug 21 07:56:26 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=140991510 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.140991510 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_iso_retraction.1796866429 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 7079050597 ps |
| CPU time | 53.62 seconds |
| Started | Aug 21 07:55:53 AM UTC 24 |
| Finished | Aug 21 07:56:48 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1796866429 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.1796866429 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_link_in_err.4122523080 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 282419852 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:55:53 AM UTC 24 |
| Finished | Aug 21 07:55:56 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4122523080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.4122523080 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_link_resume.3007809044 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 11492830361 ps |
| CPU time | 22.4 seconds |
| Started | Aug 21 07:55:53 AM UTC 24 |
| Finished | Aug 21 07:56:17 AM UTC 24 |
| Peak memory | 218344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3007809044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3007809044 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_link_suspend.725049808 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 10036996480 ps |
| CPU time | 15.43 seconds |
| Started | Aug 21 07:55:55 AM UTC 24 |
| Finished | Aug 21 07:56:11 AM UTC 24 |
| Peak memory | 218300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=725049808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.725049808 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_low_speed_traffic.408859012 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 4416567238 ps |
| CPU time | 47.48 seconds |
| Started | Aug 21 07:55:55 AM UTC 24 |
| Finished | Aug 21 07:56:44 AM UTC 24 |
| Peak memory | 235208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=408859012 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.408859012 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_max_inter_pkt_delay.1722530911 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 2209180322 ps |
| CPU time | 17.95 seconds |
| Started | Aug 21 07:55:55 AM UTC 24 |
| Finished | Aug 21 07:56:14 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1722530911 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1722530911 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_max_length_in_transaction.3963854471 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 244662975 ps |
| CPU time | 1.75 seconds |
| Started | Aug 21 07:55:55 AM UTC 24 |
| Finished | Aug 21 07:55:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3963854471 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.3963854471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_max_length_out_transaction.2233155190 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 181533344 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 07:55:55 AM UTC 24 |
| Finished | Aug 21 07:55:57 AM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2233155190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2233155190 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_max_non_iso_usb_traffic.3493958900 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 3540462430 ps |
| CPU time | 35.87 seconds |
| Started | Aug 21 07:55:55 AM UTC 24 |
| Finished | Aug 21 07:56:32 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3493958900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_non_iso_usb_traffic.3493958900 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_max_usb_traffic.2187184012 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 3152236220 ps |
| CPU time | 89.47 seconds |
| Started | Aug 21 07:55:55 AM UTC 24 |
| Finished | Aug 21 07:57:26 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2187184012 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2187184012 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_min_inter_pkt_delay.906873170 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 3701677164 ps |
| CPU time | 92.78 seconds |
| Started | Aug 21 07:55:56 AM UTC 24 |
| Finished | Aug 21 07:57:31 AM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=906873170 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.906873170 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_min_length_in_transaction.3194343522 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 161384663 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:55:56 AM UTC 24 |
| Finished | Aug 21 07:55:58 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3194343522 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.3194343522 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_min_length_out_transaction.1394129154 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 200869000 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:55:56 AM UTC 24 |
| Finished | Aug 21 07:55:59 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1394129154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1394129154 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_nak_trans.554654730 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 237644138 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 07:55:56 AM UTC 24 |
| Finished | Aug 21 07:55:59 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=554654730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.554654730 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_out_iso.3476487016 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 179529501 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 07:55:58 AM UTC 24 |
| Finished | Aug 21 07:56:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3476487016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3476487016 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_out_stall.3876866738 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 232630748 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 07:55:58 AM UTC 24 |
| Finished | Aug 21 07:56:00 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3876866738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3876866738 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_out_trans_nak.3464598308 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 179021574 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:55:58 AM UTC 24 |
| Finished | Aug 21 07:56:00 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3464598308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3464598308 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_pending_in_trans.36542419 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 167484803 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:55:58 AM UTC 24 |
| Finished | Aug 21 07:56:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36542419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.36542419 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_phy_config_pinflip.1373994907 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 286858328 ps |
| CPU time | 1.97 seconds |
| Started | Aug 21 07:55:59 AM UTC 24 |
| Finished | Aug 21 07:56:02 AM UTC 24 |
| Peak memory | 215992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1373994907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.1373994907 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_phy_config_usb_ref_disable.1866611347 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 158722696 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 07:55:59 AM UTC 24 |
| Finished | Aug 21 07:56:01 AM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1866611347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1866611347 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_phy_pins_sense.4262747131 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 103836521 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 07:56:00 AM UTC 24 |
| Finished | Aug 21 07:56:03 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4262747131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.4262747131 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_pkt_buffer.760958244 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 21151386169 ps |
| CPU time | 55.21 seconds |
| Started | Aug 21 07:56:00 AM UTC 24 |
| Finished | Aug 21 07:56:57 AM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=760958244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.760958244 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_pkt_received.2110270877 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 158471817 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:56:01 AM UTC 24 |
| Finished | Aug 21 07:56:03 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2110270877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2110270877 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_pkt_sent.1683570628 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 177349133 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:56:01 AM UTC 24 |
| Finished | Aug 21 07:56:03 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683570628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1683570628 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_random_length_in_transaction.1575371977 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 242900242 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 07:56:01 AM UTC 24 |
| Finished | Aug 21 07:56:03 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1575371977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.1575371977 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_random_length_out_transaction.474577990 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 222349628 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 07:56:02 AM UTC 24 |
| Finished | Aug 21 07:56:05 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=474577990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.474577990 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_resume_link_active.1730356847 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 20184523172 ps |
| CPU time | 34.29 seconds |
| Started | Aug 21 07:56:02 AM UTC 24 |
| Finished | Aug 21 07:56:38 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1730356847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_resume_link_active.1730356847 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_rx_crc_err.4104954037 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 159206343 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 07:56:02 AM UTC 24 |
| Finished | Aug 21 07:56:04 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4104954037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.4104954037 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_rx_full.360539367 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 300102077 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:56:02 AM UTC 24 |
| Finished | Aug 21 07:56:05 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=360539367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_full.360539367 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_setup_stage.2464798113 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 165383715 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:56:02 AM UTC 24 |
| Finished | Aug 21 07:56:05 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2464798113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.2464798113 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_setup_trans_ignored.339446327 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 173332897 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:56:02 AM UTC 24 |
| Finished | Aug 21 07:56:05 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=339446327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.339446327 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_smoke.1948239028 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 285293476 ps |
| CPU time | 1.98 seconds |
| Started | Aug 21 07:56:04 AM UTC 24 |
| Finished | Aug 21 07:56:07 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1948239028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1948239028 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_spurious_pids_ignored.2842693409 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 3301273554 ps |
| CPU time | 84.93 seconds |
| Started | Aug 21 07:56:04 AM UTC 24 |
| Finished | Aug 21 07:57:31 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2842693409 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.2842693409 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_stall_priority_over_nak.2130481391 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 166553908 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 07:56:04 AM UTC 24 |
| Finished | Aug 21 07:56:06 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2130481391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2130481391 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_stall_trans.1648307250 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 204625363 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:56:04 AM UTC 24 |
| Finished | Aug 21 07:56:07 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1648307250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.1648307250 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_stream_len_max.2062446467 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 875152501 ps |
| CPU time | 2.81 seconds |
| Started | Aug 21 07:56:04 AM UTC 24 |
| Finished | Aug 21 07:56:08 AM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2062446467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.2062446467 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_streaming_out.3676998333 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 3325491428 ps |
| CPU time | 31 seconds |
| Started | Aug 21 07:56:04 AM UTC 24 |
| Finished | Aug 21 07:56:36 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3676998333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3676998333 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_timeout_missing_host_handshake.3892983319 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 588110223 ps |
| CPU time | 13.2 seconds |
| Started | Aug 21 07:55:49 AM UTC 24 |
| Finished | Aug 21 07:56:03 AM UTC 24 |
| Peak memory | 218192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3892983319 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing _host_handshake.3892983319 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/13.usbdev_tx_rx_disruption.2185605698 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 533831827 ps |
| CPU time | 1.89 seconds |
| Started | Aug 21 07:56:04 AM UTC 24 |
| Finished | Aug 21 07:56:07 AM UTC 24 |
| Peak memory | 216376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2185605698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.usbdev_tx_rx_disruption.2185605698 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/13.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/130.usbdev_tx_rx_disruption.1078272239 |
| Short name | T3236 |
| Test name | |
| Test status | |
| Simulation time | 569057536 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:06:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1078272239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 130.usbdev_tx_rx_disruption.1078272239 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/130.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/131.usbdev_endpoint_types.1322015668 |
| Short name | T3240 |
| Test name | |
| Test status | |
| Simulation time | 288698434 ps |
| CPU time | 0.94 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:06:06 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1322015668 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_endpoint_types.1322015668 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/131.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/131.usbdev_tx_rx_disruption.253848847 |
| Short name | T3212 |
| Test name | |
| Test status | |
| Simulation time | 490716379 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:55 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=253848847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 131.usbdev_tx_rx_disruption.253848847 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/131.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/132.usbdev_endpoint_types.3146038108 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 170859783 ps |
| CPU time | 0.74 seconds |
| Started | Aug 21 08:05:52 AM UTC 24 |
| Finished | Aug 21 08:05:54 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3146038108 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_endpoint_types.3146038108 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/132.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/132.usbdev_tx_rx_disruption.3701525779 |
| Short name | T3211 |
| Test name | |
| Test status | |
| Simulation time | 436254258 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:05:55 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3701525779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 132.usbdev_tx_rx_disruption.3701525779 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/132.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/133.usbdev_tx_rx_disruption.3090963864 |
| Short name | T3241 |
| Test name | |
| Test status | |
| Simulation time | 447017296 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3090963864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 133.usbdev_tx_rx_disruption.3090963864 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/133.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/134.usbdev_tx_rx_disruption.1649104754 |
| Short name | T3243 |
| Test name | |
| Test status | |
| Simulation time | 561322965 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1649104754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 134.usbdev_tx_rx_disruption.1649104754 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/134.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/135.usbdev_endpoint_types.1612403828 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 236718759 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:16 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1612403828 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_endpoint_types.1612403828 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/135.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/135.usbdev_tx_rx_disruption.934219841 |
| Short name | T3261 |
| Test name | |
| Test status | |
| Simulation time | 622260338 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=934219841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 135.usbdev_tx_rx_disruption.934219841 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/135.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/136.usbdev_tx_rx_disruption.496496768 |
| Short name | T3221 |
| Test name | |
| Test status | |
| Simulation time | 466693724 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:05:56 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=496496768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 136.usbdev_tx_rx_disruption.496496768 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/136.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/137.usbdev_endpoint_types.2503053739 |
| Short name | T3258 |
| Test name | |
| Test status | |
| Simulation time | 327474304 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:16 AM UTC 24 |
| Peak memory | 216432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2503053739 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_endpoint_types.2503053739 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/137.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/137.usbdev_tx_rx_disruption.1061966597 |
| Short name | T3267 |
| Test name | |
| Test status | |
| Simulation time | 604283601 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1061966597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 137.usbdev_tx_rx_disruption.1061966597 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/137.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/138.usbdev_endpoint_types.2706040405 |
| Short name | T3257 |
| Test name | |
| Test status | |
| Simulation time | 292671295 ps |
| CPU time | 0.91 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:16 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2706040405 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_endpoint_types.2706040405 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/138.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/138.usbdev_tx_rx_disruption.2403575555 |
| Short name | T3268 |
| Test name | |
| Test status | |
| Simulation time | 646856342 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2403575555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 138.usbdev_tx_rx_disruption.2403575555 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/138.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/139.usbdev_endpoint_types.1962199543 |
| Short name | T3256 |
| Test name | |
| Test status | |
| Simulation time | 220236233 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:16 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1962199543 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_endpoint_types.1962199543 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/139.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/139.usbdev_tx_rx_disruption.112884519 |
| Short name | T3269 |
| Test name | |
| Test status | |
| Simulation time | 593228513 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=112884519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 139.usbdev_tx_rx_disruption.112884519 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/139.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_alert_test.683237844 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 38273711 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 07:56:27 AM UTC 24 |
| Finished | Aug 21 07:56:29 AM UTC 24 |
| Peak memory | 216236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=683237844 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.683237844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_aon_wake_disconnect.1633707597 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 11893290054 ps |
| CPU time | 21.36 seconds |
| Started | Aug 21 07:56:06 AM UTC 24 |
| Finished | Aug 21 07:56:28 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1633707597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbd ev_aon_wake_disconnect.1633707597 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_aon_wake_reset.3784526106 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 14050116241 ps |
| CPU time | 20.4 seconds |
| Started | Aug 21 07:56:06 AM UTC 24 |
| Finished | Aug 21 07:56:27 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3784526106 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3784526106 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_aon_wake_resume.2691476279 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 24799910136 ps |
| CPU time | 33 seconds |
| Started | Aug 21 07:56:06 AM UTC 24 |
| Finished | Aug 21 07:56:40 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2691476279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbd ev_aon_wake_resume.2691476279 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_av_buffer.3721218003 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 198571010 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:56:06 AM UTC 24 |
| Finished | Aug 21 07:56:08 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3721218003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3721218003 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_bitstuff_err.395370888 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 161854606 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 07:56:07 AM UTC 24 |
| Finished | Aug 21 07:56:09 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=395370888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.395370888 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_data_toggle_clear.2780982053 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 292755540 ps |
| CPU time | 1.76 seconds |
| Started | Aug 21 07:56:07 AM UTC 24 |
| Finished | Aug 21 07:56:10 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2780982053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.2780982053 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_data_toggle_restore.2551936856 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 353673724 ps |
| CPU time | 1.96 seconds |
| Started | Aug 21 07:56:08 AM UTC 24 |
| Finished | Aug 21 07:56:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2551936856 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2551936856 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_device_address.3737511385 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 41320402458 ps |
| CPU time | 77.74 seconds |
| Started | Aug 21 07:56:08 AM UTC 24 |
| Finished | Aug 21 07:57:28 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3737511385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.3737511385 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_device_timeout.1962846838 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 3652862367 ps |
| CPU time | 24.43 seconds |
| Started | Aug 21 07:56:09 AM UTC 24 |
| Finished | Aug 21 07:56:34 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1962846838 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.1962846838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_disable_endpoint.3331326817 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 683994300 ps |
| CPU time | 3.16 seconds |
| Started | Aug 21 07:56:09 AM UTC 24 |
| Finished | Aug 21 07:56:13 AM UTC 24 |
| Peak memory | 218040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3331326817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3331326817 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_disconnected.3546919575 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 144470619 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:56:09 AM UTC 24 |
| Finished | Aug 21 07:56:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3546919575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3546919575 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_enable.2754289603 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 57795123 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 07:56:10 AM UTC 24 |
| Finished | Aug 21 07:56:12 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2754289603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2754289603 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_endpoint_access.3264337069 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 953676495 ps |
| CPU time | 4.99 seconds |
| Started | Aug 21 07:56:10 AM UTC 24 |
| Finished | Aug 21 07:56:16 AM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3264337069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3264337069 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_endpoint_types.2199561859 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 222383477 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:56:10 AM UTC 24 |
| Finished | Aug 21 07:56:13 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2199561859 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_types.2199561859 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_fifo_rst.464571688 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 188017022 ps |
| CPU time | 2.29 seconds |
| Started | Aug 21 07:56:10 AM UTC 24 |
| Finished | Aug 21 07:56:14 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=464571688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.464571688 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_in_iso.2557390938 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 230474276 ps |
| CPU time | 2.07 seconds |
| Started | Aug 21 07:56:12 AM UTC 24 |
| Finished | Aug 21 07:56:15 AM UTC 24 |
| Peak memory | 228328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2557390938 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2557390938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_in_stall.265569421 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 180414019 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:56:13 AM UTC 24 |
| Finished | Aug 21 07:56:16 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=265569421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.265569421 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_in_trans.730427506 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 235759003 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:56:13 AM UTC 24 |
| Finished | Aug 21 07:56:16 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=730427506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.730427506 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_invalid_sync.3175748489 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 3696383398 ps |
| CPU time | 35.01 seconds |
| Started | Aug 21 07:56:12 AM UTC 24 |
| Finished | Aug 21 07:56:48 AM UTC 24 |
| Peak memory | 235180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3175748489 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.3175748489 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_iso_retraction.458227783 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 6917279090 ps |
| CPU time | 79.99 seconds |
| Started | Aug 21 07:56:13 AM UTC 24 |
| Finished | Aug 21 07:57:35 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=458227783 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.458227783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_link_in_err.594209043 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 284265511 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:56:13 AM UTC 24 |
| Finished | Aug 21 07:56:16 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=594209043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.594209043 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_link_resume.4102538893 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 14940915324 ps |
| CPU time | 23.14 seconds |
| Started | Aug 21 07:56:14 AM UTC 24 |
| Finished | Aug 21 07:56:38 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4102538893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.4102538893 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_link_suspend.2312901500 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 10708085315 ps |
| CPU time | 15.01 seconds |
| Started | Aug 21 07:56:14 AM UTC 24 |
| Finished | Aug 21 07:56:30 AM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2312901500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.2312901500 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_low_speed_traffic.2739442916 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 3350678781 ps |
| CPU time | 35.2 seconds |
| Started | Aug 21 07:56:14 AM UTC 24 |
| Finished | Aug 21 07:56:50 AM UTC 24 |
| Peak memory | 230628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2739442916 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.2739442916 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_max_inter_pkt_delay.3980417239 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 2590525937 ps |
| CPU time | 18.15 seconds |
| Started | Aug 21 07:56:15 AM UTC 24 |
| Finished | Aug 21 07:56:34 AM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3980417239 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.3980417239 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_max_length_in_transaction.2037400969 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 285078416 ps |
| CPU time | 1.84 seconds |
| Started | Aug 21 07:56:15 AM UTC 24 |
| Finished | Aug 21 07:56:18 AM UTC 24 |
| Peak memory | 216212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2037400969 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2037400969 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_max_length_out_transaction.1915152908 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 208296538 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:56:15 AM UTC 24 |
| Finished | Aug 21 07:56:17 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1915152908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1915152908 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_max_non_iso_usb_traffic.2972362546 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 2896043823 ps |
| CPU time | 26.34 seconds |
| Started | Aug 21 07:56:15 AM UTC 24 |
| Finished | Aug 21 07:56:43 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2972362546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_non_iso_usb_traffic.2972362546 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_max_usb_traffic.2706795085 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 2823011133 ps |
| CPU time | 30.35 seconds |
| Started | Aug 21 07:56:15 AM UTC 24 |
| Finished | Aug 21 07:56:47 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2706795085 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.2706795085 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_min_inter_pkt_delay.365588546 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 1771317698 ps |
| CPU time | 47.03 seconds |
| Started | Aug 21 07:56:17 AM UTC 24 |
| Finished | Aug 21 07:57:06 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=365588546 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.365588546 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_min_length_in_transaction.879874544 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 152535036 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 07:56:17 AM UTC 24 |
| Finished | Aug 21 07:56:19 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=879874544 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.879874544 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_min_length_out_transaction.4058036975 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 161734589 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:56:17 AM UTC 24 |
| Finished | Aug 21 07:56:19 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4058036975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.4058036975 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_out_iso.1450733232 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 154255433 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:56:17 AM UTC 24 |
| Finished | Aug 21 07:56:20 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1450733232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1450733232 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_out_stall.3101394316 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 180612517 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:56:17 AM UTC 24 |
| Finished | Aug 21 07:56:20 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3101394316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3101394316 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_out_trans_nak.2734645110 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 152067201 ps |
| CPU time | 1 seconds |
| Started | Aug 21 07:56:18 AM UTC 24 |
| Finished | Aug 21 07:56:20 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2734645110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2734645110 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_pending_in_trans.1800650892 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 148174377 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 07:56:18 AM UTC 24 |
| Finished | Aug 21 07:56:21 AM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1800650892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.1800650892 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_phy_config_pinflip.465429493 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 182451995 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:56:19 AM UTC 24 |
| Finished | Aug 21 07:56:21 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=465429493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.465429493 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_phy_config_usb_ref_disable.2495221683 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 148564174 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:56:20 AM UTC 24 |
| Finished | Aug 21 07:56:22 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2495221683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2495221683 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_phy_pins_sense.534381320 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 48646538 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 07:56:21 AM UTC 24 |
| Finished | Aug 21 07:56:23 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=534381320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.534381320 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_pkt_buffer.1398183961 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 11173201295 ps |
| CPU time | 37.82 seconds |
| Started | Aug 21 07:56:21 AM UTC 24 |
| Finished | Aug 21 07:57:00 AM UTC 24 |
| Peak memory | 228448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1398183961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1398183961 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_pkt_received.292574675 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 195900377 ps |
| CPU time | 1.16 seconds |
| Started | Aug 21 07:56:21 AM UTC 24 |
| Finished | Aug 21 07:56:23 AM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=292574675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.292574675 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_pkt_sent.231556943 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 212212797 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 07:56:21 AM UTC 24 |
| Finished | Aug 21 07:56:23 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=231556943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.231556943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_random_length_in_transaction.3156738741 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 212486484 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:56:21 AM UTC 24 |
| Finished | Aug 21 07:56:24 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3156738741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3156738741 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_random_length_out_transaction.2906736932 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 183776906 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:56:21 AM UTC 24 |
| Finished | Aug 21 07:56:24 AM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2906736932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.2906736932 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_resume_link_active.724842838 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 20164190792 ps |
| CPU time | 31.62 seconds |
| Started | Aug 21 07:56:21 AM UTC 24 |
| Finished | Aug 21 07:56:54 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=724842838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_resume_link_active.724842838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_rx_crc_err.1818198639 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 179498884 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:56:21 AM UTC 24 |
| Finished | Aug 21 07:56:24 AM UTC 24 |
| Peak memory | 216408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1818198639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.1818198639 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_rx_full.505544053 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 352007813 ps |
| CPU time | 2.14 seconds |
| Started | Aug 21 07:56:23 AM UTC 24 |
| Finished | Aug 21 07:56:26 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=505544053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_full.505544053 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_setup_stage.1481817045 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 211364398 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:56:23 AM UTC 24 |
| Finished | Aug 21 07:56:25 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1481817045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1481817045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_setup_trans_ignored.171849062 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 182172792 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:56:25 AM UTC 24 |
| Finished | Aug 21 07:56:27 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=171849062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.171849062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_smoke.267301633 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 221147951 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:56:25 AM UTC 24 |
| Finished | Aug 21 07:56:27 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=267301633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.267301633 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_spurious_pids_ignored.3557415226 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 2106784359 ps |
| CPU time | 53.83 seconds |
| Started | Aug 21 07:56:25 AM UTC 24 |
| Finished | Aug 21 07:57:20 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3557415226 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.3557415226 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_stall_priority_over_nak.1779821942 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 199173207 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 07:56:25 AM UTC 24 |
| Finished | Aug 21 07:56:28 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1779821942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.1779821942 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_stall_trans.3108991886 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 178370469 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 07:56:25 AM UTC 24 |
| Finished | Aug 21 07:56:27 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3108991886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3108991886 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_stream_len_max.3946912684 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 983053793 ps |
| CPU time | 3.15 seconds |
| Started | Aug 21 07:56:25 AM UTC 24 |
| Finished | Aug 21 07:56:29 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3946912684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.3946912684 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_streaming_out.3741031657 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 3188683428 ps |
| CPU time | 85.46 seconds |
| Started | Aug 21 07:56:25 AM UTC 24 |
| Finished | Aug 21 07:57:53 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3741031657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3741031657 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_timeout_missing_host_handshake.1116442643 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 541946914 ps |
| CPU time | 10.09 seconds |
| Started | Aug 21 07:56:09 AM UTC 24 |
| Finished | Aug 21 07:56:20 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1116442643 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing _host_handshake.1116442643 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/14.usbdev_tx_rx_disruption.1285284685 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 581700330 ps |
| CPU time | 2.69 seconds |
| Started | Aug 21 07:56:25 AM UTC 24 |
| Finished | Aug 21 07:56:29 AM UTC 24 |
| Peak memory | 218192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1285284685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 14.usbdev_tx_rx_disruption.1285284685 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/14.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/140.usbdev_endpoint_types.1927411302 |
| Short name | T3263 |
| Test name | |
| Test status | |
| Simulation time | 550138053 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1927411302 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_endpoint_types.1927411302 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/140.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/140.usbdev_tx_rx_disruption.11734965 |
| Short name | T3271 |
| Test name | |
| Test status | |
| Simulation time | 604292019 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=11734965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 140.usbdev_tx_rx_disruption.11734965 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/140.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/141.usbdev_tx_rx_disruption.1059311759 |
| Short name | T3272 |
| Test name | |
| Test status | |
| Simulation time | 619064270 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1059311759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 141.usbdev_tx_rx_disruption.1059311759 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/141.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/142.usbdev_endpoint_types.1679729080 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 457009475 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1679729080 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_endpoint_types.1679729080 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/142.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/142.usbdev_tx_rx_disruption.119788618 |
| Short name | T3213 |
| Test name | |
| Test status | |
| Simulation time | 440949631 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:05:55 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=119788618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 142.usbdev_tx_rx_disruption.119788618 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/142.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/143.usbdev_endpoint_types.1234090364 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 449000124 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 08:05:53 AM UTC 24 |
| Finished | Aug 21 08:05:55 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1234090364 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_endpoint_types.1234090364 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/143.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/143.usbdev_tx_rx_disruption.1772793114 |
| Short name | T3276 |
| Test name | |
| Test status | |
| Simulation time | 490773773 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:05:55 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1772793114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 143.usbdev_tx_rx_disruption.1772793114 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/143.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/144.usbdev_endpoint_types.1927957604 |
| Short name | T3281 |
| Test name | |
| Test status | |
| Simulation time | 280291020 ps |
| CPU time | 0.96 seconds |
| Started | Aug 21 08:05:56 AM UTC 24 |
| Finished | Aug 21 08:06:18 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1927957604 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_endpoint_types.1927957604 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/144.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/144.usbdev_tx_rx_disruption.1100268853 |
| Short name | T3237 |
| Test name | |
| Test status | |
| Simulation time | 521949377 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:05:56 AM UTC 24 |
| Finished | Aug 21 08:06:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1100268853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 144.usbdev_tx_rx_disruption.1100268853 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/144.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/145.usbdev_endpoint_types.3677255574 |
| Short name | T3280 |
| Test name | |
| Test status | |
| Simulation time | 231041833 ps |
| CPU time | 0.88 seconds |
| Started | Aug 21 08:05:56 AM UTC 24 |
| Finished | Aug 21 08:06:18 AM UTC 24 |
| Peak memory | 215380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3677255574 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_endpoint_types.3677255574 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/145.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/145.usbdev_tx_rx_disruption.2358041870 |
| Short name | T3290 |
| Test name | |
| Test status | |
| Simulation time | 453520904 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:05:56 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2358041870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 145.usbdev_tx_rx_disruption.2358041870 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/145.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/146.usbdev_endpoint_types.2876268472 |
| Short name | T3283 |
| Test name | |
| Test status | |
| Simulation time | 336532608 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 08:05:56 AM UTC 24 |
| Finished | Aug 21 08:06:18 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2876268472 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_endpoint_types.2876268472 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/146.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/146.usbdev_tx_rx_disruption.1867767518 |
| Short name | T3238 |
| Test name | |
| Test status | |
| Simulation time | 468883122 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:05:56 AM UTC 24 |
| Finished | Aug 21 08:06:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1867767518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 146.usbdev_tx_rx_disruption.1867767518 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/146.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/147.usbdev_tx_rx_disruption.3169854250 |
| Short name | T3288 |
| Test name | |
| Test status | |
| Simulation time | 454735444 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:05:56 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3169854250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 147.usbdev_tx_rx_disruption.3169854250 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/147.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/148.usbdev_endpoint_types.194009294 |
| Short name | T3285 |
| Test name | |
| Test status | |
| Simulation time | 433505739 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=194009294 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_endpoint_types.194009294 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/148.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/148.usbdev_tx_rx_disruption.3341200198 |
| Short name | T3286 |
| Test name | |
| Test status | |
| Simulation time | 458956469 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 215896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3341200198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 148.usbdev_tx_rx_disruption.3341200198 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/148.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/149.usbdev_endpoint_types.3051337862 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 480195470 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:00 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3051337862 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_endpoint_types.3051337862 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/149.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/149.usbdev_tx_rx_disruption.3227328347 |
| Short name | T3292 |
| Test name | |
| Test status | |
| Simulation time | 496763020 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3227328347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 149.usbdev_tx_rx_disruption.3227328347 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/149.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_alert_test.2850142524 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 65207944 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 07:56:47 AM UTC 24 |
| Finished | Aug 21 07:56:49 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2850142524 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2850142524 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_aon_wake_disconnect.3791577389 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 10166326061 ps |
| CPU time | 15.56 seconds |
| Started | Aug 21 07:56:27 AM UTC 24 |
| Finished | Aug 21 07:56:44 AM UTC 24 |
| Peak memory | 218104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3791577389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbd ev_aon_wake_disconnect.3791577389 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_aon_wake_reset.2453385800 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 20719493409 ps |
| CPU time | 26.58 seconds |
| Started | Aug 21 07:56:27 AM UTC 24 |
| Finished | Aug 21 07:56:55 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2453385800 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.2453385800 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_aon_wake_resume.870326431 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 28893029624 ps |
| CPU time | 43.82 seconds |
| Started | Aug 21 07:56:27 AM UTC 24 |
| Finished | Aug 21 07:57:12 AM UTC 24 |
| Peak memory | 218348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=870326431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbde v_aon_wake_resume.870326431 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_av_buffer.3558467408 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 177093533 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:56:29 AM UTC 24 |
| Finished | Aug 21 07:56:31 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3558467408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3558467408 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_bitstuff_err.369427463 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 142083060 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:56:29 AM UTC 24 |
| Finished | Aug 21 07:56:31 AM UTC 24 |
| Peak memory | 216368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=369427463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.369427463 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_data_toggle_clear.2302570917 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 403451564 ps |
| CPU time | 1.9 seconds |
| Started | Aug 21 07:56:29 AM UTC 24 |
| Finished | Aug 21 07:56:32 AM UTC 24 |
| Peak memory | 216376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2302570917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.2302570917 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_data_toggle_restore.3077348484 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 491121185 ps |
| CPU time | 2.32 seconds |
| Started | Aug 21 07:56:29 AM UTC 24 |
| Finished | Aug 21 07:56:32 AM UTC 24 |
| Peak memory | 218136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3077348484 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3077348484 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_device_address.2448382443 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 49445154155 ps |
| CPU time | 77.56 seconds |
| Started | Aug 21 07:56:29 AM UTC 24 |
| Finished | Aug 21 07:57:48 AM UTC 24 |
| Peak memory | 218252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2448382443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.2448382443 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_device_timeout.1667603616 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 144745463 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:56:29 AM UTC 24 |
| Finished | Aug 21 07:56:31 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1667603616 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.1667603616 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_disable_endpoint.4046272058 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 683231490 ps |
| CPU time | 3.2 seconds |
| Started | Aug 21 07:56:30 AM UTC 24 |
| Finished | Aug 21 07:56:35 AM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4046272058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.4046272058 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_disconnected.1028744551 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 142412545 ps |
| CPU time | 1.16 seconds |
| Started | Aug 21 07:56:30 AM UTC 24 |
| Finished | Aug 21 07:56:33 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1028744551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1028744551 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_enable.4117361343 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 61922569 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 07:56:30 AM UTC 24 |
| Finished | Aug 21 07:56:32 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4117361343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.4117361343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_endpoint_access.442259475 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 778850872 ps |
| CPU time | 3.5 seconds |
| Started | Aug 21 07:56:31 AM UTC 24 |
| Finished | Aug 21 07:56:35 AM UTC 24 |
| Peak memory | 218352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=442259475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.442259475 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_fifo_rst.1735354102 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 269405456 ps |
| CPU time | 2.79 seconds |
| Started | Aug 21 07:56:32 AM UTC 24 |
| Finished | Aug 21 07:56:36 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1735354102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1735354102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_in_iso.180811785 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 242222804 ps |
| CPU time | 1.72 seconds |
| Started | Aug 21 07:56:32 AM UTC 24 |
| Finished | Aug 21 07:56:35 AM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=180811785 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.180811785 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_in_stall.784778128 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 143950289 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:56:33 AM UTC 24 |
| Finished | Aug 21 07:56:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=784778128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.784778128 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_in_trans.3560906996 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 278795463 ps |
| CPU time | 1.89 seconds |
| Started | Aug 21 07:56:33 AM UTC 24 |
| Finished | Aug 21 07:56:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3560906996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3560906996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_invalid_sync.3778301599 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 4932978971 ps |
| CPU time | 48.44 seconds |
| Started | Aug 21 07:56:32 AM UTC 24 |
| Finished | Aug 21 07:57:22 AM UTC 24 |
| Peak memory | 230360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3778301599 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.3778301599 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_iso_retraction.907024389 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 4832059557 ps |
| CPU time | 35.26 seconds |
| Started | Aug 21 07:56:33 AM UTC 24 |
| Finished | Aug 21 07:57:10 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=907024389 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.907024389 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_link_in_err.3147652060 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 231710325 ps |
| CPU time | 1.73 seconds |
| Started | Aug 21 07:56:33 AM UTC 24 |
| Finished | Aug 21 07:56:36 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3147652060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3147652060 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_link_resume.2580478817 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 24560036701 ps |
| CPU time | 45.27 seconds |
| Started | Aug 21 07:56:34 AM UTC 24 |
| Finished | Aug 21 07:57:20 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2580478817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.2580478817 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_link_suspend.3269791876 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 8921843604 ps |
| CPU time | 12.88 seconds |
| Started | Aug 21 07:56:35 AM UTC 24 |
| Finished | Aug 21 07:56:49 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3269791876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3269791876 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_low_speed_traffic.1315550649 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 4798841258 ps |
| CPU time | 123.81 seconds |
| Started | Aug 21 07:56:35 AM UTC 24 |
| Finished | Aug 21 07:58:41 AM UTC 24 |
| Peak memory | 230668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1315550649 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.1315550649 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_max_inter_pkt_delay.4033955696 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 2077851891 ps |
| CPU time | 22.4 seconds |
| Started | Aug 21 07:56:35 AM UTC 24 |
| Finished | Aug 21 07:56:59 AM UTC 24 |
| Peak memory | 228324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4033955696 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.4033955696 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_max_length_in_transaction.1756261660 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 263278708 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 07:56:36 AM UTC 24 |
| Finished | Aug 21 07:56:39 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1756261660 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.1756261660 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_max_length_out_transaction.4021301114 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 203553570 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 07:56:36 AM UTC 24 |
| Finished | Aug 21 07:56:39 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4021301114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.4021301114 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_max_non_iso_usb_traffic.2590915426 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 3004886732 ps |
| CPU time | 79.49 seconds |
| Started | Aug 21 07:56:36 AM UTC 24 |
| Finished | Aug 21 07:57:58 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2590915426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_non_iso_usb_traffic.2590915426 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_min_inter_pkt_delay.2339766125 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 2602773541 ps |
| CPU time | 70.99 seconds |
| Started | Aug 21 07:56:36 AM UTC 24 |
| Finished | Aug 21 07:57:49 AM UTC 24 |
| Peak memory | 228608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2339766125 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.2339766125 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_min_length_in_transaction.3655876026 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 155141445 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:56:36 AM UTC 24 |
| Finished | Aug 21 07:56:39 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3655876026 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3655876026 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_min_length_out_transaction.2336319569 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 158912081 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 07:56:38 AM UTC 24 |
| Finished | Aug 21 07:56:40 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2336319569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2336319569 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_nak_trans.687812631 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 189583296 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:56:38 AM UTC 24 |
| Finished | Aug 21 07:56:40 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=687812631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.687812631 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_out_iso.2801649185 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 192538191 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:56:38 AM UTC 24 |
| Finished | Aug 21 07:56:40 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2801649185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2801649185 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_out_stall.3988054907 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 197421468 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:56:39 AM UTC 24 |
| Finished | Aug 21 07:56:41 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3988054907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3988054907 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_out_trans_nak.2979192530 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 185770167 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 07:56:39 AM UTC 24 |
| Finished | Aug 21 07:56:42 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2979192530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2979192530 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_pending_in_trans.2471912319 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 158709296 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:56:40 AM UTC 24 |
| Finished | Aug 21 07:56:43 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2471912319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2471912319 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_phy_config_pinflip.3945318885 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 286673691 ps |
| CPU time | 1.94 seconds |
| Started | Aug 21 07:56:40 AM UTC 24 |
| Finished | Aug 21 07:56:43 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3945318885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.3945318885 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_phy_config_usb_ref_disable.735323438 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 139341520 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:56:40 AM UTC 24 |
| Finished | Aug 21 07:56:43 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=735323438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.735323438 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_phy_pins_sense.1711143655 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 139912261 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:56:41 AM UTC 24 |
| Finished | Aug 21 07:56:43 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1711143655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1711143655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_pkt_buffer.437852735 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 19160089230 ps |
| CPU time | 54.08 seconds |
| Started | Aug 21 07:56:42 AM UTC 24 |
| Finished | Aug 21 07:57:38 AM UTC 24 |
| Peak memory | 228512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=437852735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.437852735 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_pkt_received.2239775394 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 173759807 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:56:42 AM UTC 24 |
| Finished | Aug 21 07:56:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2239775394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2239775394 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_pkt_sent.980687481 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 212567293 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 07:56:42 AM UTC 24 |
| Finished | Aug 21 07:56:45 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=980687481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.980687481 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_random_length_in_transaction.1572226266 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 204478032 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:56:42 AM UTC 24 |
| Finished | Aug 21 07:56:45 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1572226266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.1572226266 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_random_length_out_transaction.81544409 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 231706648 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 07:56:43 AM UTC 24 |
| Finished | Aug 21 07:56:46 AM UTC 24 |
| Peak memory | 216592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=81544409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.81544409 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_resume_link_active.2455138119 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 20199104231 ps |
| CPU time | 28.65 seconds |
| Started | Aug 21 07:56:45 AM UTC 24 |
| Finished | Aug 21 07:57:15 AM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2455138119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_resume_link_active.2455138119 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_rx_crc_err.2269918761 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 149665230 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:56:45 AM UTC 24 |
| Finished | Aug 21 07:56:47 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2269918761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2269918761 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_rx_full.23376447 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 247542581 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:56:45 AM UTC 24 |
| Finished | Aug 21 07:56:47 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23376447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_full.23376447 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_setup_stage.3230551850 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 149636513 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 07:56:45 AM UTC 24 |
| Finished | Aug 21 07:56:47 AM UTC 24 |
| Peak memory | 216368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3230551850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3230551850 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_setup_trans_ignored.3868390017 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 169020186 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:56:45 AM UTC 24 |
| Finished | Aug 21 07:56:47 AM UTC 24 |
| Peak memory | 216436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3868390017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.3868390017 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_smoke.862634698 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 242039434 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:56:45 AM UTC 24 |
| Finished | Aug 21 07:56:47 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=862634698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.862634698 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_spurious_pids_ignored.483740567 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 2130575955 ps |
| CPU time | 54.42 seconds |
| Started | Aug 21 07:56:45 AM UTC 24 |
| Finished | Aug 21 07:57:41 AM UTC 24 |
| Peak memory | 235120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=483740567 -assert nopostproc +UVM_TESTNAME=usbdev_bas e_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.483740567 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_stall_priority_over_nak.1594569719 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 183720024 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:56:46 AM UTC 24 |
| Finished | Aug 21 07:56:49 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1594569719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1594569719 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_stall_trans.1482235670 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 199370598 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:56:46 AM UTC 24 |
| Finished | Aug 21 07:56:49 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1482235670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1482235670 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_stream_len_max.2371154728 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 1020888527 ps |
| CPU time | 2.62 seconds |
| Started | Aug 21 07:56:47 AM UTC 24 |
| Finished | Aug 21 07:56:51 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2371154728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.2371154728 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_streaming_out.1728533056 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 2205084832 ps |
| CPU time | 51.61 seconds |
| Started | Aug 21 07:56:46 AM UTC 24 |
| Finished | Aug 21 07:57:40 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1728533056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.1728533056 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_timeout_missing_host_handshake.3285203106 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 4346225291 ps |
| CPU time | 29.08 seconds |
| Started | Aug 21 07:56:29 AM UTC 24 |
| Finished | Aug 21 07:56:59 AM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3285203106 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing _host_handshake.3285203106 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/15.usbdev_tx_rx_disruption.3069271504 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 451936392 ps |
| CPU time | 1.73 seconds |
| Started | Aug 21 07:56:47 AM UTC 24 |
| Finished | Aug 21 07:56:50 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3069271504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.usbdev_tx_rx_disruption.3069271504 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/15.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/150.usbdev_endpoint_types.2834378546 |
| Short name | T3279 |
| Test name | |
| Test status | |
| Simulation time | 234175838 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:18 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2834378546 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_endpoint_types.2834378546 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/150.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/150.usbdev_tx_rx_disruption.3563660483 |
| Short name | T3287 |
| Test name | |
| Test status | |
| Simulation time | 520010820 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3563660483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 150.usbdev_tx_rx_disruption.3563660483 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/150.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/151.usbdev_endpoint_types.4034322705 |
| Short name | T3284 |
| Test name | |
| Test status | |
| Simulation time | 380377849 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4034322705 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_endpoint_types.4034322705 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/151.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/151.usbdev_tx_rx_disruption.4132559982 |
| Short name | T3254 |
| Test name | |
| Test status | |
| Simulation time | 641542352 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4132559982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 151.usbdev_tx_rx_disruption.4132559982 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/151.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/152.usbdev_endpoint_types.1997428453 |
| Short name | T3275 |
| Test name | |
| Test status | |
| Simulation time | 185705920 ps |
| CPU time | 0.79 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1997428453 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_endpoint_types.1997428453 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/152.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/152.usbdev_tx_rx_disruption.816051136 |
| Short name | T3253 |
| Test name | |
| Test status | |
| Simulation time | 521543962 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=816051136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 152.usbdev_tx_rx_disruption.816051136 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/152.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/153.usbdev_endpoint_types.218329697 |
| Short name | T3224 |
| Test name | |
| Test status | |
| Simulation time | 400135437 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:00 AM UTC 24 |
| Peak memory | 214876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=218329697 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_endpoint_types.218329697 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/153.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/153.usbdev_tx_rx_disruption.1479523364 |
| Short name | T3225 |
| Test name | |
| Test status | |
| Simulation time | 527347583 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:00 AM UTC 24 |
| Peak memory | 215064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1479523364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 153.usbdev_tx_rx_disruption.1479523364 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/153.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/154.usbdev_endpoint_types.2919033485 |
| Short name | T3227 |
| Test name | |
| Test status | |
| Simulation time | 693204740 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:01 AM UTC 24 |
| Peak memory | 216212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2919033485 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_endpoint_types.2919033485 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/154.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/154.usbdev_tx_rx_disruption.3261676205 |
| Short name | T3231 |
| Test name | |
| Test status | |
| Simulation time | 608626009 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:01 AM UTC 24 |
| Peak memory | 215188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3261676205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 154.usbdev_tx_rx_disruption.3261676205 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/154.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/155.usbdev_endpoint_types.747427828 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 313046459 ps |
| CPU time | 0.96 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=747427828 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_endpoint_types.747427828 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/155.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/155.usbdev_tx_rx_disruption.3445172572 |
| Short name | T3228 |
| Test name | |
| Test status | |
| Simulation time | 624544070 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:01 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3445172572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 155.usbdev_tx_rx_disruption.3445172572 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/155.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/156.usbdev_tx_rx_disruption.1439793522 |
| Short name | T3230 |
| Test name | |
| Test status | |
| Simulation time | 604873492 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:01 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1439793522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 156.usbdev_tx_rx_disruption.1439793522 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/156.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/157.usbdev_endpoint_types.1018001191 |
| Short name | T3223 |
| Test name | |
| Test status | |
| Simulation time | 164074333 ps |
| CPU time | 0.78 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:00 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1018001191 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_endpoint_types.1018001191 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/157.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/157.usbdev_tx_rx_disruption.2809033551 |
| Short name | T3232 |
| Test name | |
| Test status | |
| Simulation time | 631402996 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:01 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2809033551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 157.usbdev_tx_rx_disruption.2809033551 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/157.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/158.usbdev_endpoint_types.79489661 |
| Short name | T3226 |
| Test name | |
| Test status | |
| Simulation time | 312617968 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:00 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=79489661 -assert nopostproc +UVM_TESTNAME=usbdev _base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_endpoint_types.79489661 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/158.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/158.usbdev_tx_rx_disruption.2276288724 |
| Short name | T3229 |
| Test name | |
| Test status | |
| Simulation time | 454387561 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:01 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2276288724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 158.usbdev_tx_rx_disruption.2276288724 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/158.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/159.usbdev_endpoint_types.1899955297 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 469968567 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:01 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1899955297 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_endpoint_types.1899955297 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/159.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/159.usbdev_tx_rx_disruption.398654833 |
| Short name | T3234 |
| Test name | |
| Test status | |
| Simulation time | 799635245 ps |
| CPU time | 1.86 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:01 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=398654833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 159.usbdev_tx_rx_disruption.398654833 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/159.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_alert_test.631914871 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 39224027 ps |
| CPU time | 1 seconds |
| Started | Aug 21 07:57:04 AM UTC 24 |
| Finished | Aug 21 07:57:06 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=631914871 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.631914871 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_aon_wake_disconnect.4186659201 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 9881108052 ps |
| CPU time | 14.02 seconds |
| Started | Aug 21 07:56:47 AM UTC 24 |
| Finished | Aug 21 07:57:02 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4186659201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbd ev_aon_wake_disconnect.4186659201 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_aon_wake_reset.857589222 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 15808829724 ps |
| CPU time | 19.7 seconds |
| Started | Aug 21 07:56:51 AM UTC 24 |
| Finished | Aug 21 07:57:12 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=857589222 -assert nopostp roc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.857589222 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_aon_wake_resume.4081012790 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 29361120571 ps |
| CPU time | 33.8 seconds |
| Started | Aug 21 07:56:51 AM UTC 24 |
| Finished | Aug 21 07:57:27 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4081012790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbd ev_aon_wake_resume.4081012790 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_av_buffer.646132695 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 166408979 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 07:56:52 AM UTC 24 |
| Finished | Aug 21 07:56:54 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=646132695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.646132695 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_bitstuff_err.3662319251 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 137702939 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 07:56:52 AM UTC 24 |
| Finished | Aug 21 07:56:54 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3662319251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3662319251 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_data_toggle_clear.2947349710 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 216587515 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 07:56:52 AM UTC 24 |
| Finished | Aug 21 07:56:54 AM UTC 24 |
| Peak memory | 216364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2947349710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.2947349710 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_device_address.1087721968 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 42280841656 ps |
| CPU time | 73.85 seconds |
| Started | Aug 21 07:56:52 AM UTC 24 |
| Finished | Aug 21 07:58:07 AM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1087721968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.1087721968 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_device_timeout.3906293924 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 5042494983 ps |
| CPU time | 30.25 seconds |
| Started | Aug 21 07:56:52 AM UTC 24 |
| Finished | Aug 21 07:57:24 AM UTC 24 |
| Peak memory | 218376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3906293924 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.3906293924 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_disable_endpoint.3681948101 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 556056676 ps |
| CPU time | 2.38 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:56:57 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3681948101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3681948101 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_disconnected.7351408 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 151784992 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:56:56 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=7351408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.7351408 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_enable.3271126305 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 74547762 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:56:56 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3271126305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3271126305 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_endpoint_access.1695062367 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 990153599 ps |
| CPU time | 2.94 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:56:58 AM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1695062367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1695062367 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_endpoint_types.2709035036 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 262924435 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:56:56 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2709035036 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_types.2709035036 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_fifo_rst.1640078556 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 244308125 ps |
| CPU time | 2.4 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:56:57 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1640078556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.1640078556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_in_iso.3482655213 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 241168042 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:56:57 AM UTC 24 |
| Peak memory | 226592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3482655213 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3482655213 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_in_stall.892806134 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 172081977 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:56:57 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=892806134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.892806134 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_in_trans.1793446741 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 177108876 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:56:56 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1793446741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1793446741 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_invalid_sync.4123654491 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 3212858811 ps |
| CPU time | 31.92 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:57:27 AM UTC 24 |
| Peak memory | 228588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4123654491 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.4123654491 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_iso_retraction.1444661269 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 5142093754 ps |
| CPU time | 34.99 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:57:31 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1444661269 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.1444661269 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_link_in_err.3455435356 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 194666995 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:56:57 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3455435356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3455435356 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_link_resume.916264924 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 5688853352 ps |
| CPU time | 9.28 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:57:05 AM UTC 24 |
| Peak memory | 228408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=916264924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.916264924 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_link_suspend.3026680905 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 4013119550 ps |
| CPU time | 7.35 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:57:03 AM UTC 24 |
| Peak memory | 228352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3026680905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.3026680905 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_low_speed_traffic.2862764167 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 4961300223 ps |
| CPU time | 33.79 seconds |
| Started | Aug 21 07:56:56 AM UTC 24 |
| Finished | Aug 21 07:57:31 AM UTC 24 |
| Peak memory | 230112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2862764167 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.2862764167 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_max_inter_pkt_delay.2748131846 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 2180267837 ps |
| CPU time | 15.9 seconds |
| Started | Aug 21 07:56:56 AM UTC 24 |
| Finished | Aug 21 07:57:13 AM UTC 24 |
| Peak memory | 228164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2748131846 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.2748131846 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_max_length_in_transaction.4022008986 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 247369022 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:56:56 AM UTC 24 |
| Finished | Aug 21 07:56:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4022008986 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.4022008986 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_max_length_out_transaction.998078896 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 195779292 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 07:56:56 AM UTC 24 |
| Finished | Aug 21 07:56:58 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=998078896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.998078896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_max_non_iso_usb_traffic.1520844929 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 2369279825 ps |
| CPU time | 18.03 seconds |
| Started | Aug 21 07:56:56 AM UTC 24 |
| Finished | Aug 21 07:57:15 AM UTC 24 |
| Peak memory | 228620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1520844929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_non_iso_usb_traffic.1520844929 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_min_inter_pkt_delay.529752304 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 3780548306 ps |
| CPU time | 98.07 seconds |
| Started | Aug 21 07:56:56 AM UTC 24 |
| Finished | Aug 21 07:58:36 AM UTC 24 |
| Peak memory | 228688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=529752304 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.529752304 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_min_length_in_transaction.3517101275 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 158281686 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:56:58 AM UTC 24 |
| Finished | Aug 21 07:57:00 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3517101275 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3517101275 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_min_length_out_transaction.3488575545 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 157832304 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:56:58 AM UTC 24 |
| Finished | Aug 21 07:57:00 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3488575545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3488575545 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_nak_trans.3534756169 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 241149223 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:56:58 AM UTC 24 |
| Finished | Aug 21 07:57:00 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3534756169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3534756169 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_out_iso.2867988896 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 207606832 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:56:58 AM UTC 24 |
| Finished | Aug 21 07:57:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2867988896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2867988896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_out_stall.285483917 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 186114466 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:56:58 AM UTC 24 |
| Finished | Aug 21 07:57:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=285483917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.285483917 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_out_trans_nak.1646150265 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 181457553 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 07:56:58 AM UTC 24 |
| Finished | Aug 21 07:57:00 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1646150265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1646150265 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_pending_in_trans.4019707097 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 146478150 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 07:56:58 AM UTC 24 |
| Finished | Aug 21 07:57:00 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4019707097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.4019707097 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_phy_config_pinflip.33671743 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 183703730 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:56:58 AM UTC 24 |
| Finished | Aug 21 07:57:00 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33671743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.33671743 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_phy_config_usb_ref_disable.1801164061 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 144817872 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:57:00 AM UTC 24 |
| Finished | Aug 21 07:57:02 AM UTC 24 |
| Peak memory | 216260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1801164061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1801164061 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_phy_pins_sense.990977079 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 61276276 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 07:57:00 AM UTC 24 |
| Finished | Aug 21 07:57:02 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=990977079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.990977079 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_pkt_buffer.2231059930 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 18033704890 ps |
| CPU time | 49.47 seconds |
| Started | Aug 21 07:57:00 AM UTC 24 |
| Finished | Aug 21 07:57:51 AM UTC 24 |
| Peak memory | 228648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2231059930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2231059930 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_pkt_received.3083333343 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 170864127 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 07:57:00 AM UTC 24 |
| Finished | Aug 21 07:57:02 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3083333343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3083333343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_pkt_sent.2970908872 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 215304309 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:57:00 AM UTC 24 |
| Finished | Aug 21 07:57:03 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2970908872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2970908872 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_random_length_in_transaction.3480312094 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 246809985 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 07:57:00 AM UTC 24 |
| Finished | Aug 21 07:57:03 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3480312094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.3480312094 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_random_length_out_transaction.3552654959 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 185658372 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 07:57:00 AM UTC 24 |
| Finished | Aug 21 07:57:02 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3552654959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.3552654959 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_resume_link_active.2192611597 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 20168142601 ps |
| CPU time | 33.1 seconds |
| Started | Aug 21 07:57:01 AM UTC 24 |
| Finished | Aug 21 07:57:36 AM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2192611597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_resume_link_active.2192611597 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_rx_crc_err.1723419184 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 169326235 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:57:02 AM UTC 24 |
| Finished | Aug 21 07:57:04 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1723419184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.1723419184 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_rx_full.1510134803 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 393186086 ps |
| CPU time | 1.96 seconds |
| Started | Aug 21 07:57:02 AM UTC 24 |
| Finished | Aug 21 07:57:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1510134803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_full.1510134803 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_setup_stage.2595210978 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 154115380 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:57:02 AM UTC 24 |
| Finished | Aug 21 07:57:04 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2595210978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2595210978 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_setup_trans_ignored.306899169 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 204543092 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:57:02 AM UTC 24 |
| Finished | Aug 21 07:57:04 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=306899169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.306899169 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_smoke.2494428404 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 197331590 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 07:57:02 AM UTC 24 |
| Finished | Aug 21 07:57:05 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2494428404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2494428404 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_spurious_pids_ignored.534701877 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 3942500105 ps |
| CPU time | 109.66 seconds |
| Started | Aug 21 07:57:02 AM UTC 24 |
| Finished | Aug 21 07:58:54 AM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=534701877 -assert nopostproc +UVM_TESTNAME=usbdev_bas e_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.534701877 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_stall_priority_over_nak.3179152528 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 206130684 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:57:02 AM UTC 24 |
| Finished | Aug 21 07:57:04 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3179152528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.3179152528 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_stall_trans.2909859934 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 163167870 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 07:57:02 AM UTC 24 |
| Finished | Aug 21 07:57:05 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2909859934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2909859934 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_stream_len_max.1734590495 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 1087817455 ps |
| CPU time | 2.88 seconds |
| Started | Aug 21 07:57:04 AM UTC 24 |
| Finished | Aug 21 07:57:08 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1734590495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.1734590495 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_streaming_out.1616624442 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 3495932250 ps |
| CPU time | 24.43 seconds |
| Started | Aug 21 07:57:02 AM UTC 24 |
| Finished | Aug 21 07:57:28 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1616624442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.1616624442 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_timeout_missing_host_handshake.3945337895 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 2452908005 ps |
| CPU time | 21.22 seconds |
| Started | Aug 21 07:56:54 AM UTC 24 |
| Finished | Aug 21 07:57:16 AM UTC 24 |
| Peak memory | 218312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3945337895 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing _host_handshake.3945337895 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/16.usbdev_tx_rx_disruption.1636738136 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 559399820 ps |
| CPU time | 2.77 seconds |
| Started | Aug 21 07:57:04 AM UTC 24 |
| Finished | Aug 21 07:57:08 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1636738136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 16.usbdev_tx_rx_disruption.1636738136 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/16.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/160.usbdev_endpoint_types.1128627317 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 609849887 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:05:58 AM UTC 24 |
| Finished | Aug 21 08:06:01 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1128627317 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_endpoint_types.1128627317 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/160.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/160.usbdev_tx_rx_disruption.1285335891 |
| Short name | T3273 |
| Test name | |
| Test status | |
| Simulation time | 599007066 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:06:01 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1285335891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 160.usbdev_tx_rx_disruption.1285335891 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/160.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/161.usbdev_endpoint_types.288173770 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 207203076 ps |
| CPU time | 0.87 seconds |
| Started | Aug 21 08:06:01 AM UTC 24 |
| Finished | Aug 21 08:06:16 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=288173770 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_endpoint_types.288173770 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/161.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/161.usbdev_tx_rx_disruption.701652090 |
| Short name | T3270 |
| Test name | |
| Test status | |
| Simulation time | 471083467 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:06:01 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=701652090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 161.usbdev_tx_rx_disruption.701652090 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/161.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/162.usbdev_endpoint_types.4278998126 |
| Short name | T3277 |
| Test name | |
| Test status | |
| Simulation time | 856115621 ps |
| CPU time | 1.85 seconds |
| Started | Aug 21 08:06:01 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4278998126 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_endpoint_types.4278998126 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/162.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/162.usbdev_tx_rx_disruption.2948002735 |
| Short name | T3247 |
| Test name | |
| Test status | |
| Simulation time | 451790939 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:06:01 AM UTC 24 |
| Finished | Aug 21 08:06:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2948002735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 162.usbdev_tx_rx_disruption.2948002735 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/162.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/163.usbdev_endpoint_types.102756994 |
| Short name | T3245 |
| Test name | |
| Test status | |
| Simulation time | 451454545 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:06:01 AM UTC 24 |
| Finished | Aug 21 08:06:11 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=102756994 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_endpoint_types.102756994 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/163.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/163.usbdev_tx_rx_disruption.2478662954 |
| Short name | T3248 |
| Test name | |
| Test status | |
| Simulation time | 513640891 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:06:01 AM UTC 24 |
| Finished | Aug 21 08:06:12 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2478662954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 163.usbdev_tx_rx_disruption.2478662954 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/163.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/164.usbdev_endpoint_types.2773246424 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 481660496 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:06:01 AM UTC 24 |
| Finished | Aug 21 08:06:18 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2773246424 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_endpoint_types.2773246424 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/164.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/164.usbdev_tx_rx_disruption.4032358897 |
| Short name | T3246 |
| Test name | |
| Test status | |
| Simulation time | 478228268 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 08:06:01 AM UTC 24 |
| Finished | Aug 21 08:06:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4032358897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 164.usbdev_tx_rx_disruption.4032358897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/164.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/165.usbdev_endpoint_types.3913116491 |
| Short name | T3278 |
| Test name | |
| Test status | |
| Simulation time | 505772273 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 08:06:01 AM UTC 24 |
| Finished | Aug 21 08:06:18 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3913116491 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_endpoint_types.3913116491 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/165.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/165.usbdev_tx_rx_disruption.1792211527 |
| Short name | T3265 |
| Test name | |
| Test status | |
| Simulation time | 658382962 ps |
| CPU time | 1.73 seconds |
| Started | Aug 21 08:06:04 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1792211527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 165.usbdev_tx_rx_disruption.1792211527 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/165.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/166.usbdev_endpoint_types.1779533427 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 585892844 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:06:04 AM UTC 24 |
| Finished | Aug 21 08:06:06 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1779533427 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_endpoint_types.1779533427 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/166.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/166.usbdev_tx_rx_disruption.659995044 |
| Short name | T3242 |
| Test name | |
| Test status | |
| Simulation time | 610374417 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:06:04 AM UTC 24 |
| Finished | Aug 21 08:06:06 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=659995044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 166.usbdev_tx_rx_disruption.659995044 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/166.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/167.usbdev_tx_rx_disruption.2194438896 |
| Short name | T3259 |
| Test name | |
| Test status | |
| Simulation time | 565232306 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:06:04 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2194438896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 167.usbdev_tx_rx_disruption.2194438896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/167.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/168.usbdev_endpoint_types.3909131601 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 401766051 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 08:06:04 AM UTC 24 |
| Finished | Aug 21 08:06:16 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3909131601 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_endpoint_types.3909131601 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/168.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/168.usbdev_tx_rx_disruption.1877656706 |
| Short name | T3266 |
| Test name | |
| Test status | |
| Simulation time | 553919025 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:06:04 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1877656706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 168.usbdev_tx_rx_disruption.1877656706 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/168.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/169.usbdev_endpoint_types.3679175371 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 819619476 ps |
| CPU time | 1.82 seconds |
| Started | Aug 21 08:06:04 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3679175371 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_endpoint_types.3679175371 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/169.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/169.usbdev_tx_rx_disruption.1472594102 |
| Short name | T3264 |
| Test name | |
| Test status | |
| Simulation time | 538103186 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:06:04 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1472594102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 169.usbdev_tx_rx_disruption.1472594102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/169.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_alert_test.358434506 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 26737494 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 07:57:19 AM UTC 24 |
| Finished | Aug 21 07:57:21 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=358434506 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.358434506 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_aon_wake_disconnect.1476501435 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 4242463097 ps |
| CPU time | 12.12 seconds |
| Started | Aug 21 07:57:04 AM UTC 24 |
| Finished | Aug 21 07:57:17 AM UTC 24 |
| Peak memory | 228352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1476501435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbd ev_aon_wake_disconnect.1476501435 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_aon_wake_reset.1802676885 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 19752466535 ps |
| CPU time | 27.83 seconds |
| Started | Aug 21 07:57:04 AM UTC 24 |
| Finished | Aug 21 07:57:33 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1802676885 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.1802676885 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_aon_wake_resume.1519661943 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 24028617011 ps |
| CPU time | 47.99 seconds |
| Started | Aug 21 07:57:04 AM UTC 24 |
| Finished | Aug 21 07:57:54 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1519661943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbd ev_aon_wake_resume.1519661943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_av_buffer.3713244515 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 144269177 ps |
| CPU time | 0.8 seconds |
| Started | Aug 21 07:57:04 AM UTC 24 |
| Finished | Aug 21 07:57:06 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3713244515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3713244515 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_bitstuff_err.4146681729 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 141570579 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 07:57:04 AM UTC 24 |
| Finished | Aug 21 07:57:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4146681729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.4146681729 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_data_toggle_clear.2353652645 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 182216017 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:57:05 AM UTC 24 |
| Finished | Aug 21 07:57:08 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2353652645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2353652645 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_data_toggle_restore.866919508 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 342741804 ps |
| CPU time | 1.82 seconds |
| Started | Aug 21 07:57:05 AM UTC 24 |
| Finished | Aug 21 07:57:08 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=866919508 -assert nopostproc +UVM_TESTNAME=us bdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.866919508 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_device_address.114087809 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 25338526134 ps |
| CPU time | 46.82 seconds |
| Started | Aug 21 07:57:05 AM UTC 24 |
| Finished | Aug 21 07:57:54 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=114087809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.114087809 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_device_timeout.3841441435 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 4338203603 ps |
| CPU time | 28.13 seconds |
| Started | Aug 21 07:57:05 AM UTC 24 |
| Finished | Aug 21 07:57:35 AM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3841441435 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.3841441435 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_disable_endpoint.1312347965 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 791211888 ps |
| CPU time | 2.67 seconds |
| Started | Aug 21 07:57:07 AM UTC 24 |
| Finished | Aug 21 07:57:11 AM UTC 24 |
| Peak memory | 218032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1312347965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1312347965 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_disconnected.2086034445 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 229118891 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 07:57:07 AM UTC 24 |
| Finished | Aug 21 07:57:09 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2086034445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2086034445 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_enable.1812089483 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 56477933 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 07:57:07 AM UTC 24 |
| Finished | Aug 21 07:57:09 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1812089483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1812089483 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_endpoint_access.3356344876 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 920256716 ps |
| CPU time | 4.64 seconds |
| Started | Aug 21 07:57:07 AM UTC 24 |
| Finished | Aug 21 07:57:13 AM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3356344876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.3356344876 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_endpoint_types.791744387 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 494098533 ps |
| CPU time | 2.19 seconds |
| Started | Aug 21 07:57:07 AM UTC 24 |
| Finished | Aug 21 07:57:11 AM UTC 24 |
| Peak memory | 218172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=791744387 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_types.791744387 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_fifo_rst.1540239641 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 157076061 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:57:07 AM UTC 24 |
| Finished | Aug 21 07:57:10 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1540239641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1540239641 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_in_iso.3135010008 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 167444717 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:57:07 AM UTC 24 |
| Finished | Aug 21 07:57:10 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3135010008 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.3135010008 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_in_stall.2416001368 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 146865272 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:57:07 AM UTC 24 |
| Finished | Aug 21 07:57:09 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2416001368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2416001368 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_in_trans.1378330545 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 170223241 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 07:57:08 AM UTC 24 |
| Finished | Aug 21 07:57:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1378330545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1378330545 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_invalid_sync.2494516946 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 4747853359 ps |
| CPU time | 122.17 seconds |
| Started | Aug 21 07:57:07 AM UTC 24 |
| Finished | Aug 21 07:59:12 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2494516946 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.2494516946 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_iso_retraction.2074007470 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 3843238667 ps |
| CPU time | 24.43 seconds |
| Started | Aug 21 07:57:08 AM UTC 24 |
| Finished | Aug 21 07:57:34 AM UTC 24 |
| Peak memory | 218312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2074007470 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.2074007470 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_link_in_err.394987771 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 180787109 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 07:57:08 AM UTC 24 |
| Finished | Aug 21 07:57:10 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=394987771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.394987771 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_link_resume.3586345890 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 34315338048 ps |
| CPU time | 54.58 seconds |
| Started | Aug 21 07:57:08 AM UTC 24 |
| Finished | Aug 21 07:58:05 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3586345890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.3586345890 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_link_suspend.3809764843 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 10444879014 ps |
| CPU time | 20.52 seconds |
| Started | Aug 21 07:57:10 AM UTC 24 |
| Finished | Aug 21 07:57:31 AM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3809764843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.3809764843 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_low_speed_traffic.398529176 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 2769928196 ps |
| CPU time | 18.79 seconds |
| Started | Aug 21 07:57:10 AM UTC 24 |
| Finished | Aug 21 07:57:30 AM UTC 24 |
| Peak memory | 230456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=398529176 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.398529176 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_max_inter_pkt_delay.243239710 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 3031363366 ps |
| CPU time | 28.69 seconds |
| Started | Aug 21 07:57:10 AM UTC 24 |
| Finished | Aug 21 07:57:40 AM UTC 24 |
| Peak memory | 230544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=243239710 -assert nopostproc +UVM _TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.243239710 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_max_length_in_transaction.1362819566 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 239198329 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:57:11 AM UTC 24 |
| Finished | Aug 21 07:57:13 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1362819566 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.1362819566 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_max_length_out_transaction.1103473213 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 181829769 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:57:11 AM UTC 24 |
| Finished | Aug 21 07:57:13 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1103473213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1103473213 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_max_non_iso_usb_traffic.3465076655 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 3056890332 ps |
| CPU time | 27.59 seconds |
| Started | Aug 21 07:57:11 AM UTC 24 |
| Finished | Aug 21 07:57:40 AM UTC 24 |
| Peak memory | 228524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3465076655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_non_iso_usb_traffic.3465076655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_min_inter_pkt_delay.3547524035 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 1961007669 ps |
| CPU time | 45.96 seconds |
| Started | Aug 21 07:57:11 AM UTC 24 |
| Finished | Aug 21 07:57:59 AM UTC 24 |
| Peak memory | 228272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3547524035 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3547524035 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_min_length_in_transaction.834915990 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 158416845 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:57:11 AM UTC 24 |
| Finished | Aug 21 07:57:14 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=834915990 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.834915990 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_min_length_out_transaction.27638934 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 205583052 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 07:57:11 AM UTC 24 |
| Finished | Aug 21 07:57:14 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27638934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_ 2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.27638934 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_nak_trans.1454154387 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 198211125 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:57:11 AM UTC 24 |
| Finished | Aug 21 07:57:14 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1454154387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1454154387 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_out_iso.2220150545 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 198581515 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 07:57:11 AM UTC 24 |
| Finished | Aug 21 07:57:14 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2220150545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2220150545 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_out_stall.1504647114 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 165120292 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:57:14 AM UTC 24 |
| Finished | Aug 21 07:57:17 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1504647114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1504647114 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_out_trans_nak.1002461036 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 175247264 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 07:57:14 AM UTC 24 |
| Finished | Aug 21 07:57:17 AM UTC 24 |
| Peak memory | 216368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1002461036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1002461036 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_pending_in_trans.3748246378 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 221322115 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:57:14 AM UTC 24 |
| Finished | Aug 21 07:57:17 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3748246378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3748246378 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_phy_config_pinflip.181020664 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 259968902 ps |
| CPU time | 1.75 seconds |
| Started | Aug 21 07:57:14 AM UTC 24 |
| Finished | Aug 21 07:57:17 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=181020664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.181020664 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_phy_config_usb_ref_disable.4050020419 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 155401140 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:57:14 AM UTC 24 |
| Finished | Aug 21 07:57:17 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4050020419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.4050020419 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_phy_pins_sense.1842445654 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 41970422 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 07:57:14 AM UTC 24 |
| Finished | Aug 21 07:57:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1842445654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1842445654 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_pkt_buffer.2263570938 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 16424068963 ps |
| CPU time | 42.7 seconds |
| Started | Aug 21 07:57:14 AM UTC 24 |
| Finished | Aug 21 07:57:59 AM UTC 24 |
| Peak memory | 228640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2263570938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2263570938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_pkt_received.2279951524 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 234840858 ps |
| CPU time | 1.7 seconds |
| Started | Aug 21 07:57:14 AM UTC 24 |
| Finished | Aug 21 07:57:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2279951524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2279951524 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_pkt_sent.979986639 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 177923327 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:57:16 AM UTC 24 |
| Finished | Aug 21 07:57:18 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=979986639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.979986639 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_random_length_in_transaction.961370359 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 240249945 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 07:57:16 AM UTC 24 |
| Finished | Aug 21 07:57:18 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=961370359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.961370359 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_random_length_out_transaction.2929907165 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 230450369 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 07:57:16 AM UTC 24 |
| Finished | Aug 21 07:57:18 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2929907165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.2929907165 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_resume_link_active.1122216508 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 20158903549 ps |
| CPU time | 32.51 seconds |
| Started | Aug 21 07:57:16 AM UTC 24 |
| Finished | Aug 21 07:57:50 AM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1122216508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_resume_link_active.1122216508 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_rx_crc_err.3268117976 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 177149026 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:57:17 AM UTC 24 |
| Finished | Aug 21 07:57:20 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3268117976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.3268117976 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_rx_full.1726083828 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 342849031 ps |
| CPU time | 2.28 seconds |
| Started | Aug 21 07:57:17 AM UTC 24 |
| Finished | Aug 21 07:57:21 AM UTC 24 |
| Peak memory | 218132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1726083828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_full.1726083828 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_setup_stage.3713661599 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 147983763 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:57:17 AM UTC 24 |
| Finished | Aug 21 07:57:20 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3713661599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3713661599 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_setup_trans_ignored.2169429224 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 150631816 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:57:17 AM UTC 24 |
| Finished | Aug 21 07:57:20 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2169429224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2169429224 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_smoke.1758030325 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 240836025 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:57:18 AM UTC 24 |
| Finished | Aug 21 07:57:20 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1758030325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1758030325 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_spurious_pids_ignored.498797451 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 3978938941 ps |
| CPU time | 37.2 seconds |
| Started | Aug 21 07:57:18 AM UTC 24 |
| Finished | Aug 21 07:57:56 AM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=498797451 -assert nopostproc +UVM_TESTNAME=usbdev_bas e_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.498797451 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_stall_priority_over_nak.3856422195 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 159665194 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 07:57:19 AM UTC 24 |
| Finished | Aug 21 07:57:21 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3856422195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3856422195 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_stall_trans.2555694631 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 187443082 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:57:19 AM UTC 24 |
| Finished | Aug 21 07:57:21 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2555694631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2555694631 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_stream_len_max.65854436 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 1075666327 ps |
| CPU time | 3.68 seconds |
| Started | Aug 21 07:57:19 AM UTC 24 |
| Finished | Aug 21 07:57:24 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=65854436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.65854436 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_streaming_out.118302987 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 3682868848 ps |
| CPU time | 26.65 seconds |
| Started | Aug 21 07:57:19 AM UTC 24 |
| Finished | Aug 21 07:57:47 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=118302987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.118302987 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_timeout_missing_host_handshake.3413221769 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 1124820336 ps |
| CPU time | 12.16 seconds |
| Started | Aug 21 07:57:05 AM UTC 24 |
| Finished | Aug 21 07:57:19 AM UTC 24 |
| Peak memory | 218120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3413221769 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing _host_handshake.3413221769 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/17.usbdev_tx_rx_disruption.3379090204 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 626665405 ps |
| CPU time | 1.95 seconds |
| Started | Aug 21 07:57:19 AM UTC 24 |
| Finished | Aug 21 07:57:22 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3379090204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.usbdev_tx_rx_disruption.3379090204 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/17.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/170.usbdev_endpoint_types.4002999523 |
| Short name | T3250 |
| Test name | |
| Test status | |
| Simulation time | 263758103 ps |
| CPU time | 0.86 seconds |
| Started | Aug 21 08:06:06 AM UTC 24 |
| Finished | Aug 21 08:06:15 AM UTC 24 |
| Peak memory | 216052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4002999523 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_endpoint_types.4002999523 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/170.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/170.usbdev_tx_rx_disruption.3620072501 |
| Short name | T3252 |
| Test name | |
| Test status | |
| Simulation time | 624189658 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:06:06 AM UTC 24 |
| Finished | Aug 21 08:06:16 AM UTC 24 |
| Peak memory | 216024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3620072501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 170.usbdev_tx_rx_disruption.3620072501 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/170.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/171.usbdev_tx_rx_disruption.2613877406 |
| Short name | T3294 |
| Test name | |
| Test status | |
| Simulation time | 502558722 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:06:09 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 216268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2613877406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 171.usbdev_tx_rx_disruption.2613877406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/171.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/172.usbdev_tx_rx_disruption.2132807404 |
| Short name | T3295 |
| Test name | |
| Test status | |
| Simulation time | 664532732 ps |
| CPU time | 1.71 seconds |
| Started | Aug 21 08:06:09 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 216440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2132807404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 172.usbdev_tx_rx_disruption.2132807404 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/172.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/173.usbdev_endpoint_types.1899961678 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 509183956 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:06:09 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1899961678 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_endpoint_types.1899961678 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/173.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/174.usbdev_endpoint_types.835370713 |
| Short name | T3251 |
| Test name | |
| Test status | |
| Simulation time | 448896555 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:06:09 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 216212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=835370713 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_endpoint_types.835370713 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/174.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/174.usbdev_tx_rx_disruption.1988733636 |
| Short name | T3293 |
| Test name | |
| Test status | |
| Simulation time | 492655114 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:06:09 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1988733636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 174.usbdev_tx_rx_disruption.1988733636 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/174.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/175.usbdev_endpoint_types.2321883096 |
| Short name | T3289 |
| Test name | |
| Test status | |
| Simulation time | 428096940 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:06:09 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 214672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2321883096 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_endpoint_types.2321883096 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/175.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/175.usbdev_tx_rx_disruption.584564031 |
| Short name | T3291 |
| Test name | |
| Test status | |
| Simulation time | 521408063 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:06:09 AM UTC 24 |
| Finished | Aug 21 08:06:19 AM UTC 24 |
| Peak memory | 216720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=584564031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 175.usbdev_tx_rx_disruption.584564031 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/175.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/176.usbdev_endpoint_types.988984702 |
| Short name | T3260 |
| Test name | |
| Test status | |
| Simulation time | 447542833 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 08:06:13 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=988984702 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_endpoint_types.988984702 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/176.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/176.usbdev_tx_rx_disruption.1145167828 |
| Short name | T3274 |
| Test name | |
| Test status | |
| Simulation time | 553997472 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:06:13 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1145167828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 176.usbdev_tx_rx_disruption.1145167828 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/176.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/177.usbdev_endpoint_types.4033635942 |
| Short name | T3262 |
| Test name | |
| Test status | |
| Simulation time | 531006965 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:06:13 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4033635942 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_endpoint_types.4033635942 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/177.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/177.usbdev_tx_rx_disruption.2644617520 |
| Short name | T3255 |
| Test name | |
| Test status | |
| Simulation time | 499770787 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:06:13 AM UTC 24 |
| Finished | Aug 21 08:06:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2644617520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 177.usbdev_tx_rx_disruption.2644617520 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/177.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/178.usbdev_endpoint_types.1028626138 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 403306077 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 08:06:15 AM UTC 24 |
| Finished | Aug 21 08:06:17 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1028626138 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.usbdev_endpoint_types.1028626138 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/178.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/178.usbdev_tx_rx_disruption.3744584986 |
| Short name | T3299 |
| Test name | |
| Test status | |
| Simulation time | 538241734 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:06:18 AM UTC 24 |
| Finished | Aug 21 08:06:21 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3744584986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 178.usbdev_tx_rx_disruption.3744584986 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/178.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/179.usbdev_endpoint_types.971492030 |
| Short name | T3296 |
| Test name | |
| Test status | |
| Simulation time | 294945069 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 08:06:18 AM UTC 24 |
| Finished | Aug 21 08:06:20 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=971492030 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.usbdev_endpoint_types.971492030 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/179.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/179.usbdev_tx_rx_disruption.794614763 |
| Short name | T3300 |
| Test name | |
| Test status | |
| Simulation time | 579218058 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:06:18 AM UTC 24 |
| Finished | Aug 21 08:06:21 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=794614763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 179.usbdev_tx_rx_disruption.794614763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/179.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_alert_test.862693330 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 33105454 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 07:57:35 AM UTC 24 |
| Finished | Aug 21 07:57:37 AM UTC 24 |
| Peak memory | 216172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=862693330 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.862693330 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_aon_wake_disconnect.3090876981 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 9639252200 ps |
| CPU time | 14.62 seconds |
| Started | Aug 21 07:57:21 AM UTC 24 |
| Finished | Aug 21 07:57:36 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3090876981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbd ev_aon_wake_disconnect.3090876981 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_aon_wake_reset.1381806180 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 20585601220 ps |
| CPU time | 31.19 seconds |
| Started | Aug 21 07:57:21 AM UTC 24 |
| Finished | Aug 21 07:57:53 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1381806180 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1381806180 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_aon_wake_resume.10452852 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 23307044885 ps |
| CPU time | 35.7 seconds |
| Started | Aug 21 07:57:21 AM UTC 24 |
| Finished | Aug 21 07:57:58 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=10452852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev _aon_wake_resume.10452852 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_av_buffer.3619529362 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 230026517 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 07:57:21 AM UTC 24 |
| Finished | Aug 21 07:57:23 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3619529362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3619529362 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_bitstuff_err.614295142 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 147354635 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:57:21 AM UTC 24 |
| Finished | Aug 21 07:57:23 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=614295142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.614295142 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_data_toggle_clear.3710538887 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 234717968 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 07:57:22 AM UTC 24 |
| Finished | Aug 21 07:57:25 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3710538887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3710538887 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_data_toggle_restore.947673530 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 948200820 ps |
| CPU time | 4.13 seconds |
| Started | Aug 21 07:57:22 AM UTC 24 |
| Finished | Aug 21 07:57:27 AM UTC 24 |
| Peak memory | 218348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=947673530 -assert nopostproc +UVM_TESTNAME=us bdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.947673530 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_device_address.4085149174 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 17357089156 ps |
| CPU time | 29.5 seconds |
| Started | Aug 21 07:57:22 AM UTC 24 |
| Finished | Aug 21 07:57:53 AM UTC 24 |
| Peak memory | 218252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4085149174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.4085149174 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_device_timeout.755636897 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 1187969244 ps |
| CPU time | 25.9 seconds |
| Started | Aug 21 07:57:22 AM UTC 24 |
| Finished | Aug 21 07:57:49 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=755636897 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.755636897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_disable_endpoint.1392179640 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 620543284 ps |
| CPU time | 1.76 seconds |
| Started | Aug 21 07:57:22 AM UTC 24 |
| Finished | Aug 21 07:57:25 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1392179640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1392179640 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_disconnected.3035663109 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 158561677 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 07:57:22 AM UTC 24 |
| Finished | Aug 21 07:57:25 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3035663109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3035663109 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_enable.4242376119 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 93664575 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 07:57:24 AM UTC 24 |
| Finished | Aug 21 07:57:26 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4242376119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.4242376119 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_endpoint_access.4171977682 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 973647532 ps |
| CPU time | 4.28 seconds |
| Started | Aug 21 07:57:24 AM UTC 24 |
| Finished | Aug 21 07:57:29 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4171977682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.4171977682 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_endpoint_types.4270783368 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 737178207 ps |
| CPU time | 2.73 seconds |
| Started | Aug 21 07:57:24 AM UTC 24 |
| Finished | Aug 21 07:57:28 AM UTC 24 |
| Peak memory | 218104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4270783368 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_types.4270783368 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_fifo_rst.3209697029 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 270905772 ps |
| CPU time | 3.3 seconds |
| Started | Aug 21 07:57:24 AM UTC 24 |
| Finished | Aug 21 07:57:28 AM UTC 24 |
| Peak memory | 218048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3209697029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3209697029 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_in_iso.4055507685 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 246998680 ps |
| CPU time | 2.12 seconds |
| Started | Aug 21 07:57:25 AM UTC 24 |
| Finished | Aug 21 07:57:28 AM UTC 24 |
| Peak memory | 228392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4055507685 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.4055507685 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_in_stall.687462630 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 140080931 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 07:57:25 AM UTC 24 |
| Finished | Aug 21 07:57:27 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=687462630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.687462630 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_in_trans.4023690973 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 292347079 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:57:25 AM UTC 24 |
| Finished | Aug 21 07:57:28 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4023690973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.4023690973 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_invalid_sync.807411582 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 4370455144 ps |
| CPU time | 40.51 seconds |
| Started | Aug 21 07:57:25 AM UTC 24 |
| Finished | Aug 21 07:58:07 AM UTC 24 |
| Peak memory | 230580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=807411582 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.807411582 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_iso_retraction.1978720458 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 11875891322 ps |
| CPU time | 78.53 seconds |
| Started | Aug 21 07:57:27 AM UTC 24 |
| Finished | Aug 21 07:58:47 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1978720458 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.1978720458 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_link_in_err.230735534 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 241179323 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:57:27 AM UTC 24 |
| Finished | Aug 21 07:57:29 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=230735534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.230735534 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_link_resume.3011105158 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 27950619958 ps |
| CPU time | 39.69 seconds |
| Started | Aug 21 07:57:27 AM UTC 24 |
| Finished | Aug 21 07:58:08 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3011105158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.3011105158 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_link_suspend.2647918978 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 10052130251 ps |
| CPU time | 16.36 seconds |
| Started | Aug 21 07:57:28 AM UTC 24 |
| Finished | Aug 21 07:57:46 AM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2647918978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2647918978 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_low_speed_traffic.1100843 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 3229697384 ps |
| CPU time | 26.4 seconds |
| Started | Aug 21 07:57:28 AM UTC 24 |
| Finished | Aug 21 07:57:56 AM UTC 24 |
| Peak memory | 228616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1100843 -assert nopostproc +UVM_TESTNAME=usbdev_ base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.1100843 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_max_inter_pkt_delay.2465375922 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 2779960038 ps |
| CPU time | 24.17 seconds |
| Started | Aug 21 07:57:28 AM UTC 24 |
| Finished | Aug 21 07:57:54 AM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2465375922 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.2465375922 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_max_length_in_transaction.3699169788 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 235827491 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 07:57:28 AM UTC 24 |
| Finished | Aug 21 07:57:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3699169788 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3699169788 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_max_length_out_transaction.42616149 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 235892135 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:57:28 AM UTC 24 |
| Finished | Aug 21 07:57:31 AM UTC 24 |
| Peak memory | 216308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42616149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_ 2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.42616149 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_max_non_iso_usb_traffic.3542374663 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 2147542278 ps |
| CPU time | 19.55 seconds |
| Started | Aug 21 07:57:28 AM UTC 24 |
| Finished | Aug 21 07:57:49 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3542374663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_non_iso_usb_traffic.3542374663 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_min_inter_pkt_delay.2587725752 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 3837557749 ps |
| CPU time | 98.06 seconds |
| Started | Aug 21 07:57:30 AM UTC 24 |
| Finished | Aug 21 07:59:10 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2587725752 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.2587725752 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_min_length_in_transaction.3229941535 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 152065070 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:57:30 AM UTC 24 |
| Finished | Aug 21 07:57:33 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3229941535 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3229941535 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_min_length_out_transaction.3613367055 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 149798108 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 07:57:30 AM UTC 24 |
| Finished | Aug 21 07:57:32 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3613367055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3613367055 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_out_iso.2871639324 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 203494794 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 07:57:30 AM UTC 24 |
| Finished | Aug 21 07:57:33 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2871639324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2871639324 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_out_stall.1888639391 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 168598902 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:57:30 AM UTC 24 |
| Finished | Aug 21 07:57:33 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1888639391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1888639391 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_out_trans_nak.2723960179 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 247557610 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 07:57:30 AM UTC 24 |
| Finished | Aug 21 07:57:33 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2723960179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2723960179 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_pending_in_trans.1637467568 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 167485528 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 07:57:32 AM UTC 24 |
| Finished | Aug 21 07:57:34 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1637467568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1637467568 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_phy_config_pinflip.1320831174 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 205028738 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:57:32 AM UTC 24 |
| Finished | Aug 21 07:57:34 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1320831174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.1320831174 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_phy_config_usb_ref_disable.3177109001 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 144437849 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:57:32 AM UTC 24 |
| Finished | Aug 21 07:57:34 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3177109001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3177109001 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_phy_pins_sense.492085141 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 45708861 ps |
| CPU time | 0.96 seconds |
| Started | Aug 21 07:57:32 AM UTC 24 |
| Finished | Aug 21 07:57:34 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=492085141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.492085141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_pkt_buffer.3109564949 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 19790537919 ps |
| CPU time | 53.39 seconds |
| Started | Aug 21 07:57:32 AM UTC 24 |
| Finished | Aug 21 07:58:27 AM UTC 24 |
| Peak memory | 235300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3109564949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3109564949 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_pkt_received.12280705 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 198617274 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 07:57:32 AM UTC 24 |
| Finished | Aug 21 07:57:34 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=12280705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.12280705 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_pkt_sent.741683580 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 165900051 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:57:32 AM UTC 24 |
| Finished | Aug 21 07:57:35 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=741683580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.741683580 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_random_length_in_transaction.3635339833 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 215600438 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 07:57:32 AM UTC 24 |
| Finished | Aug 21 07:57:35 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3635339833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3635339833 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_random_length_out_transaction.2376754988 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 202464371 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 07:57:33 AM UTC 24 |
| Finished | Aug 21 07:57:36 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2376754988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.2376754988 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_resume_link_active.3493132158 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 20165379013 ps |
| CPU time | 30.9 seconds |
| Started | Aug 21 07:57:33 AM UTC 24 |
| Finished | Aug 21 07:58:06 AM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3493132158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_resume_link_active.3493132158 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_rx_crc_err.3888003689 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 195446215 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 07:57:33 AM UTC 24 |
| Finished | Aug 21 07:57:36 AM UTC 24 |
| Peak memory | 216416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3888003689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3888003689 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_setup_stage.2184838435 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 153384245 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 07:57:34 AM UTC 24 |
| Finished | Aug 21 07:57:36 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2184838435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2184838435 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_setup_trans_ignored.92711081 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 157370398 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:57:34 AM UTC 24 |
| Finished | Aug 21 07:57:36 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=92711081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.92711081 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_smoke.163390234 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 214050998 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 07:57:35 AM UTC 24 |
| Finished | Aug 21 07:57:38 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=163390234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.163390234 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_spurious_pids_ignored.1992000219 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 2778173375 ps |
| CPU time | 20.99 seconds |
| Started | Aug 21 07:57:35 AM UTC 24 |
| Finished | Aug 21 07:57:57 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1992000219 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.1992000219 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_stall_priority_over_nak.2449081319 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 242654132 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 07:57:35 AM UTC 24 |
| Finished | Aug 21 07:57:37 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2449081319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2449081319 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_stall_trans.1965099678 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 204530287 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:57:35 AM UTC 24 |
| Finished | Aug 21 07:57:38 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1965099678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1965099678 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_stream_len_max.1665106561 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 637525090 ps |
| CPU time | 1.95 seconds |
| Started | Aug 21 07:57:35 AM UTC 24 |
| Finished | Aug 21 07:57:38 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1665106561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.1665106561 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_streaming_out.2974843955 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 2425814273 ps |
| CPU time | 23.6 seconds |
| Started | Aug 21 07:57:35 AM UTC 24 |
| Finished | Aug 21 07:58:00 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2974843955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2974843955 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_timeout_missing_host_handshake.2686250562 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 10390314587 ps |
| CPU time | 66.16 seconds |
| Started | Aug 21 07:57:22 AM UTC 24 |
| Finished | Aug 21 07:58:30 AM UTC 24 |
| Peak memory | 218312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2686250562 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing _host_handshake.2686250562 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/18.usbdev_tx_rx_disruption.2199862632 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 634196474 ps |
| CPU time | 3.09 seconds |
| Started | Aug 21 07:57:35 AM UTC 24 |
| Finished | Aug 21 07:57:39 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2199862632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.usbdev_tx_rx_disruption.2199862632 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/18.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/180.usbdev_endpoint_types.2545844987 |
| Short name | T3298 |
| Test name | |
| Test status | |
| Simulation time | 519082848 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:06:18 AM UTC 24 |
| Finished | Aug 21 08:06:21 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2545844987 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_endpoint_types.2545844987 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/180.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/180.usbdev_tx_rx_disruption.1095332442 |
| Short name | T3359 |
| Test name | |
| Test status | |
| Simulation time | 585464660 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:06:18 AM UTC 24 |
| Finished | Aug 21 08:06:38 AM UTC 24 |
| Peak memory | 218032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1095332442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 180.usbdev_tx_rx_disruption.1095332442 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/180.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/181.usbdev_endpoint_types.2066271084 |
| Short name | T3385 |
| Test name | |
| Test status | |
| Simulation time | 304467444 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:06:18 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2066271084 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_endpoint_types.2066271084 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/181.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/181.usbdev_tx_rx_disruption.2779518609 |
| Short name | T3396 |
| Test name | |
| Test status | |
| Simulation time | 586296443 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:06:18 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2779518609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 181.usbdev_tx_rx_disruption.2779518609 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/181.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/182.usbdev_endpoint_types.1253436199 |
| Short name | T3399 |
| Test name | |
| Test status | |
| Simulation time | 545643393 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 08:06:18 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1253436199 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_endpoint_types.1253436199 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/182.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/182.usbdev_tx_rx_disruption.989625821 |
| Short name | T3297 |
| Test name | |
| Test status | |
| Simulation time | 441220988 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:06:18 AM UTC 24 |
| Finished | Aug 21 08:06:21 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=989625821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 182.usbdev_tx_rx_disruption.989625821 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/182.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/183.usbdev_endpoint_types.3606706471 |
| Short name | T3395 |
| Test name | |
| Test status | |
| Simulation time | 553330145 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:06:18 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3606706471 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_endpoint_types.3606706471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/183.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/183.usbdev_tx_rx_disruption.3754826937 |
| Short name | T3403 |
| Test name | |
| Test status | |
| Simulation time | 605963351 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:06:18 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3754826937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 183.usbdev_tx_rx_disruption.3754826937 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/183.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/184.usbdev_endpoint_types.4218376125 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 324686895 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:06:18 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 214804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4218376125 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_endpoint_types.4218376125 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/184.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/184.usbdev_tx_rx_disruption.3535484972 |
| Short name | T3415 |
| Test name | |
| Test status | |
| Simulation time | 524178394 ps |
| CPU time | 1.88 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:06:49 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3535484972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 184.usbdev_tx_rx_disruption.3535484972 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/184.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/185.usbdev_tx_rx_disruption.3503758157 |
| Short name | T3405 |
| Test name | |
| Test status | |
| Simulation time | 498784222 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3503758157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 185.usbdev_tx_rx_disruption.3503758157 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/185.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/186.usbdev_endpoint_types.3379903450 |
| Short name | T3414 |
| Test name | |
| Test status | |
| Simulation time | 586725596 ps |
| CPU time | 1.85 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:06:49 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3379903450 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_endpoint_types.3379903450 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/186.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/186.usbdev_tx_rx_disruption.3373446128 |
| Short name | T3409 |
| Test name | |
| Test status | |
| Simulation time | 484948970 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:06:49 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3373446128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 186.usbdev_tx_rx_disruption.3373446128 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/186.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/187.usbdev_tx_rx_disruption.3828360978 |
| Short name | T3407 |
| Test name | |
| Test status | |
| Simulation time | 446026397 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:06:49 AM UTC 24 |
| Peak memory | 216432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3828360978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 187.usbdev_tx_rx_disruption.3828360978 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/187.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/188.usbdev_tx_rx_disruption.3405196337 |
| Short name | T3301 |
| Test name | |
| Test status | |
| Simulation time | 550939765 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:06:21 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3405196337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 188.usbdev_tx_rx_disruption.3405196337 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/188.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_alert_test.4096988360 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 34215476 ps |
| CPU time | 0.8 seconds |
| Started | Aug 21 07:57:53 AM UTC 24 |
| Finished | Aug 21 07:57:55 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4096988360 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.4096988360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_aon_wake_disconnect.626947689 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 9935053308 ps |
| CPU time | 17.94 seconds |
| Started | Aug 21 07:57:35 AM UTC 24 |
| Finished | Aug 21 07:57:54 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=626947689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbde v_aon_wake_disconnect.626947689 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_aon_wake_reset.3974763146 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 20894460931 ps |
| CPU time | 32.87 seconds |
| Started | Aug 21 07:57:37 AM UTC 24 |
| Finished | Aug 21 07:58:11 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3974763146 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3974763146 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_aon_wake_resume.2551620844 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 30268696783 ps |
| CPU time | 43.42 seconds |
| Started | Aug 21 07:57:37 AM UTC 24 |
| Finished | Aug 21 07:58:21 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2551620844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbd ev_aon_wake_resume.2551620844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_av_buffer.1368397505 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 178561714 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:57:37 AM UTC 24 |
| Finished | Aug 21 07:57:39 AM UTC 24 |
| Peak memory | 216408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1368397505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1368397505 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_bitstuff_err.797507594 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 155921983 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:57:37 AM UTC 24 |
| Finished | Aug 21 07:57:39 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=797507594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.797507594 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_data_toggle_clear.3337699001 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 341981642 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:57:37 AM UTC 24 |
| Finished | Aug 21 07:57:39 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3337699001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.3337699001 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_data_toggle_restore.3182114935 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 655731785 ps |
| CPU time | 3.33 seconds |
| Started | Aug 21 07:57:37 AM UTC 24 |
| Finished | Aug 21 07:57:41 AM UTC 24 |
| Peak memory | 218136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3182114935 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3182114935 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_device_address.3590526080 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 47627177592 ps |
| CPU time | 79.39 seconds |
| Started | Aug 21 07:57:37 AM UTC 24 |
| Finished | Aug 21 07:58:58 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3590526080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.3590526080 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_device_timeout.1297322413 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 1324284450 ps |
| CPU time | 28.32 seconds |
| Started | Aug 21 07:57:38 AM UTC 24 |
| Finished | Aug 21 07:58:08 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1297322413 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.1297322413 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_disable_endpoint.2152850962 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 882472582 ps |
| CPU time | 2.75 seconds |
| Started | Aug 21 07:57:38 AM UTC 24 |
| Finished | Aug 21 07:57:42 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2152850962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.2152850962 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_disconnected.1478041277 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 134872808 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 07:57:38 AM UTC 24 |
| Finished | Aug 21 07:57:40 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1478041277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1478041277 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_enable.3844457655 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 75139071 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 07:57:38 AM UTC 24 |
| Finished | Aug 21 07:57:40 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3844457655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3844457655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_endpoint_access.997487458 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 905879990 ps |
| CPU time | 2.76 seconds |
| Started | Aug 21 07:57:38 AM UTC 24 |
| Finished | Aug 21 07:57:42 AM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=997487458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.997487458 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_endpoint_types.3630336536 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 151182713 ps |
| CPU time | 1 seconds |
| Started | Aug 21 07:57:38 AM UTC 24 |
| Finished | Aug 21 07:57:40 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3630336536 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_types.3630336536 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_fifo_rst.4242388670 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 215089633 ps |
| CPU time | 2.09 seconds |
| Started | Aug 21 07:57:40 AM UTC 24 |
| Finished | Aug 21 07:57:43 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4242388670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.4242388670 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_in_iso.1948430635 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 193689648 ps |
| CPU time | 1.78 seconds |
| Started | Aug 21 07:57:40 AM UTC 24 |
| Finished | Aug 21 07:57:43 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1948430635 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1948430635 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_in_stall.1741149685 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 177118191 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:57:40 AM UTC 24 |
| Finished | Aug 21 07:57:42 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1741149685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1741149685 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_in_trans.1141904762 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 207576346 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 07:57:40 AM UTC 24 |
| Finished | Aug 21 07:57:43 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1141904762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1141904762 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_invalid_sync.2431077797 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 3411005170 ps |
| CPU time | 87.15 seconds |
| Started | Aug 21 07:57:40 AM UTC 24 |
| Finished | Aug 21 07:59:09 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2431077797 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.2431077797 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_iso_retraction.4177489460 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 5355085734 ps |
| CPU time | 37.1 seconds |
| Started | Aug 21 07:57:40 AM UTC 24 |
| Finished | Aug 21 07:58:19 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4177489460 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.4177489460 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_link_in_err.4023719054 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 196956203 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 07:57:42 AM UTC 24 |
| Finished | Aug 21 07:57:44 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4023719054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.4023719054 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_link_resume.3785103986 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 30901043974 ps |
| CPU time | 51.52 seconds |
| Started | Aug 21 07:57:42 AM UTC 24 |
| Finished | Aug 21 07:58:35 AM UTC 24 |
| Peak memory | 218344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3785103986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3785103986 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_link_suspend.756057418 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 10020660343 ps |
| CPU time | 14.03 seconds |
| Started | Aug 21 07:57:42 AM UTC 24 |
| Finished | Aug 21 07:57:57 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=756057418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.756057418 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_low_speed_traffic.919734357 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 6085402479 ps |
| CPU time | 173.79 seconds |
| Started | Aug 21 07:57:42 AM UTC 24 |
| Finished | Aug 21 08:00:39 AM UTC 24 |
| Peak memory | 235348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=919734357 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.919734357 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_max_inter_pkt_delay.1076612600 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 3010106758 ps |
| CPU time | 81.09 seconds |
| Started | Aug 21 07:57:42 AM UTC 24 |
| Finished | Aug 21 07:59:05 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1076612600 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.1076612600 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_max_length_in_transaction.231634621 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 238517867 ps |
| CPU time | 1.67 seconds |
| Started | Aug 21 07:57:42 AM UTC 24 |
| Finished | Aug 21 07:57:45 AM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=231634621 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.231634621 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_max_length_out_transaction.1564133143 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 187297352 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:57:42 AM UTC 24 |
| Finished | Aug 21 07:57:44 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1564133143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1564133143 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_max_non_iso_usb_traffic.1146037692 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 2778787899 ps |
| CPU time | 21.28 seconds |
| Started | Aug 21 07:57:43 AM UTC 24 |
| Finished | Aug 21 07:58:06 AM UTC 24 |
| Peak memory | 218404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1146037692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_non_iso_usb_traffic.1146037692 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_min_length_in_transaction.660212331 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 152055054 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:57:44 AM UTC 24 |
| Finished | Aug 21 07:57:46 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=660212331 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.660212331 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_min_length_out_transaction.61449892 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 157619756 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:57:44 AM UTC 24 |
| Finished | Aug 21 07:57:46 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=61449892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_ 2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.61449892 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_nak_trans.3977256928 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 214181520 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:57:44 AM UTC 24 |
| Finished | Aug 21 07:57:46 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3977256928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3977256928 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_out_iso.3036033074 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 195158400 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 07:57:44 AM UTC 24 |
| Finished | Aug 21 07:57:46 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3036033074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.3036033074 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_out_stall.962404111 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 144036116 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:57:45 AM UTC 24 |
| Finished | Aug 21 07:57:47 AM UTC 24 |
| Peak memory | 216376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=962404111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.962404111 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_out_trans_nak.1885195955 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 192967580 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:57:45 AM UTC 24 |
| Finished | Aug 21 07:57:47 AM UTC 24 |
| Peak memory | 216344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1885195955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1885195955 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_pending_in_trans.2342934351 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 160482484 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:57:45 AM UTC 24 |
| Finished | Aug 21 07:57:47 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2342934351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2342934351 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_phy_config_pinflip.3578470776 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 257928934 ps |
| CPU time | 1.76 seconds |
| Started | Aug 21 07:57:46 AM UTC 24 |
| Finished | Aug 21 07:57:49 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3578470776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3578470776 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_phy_config_usb_ref_disable.4294127185 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 153987512 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:57:46 AM UTC 24 |
| Finished | Aug 21 07:57:49 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4294127185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.4294127185 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_phy_pins_sense.713026842 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 50587121 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 07:57:48 AM UTC 24 |
| Finished | Aug 21 07:57:50 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=713026842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.713026842 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_pkt_buffer.1532755906 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 8568143294 ps |
| CPU time | 24.35 seconds |
| Started | Aug 21 07:57:48 AM UTC 24 |
| Finished | Aug 21 07:58:13 AM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1532755906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1532755906 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_pkt_received.2106203490 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 170051749 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:57:48 AM UTC 24 |
| Finished | Aug 21 07:57:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2106203490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2106203490 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_pkt_sent.2783485184 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 190137768 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 07:57:48 AM UTC 24 |
| Finished | Aug 21 07:57:50 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2783485184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2783485184 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_random_length_in_transaction.3496729693 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 217909104 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 07:57:49 AM UTC 24 |
| Finished | Aug 21 07:57:52 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3496729693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3496729693 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_random_length_out_transaction.1942104774 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 184556183 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:57:49 AM UTC 24 |
| Finished | Aug 21 07:57:52 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1942104774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.1942104774 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_resume_link_active.1207970686 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 20168412533 ps |
| CPU time | 27.57 seconds |
| Started | Aug 21 07:57:49 AM UTC 24 |
| Finished | Aug 21 07:58:18 AM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1207970686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_resume_link_active.1207970686 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_rx_crc_err.882190220 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 242024891 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:57:50 AM UTC 24 |
| Finished | Aug 21 07:57:52 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=882190220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.882190220 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_rx_full.3833864501 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 411058735 ps |
| CPU time | 2.13 seconds |
| Started | Aug 21 07:57:50 AM UTC 24 |
| Finished | Aug 21 07:57:53 AM UTC 24 |
| Peak memory | 218004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3833864501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_full.3833864501 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_setup_stage.3296547211 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 158913773 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:57:50 AM UTC 24 |
| Finished | Aug 21 07:57:52 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3296547211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3296547211 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_setup_trans_ignored.2275449014 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 152279206 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:57:50 AM UTC 24 |
| Finished | Aug 21 07:57:52 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2275449014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2275449014 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_smoke.1125752223 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 240024845 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:57:51 AM UTC 24 |
| Finished | Aug 21 07:57:54 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1125752223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1125752223 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_spurious_pids_ignored.1239224188 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 2963348326 ps |
| CPU time | 21.63 seconds |
| Started | Aug 21 07:57:51 AM UTC 24 |
| Finished | Aug 21 07:58:14 AM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1239224188 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.1239224188 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_stall_priority_over_nak.3029838876 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 200905863 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 07:57:51 AM UTC 24 |
| Finished | Aug 21 07:57:53 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3029838876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3029838876 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_stall_trans.675368421 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 188216261 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:57:51 AM UTC 24 |
| Finished | Aug 21 07:57:54 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=675368421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.675368421 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_stream_len_max.2973554986 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 1202770323 ps |
| CPU time | 3.83 seconds |
| Started | Aug 21 07:57:51 AM UTC 24 |
| Finished | Aug 21 07:57:56 AM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2973554986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.2973554986 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_streaming_out.1827340925 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 2264400635 ps |
| CPU time | 20.74 seconds |
| Started | Aug 21 07:57:51 AM UTC 24 |
| Finished | Aug 21 07:58:13 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1827340925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1827340925 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_timeout_missing_host_handshake.2456867543 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 2439719934 ps |
| CPU time | 18.7 seconds |
| Started | Aug 21 07:57:38 AM UTC 24 |
| Finished | Aug 21 07:57:58 AM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2456867543 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing _host_handshake.2456867543 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/19.usbdev_tx_rx_disruption.2874193494 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 523031148 ps |
| CPU time | 2.1 seconds |
| Started | Aug 21 07:57:51 AM UTC 24 |
| Finished | Aug 21 07:57:55 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2874193494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 19.usbdev_tx_rx_disruption.2874193494 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/19.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/192.usbdev_endpoint_types.1863065427 |
| Short name | T3428 |
| Test name | |
| Test status | |
| Simulation time | 428346052 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:06:56 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1863065427 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_endpoint_types.1863065427 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/192.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/192.usbdev_tx_rx_disruption.1588651982 |
| Short name | T3490 |
| Test name | |
| Test status | |
| Simulation time | 511927949 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 217616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1588651982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 192.usbdev_tx_rx_disruption.1588651982 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/192.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/193.usbdev_endpoint_types.2507504777 |
| Short name | T3424 |
| Test name | |
| Test status | |
| Simulation time | 205606459 ps |
| CPU time | 0.76 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:06:55 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2507504777 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_endpoint_types.2507504777 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/193.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/193.usbdev_tx_rx_disruption.2528269100 |
| Short name | T3493 |
| Test name | |
| Test status | |
| Simulation time | 650259945 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 08:06:19 AM UTC 24 |
| Finished | Aug 21 08:07:17 AM UTC 24 |
| Peak memory | 216440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2528269100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 193.usbdev_tx_rx_disruption.2528269100 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/193.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/194.usbdev_tx_rx_disruption.830691229 |
| Short name | T3319 |
| Test name | |
| Test status | |
| Simulation time | 633574052 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:27 AM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=830691229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 194.usbdev_tx_rx_disruption.830691229 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/194.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/195.usbdev_endpoint_types.2769404430 |
| Short name | T3310 |
| Test name | |
| Test status | |
| Simulation time | 163523350 ps |
| CPU time | 0.77 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:26 AM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2769404430 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_endpoint_types.2769404430 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/195.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/195.usbdev_tx_rx_disruption.3681117385 |
| Short name | T3317 |
| Test name | |
| Test status | |
| Simulation time | 541623645 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:27 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3681117385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 195.usbdev_tx_rx_disruption.3681117385 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/195.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/196.usbdev_endpoint_types.2853567996 |
| Short name | T3302 |
| Test name | |
| Test status | |
| Simulation time | 564508017 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:24 AM UTC 24 |
| Peak memory | 216028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2853567996 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_endpoint_types.2853567996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/196.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/196.usbdev_tx_rx_disruption.3124390374 |
| Short name | T3316 |
| Test name | |
| Test status | |
| Simulation time | 511169222 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3124390374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 196.usbdev_tx_rx_disruption.3124390374 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/196.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/197.usbdev_endpoint_types.2574288095 |
| Short name | T3313 |
| Test name | |
| Test status | |
| Simulation time | 415691307 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:27 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2574288095 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_endpoint_types.2574288095 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/197.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/197.usbdev_tx_rx_disruption.683158869 |
| Short name | T3315 |
| Test name | |
| Test status | |
| Simulation time | 520927820 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:27 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=683158869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 197.usbdev_tx_rx_disruption.683158869 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/197.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/198.usbdev_endpoint_types.879720222 |
| Short name | T3318 |
| Test name | |
| Test status | |
| Simulation time | 541539814 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=879720222 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_endpoint_types.879720222 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/198.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/198.usbdev_tx_rx_disruption.1672170538 |
| Short name | T3320 |
| Test name | |
| Test status | |
| Simulation time | 613408414 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:27 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1672170538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 198.usbdev_tx_rx_disruption.1672170538 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/198.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/199.usbdev_endpoint_types.4019953349 |
| Short name | T3311 |
| Test name | |
| Test status | |
| Simulation time | 176543076 ps |
| CPU time | 0.8 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:26 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4019953349 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.usbdev_endpoint_types.4019953349 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/199.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/199.usbdev_tx_rx_disruption.4110702268 |
| Short name | T3324 |
| Test name | |
| Test status | |
| Simulation time | 469491405 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4110702268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 199.usbdev_tx_rx_disruption.4110702268 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/199.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_alert_test.1760624837 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 52922915 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 07:51:01 AM UTC 24 |
| Finished | Aug 21 07:51:03 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1760624837 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.1760624837 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_disconnect.3220687169 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6679959200 ps |
| CPU time | 12.26 seconds |
| Started | Aug 21 07:50:29 AM UTC 24 |
| Finished | Aug 21 07:50:42 AM UTC 24 |
| Peak memory | 228540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3220687169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbde v_aon_wake_disconnect.3220687169 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_resume.1544299092 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 23953247001 ps |
| CPU time | 50.96 seconds |
| Started | Aug 21 07:50:29 AM UTC 24 |
| Finished | Aug 21 07:51:21 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1544299092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbde v_aon_wake_resume.1544299092 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_av_buffer.1307681666 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 153223229 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:50:29 AM UTC 24 |
| Finished | Aug 21 07:50:31 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1307681666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1307681666 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_av_empty.3989334188 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 249991735 ps |
| CPU time | 1.16 seconds |
| Started | Aug 21 07:50:29 AM UTC 24 |
| Finished | Aug 21 07:50:31 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3989334188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.3989334188 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_av_empty/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_av_overflow.2199742903 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 188311572 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:50:29 AM UTC 24 |
| Finished | Aug 21 07:50:32 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2199742903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2199742903 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_av_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_bitstuff_err.284871668 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 185573837 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:50:29 AM UTC 24 |
| Finished | Aug 21 07:50:31 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=284871668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.284871668 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_clear.3218115894 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 365343737 ps |
| CPU time | 2.33 seconds |
| Started | Aug 21 07:50:29 AM UTC 24 |
| Finished | Aug 21 07:50:33 AM UTC 24 |
| Peak memory | 218012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3218115894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.3218115894 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_restore.3563783223 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 893449459 ps |
| CPU time | 4.12 seconds |
| Started | Aug 21 07:50:30 AM UTC 24 |
| Finished | Aug 21 07:50:35 AM UTC 24 |
| Peak memory | 218148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3563783223 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3563783223 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_device_address.4198585073 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 32708155247 ps |
| CPU time | 66.63 seconds |
| Started | Aug 21 07:50:30 AM UTC 24 |
| Finished | Aug 21 07:51:38 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4198585073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.4198585073 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_device_timeout.1888881971 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2938855807 ps |
| CPU time | 30.93 seconds |
| Started | Aug 21 07:50:30 AM UTC 24 |
| Finished | Aug 21 07:51:03 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1888881971 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.1888881971 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_disable_endpoint.972851475 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 984379096 ps |
| CPU time | 2.53 seconds |
| Started | Aug 21 07:50:31 AM UTC 24 |
| Finished | Aug 21 07:50:35 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=972851475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.972851475 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_disconnected.754658516 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 158720819 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:50:32 AM UTC 24 |
| Finished | Aug 21 07:50:34 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=754658516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.754658516 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_enable.2337616506 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 46171870 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 07:50:32 AM UTC 24 |
| Finished | Aug 21 07:50:34 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2337616506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2337616506 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_access.781963922 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1081444856 ps |
| CPU time | 3.11 seconds |
| Started | Aug 21 07:50:32 AM UTC 24 |
| Finished | Aug 21 07:50:36 AM UTC 24 |
| Peak memory | 218148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=781963922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.781963922 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_rst.4012810859 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 340780091 ps |
| CPU time | 3.3 seconds |
| Started | Aug 21 07:50:33 AM UTC 24 |
| Finished | Aug 21 07:50:37 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4012810859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.4012810859 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_freq_hiclk_max.2516823727 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 102320629611 ps |
| CPU time | 178.47 seconds |
| Started | Aug 21 07:50:33 AM UTC 24 |
| Finished | Aug 21 07:53:34 AM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_ freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2516823727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_p hase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.2516823727 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_freq_hiclk_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_freq_loclk.1955262452 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 87106607373 ps |
| CPU time | 162.71 seconds |
| Started | Aug 21 07:50:33 AM UTC 24 |
| Finished | Aug 21 07:53:18 AM UTC 24 |
| Peak memory | 218368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1955262452 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.1955262452 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_freq_loclk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_freq_loclk_max.1151978274 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 101152244298 ps |
| CPU time | 196.29 seconds |
| Started | Aug 21 07:50:35 AM UTC 24 |
| Finished | Aug 21 07:53:54 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_d rifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1151978274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_p hase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1151978274 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_freq_loclk_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_freq_phase.1020655606 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 84188789713 ps |
| CPU time | 163.36 seconds |
| Started | Aug 21 07:50:35 AM UTC 24 |
| Finished | Aug 21 07:53:21 AM UTC 24 |
| Peak memory | 218192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1020655606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.1020655606 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_freq_phase/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_in_iso.2342817714 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 252662427 ps |
| CPU time | 2.16 seconds |
| Started | Aug 21 07:50:35 AM UTC 24 |
| Finished | Aug 21 07:50:38 AM UTC 24 |
| Peak memory | 228516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2342817714 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2342817714 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_in_stall.2313485043 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 138195342 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:50:36 AM UTC 24 |
| Finished | Aug 21 07:50:38 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2313485043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2313485043 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_in_trans.749952184 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 266595465 ps |
| CPU time | 1.7 seconds |
| Started | Aug 21 07:50:36 AM UTC 24 |
| Finished | Aug 21 07:50:39 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=749952184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.749952184 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_invalid_sync.288228136 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 2961931055 ps |
| CPU time | 27.11 seconds |
| Started | Aug 21 07:50:35 AM UTC 24 |
| Finished | Aug 21 07:51:03 AM UTC 24 |
| Peak memory | 228644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=288228136 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.288228136 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_iso_retraction.1555676629 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 7845948029 ps |
| CPU time | 49.16 seconds |
| Started | Aug 21 07:50:36 AM UTC 24 |
| Finished | Aug 21 07:51:27 AM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1555676629 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.1555676629 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_link_in_err.4175134688 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 218745551 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:50:36 AM UTC 24 |
| Finished | Aug 21 07:50:38 AM UTC 24 |
| Peak memory | 216472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4175134688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.4175134688 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_link_resume.815287010 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 11642602857 ps |
| CPU time | 23.09 seconds |
| Started | Aug 21 07:50:36 AM UTC 24 |
| Finished | Aug 21 07:51:00 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=815287010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.815287010 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_link_suspend.1720627069 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 5956912121 ps |
| CPU time | 17.35 seconds |
| Started | Aug 21 07:50:37 AM UTC 24 |
| Finished | Aug 21 07:50:56 AM UTC 24 |
| Peak memory | 228612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1720627069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.1720627069 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_low_speed_traffic.1498641340 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 3786890747 ps |
| CPU time | 39.42 seconds |
| Started | Aug 21 07:50:38 AM UTC 24 |
| Finished | Aug 21 07:51:19 AM UTC 24 |
| Peak memory | 235268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1498641340 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.1498641340 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_max_inter_pkt_delay.2404038812 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 2098219686 ps |
| CPU time | 60.79 seconds |
| Started | Aug 21 07:50:38 AM UTC 24 |
| Finished | Aug 21 07:51:41 AM UTC 24 |
| Peak memory | 228556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2404038812 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.2404038812 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_in_transaction.1069613585 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 235088140 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:50:38 AM UTC 24 |
| Finished | Aug 21 07:50:41 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1069613585 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.1069613585 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_out_transaction.2491029819 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 187572855 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:50:39 AM UTC 24 |
| Finished | Aug 21 07:50:42 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2491029819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2491029819 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_max_non_iso_usb_traffic.1675262718 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2197015283 ps |
| CPU time | 20.23 seconds |
| Started | Aug 21 07:50:40 AM UTC 24 |
| Finished | Aug 21 07:51:01 AM UTC 24 |
| Peak memory | 235252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1675262718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_non_iso_usb_traffic.1675262718 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_max_usb_traffic.2523436739 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2595397771 ps |
| CPU time | 23.21 seconds |
| Started | Aug 21 07:50:40 AM UTC 24 |
| Finished | Aug 21 07:51:04 AM UTC 24 |
| Peak memory | 230636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2523436739 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.2523436739 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_min_inter_pkt_delay.2285810731 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 3690180575 ps |
| CPU time | 34.4 seconds |
| Started | Aug 21 07:50:41 AM UTC 24 |
| Finished | Aug 21 07:51:16 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2285810731 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.2285810731 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_in_transaction.1636882832 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 157286024 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:50:42 AM UTC 24 |
| Finished | Aug 21 07:50:44 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1636882832 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1636882832 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_out_transaction.4260303043 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 187438014 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:50:42 AM UTC 24 |
| Finished | Aug 21 07:50:44 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4260303043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.4260303043 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_nak_trans.2771473685 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 203699475 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 07:50:43 AM UTC 24 |
| Finished | Aug 21 07:50:46 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2771473685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2771473685 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_out_iso.2572195640 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 174710776 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:50:43 AM UTC 24 |
| Finished | Aug 21 07:50:46 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2572195640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2572195640 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_out_stall.720409797 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 159170689 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:50:43 AM UTC 24 |
| Finished | Aug 21 07:50:46 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=720409797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.720409797 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_out_trans_nak.396296320 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 173286438 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:50:45 AM UTC 24 |
| Finished | Aug 21 07:50:48 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=396296320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.396296320 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_pending_in_trans.2033486346 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 196615659 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 07:50:45 AM UTC 24 |
| Finished | Aug 21 07:50:48 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2033486346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2033486346 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_pinflip.39551157 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 231327048 ps |
| CPU time | 1.7 seconds |
| Started | Aug 21 07:50:45 AM UTC 24 |
| Finished | Aug 21 07:50:48 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39551157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.39551157 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_rand_bus_type.1388280452 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 252251754 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 07:50:47 AM UTC 24 |
| Finished | Aug 21 07:50:49 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1388280452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_ 2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1388280452 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_phy_config_rand_bus_type/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_usb_ref_disable.4283045582 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 152109507 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:50:47 AM UTC 24 |
| Finished | Aug 21 07:50:49 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4283045582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.4283045582 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_phy_pins_sense.646777776 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 34420954 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 07:50:47 AM UTC 24 |
| Finished | Aug 21 07:50:49 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=646777776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.646777776 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_buffer.3407486284 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 10303247516 ps |
| CPU time | 29.2 seconds |
| Started | Aug 21 07:50:49 AM UTC 24 |
| Finished | Aug 21 07:51:19 AM UTC 24 |
| Peak memory | 228580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3407486284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3407486284 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_received.4147842337 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 174287571 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:50:49 AM UTC 24 |
| Finished | Aug 21 07:50:51 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4147842337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.4147842337 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_sent.4167030089 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 268967340 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 07:50:49 AM UTC 24 |
| Finished | Aug 21 07:50:52 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4167030089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.4167030089 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_rand_bus_disconnects.2854085046 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 11060408192 ps |
| CPU time | 273.58 seconds |
| Started | Aug 21 07:50:50 AM UTC 24 |
| Finished | Aug 21 07:55:28 AM UTC 24 |
| Peak memory | 234848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2854085046 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.2854085046 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_rand_bus_resets.3615308936 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2386508932 ps |
| CPU time | 16.21 seconds |
| Started | Aug 21 07:50:50 AM UTC 24 |
| Finished | Aug 21 07:51:07 AM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3615308936 -assert nopostproc +UVM_TESTNAME=usbdev_ base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3615308936 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_rand_suspends.1016490989 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 6635616218 ps |
| CPU time | 82.52 seconds |
| Started | Aug 21 07:50:52 AM UTC 24 |
| Finished | Aug 21 07:52:17 AM UTC 24 |
| Peak memory | 235308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1016490989 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.1016490989 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_rand_suspends/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_in_transaction.1681230329 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 160653169 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:50:50 AM UTC 24 |
| Finished | Aug 21 07:50:52 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1681230329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1681230329 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_out_transaction.351739795 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 168184036 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:50:50 AM UTC 24 |
| Finished | Aug 21 07:50:52 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=351739795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.351739795 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_resume_link_active.3847436441 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 20180830889 ps |
| CPU time | 40.29 seconds |
| Started | Aug 21 07:50:52 AM UTC 24 |
| Finished | Aug 21 07:51:34 AM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3847436441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_resume_link_active.3847436441 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_rx_crc_err.3377387234 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 194198874 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:50:52 AM UTC 24 |
| Finished | Aug 21 07:50:55 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3377387234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3377387234 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_rx_pid_err.3722201112 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 162913043 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:50:54 AM UTC 24 |
| Finished | Aug 21 07:50:56 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3722201112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.3722201112 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_rx_pid_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_sec_cm.1312020462 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 814198758 ps |
| CPU time | 2.77 seconds |
| Started | Aug 21 07:51:01 AM UTC 24 |
| Finished | Aug 21 07:51:05 AM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1312020462 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1312020462 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority.2915412022 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 359817806 ps |
| CPU time | 2.05 seconds |
| Started | Aug 21 07:50:56 AM UTC 24 |
| Finished | Aug 21 07:50:59 AM UTC 24 |
| Peak memory | 218004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2915412022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.2915412022 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_setup_priority/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority_over_stall_response.3454457125 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 227087532 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 07:50:56 AM UTC 24 |
| Finished | Aug 21 07:50:58 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3454457125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3454457125 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_setup_priority_over_stall_response/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_setup_stage.4158337829 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 156130465 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:50:57 AM UTC 24 |
| Finished | Aug 21 07:51:00 AM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4158337829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.4158337829 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_setup_trans_ignored.2767286112 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 204031931 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 07:50:57 AM UTC 24 |
| Finished | Aug 21 07:50:59 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2767286112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2767286112 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_smoke.2433646590 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 172802732 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:50:57 AM UTC 24 |
| Finished | Aug 21 07:51:00 AM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2433646590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2433646590 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_spurious_pids_ignored.1058187466 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1888765023 ps |
| CPU time | 19.39 seconds |
| Started | Aug 21 07:50:57 AM UTC 24 |
| Finished | Aug 21 07:51:18 AM UTC 24 |
| Peak memory | 230264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1058187466 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1058187466 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_stall_priority_over_nak.2994472994 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 174087411 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:50:57 AM UTC 24 |
| Finished | Aug 21 07:51:00 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2994472994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2994472994 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_stall_trans.2143612673 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 158736841 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:50:58 AM UTC 24 |
| Finished | Aug 21 07:51:01 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2143612673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2143612673 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_stream_len_max.425493528 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 374058958 ps |
| CPU time | 2.15 seconds |
| Started | Aug 21 07:51:00 AM UTC 24 |
| Finished | Aug 21 07:51:03 AM UTC 24 |
| Peak memory | 218112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=425493528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.425493528 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_streaming_out.3297241611 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 2782780880 ps |
| CPU time | 71.78 seconds |
| Started | Aug 21 07:50:59 AM UTC 24 |
| Finished | Aug 21 07:52:13 AM UTC 24 |
| Peak memory | 228612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3297241611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.3297241611 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_stress_usb_traffic.2939668513 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 12267590039 ps |
| CPU time | 228.81 seconds |
| Started | Aug 21 07:51:01 AM UTC 24 |
| Finished | Aug 21 07:54:53 AM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_ disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2939668513 -assert nopo stproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.2939668513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_stress_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/2.usbdev_timeout_missing_host_handshake.3375287591 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1201585545 ps |
| CPU time | 28.42 seconds |
| Started | Aug 21 07:50:30 AM UTC 24 |
| Finished | Aug 21 07:51:00 AM UTC 24 |
| Peak memory | 218124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3375287591 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_ host_handshake.3375287591 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/2.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_alert_test.2584447448 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 35921331 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 07:58:05 AM UTC 24 |
| Finished | Aug 21 07:58:07 AM UTC 24 |
| Peak memory | 216356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2584447448 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.2584447448 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_aon_wake_disconnect.3176593832 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 9491186264 ps |
| CPU time | 14.72 seconds |
| Started | Aug 21 07:57:53 AM UTC 24 |
| Finished | Aug 21 07:58:09 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3176593832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbd ev_aon_wake_disconnect.3176593832 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_aon_wake_reset.2046407296 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 13464440092 ps |
| CPU time | 19.38 seconds |
| Started | Aug 21 07:57:53 AM UTC 24 |
| Finished | Aug 21 07:58:14 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2046407296 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2046407296 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_aon_wake_resume.29232061 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 24443318165 ps |
| CPU time | 34.9 seconds |
| Started | Aug 21 07:57:53 AM UTC 24 |
| Finished | Aug 21 07:58:29 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=29232061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev _aon_wake_resume.29232061 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_av_buffer.1654235142 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 156794086 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:57:53 AM UTC 24 |
| Finished | Aug 21 07:57:56 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1654235142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1654235142 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_bitstuff_err.1865029478 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 147681693 ps |
| CPU time | 1 seconds |
| Started | Aug 21 07:57:53 AM UTC 24 |
| Finished | Aug 21 07:57:55 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1865029478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1865029478 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_data_toggle_clear.503786984 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 493013320 ps |
| CPU time | 1.97 seconds |
| Started | Aug 21 07:57:53 AM UTC 24 |
| Finished | Aug 21 07:57:56 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=503786984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.503786984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_data_toggle_restore.2716945756 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 303639543 ps |
| CPU time | 1.78 seconds |
| Started | Aug 21 07:57:55 AM UTC 24 |
| Finished | Aug 21 07:57:58 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2716945756 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2716945756 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_device_address.3797231014 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 40127328851 ps |
| CPU time | 74.81 seconds |
| Started | Aug 21 07:57:55 AM UTC 24 |
| Finished | Aug 21 07:59:12 AM UTC 24 |
| Peak memory | 218356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3797231014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3797231014 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_device_timeout.2672773211 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 1030493322 ps |
| CPU time | 19.8 seconds |
| Started | Aug 21 07:57:55 AM UTC 24 |
| Finished | Aug 21 07:58:16 AM UTC 24 |
| Peak memory | 218120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2672773211 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.2672773211 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_disable_endpoint.3245945030 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 828853509 ps |
| CPU time | 2.07 seconds |
| Started | Aug 21 07:57:56 AM UTC 24 |
| Finished | Aug 21 07:57:59 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3245945030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3245945030 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_disconnected.993665797 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 172025882 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:57:56 AM UTC 24 |
| Finished | Aug 21 07:57:58 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=993665797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.993665797 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_enable.1912233262 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 41965539 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 07:57:56 AM UTC 24 |
| Finished | Aug 21 07:57:58 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1912233262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1912233262 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_endpoint_access.1385360208 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 866446665 ps |
| CPU time | 2.48 seconds |
| Started | Aug 21 07:57:56 AM UTC 24 |
| Finished | Aug 21 07:57:59 AM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1385360208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.1385360208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_endpoint_types.1325249920 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 158679880 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:57:56 AM UTC 24 |
| Finished | Aug 21 07:57:58 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1325249920 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_types.1325249920 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_fifo_rst.1589263884 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 402319144 ps |
| CPU time | 2.88 seconds |
| Started | Aug 21 07:57:56 AM UTC 24 |
| Finished | Aug 21 07:58:00 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1589263884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1589263884 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_in_iso.1626650813 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 195047609 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 07:57:56 AM UTC 24 |
| Finished | Aug 21 07:57:59 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1626650813 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1626650813 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_in_stall.1000490236 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 136804168 ps |
| CPU time | 1.16 seconds |
| Started | Aug 21 07:57:56 AM UTC 24 |
| Finished | Aug 21 07:57:58 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1000490236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1000490236 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_in_trans.3602430691 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 175776860 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 07:57:57 AM UTC 24 |
| Finished | Aug 21 07:57:59 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3602430691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3602430691 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_invalid_sync.2538922184 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 3248200614 ps |
| CPU time | 29.69 seconds |
| Started | Aug 21 07:57:56 AM UTC 24 |
| Finished | Aug 21 07:58:27 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2538922184 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.2538922184 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_iso_retraction.501643303 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 9498992358 ps |
| CPU time | 104.97 seconds |
| Started | Aug 21 07:57:57 AM UTC 24 |
| Finished | Aug 21 07:59:44 AM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=501643303 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.501643303 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_link_in_err.3761893921 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 195317454 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 07:57:57 AM UTC 24 |
| Finished | Aug 21 07:57:59 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3761893921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3761893921 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_link_resume.1038753532 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 35017548200 ps |
| CPU time | 58.41 seconds |
| Started | Aug 21 07:57:57 AM UTC 24 |
| Finished | Aug 21 07:58:57 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1038753532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.1038753532 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_link_suspend.2939088935 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 9055393686 ps |
| CPU time | 15.61 seconds |
| Started | Aug 21 07:57:57 AM UTC 24 |
| Finished | Aug 21 07:58:14 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2939088935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2939088935 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_low_speed_traffic.3521170705 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 3168008960 ps |
| CPU time | 80.2 seconds |
| Started | Aug 21 07:57:57 AM UTC 24 |
| Finished | Aug 21 07:59:20 AM UTC 24 |
| Peak memory | 228684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3521170705 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.3521170705 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_max_inter_pkt_delay.1694205260 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 1953783668 ps |
| CPU time | 48.92 seconds |
| Started | Aug 21 07:57:59 AM UTC 24 |
| Finished | Aug 21 07:58:50 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1694205260 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.1694205260 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_max_length_in_transaction.3130293236 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 265112404 ps |
| CPU time | 1.7 seconds |
| Started | Aug 21 07:57:59 AM UTC 24 |
| Finished | Aug 21 07:58:02 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3130293236 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.3130293236 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_max_length_out_transaction.3924279422 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 193253361 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 07:57:59 AM UTC 24 |
| Finished | Aug 21 07:58:02 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3924279422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.3924279422 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_max_non_iso_usb_traffic.2736363518 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 2445298661 ps |
| CPU time | 22.59 seconds |
| Started | Aug 21 07:57:59 AM UTC 24 |
| Finished | Aug 21 07:58:23 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2736363518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_non_iso_usb_traffic.2736363518 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_min_inter_pkt_delay.3466307188 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 2390430745 ps |
| CPU time | 63.89 seconds |
| Started | Aug 21 07:57:59 AM UTC 24 |
| Finished | Aug 21 07:59:05 AM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3466307188 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.3466307188 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_min_length_in_transaction.2251734662 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 151879389 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:57:59 AM UTC 24 |
| Finished | Aug 21 07:58:02 AM UTC 24 |
| Peak memory | 216344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2251734662 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.2251734662 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_min_length_out_transaction.646239192 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 196606980 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 07:57:59 AM UTC 24 |
| Finished | Aug 21 07:58:02 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=646239192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.646239192 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_out_iso.1988876366 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 193987733 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:57:59 AM UTC 24 |
| Finished | Aug 21 07:58:02 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1988876366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.1988876366 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_out_stall.3051408940 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 180002243 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 07:58:00 AM UTC 24 |
| Finished | Aug 21 07:58:02 AM UTC 24 |
| Peak memory | 216412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3051408940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3051408940 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_out_trans_nak.3087303146 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 159944263 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 07:58:00 AM UTC 24 |
| Finished | Aug 21 07:58:02 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3087303146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3087303146 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_pending_in_trans.2006168760 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 144229277 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:58:00 AM UTC 24 |
| Finished | Aug 21 07:58:02 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2006168760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2006168760 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_phy_config_pinflip.1178302808 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 197495349 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 07:58:01 AM UTC 24 |
| Finished | Aug 21 07:58:03 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1178302808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.1178302808 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_phy_config_usb_ref_disable.2743668412 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 147332713 ps |
| CPU time | 1 seconds |
| Started | Aug 21 07:58:01 AM UTC 24 |
| Finished | Aug 21 07:58:03 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2743668412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2743668412 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_phy_pins_sense.500214760 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 52723907 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 07:58:01 AM UTC 24 |
| Finished | Aug 21 07:58:03 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=500214760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.500214760 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_pkt_buffer.49893323 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 6419537685 ps |
| CPU time | 20.75 seconds |
| Started | Aug 21 07:58:01 AM UTC 24 |
| Finished | Aug 21 07:58:23 AM UTC 24 |
| Peak memory | 235364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=49893323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.49893323 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_pkt_received.3387633108 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 175808493 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:58:01 AM UTC 24 |
| Finished | Aug 21 07:58:04 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3387633108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3387633108 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_pkt_sent.2361671499 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 233037327 ps |
| CPU time | 1.73 seconds |
| Started | Aug 21 07:58:01 AM UTC 24 |
| Finished | Aug 21 07:58:04 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2361671499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2361671499 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_random_length_in_transaction.2870164787 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 193743465 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 07:58:01 AM UTC 24 |
| Finished | Aug 21 07:58:04 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2870164787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.2870164787 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_random_length_out_transaction.3492131772 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 240185957 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 07:58:03 AM UTC 24 |
| Finished | Aug 21 07:58:06 AM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3492131772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3492131772 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_rx_crc_err.2292280838 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 165815247 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:58:03 AM UTC 24 |
| Finished | Aug 21 07:58:06 AM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2292280838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.2292280838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_rx_full.2692823440 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 285845094 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 07:58:03 AM UTC 24 |
| Finished | Aug 21 07:58:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2692823440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_full.2692823440 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_setup_stage.1470513353 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 157694640 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:58:03 AM UTC 24 |
| Finished | Aug 21 07:58:05 AM UTC 24 |
| Peak memory | 216316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1470513353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1470513353 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_setup_trans_ignored.3819497066 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 189864349 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 07:58:03 AM UTC 24 |
| Finished | Aug 21 07:58:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3819497066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3819497066 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_smoke.4076004228 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 288647603 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:58:03 AM UTC 24 |
| Finished | Aug 21 07:58:06 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4076004228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.4076004228 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_spurious_pids_ignored.3665448142 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 3528812775 ps |
| CPU time | 29.51 seconds |
| Started | Aug 21 07:58:03 AM UTC 24 |
| Finished | Aug 21 07:58:34 AM UTC 24 |
| Peak memory | 230476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3665448142 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.3665448142 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_stall_priority_over_nak.2917502938 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 157809606 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:58:03 AM UTC 24 |
| Finished | Aug 21 07:58:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2917502938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2917502938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_stall_trans.3335928190 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 165546170 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:58:03 AM UTC 24 |
| Finished | Aug 21 07:58:06 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3335928190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3335928190 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_stream_len_max.880515368 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 1323538089 ps |
| CPU time | 3.91 seconds |
| Started | Aug 21 07:58:05 AM UTC 24 |
| Finished | Aug 21 07:58:10 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=880515368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.880515368 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_streaming_out.1263845227 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 1638299942 ps |
| CPU time | 15.33 seconds |
| Started | Aug 21 07:58:03 AM UTC 24 |
| Finished | Aug 21 07:58:20 AM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1263845227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.1263845227 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_timeout_missing_host_handshake.1055576011 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 877603760 ps |
| CPU time | 5.25 seconds |
| Started | Aug 21 07:57:56 AM UTC 24 |
| Finished | Aug 21 07:58:02 AM UTC 24 |
| Peak memory | 218120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1055576011 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing _host_handshake.1055576011 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/20.usbdev_tx_rx_disruption.1166394004 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 480740291 ps |
| CPU time | 2.35 seconds |
| Started | Aug 21 07:58:05 AM UTC 24 |
| Finished | Aug 21 07:58:08 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1166394004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 20.usbdev_tx_rx_disruption.1166394004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/20.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/200.usbdev_tx_rx_disruption.1350764792 |
| Short name | T3327 |
| Test name | |
| Test status | |
| Simulation time | 512005971 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:30 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1350764792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 200.usbdev_tx_rx_disruption.1350764792 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/200.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/201.usbdev_tx_rx_disruption.1370094816 |
| Short name | T3303 |
| Test name | |
| Test status | |
| Simulation time | 613715544 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:24 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1370094816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 201.usbdev_tx_rx_disruption.1370094816 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/201.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/202.usbdev_tx_rx_disruption.3580018106 |
| Short name | T3330 |
| Test name | |
| Test status | |
| Simulation time | 602421314 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3580018106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 202.usbdev_tx_rx_disruption.3580018106 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/202.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/203.usbdev_tx_rx_disruption.3759937221 |
| Short name | T3323 |
| Test name | |
| Test status | |
| Simulation time | 466648700 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:27 AM UTC 24 |
| Peak memory | 216132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3759937221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 203.usbdev_tx_rx_disruption.3759937221 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/203.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/204.usbdev_tx_rx_disruption.3234181088 |
| Short name | T3326 |
| Test name | |
| Test status | |
| Simulation time | 642551204 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:28 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3234181088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 204.usbdev_tx_rx_disruption.3234181088 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/204.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/205.usbdev_tx_rx_disruption.690736261 |
| Short name | T3331 |
| Test name | |
| Test status | |
| Simulation time | 491293503 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:31 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=690736261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 205.usbdev_tx_rx_disruption.690736261 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/205.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/206.usbdev_tx_rx_disruption.79536738 |
| Short name | T3321 |
| Test name | |
| Test status | |
| Simulation time | 457252892 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:27 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=79536738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 206.usbdev_tx_rx_disruption.79536738 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/206.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/207.usbdev_tx_rx_disruption.3355353211 |
| Short name | T3325 |
| Test name | |
| Test status | |
| Simulation time | 470554455 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:28 AM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3355353211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 207.usbdev_tx_rx_disruption.3355353211 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/207.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/208.usbdev_tx_rx_disruption.1099193848 |
| Short name | T3306 |
| Test name | |
| Test status | |
| Simulation time | 587655033 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:06:21 AM UTC 24 |
| Finished | Aug 21 08:06:25 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1099193848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 208.usbdev_tx_rx_disruption.1099193848 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/208.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/209.usbdev_tx_rx_disruption.137004589 |
| Short name | T3328 |
| Test name | |
| Test status | |
| Simulation time | 618035535 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:06:22 AM UTC 24 |
| Finished | Aug 21 08:06:30 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=137004589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 209.usbdev_tx_rx_disruption.137004589 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/209.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_alert_test.3882159157 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 41245844 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 07:58:20 AM UTC 24 |
| Finished | Aug 21 07:58:21 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3882159157 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.3882159157 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_aon_wake_disconnect.2613307779 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 6440506248 ps |
| CPU time | 9.34 seconds |
| Started | Aug 21 07:58:05 AM UTC 24 |
| Finished | Aug 21 07:58:15 AM UTC 24 |
| Peak memory | 228412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2613307779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbd ev_aon_wake_disconnect.2613307779 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_aon_wake_reset.2752268390 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 14567537512 ps |
| CPU time | 22.86 seconds |
| Started | Aug 21 07:58:05 AM UTC 24 |
| Finished | Aug 21 07:58:29 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2752268390 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2752268390 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_aon_wake_resume.2052820097 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 30642161004 ps |
| CPU time | 39.05 seconds |
| Started | Aug 21 07:58:07 AM UTC 24 |
| Finished | Aug 21 07:58:47 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2052820097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbd ev_aon_wake_resume.2052820097 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_av_buffer.1045701223 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 175656049 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 07:58:07 AM UTC 24 |
| Finished | Aug 21 07:58:09 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1045701223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1045701223 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_bitstuff_err.1210120110 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 148046213 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:58:07 AM UTC 24 |
| Finished | Aug 21 07:58:09 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1210120110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.1210120110 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_data_toggle_clear.4258512327 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 355179725 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:58:07 AM UTC 24 |
| Finished | Aug 21 07:58:09 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4258512327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.4258512327 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_data_toggle_restore.2056897084 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 771851727 ps |
| CPU time | 2.67 seconds |
| Started | Aug 21 07:58:07 AM UTC 24 |
| Finished | Aug 21 07:58:11 AM UTC 24 |
| Peak memory | 218072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2056897084 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2056897084 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_device_address.1111912407 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 40947522836 ps |
| CPU time | 72.43 seconds |
| Started | Aug 21 07:58:07 AM UTC 24 |
| Finished | Aug 21 07:59:21 AM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1111912407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.1111912407 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_device_timeout.1626520141 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 1578398362 ps |
| CPU time | 9.4 seconds |
| Started | Aug 21 07:58:07 AM UTC 24 |
| Finished | Aug 21 07:58:17 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1626520141 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.1626520141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_disable_endpoint.2313906937 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 981700979 ps |
| CPU time | 3.14 seconds |
| Started | Aug 21 07:58:07 AM UTC 24 |
| Finished | Aug 21 07:58:11 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2313906937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.2313906937 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_disconnected.1876556144 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 135477053 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:58:07 AM UTC 24 |
| Finished | Aug 21 07:58:09 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1876556144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1876556144 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_enable.2829441655 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 42379600 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 07:58:09 AM UTC 24 |
| Finished | Aug 21 07:58:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2829441655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2829441655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_endpoint_access.2033947082 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 1060756726 ps |
| CPU time | 4.07 seconds |
| Started | Aug 21 07:58:09 AM UTC 24 |
| Finished | Aug 21 07:58:14 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2033947082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.2033947082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_fifo_rst.3074344325 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 367688112 ps |
| CPU time | 2.66 seconds |
| Started | Aug 21 07:58:09 AM UTC 24 |
| Finished | Aug 21 07:58:13 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3074344325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3074344325 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_in_iso.2594961229 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 201009719 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:58:09 AM UTC 24 |
| Finished | Aug 21 07:58:11 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2594961229 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2594961229 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_in_stall.3210566132 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 150651489 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 07:58:09 AM UTC 24 |
| Finished | Aug 21 07:58:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3210566132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3210566132 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_in_trans.443208055 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 214988532 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 07:58:09 AM UTC 24 |
| Finished | Aug 21 07:58:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=443208055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.443208055 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_invalid_sync.1845090253 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 4805469173 ps |
| CPU time | 44.71 seconds |
| Started | Aug 21 07:58:09 AM UTC 24 |
| Finished | Aug 21 07:58:55 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1845090253 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.1845090253 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_iso_retraction.1155880102 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 5095117623 ps |
| CPU time | 36.22 seconds |
| Started | Aug 21 07:58:09 AM UTC 24 |
| Finished | Aug 21 07:58:47 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1155880102 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.1155880102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_link_in_err.309184205 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 192472881 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:58:11 AM UTC 24 |
| Finished | Aug 21 07:58:13 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=309184205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.309184205 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_link_resume.1735276945 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 8043189015 ps |
| CPU time | 13.13 seconds |
| Started | Aug 21 07:58:11 AM UTC 24 |
| Finished | Aug 21 07:58:25 AM UTC 24 |
| Peak memory | 228088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1735276945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.1735276945 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_link_suspend.944591666 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 9498014607 ps |
| CPU time | 13.27 seconds |
| Started | Aug 21 07:58:11 AM UTC 24 |
| Finished | Aug 21 07:58:25 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=944591666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.944591666 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_low_speed_traffic.1842263347 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 4203684577 ps |
| CPU time | 31.83 seconds |
| Started | Aug 21 07:58:11 AM UTC 24 |
| Finished | Aug 21 07:58:44 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1842263347 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1842263347 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_max_inter_pkt_delay.3488364722 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 1672322533 ps |
| CPU time | 47.05 seconds |
| Started | Aug 21 07:58:11 AM UTC 24 |
| Finished | Aug 21 07:58:59 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3488364722 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.3488364722 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_max_length_in_transaction.4072663140 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 237774827 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 07:58:11 AM UTC 24 |
| Finished | Aug 21 07:58:13 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4072663140 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.4072663140 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_max_length_out_transaction.888240528 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 196276903 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 07:58:12 AM UTC 24 |
| Finished | Aug 21 07:58:14 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=888240528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.888240528 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_max_non_iso_usb_traffic.3725808813 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 2906478608 ps |
| CPU time | 26.01 seconds |
| Started | Aug 21 07:58:12 AM UTC 24 |
| Finished | Aug 21 07:58:39 AM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3725808813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_non_iso_usb_traffic.3725808813 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_min_inter_pkt_delay.1599695017 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 3133894036 ps |
| CPU time | 76.74 seconds |
| Started | Aug 21 07:58:12 AM UTC 24 |
| Finished | Aug 21 07:59:31 AM UTC 24 |
| Peak memory | 235240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1599695017 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1599695017 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_min_length_in_transaction.1351112548 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 205197568 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:58:12 AM UTC 24 |
| Finished | Aug 21 07:58:15 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1351112548 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1351112548 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_min_length_out_transaction.3547368601 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 154895728 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:58:12 AM UTC 24 |
| Finished | Aug 21 07:58:15 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3547368601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3547368601 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_out_iso.3341799904 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 157347592 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 07:58:12 AM UTC 24 |
| Finished | Aug 21 07:58:15 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3341799904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3341799904 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_out_stall.3097391485 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 158419092 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:58:14 AM UTC 24 |
| Finished | Aug 21 07:58:16 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3097391485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3097391485 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_out_trans_nak.2009936905 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 174331209 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:58:14 AM UTC 24 |
| Finished | Aug 21 07:58:16 AM UTC 24 |
| Peak memory | 216344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2009936905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2009936905 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_pending_in_trans.169224996 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 171259082 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:58:14 AM UTC 24 |
| Finished | Aug 21 07:58:16 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=169224996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.169224996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_phy_config_pinflip.3273142334 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 229519201 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 07:58:14 AM UTC 24 |
| Finished | Aug 21 07:58:17 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3273142334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3273142334 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_phy_config_usb_ref_disable.785417788 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 166058189 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:58:14 AM UTC 24 |
| Finished | Aug 21 07:58:17 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=785417788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.785417788 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_phy_pins_sense.566086080 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 32489595 ps |
| CPU time | 0.72 seconds |
| Started | Aug 21 07:58:14 AM UTC 24 |
| Finished | Aug 21 07:58:16 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=566086080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.566086080 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_pkt_buffer.2768886103 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 18778923918 ps |
| CPU time | 47.43 seconds |
| Started | Aug 21 07:58:16 AM UTC 24 |
| Finished | Aug 21 07:59:05 AM UTC 24 |
| Peak memory | 235172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2768886103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2768886103 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_pkt_received.119886095 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 156295644 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:58:16 AM UTC 24 |
| Finished | Aug 21 07:58:18 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=119886095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.119886095 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_pkt_sent.3236322741 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 248610174 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:58:16 AM UTC 24 |
| Finished | Aug 21 07:58:18 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3236322741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3236322741 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_random_length_in_transaction.1689087207 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 215176103 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:58:16 AM UTC 24 |
| Finished | Aug 21 07:58:18 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1689087207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.1689087207 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_random_length_out_transaction.2952490721 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 222249149 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:58:16 AM UTC 24 |
| Finished | Aug 21 07:58:19 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2952490721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2952490721 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_rx_crc_err.703958478 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 194882401 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:58:16 AM UTC 24 |
| Finished | Aug 21 07:58:19 AM UTC 24 |
| Peak memory | 216084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=703958478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.703958478 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_rx_full.3758926922 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 364190793 ps |
| CPU time | 1.75 seconds |
| Started | Aug 21 07:58:16 AM UTC 24 |
| Finished | Aug 21 07:58:19 AM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3758926922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_full.3758926922 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_setup_stage.227937773 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 158832683 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 07:58:16 AM UTC 24 |
| Finished | Aug 21 07:58:18 AM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=227937773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.227937773 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_setup_trans_ignored.616830138 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 194108709 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 07:58:16 AM UTC 24 |
| Finished | Aug 21 07:58:19 AM UTC 24 |
| Peak memory | 216344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=616830138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.616830138 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_smoke.3866248546 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 226469563 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 07:58:18 AM UTC 24 |
| Finished | Aug 21 07:58:20 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3866248546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3866248546 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_spurious_pids_ignored.2609690420 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 3078380231 ps |
| CPU time | 28.46 seconds |
| Started | Aug 21 07:58:18 AM UTC 24 |
| Finished | Aug 21 07:58:48 AM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2609690420 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.2609690420 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_stall_priority_over_nak.3950138886 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 199643814 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:58:18 AM UTC 24 |
| Finished | Aug 21 07:58:20 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3950138886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.3950138886 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_stall_trans.3911617354 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 156239319 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 07:58:18 AM UTC 24 |
| Finished | Aug 21 07:58:20 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3911617354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3911617354 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_stream_len_max.704602629 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 606738310 ps |
| CPU time | 2.29 seconds |
| Started | Aug 21 07:58:18 AM UTC 24 |
| Finished | Aug 21 07:58:21 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=704602629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.704602629 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_streaming_out.3025234481 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 3193545352 ps |
| CPU time | 31.36 seconds |
| Started | Aug 21 07:58:18 AM UTC 24 |
| Finished | Aug 21 07:58:51 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3025234481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.3025234481 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_timeout_missing_host_handshake.2811211734 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 1548108115 ps |
| CPU time | 32.84 seconds |
| Started | Aug 21 07:58:07 AM UTC 24 |
| Finished | Aug 21 07:58:41 AM UTC 24 |
| Peak memory | 218192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2811211734 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing _host_handshake.2811211734 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/21.usbdev_tx_rx_disruption.3913221961 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 483478999 ps |
| CPU time | 1.88 seconds |
| Started | Aug 21 07:58:18 AM UTC 24 |
| Finished | Aug 21 07:58:21 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3913221961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 21.usbdev_tx_rx_disruption.3913221961 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/21.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/210.usbdev_tx_rx_disruption.3547293928 |
| Short name | T3332 |
| Test name | |
| Test status | |
| Simulation time | 603845806 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:06:22 AM UTC 24 |
| Finished | Aug 21 08:06:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3547293928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 210.usbdev_tx_rx_disruption.3547293928 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/210.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/211.usbdev_tx_rx_disruption.149894415 |
| Short name | T3335 |
| Test name | |
| Test status | |
| Simulation time | 536396399 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:06:22 AM UTC 24 |
| Finished | Aug 21 08:06:31 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=149894415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 211.usbdev_tx_rx_disruption.149894415 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/211.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/212.usbdev_tx_rx_disruption.2479612921 |
| Short name | T3333 |
| Test name | |
| Test status | |
| Simulation time | 534191503 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:06:22 AM UTC 24 |
| Finished | Aug 21 08:06:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2479612921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 212.usbdev_tx_rx_disruption.2479612921 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/212.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/213.usbdev_tx_rx_disruption.3913831133 |
| Short name | T3305 |
| Test name | |
| Test status | |
| Simulation time | 552161162 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:06:22 AM UTC 24 |
| Finished | Aug 21 08:06:25 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3913831133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 213.usbdev_tx_rx_disruption.3913831133 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/213.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/214.usbdev_tx_rx_disruption.2723070663 |
| Short name | T3336 |
| Test name | |
| Test status | |
| Simulation time | 684137490 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 08:06:22 AM UTC 24 |
| Finished | Aug 21 08:06:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2723070663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 214.usbdev_tx_rx_disruption.2723070663 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/214.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/215.usbdev_tx_rx_disruption.1756511928 |
| Short name | T3329 |
| Test name | |
| Test status | |
| Simulation time | 491924528 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:06:22 AM UTC 24 |
| Finished | Aug 21 08:06:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1756511928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 215.usbdev_tx_rx_disruption.1756511928 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/215.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/216.usbdev_tx_rx_disruption.2016533039 |
| Short name | T3334 |
| Test name | |
| Test status | |
| Simulation time | 569430458 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:06:22 AM UTC 24 |
| Finished | Aug 21 08:06:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2016533039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 216.usbdev_tx_rx_disruption.2016533039 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/216.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/217.usbdev_tx_rx_disruption.1436300994 |
| Short name | T3354 |
| Test name | |
| Test status | |
| Simulation time | 564072455 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:06:22 AM UTC 24 |
| Finished | Aug 21 08:06:37 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1436300994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 217.usbdev_tx_rx_disruption.1436300994 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/217.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/218.usbdev_tx_rx_disruption.2446011510 |
| Short name | T3355 |
| Test name | |
| Test status | |
| Simulation time | 445157909 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 08:06:22 AM UTC 24 |
| Finished | Aug 21 08:06:38 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2446011510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 218.usbdev_tx_rx_disruption.2446011510 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/218.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/219.usbdev_tx_rx_disruption.2943611231 |
| Short name | T3312 |
| Test name | |
| Test status | |
| Simulation time | 554886491 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:06:23 AM UTC 24 |
| Finished | Aug 21 08:06:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2943611231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 219.usbdev_tx_rx_disruption.2943611231 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/219.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_alert_test.1398726651 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 57090688 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 07:58:34 AM UTC 24 |
| Finished | Aug 21 07:58:36 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1398726651 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.1398726651 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_aon_wake_disconnect.1900964869 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 9339602599 ps |
| CPU time | 14.97 seconds |
| Started | Aug 21 07:58:20 AM UTC 24 |
| Finished | Aug 21 07:58:36 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1900964869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbd ev_aon_wake_disconnect.1900964869 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_aon_wake_reset.2450138606 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 21215514426 ps |
| CPU time | 25.94 seconds |
| Started | Aug 21 07:58:20 AM UTC 24 |
| Finished | Aug 21 07:58:47 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2450138606 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.2450138606 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_aon_wake_resume.407663441 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 25546480557 ps |
| CPU time | 42.9 seconds |
| Started | Aug 21 07:58:20 AM UTC 24 |
| Finished | Aug 21 07:59:04 AM UTC 24 |
| Peak memory | 228488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=407663441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbde v_aon_wake_resume.407663441 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_av_buffer.4189047951 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 200255892 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 07:58:20 AM UTC 24 |
| Finished | Aug 21 07:58:22 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4189047951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.4189047951 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_bitstuff_err.1859231908 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 141932478 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 07:58:20 AM UTC 24 |
| Finished | Aug 21 07:58:22 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1859231908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.1859231908 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_data_toggle_clear.1554787524 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 243633623 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 07:58:20 AM UTC 24 |
| Finished | Aug 21 07:58:23 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1554787524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.1554787524 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_device_address.2107787717 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 31345849392 ps |
| CPU time | 57.5 seconds |
| Started | Aug 21 07:58:20 AM UTC 24 |
| Finished | Aug 21 07:59:19 AM UTC 24 |
| Peak memory | 218252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2107787717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2107787717 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_device_timeout.3293705783 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 1506836287 ps |
| CPU time | 27.78 seconds |
| Started | Aug 21 07:58:20 AM UTC 24 |
| Finished | Aug 21 07:58:49 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3293705783 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.3293705783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_disable_endpoint.427730600 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 774578609 ps |
| CPU time | 2.64 seconds |
| Started | Aug 21 07:58:21 AM UTC 24 |
| Finished | Aug 21 07:58:25 AM UTC 24 |
| Peak memory | 218032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=427730600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.427730600 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_disconnected.2818300436 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 172349405 ps |
| CPU time | 1 seconds |
| Started | Aug 21 07:58:21 AM UTC 24 |
| Finished | Aug 21 07:58:23 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2818300436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2818300436 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_enable.4152455668 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 39953326 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 07:58:21 AM UTC 24 |
| Finished | Aug 21 07:58:23 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4152455668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.4152455668 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_endpoint_access.2951748528 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 1023174576 ps |
| CPU time | 3.58 seconds |
| Started | Aug 21 07:58:21 AM UTC 24 |
| Finished | Aug 21 07:58:26 AM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2951748528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.2951748528 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_fifo_rst.3926554603 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 341305865 ps |
| CPU time | 2.46 seconds |
| Started | Aug 21 07:58:23 AM UTC 24 |
| Finished | Aug 21 07:58:26 AM UTC 24 |
| Peak memory | 218060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3926554603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3926554603 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_in_iso.3082700387 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 187110492 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:58:23 AM UTC 24 |
| Finished | Aug 21 07:58:25 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3082700387 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3082700387 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_in_stall.1277148598 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 149459614 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 07:58:23 AM UTC 24 |
| Finished | Aug 21 07:58:25 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1277148598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1277148598 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_in_trans.657396146 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 179023179 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 07:58:23 AM UTC 24 |
| Finished | Aug 21 07:58:25 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=657396146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.657396146 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_invalid_sync.262580171 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 2538532545 ps |
| CPU time | 18.32 seconds |
| Started | Aug 21 07:58:23 AM UTC 24 |
| Finished | Aug 21 07:58:42 AM UTC 24 |
| Peak memory | 235188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=262580171 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.262580171 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_iso_retraction.2804225989 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 6512405055 ps |
| CPU time | 74.84 seconds |
| Started | Aug 21 07:58:23 AM UTC 24 |
| Finished | Aug 21 07:59:40 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2804225989 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.2804225989 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_link_in_err.2089854956 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 235102372 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:58:24 AM UTC 24 |
| Finished | Aug 21 07:58:27 AM UTC 24 |
| Peak memory | 216144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2089854956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2089854956 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_link_resume.3970766863 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 7756014507 ps |
| CPU time | 11.44 seconds |
| Started | Aug 21 07:58:24 AM UTC 24 |
| Finished | Aug 21 07:58:37 AM UTC 24 |
| Peak memory | 218104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3970766863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3970766863 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_link_suspend.1752166450 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 10509315849 ps |
| CPU time | 19.44 seconds |
| Started | Aug 21 07:58:24 AM UTC 24 |
| Finished | Aug 21 07:58:45 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1752166450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1752166450 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_low_speed_traffic.4209503747 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 5179694491 ps |
| CPU time | 125.28 seconds |
| Started | Aug 21 07:58:24 AM UTC 24 |
| Finished | Aug 21 08:00:32 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4209503747 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.4209503747 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_max_inter_pkt_delay.204800000 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 2070409825 ps |
| CPU time | 53.75 seconds |
| Started | Aug 21 07:58:25 AM UTC 24 |
| Finished | Aug 21 07:59:20 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=204800000 -assert nopostproc +UVM _TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.204800000 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_max_length_in_transaction.1495594077 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 239593667 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 07:58:26 AM UTC 24 |
| Finished | Aug 21 07:58:29 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1495594077 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.1495594077 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_max_length_out_transaction.2715157136 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 193989376 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 07:58:26 AM UTC 24 |
| Finished | Aug 21 07:58:28 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2715157136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2715157136 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_max_non_iso_usb_traffic.3170563478 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 1971065180 ps |
| CPU time | 18.01 seconds |
| Started | Aug 21 07:58:26 AM UTC 24 |
| Finished | Aug 21 07:58:45 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3170563478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_non_iso_usb_traffic.3170563478 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_min_inter_pkt_delay.2856581215 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 3601929215 ps |
| CPU time | 35.59 seconds |
| Started | Aug 21 07:58:26 AM UTC 24 |
| Finished | Aug 21 07:59:03 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2856581215 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.2856581215 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_min_length_in_transaction.1874799702 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 148701223 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:58:26 AM UTC 24 |
| Finished | Aug 21 07:58:28 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1874799702 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1874799702 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_min_length_out_transaction.2881162750 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 151050336 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:58:26 AM UTC 24 |
| Finished | Aug 21 07:58:29 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2881162750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2881162750 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_nak_trans.3726400010 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 218128428 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:58:26 AM UTC 24 |
| Finished | Aug 21 07:58:29 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3726400010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3726400010 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_out_iso.3177281677 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 196372515 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:58:27 AM UTC 24 |
| Finished | Aug 21 07:58:30 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3177281677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3177281677 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_out_stall.4128511677 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 205173797 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 07:58:27 AM UTC 24 |
| Finished | Aug 21 07:58:30 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4128511677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.4128511677 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_out_trans_nak.2194876501 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 181442610 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 07:58:27 AM UTC 24 |
| Finished | Aug 21 07:58:29 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2194876501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2194876501 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_pending_in_trans.2328388254 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 198610142 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:58:27 AM UTC 24 |
| Finished | Aug 21 07:58:30 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2328388254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.2328388254 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_phy_config_pinflip.1779906476 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 212943924 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 07:58:29 AM UTC 24 |
| Finished | Aug 21 07:58:32 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1779906476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1779906476 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_phy_config_usb_ref_disable.4087925461 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 159601632 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:58:29 AM UTC 24 |
| Finished | Aug 21 07:58:32 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4087925461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.4087925461 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_phy_pins_sense.2816054993 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 96742756 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 07:58:29 AM UTC 24 |
| Finished | Aug 21 07:58:32 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2816054993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2816054993 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_pkt_buffer.2252123132 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 17348159212 ps |
| CPU time | 48.61 seconds |
| Started | Aug 21 07:58:29 AM UTC 24 |
| Finished | Aug 21 07:59:19 AM UTC 24 |
| Peak memory | 228448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2252123132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2252123132 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_pkt_received.3967838520 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 160594139 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 07:58:29 AM UTC 24 |
| Finished | Aug 21 07:58:32 AM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3967838520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3967838520 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_pkt_sent.1929013057 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 213494349 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:58:29 AM UTC 24 |
| Finished | Aug 21 07:58:32 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1929013057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1929013057 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_random_length_in_transaction.2981519560 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 246818010 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:58:31 AM UTC 24 |
| Finished | Aug 21 07:58:33 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2981519560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2981519560 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_random_length_out_transaction.333781598 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 193049308 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 07:58:31 AM UTC 24 |
| Finished | Aug 21 07:58:33 AM UTC 24 |
| Peak memory | 216528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=333781598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.333781598 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_rx_crc_err.406530686 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 137234543 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:58:31 AM UTC 24 |
| Finished | Aug 21 07:58:33 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=406530686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.406530686 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_rx_full.3507682836 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 321074245 ps |
| CPU time | 2.1 seconds |
| Started | Aug 21 07:58:31 AM UTC 24 |
| Finished | Aug 21 07:58:34 AM UTC 24 |
| Peak memory | 218068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3507682836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_full.3507682836 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_setup_stage.3912512960 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 164082710 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:58:31 AM UTC 24 |
| Finished | Aug 21 07:58:33 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3912512960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3912512960 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_setup_trans_ignored.2922513532 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 189332559 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:58:31 AM UTC 24 |
| Finished | Aug 21 07:58:33 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2922513532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2922513532 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_smoke.3606001685 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 221687861 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 07:58:31 AM UTC 24 |
| Finished | Aug 21 07:58:34 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3606001685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3606001685 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_spurious_pids_ignored.1514540140 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 2708156181 ps |
| CPU time | 20.69 seconds |
| Started | Aug 21 07:58:32 AM UTC 24 |
| Finished | Aug 21 07:58:54 AM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1514540140 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.1514540140 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_stall_priority_over_nak.220409202 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 222964706 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 07:58:32 AM UTC 24 |
| Finished | Aug 21 07:58:35 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=220409202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20 24_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.220409202 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_stall_trans.1435046903 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 152156735 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:58:32 AM UTC 24 |
| Finished | Aug 21 07:58:35 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1435046903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1435046903 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_stream_len_max.3537318939 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 300274931 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 07:58:33 AM UTC 24 |
| Finished | Aug 21 07:58:35 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3537318939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.3537318939 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_streaming_out.716294016 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 2967199257 ps |
| CPU time | 21.63 seconds |
| Started | Aug 21 07:58:33 AM UTC 24 |
| Finished | Aug 21 07:58:55 AM UTC 24 |
| Peak memory | 230732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=716294016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.716294016 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_timeout_missing_host_handshake.805014249 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 715855536 ps |
| CPU time | 14.64 seconds |
| Started | Aug 21 07:58:20 AM UTC 24 |
| Finished | Aug 21 07:58:36 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=805014249 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_ host_handshake.805014249 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/22.usbdev_tx_rx_disruption.628929446 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 467910759 ps |
| CPU time | 2.48 seconds |
| Started | Aug 21 07:58:33 AM UTC 24 |
| Finished | Aug 21 07:58:36 AM UTC 24 |
| Peak memory | 218068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=628929446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.usbdev_tx_rx_disruption.628929446 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/22.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/220.usbdev_tx_rx_disruption.3682223345 |
| Short name | T3307 |
| Test name | |
| Test status | |
| Simulation time | 518919780 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:06:23 AM UTC 24 |
| Finished | Aug 21 08:06:26 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3682223345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 220.usbdev_tx_rx_disruption.3682223345 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/220.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/221.usbdev_tx_rx_disruption.241303542 |
| Short name | T3308 |
| Test name | |
| Test status | |
| Simulation time | 526763992 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 08:06:23 AM UTC 24 |
| Finished | Aug 21 08:06:26 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=241303542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 221.usbdev_tx_rx_disruption.241303542 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/221.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/222.usbdev_tx_rx_disruption.3691552094 |
| Short name | T3309 |
| Test name | |
| Test status | |
| Simulation time | 593889115 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:06:23 AM UTC 24 |
| Finished | Aug 21 08:06:26 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3691552094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 222.usbdev_tx_rx_disruption.3691552094 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/222.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/223.usbdev_tx_rx_disruption.2668097046 |
| Short name | T3314 |
| Test name | |
| Test status | |
| Simulation time | 480826831 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:06:23 AM UTC 24 |
| Finished | Aug 21 08:06:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2668097046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 223.usbdev_tx_rx_disruption.2668097046 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/223.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/224.usbdev_tx_rx_disruption.1351781612 |
| Short name | T3322 |
| Test name | |
| Test status | |
| Simulation time | 618190454 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 08:06:24 AM UTC 24 |
| Finished | Aug 21 08:06:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1351781612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 224.usbdev_tx_rx_disruption.1351781612 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/224.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/225.usbdev_tx_rx_disruption.3716560144 |
| Short name | T3358 |
| Test name | |
| Test status | |
| Simulation time | 564779789 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:06:25 AM UTC 24 |
| Finished | Aug 21 08:06:38 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3716560144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 225.usbdev_tx_rx_disruption.3716560144 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/225.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/226.usbdev_tx_rx_disruption.259133602 |
| Short name | T3389 |
| Test name | |
| Test status | |
| Simulation time | 572691534 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:06:25 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=259133602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 226.usbdev_tx_rx_disruption.259133602 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/226.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/227.usbdev_tx_rx_disruption.2206666465 |
| Short name | T3348 |
| Test name | |
| Test status | |
| Simulation time | 541893002 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:06:26 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2206666465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 227.usbdev_tx_rx_disruption.2206666465 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/227.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/228.usbdev_tx_rx_disruption.2639194749 |
| Short name | T3345 |
| Test name | |
| Test status | |
| Simulation time | 555445916 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:06:27 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2639194749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 228.usbdev_tx_rx_disruption.2639194749 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/228.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/229.usbdev_tx_rx_disruption.3741139299 |
| Short name | T3347 |
| Test name | |
| Test status | |
| Simulation time | 527055086 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:06:27 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3741139299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 229.usbdev_tx_rx_disruption.3741139299 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/229.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_alert_test.2559665354 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 45265214 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 07:58:52 AM UTC 24 |
| Finished | Aug 21 07:58:54 AM UTC 24 |
| Peak memory | 216572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2559665354 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.2559665354 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_aon_wake_disconnect.1277558174 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 11790342524 ps |
| CPU time | 20.58 seconds |
| Started | Aug 21 07:58:34 AM UTC 24 |
| Finished | Aug 21 07:58:56 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1277558174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbd ev_aon_wake_disconnect.1277558174 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_aon_wake_reset.3539319293 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 19213910895 ps |
| CPU time | 27.55 seconds |
| Started | Aug 21 07:58:34 AM UTC 24 |
| Finished | Aug 21 07:59:03 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3539319293 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3539319293 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_aon_wake_resume.1942734153 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 30991446333 ps |
| CPU time | 44.39 seconds |
| Started | Aug 21 07:58:34 AM UTC 24 |
| Finished | Aug 21 07:59:20 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1942734153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbd ev_aon_wake_resume.1942734153 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_av_buffer.919659525 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 197707378 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:58:34 AM UTC 24 |
| Finished | Aug 21 07:58:37 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=919659525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.919659525 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_bitstuff_err.4212487255 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 162874784 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:58:36 AM UTC 24 |
| Finished | Aug 21 07:58:38 AM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4212487255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.4212487255 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_data_toggle_clear.593480612 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 488507421 ps |
| CPU time | 2.83 seconds |
| Started | Aug 21 07:58:36 AM UTC 24 |
| Finished | Aug 21 07:58:40 AM UTC 24 |
| Peak memory | 217852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=593480612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.593480612 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_data_toggle_restore.2879441761 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 621292560 ps |
| CPU time | 2.85 seconds |
| Started | Aug 21 07:58:36 AM UTC 24 |
| Finished | Aug 21 07:58:40 AM UTC 24 |
| Peak memory | 218072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2879441761 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2879441761 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_device_address.4241272477 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 29593853861 ps |
| CPU time | 53.57 seconds |
| Started | Aug 21 07:58:36 AM UTC 24 |
| Finished | Aug 21 07:59:31 AM UTC 24 |
| Peak memory | 218356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4241272477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.4241272477 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_device_timeout.1597255703 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 880573568 ps |
| CPU time | 17.5 seconds |
| Started | Aug 21 07:58:36 AM UTC 24 |
| Finished | Aug 21 07:58:55 AM UTC 24 |
| Peak memory | 218120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1597255703 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.1597255703 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_disable_endpoint.2139221162 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 800805833 ps |
| CPU time | 3.02 seconds |
| Started | Aug 21 07:58:37 AM UTC 24 |
| Finished | Aug 21 07:58:42 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2139221162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2139221162 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_disconnected.3091834778 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 150767550 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:58:38 AM UTC 24 |
| Finished | Aug 21 07:58:40 AM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3091834778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.3091834778 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_enable.2690096018 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 43435656 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 07:58:38 AM UTC 24 |
| Finished | Aug 21 07:58:40 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2690096018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2690096018 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_endpoint_access.3098584390 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 875156468 ps |
| CPU time | 3.34 seconds |
| Started | Aug 21 07:58:38 AM UTC 24 |
| Finished | Aug 21 07:58:42 AM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3098584390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.3098584390 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_endpoint_types.2179237170 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 276999185 ps |
| CPU time | 1.9 seconds |
| Started | Aug 21 07:58:38 AM UTC 24 |
| Finished | Aug 21 07:58:41 AM UTC 24 |
| Peak memory | 216360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2179237170 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_types.2179237170 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_fifo_rst.3734745696 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 168313558 ps |
| CPU time | 2.54 seconds |
| Started | Aug 21 07:58:38 AM UTC 24 |
| Finished | Aug 21 07:58:41 AM UTC 24 |
| Peak memory | 218304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3734745696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3734745696 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_in_iso.2727934143 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 230579431 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 07:58:39 AM UTC 24 |
| Finished | Aug 21 07:58:42 AM UTC 24 |
| Peak memory | 226696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2727934143 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2727934143 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_in_stall.668822089 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 196906340 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 07:58:39 AM UTC 24 |
| Finished | Aug 21 07:58:42 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=668822089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.668822089 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_in_trans.654941024 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 177691087 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 07:58:40 AM UTC 24 |
| Finished | Aug 21 07:58:43 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=654941024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.654941024 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_invalid_sync.843388349 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2233435353 ps |
| CPU time | 56.6 seconds |
| Started | Aug 21 07:58:38 AM UTC 24 |
| Finished | Aug 21 07:59:36 AM UTC 24 |
| Peak memory | 228532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=843388349 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.843388349 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_iso_retraction.1748167158 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 12549687534 ps |
| CPU time | 79.69 seconds |
| Started | Aug 21 07:58:40 AM UTC 24 |
| Finished | Aug 21 08:00:02 AM UTC 24 |
| Peak memory | 218312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1748167158 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.1748167158 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_link_in_err.4035110090 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 176593933 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:58:41 AM UTC 24 |
| Finished | Aug 21 07:58:43 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4035110090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.4035110090 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_link_resume.1093492364 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 30256915427 ps |
| CPU time | 48.56 seconds |
| Started | Aug 21 07:58:41 AM UTC 24 |
| Finished | Aug 21 07:59:31 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1093492364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.1093492364 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_link_suspend.517312989 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 8430038130 ps |
| CPU time | 16.14 seconds |
| Started | Aug 21 07:58:41 AM UTC 24 |
| Finished | Aug 21 07:58:58 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=517312989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.517312989 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_low_speed_traffic.1047872585 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 3773846949 ps |
| CPU time | 96.54 seconds |
| Started | Aug 21 07:58:42 AM UTC 24 |
| Finished | Aug 21 08:00:21 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1047872585 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.1047872585 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_max_inter_pkt_delay.1338713552 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 1692788135 ps |
| CPU time | 41.8 seconds |
| Started | Aug 21 07:58:42 AM UTC 24 |
| Finished | Aug 21 07:59:25 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1338713552 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1338713552 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_max_length_in_transaction.405532105 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 259899535 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 07:58:42 AM UTC 24 |
| Finished | Aug 21 07:58:45 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=405532105 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.405532105 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_max_length_out_transaction.2266498929 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 195890377 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 07:58:42 AM UTC 24 |
| Finished | Aug 21 07:58:45 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2266498929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2266498929 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_max_non_iso_usb_traffic.2564431655 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 1718161997 ps |
| CPU time | 14.88 seconds |
| Started | Aug 21 07:58:42 AM UTC 24 |
| Finished | Aug 21 07:58:58 AM UTC 24 |
| Peak memory | 235184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2564431655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_non_iso_usb_traffic.2564431655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_min_inter_pkt_delay.708176085 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 3196273908 ps |
| CPU time | 84.08 seconds |
| Started | Aug 21 07:58:44 AM UTC 24 |
| Finished | Aug 21 08:00:10 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=708176085 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.708176085 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_min_length_in_transaction.3028553541 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 160901385 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 07:58:44 AM UTC 24 |
| Finished | Aug 21 07:58:47 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3028553541 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.3028553541 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_min_length_out_transaction.267961466 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 165960330 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:58:44 AM UTC 24 |
| Finished | Aug 21 07:58:47 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=267961466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.267961466 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_nak_trans.3045503392 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 227723051 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 07:58:44 AM UTC 24 |
| Finished | Aug 21 07:58:47 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3045503392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3045503392 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_out_iso.3269926152 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 157833170 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:58:44 AM UTC 24 |
| Finished | Aug 21 07:58:47 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3269926152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3269926152 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_out_stall.299321850 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 169389312 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:58:44 AM UTC 24 |
| Finished | Aug 21 07:58:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=299321850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.299321850 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_out_trans_nak.1963351481 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 250719984 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 07:58:45 AM UTC 24 |
| Finished | Aug 21 07:58:48 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1963351481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1963351481 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_pending_in_trans.483609938 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 205548824 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:58:45 AM UTC 24 |
| Finished | Aug 21 07:58:48 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=483609938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.483609938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_phy_config_pinflip.3120500621 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 218940891 ps |
| CPU time | 1.74 seconds |
| Started | Aug 21 07:58:45 AM UTC 24 |
| Finished | Aug 21 07:58:48 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3120500621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.3120500621 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_phy_config_usb_ref_disable.1660489464 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 147376405 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:58:47 AM UTC 24 |
| Finished | Aug 21 07:58:49 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1660489464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1660489464 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_phy_pins_sense.1785504426 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 28619123 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 07:58:47 AM UTC 24 |
| Finished | Aug 21 07:58:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1785504426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1785504426 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_pkt_buffer.3457896239 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 20303416185 ps |
| CPU time | 61.49 seconds |
| Started | Aug 21 07:58:48 AM UTC 24 |
| Finished | Aug 21 07:59:52 AM UTC 24 |
| Peak memory | 228584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3457896239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3457896239 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_pkt_received.2828327717 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 195323817 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 07:58:48 AM UTC 24 |
| Finished | Aug 21 07:58:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2828327717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2828327717 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_pkt_sent.3383365075 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 271888925 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:58:48 AM UTC 24 |
| Finished | Aug 21 07:58:51 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3383365075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3383365075 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_random_length_in_transaction.851289036 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 254604637 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:58:49 AM UTC 24 |
| Finished | Aug 21 07:58:51 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=851289036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.851289036 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_random_length_out_transaction.1001965378 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 193537559 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:58:49 AM UTC 24 |
| Finished | Aug 21 07:58:51 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1001965378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.1001965378 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_rx_crc_err.1679633606 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 145953893 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:58:49 AM UTC 24 |
| Finished | Aug 21 07:58:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1679633606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.1679633606 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_rx_full.2099582202 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 290951800 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 07:58:49 AM UTC 24 |
| Finished | Aug 21 07:58:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2099582202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_full.2099582202 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_setup_stage.4275110235 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 156466008 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:58:49 AM UTC 24 |
| Finished | Aug 21 07:58:51 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4275110235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.4275110235 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_setup_trans_ignored.3925405292 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 195316330 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:58:49 AM UTC 24 |
| Finished | Aug 21 07:58:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3925405292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3925405292 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_smoke.3263726655 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 211722707 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:58:49 AM UTC 24 |
| Finished | Aug 21 07:58:51 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3263726655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3263726655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_spurious_pids_ignored.455629856 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 2902591160 ps |
| CPU time | 20.85 seconds |
| Started | Aug 21 07:58:49 AM UTC 24 |
| Finished | Aug 21 07:59:11 AM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=455629856 -assert nopostproc +UVM_TESTNAME=usbdev_bas e_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.455629856 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_stall_priority_over_nak.4202151469 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 229303259 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:58:50 AM UTC 24 |
| Finished | Aug 21 07:58:53 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4202151469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.4202151469 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_stall_trans.2124195939 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 213635866 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 07:58:50 AM UTC 24 |
| Finished | Aug 21 07:58:53 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2124195939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2124195939 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_stream_len_max.2455059862 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 1398247028 ps |
| CPU time | 4.74 seconds |
| Started | Aug 21 07:58:50 AM UTC 24 |
| Finished | Aug 21 07:58:56 AM UTC 24 |
| Peak memory | 218124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2455059862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2455059862 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_streaming_out.141509418 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 3216019516 ps |
| CPU time | 31.39 seconds |
| Started | Aug 21 07:58:50 AM UTC 24 |
| Finished | Aug 21 07:59:23 AM UTC 24 |
| Peak memory | 228652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=141509418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.141509418 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_timeout_missing_host_handshake.1320917912 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 863680386 ps |
| CPU time | 17.45 seconds |
| Started | Aug 21 07:58:36 AM UTC 24 |
| Finished | Aug 21 07:58:55 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1320917912 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing _host_handshake.1320917912 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/23.usbdev_tx_rx_disruption.2847417870 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 649381785 ps |
| CPU time | 3.14 seconds |
| Started | Aug 21 07:58:50 AM UTC 24 |
| Finished | Aug 21 07:58:55 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2847417870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.usbdev_tx_rx_disruption.2847417870 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/23.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/230.usbdev_tx_rx_disruption.408965319 |
| Short name | T3351 |
| Test name | |
| Test status | |
| Simulation time | 563825430 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:06:27 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=408965319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 230.usbdev_tx_rx_disruption.408965319 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/230.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/231.usbdev_tx_rx_disruption.2471492366 |
| Short name | T3352 |
| Test name | |
| Test status | |
| Simulation time | 537547497 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:06:27 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2471492366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 231.usbdev_tx_rx_disruption.2471492366 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/231.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/232.usbdev_tx_rx_disruption.1142638914 |
| Short name | T3357 |
| Test name | |
| Test status | |
| Simulation time | 559917525 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:06:28 AM UTC 24 |
| Finished | Aug 21 08:06:38 AM UTC 24 |
| Peak memory | 216184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1142638914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 232.usbdev_tx_rx_disruption.1142638914 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/232.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/233.usbdev_tx_rx_disruption.1644728155 |
| Short name | T3356 |
| Test name | |
| Test status | |
| Simulation time | 479804521 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:06:28 AM UTC 24 |
| Finished | Aug 21 08:06:38 AM UTC 24 |
| Peak memory | 216124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1644728155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 233.usbdev_tx_rx_disruption.1644728155 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/233.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/234.usbdev_tx_rx_disruption.4195048896 |
| Short name | T3393 |
| Test name | |
| Test status | |
| Simulation time | 544777436 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:06:28 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4195048896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 234.usbdev_tx_rx_disruption.4195048896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/234.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/235.usbdev_tx_rx_disruption.1306984458 |
| Short name | T3404 |
| Test name | |
| Test status | |
| Simulation time | 596129350 ps |
| CPU time | 1.81 seconds |
| Started | Aug 21 08:06:28 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1306984458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 235.usbdev_tx_rx_disruption.1306984458 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/235.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/236.usbdev_tx_rx_disruption.1172359339 |
| Short name | T3390 |
| Test name | |
| Test status | |
| Simulation time | 491904412 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:06:28 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1172359339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 236.usbdev_tx_rx_disruption.1172359339 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/236.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/237.usbdev_tx_rx_disruption.4211493831 |
| Short name | T3397 |
| Test name | |
| Test status | |
| Simulation time | 602559687 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:06:28 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4211493831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 237.usbdev_tx_rx_disruption.4211493831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/237.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/238.usbdev_tx_rx_disruption.62906256 |
| Short name | T3392 |
| Test name | |
| Test status | |
| Simulation time | 484915128 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:06:28 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=62906256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 238.usbdev_tx_rx_disruption.62906256 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/238.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/239.usbdev_tx_rx_disruption.2163401183 |
| Short name | T3388 |
| Test name | |
| Test status | |
| Simulation time | 452878672 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:06:28 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2163401183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 239.usbdev_tx_rx_disruption.2163401183 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/239.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_alert_test.1808662123 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 51710169 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 07:59:07 AM UTC 24 |
| Finished | Aug 21 07:59:09 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1808662123 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.1808662123 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_aon_wake_disconnect.3726895384 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 6487599816 ps |
| CPU time | 10.22 seconds |
| Started | Aug 21 07:58:52 AM UTC 24 |
| Finished | Aug 21 07:59:04 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3726895384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbd ev_aon_wake_disconnect.3726895384 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_aon_wake_reset.3221719139 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 18985884374 ps |
| CPU time | 27.41 seconds |
| Started | Aug 21 07:58:52 AM UTC 24 |
| Finished | Aug 21 07:59:21 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3221719139 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.3221719139 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_aon_wake_resume.584721457 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 30851833725 ps |
| CPU time | 47.9 seconds |
| Started | Aug 21 07:58:52 AM UTC 24 |
| Finished | Aug 21 07:59:42 AM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=584721457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbde v_aon_wake_resume.584721457 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_av_buffer.4205828978 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 181231447 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 07:58:52 AM UTC 24 |
| Finished | Aug 21 07:58:55 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4205828978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.4205828978 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_bitstuff_err.344798028 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 208552767 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:58:52 AM UTC 24 |
| Finished | Aug 21 07:58:55 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=344798028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.344798028 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_data_toggle_clear.3989162624 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 149933218 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:58:52 AM UTC 24 |
| Finished | Aug 21 07:58:55 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3989162624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.3989162624 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_data_toggle_restore.3027931654 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 1171576364 ps |
| CPU time | 4.13 seconds |
| Started | Aug 21 07:58:52 AM UTC 24 |
| Finished | Aug 21 07:58:58 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3027931654 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3027931654 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_device_address.2314245222 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 14947716064 ps |
| CPU time | 23.29 seconds |
| Started | Aug 21 07:58:52 AM UTC 24 |
| Finished | Aug 21 07:59:17 AM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2314245222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2314245222 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_device_timeout.4267353685 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 3406712322 ps |
| CPU time | 29.12 seconds |
| Started | Aug 21 07:58:52 AM UTC 24 |
| Finished | Aug 21 07:59:23 AM UTC 24 |
| Peak memory | 218320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4267353685 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.4267353685 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_disable_endpoint.886946828 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 639742123 ps |
| CPU time | 2.16 seconds |
| Started | Aug 21 07:58:54 AM UTC 24 |
| Finished | Aug 21 07:58:57 AM UTC 24 |
| Peak memory | 218032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=886946828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.886946828 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_disconnected.1344527865 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 144285450 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:58:55 AM UTC 24 |
| Finished | Aug 21 07:58:57 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1344527865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1344527865 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_enable.3548667781 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 47042550 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 07:58:55 AM UTC 24 |
| Finished | Aug 21 07:58:57 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3548667781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3548667781 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_endpoint_access.1558002195 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 904978147 ps |
| CPU time | 2.43 seconds |
| Started | Aug 21 07:58:55 AM UTC 24 |
| Finished | Aug 21 07:58:58 AM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1558002195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1558002195 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_fifo_rst.2596162554 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 146300991 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 07:58:55 AM UTC 24 |
| Finished | Aug 21 07:58:58 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2596162554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2596162554 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_in_iso.959850738 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 172327560 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:58:55 AM UTC 24 |
| Finished | Aug 21 07:58:58 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=959850738 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.959850738 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_in_stall.2844987511 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 153283848 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:58:57 AM UTC 24 |
| Finished | Aug 21 07:59:00 AM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2844987511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2844987511 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_in_trans.2752595507 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 179608537 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:58:57 AM UTC 24 |
| Finished | Aug 21 07:59:00 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2752595507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2752595507 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_invalid_sync.1429462485 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 4091606170 ps |
| CPU time | 37.96 seconds |
| Started | Aug 21 07:58:55 AM UTC 24 |
| Finished | Aug 21 07:59:35 AM UTC 24 |
| Peak memory | 235008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1429462485 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.1429462485 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_iso_retraction.3090157854 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 10166159195 ps |
| CPU time | 70.51 seconds |
| Started | Aug 21 07:58:57 AM UTC 24 |
| Finished | Aug 21 08:00:10 AM UTC 24 |
| Peak memory | 218312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3090157854 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.3090157854 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_link_in_err.3094845487 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 191516320 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:58:57 AM UTC 24 |
| Finished | Aug 21 07:59:00 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3094845487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3094845487 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_link_resume.89292373 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 6137385443 ps |
| CPU time | 9.58 seconds |
| Started | Aug 21 07:58:57 AM UTC 24 |
| Finished | Aug 21 07:59:08 AM UTC 24 |
| Peak memory | 228464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=89292373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.89292373 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_link_suspend.3399301581 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 3408079542 ps |
| CPU time | 8.66 seconds |
| Started | Aug 21 07:58:57 AM UTC 24 |
| Finished | Aug 21 07:59:07 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3399301581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.3399301581 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_low_speed_traffic.2969622302 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 3705317289 ps |
| CPU time | 28.57 seconds |
| Started | Aug 21 07:58:57 AM UTC 24 |
| Finished | Aug 21 07:59:27 AM UTC 24 |
| Peak memory | 232652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2969622302 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.2969622302 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_max_inter_pkt_delay.2927830481 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 2013869834 ps |
| CPU time | 17.09 seconds |
| Started | Aug 21 07:58:59 AM UTC 24 |
| Finished | Aug 21 07:59:18 AM UTC 24 |
| Peak memory | 228292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2927830481 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.2927830481 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_max_length_in_transaction.1915318638 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 239355236 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 07:58:59 AM UTC 24 |
| Finished | Aug 21 07:59:02 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1915318638 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1915318638 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_max_length_out_transaction.2779307987 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 229510767 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 07:58:59 AM UTC 24 |
| Finished | Aug 21 07:59:02 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2779307987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2779307987 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_max_non_iso_usb_traffic.1255350737 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 2273637768 ps |
| CPU time | 22.28 seconds |
| Started | Aug 21 07:58:59 AM UTC 24 |
| Finished | Aug 21 07:59:23 AM UTC 24 |
| Peak memory | 228580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1255350737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_non_iso_usb_traffic.1255350737 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_min_inter_pkt_delay.1337227118 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 1989563935 ps |
| CPU time | 18.42 seconds |
| Started | Aug 21 07:58:59 AM UTC 24 |
| Finished | Aug 21 07:59:19 AM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1337227118 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.1337227118 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_min_length_in_transaction.3140109624 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 159087266 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:58:59 AM UTC 24 |
| Finished | Aug 21 07:59:02 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3140109624 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3140109624 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_min_length_out_transaction.2788707567 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 156819659 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:58:59 AM UTC 24 |
| Finished | Aug 21 07:59:02 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2788707567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2788707567 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_nak_trans.166306083 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 217198097 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 07:58:59 AM UTC 24 |
| Finished | Aug 21 07:59:02 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=166306083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.166306083 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_out_iso.3745240045 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 185016096 ps |
| CPU time | 1 seconds |
| Started | Aug 21 07:58:59 AM UTC 24 |
| Finished | Aug 21 07:59:02 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3745240045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.3745240045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_out_stall.2153876973 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 190099674 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:58:59 AM UTC 24 |
| Finished | Aug 21 07:59:02 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2153876973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2153876973 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_out_trans_nak.3221535175 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 178606240 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:59:01 AM UTC 24 |
| Finished | Aug 21 07:59:03 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3221535175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3221535175 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_pending_in_trans.1341040137 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 163555164 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:59:01 AM UTC 24 |
| Finished | Aug 21 07:59:03 AM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1341040137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1341040137 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_phy_config_pinflip.3289190342 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 243402440 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 07:59:01 AM UTC 24 |
| Finished | Aug 21 07:59:04 AM UTC 24 |
| Peak memory | 216296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3289190342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3289190342 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_phy_config_usb_ref_disable.4034908787 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 140358000 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:59:01 AM UTC 24 |
| Finished | Aug 21 07:59:03 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4034908787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.4034908787 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_phy_pins_sense.413400273 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 37053766 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 07:59:01 AM UTC 24 |
| Finished | Aug 21 07:59:03 AM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=413400273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.413400273 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_pkt_buffer.2088287498 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 14571398856 ps |
| CPU time | 38.93 seconds |
| Started | Aug 21 07:59:01 AM UTC 24 |
| Finished | Aug 21 07:59:41 AM UTC 24 |
| Peak memory | 228576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2088287498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2088287498 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_pkt_received.701466655 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 188029813 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:59:03 AM UTC 24 |
| Finished | Aug 21 07:59:05 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=701466655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.701466655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_pkt_sent.347502480 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 150502967 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 07:59:03 AM UTC 24 |
| Finished | Aug 21 07:59:05 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=347502480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.347502480 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_random_length_in_transaction.708096745 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 149492496 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 07:59:03 AM UTC 24 |
| Finished | Aug 21 07:59:05 AM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=708096745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.708096745 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_random_length_out_transaction.1008042461 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 159808602 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:59:03 AM UTC 24 |
| Finished | Aug 21 07:59:06 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1008042461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.1008042461 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_rx_crc_err.1773973872 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 151680723 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 07:59:03 AM UTC 24 |
| Finished | Aug 21 07:59:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1773973872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.1773973872 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_rx_full.749360225 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 395606240 ps |
| CPU time | 1.79 seconds |
| Started | Aug 21 07:59:03 AM UTC 24 |
| Finished | Aug 21 07:59:06 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=749360225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_full.749360225 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_setup_stage.1895144942 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 178439883 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 07:59:03 AM UTC 24 |
| Finished | Aug 21 07:59:06 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1895144942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1895144942 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_setup_trans_ignored.3001048054 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 153715185 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 07:59:05 AM UTC 24 |
| Finished | Aug 21 07:59:07 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3001048054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3001048054 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_smoke.187601135 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 225341905 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 07:59:05 AM UTC 24 |
| Finished | Aug 21 07:59:07 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=187601135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.187601135 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_spurious_pids_ignored.3242031787 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 1955933990 ps |
| CPU time | 46.7 seconds |
| Started | Aug 21 07:59:05 AM UTC 24 |
| Finished | Aug 21 07:59:53 AM UTC 24 |
| Peak memory | 228348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3242031787 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3242031787 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_stall_priority_over_nak.648399163 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 180097981 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:59:05 AM UTC 24 |
| Finished | Aug 21 07:59:07 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=648399163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20 24_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.648399163 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_stall_trans.2878786687 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 148857238 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:59:05 AM UTC 24 |
| Finished | Aug 21 07:59:08 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2878786687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2878786687 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_stream_len_max.417567996 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 430139577 ps |
| CPU time | 1.85 seconds |
| Started | Aug 21 07:59:05 AM UTC 24 |
| Finished | Aug 21 07:59:08 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=417567996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.417567996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_streaming_out.3921406210 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 3079455054 ps |
| CPU time | 28.76 seconds |
| Started | Aug 21 07:59:05 AM UTC 24 |
| Finished | Aug 21 07:59:35 AM UTC 24 |
| Peak memory | 228644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3921406210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3921406210 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_timeout_missing_host_handshake.4076786824 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 4360162987 ps |
| CPU time | 33.91 seconds |
| Started | Aug 21 07:58:54 AM UTC 24 |
| Finished | Aug 21 07:59:29 AM UTC 24 |
| Peak memory | 218312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4076786824 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing _host_handshake.4076786824 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/24.usbdev_tx_rx_disruption.1796027978 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 612749310 ps |
| CPU time | 2.18 seconds |
| Started | Aug 21 07:59:05 AM UTC 24 |
| Finished | Aug 21 07:59:09 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1796027978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.usbdev_tx_rx_disruption.1796027978 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/24.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/240.usbdev_tx_rx_disruption.3662996089 |
| Short name | T3394 |
| Test name | |
| Test status | |
| Simulation time | 436011394 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:06:28 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3662996089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 240.usbdev_tx_rx_disruption.3662996089 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/240.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/241.usbdev_tx_rx_disruption.4100931350 |
| Short name | T3401 |
| Test name | |
| Test status | |
| Simulation time | 536163392 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:06:29 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4100931350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 241.usbdev_tx_rx_disruption.4100931350 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/241.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/242.usbdev_tx_rx_disruption.3622956279 |
| Short name | T3408 |
| Test name | |
| Test status | |
| Simulation time | 646056157 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:06:29 AM UTC 24 |
| Finished | Aug 21 08:06:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3622956279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 242.usbdev_tx_rx_disruption.3622956279 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/242.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/245.usbdev_tx_rx_disruption.4189737842 |
| Short name | T3413 |
| Test name | |
| Test status | |
| Simulation time | 478979206 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 08:06:29 AM UTC 24 |
| Finished | Aug 21 08:06:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4189737842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 245.usbdev_tx_rx_disruption.4189737842 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/245.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/246.usbdev_tx_rx_disruption.705084169 |
| Short name | T3372 |
| Test name | |
| Test status | |
| Simulation time | 486328126 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:06:29 AM UTC 24 |
| Finished | Aug 21 08:06:45 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=705084169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 246.usbdev_tx_rx_disruption.705084169 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/246.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/247.usbdev_tx_rx_disruption.3078026328 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 619919700 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:06:29 AM UTC 24 |
| Finished | Aug 21 08:06:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3078026328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 247.usbdev_tx_rx_disruption.3078026328 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/247.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/248.usbdev_tx_rx_disruption.3869111102 |
| Short name | T3360 |
| Test name | |
| Test status | |
| Simulation time | 573852589 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:06:29 AM UTC 24 |
| Finished | Aug 21 08:06:39 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3869111102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 248.usbdev_tx_rx_disruption.3869111102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/248.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/249.usbdev_tx_rx_disruption.685817963 |
| Short name | T3349 |
| Test name | |
| Test status | |
| Simulation time | 441735941 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:06:31 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=685817963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 249.usbdev_tx_rx_disruption.685817963 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/249.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_alert_test.2870529112 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 40774029 ps |
| CPU time | 1 seconds |
| Started | Aug 21 07:59:21 AM UTC 24 |
| Finished | Aug 21 07:59:23 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2870529112 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2870529112 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_aon_wake_disconnect.1176322463 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 11033976944 ps |
| CPU time | 19.12 seconds |
| Started | Aug 21 07:59:07 AM UTC 24 |
| Finished | Aug 21 07:59:27 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1176322463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbd ev_aon_wake_disconnect.1176322463 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_aon_wake_reset.1511333196 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 14289935068 ps |
| CPU time | 24.11 seconds |
| Started | Aug 21 07:59:07 AM UTC 24 |
| Finished | Aug 21 07:59:33 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1511333196 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1511333196 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_aon_wake_resume.1204735416 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 25804821368 ps |
| CPU time | 44.14 seconds |
| Started | Aug 21 07:59:07 AM UTC 24 |
| Finished | Aug 21 07:59:53 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1204735416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbd ev_aon_wake_resume.1204735416 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_av_buffer.3305656756 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 183106492 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:59:07 AM UTC 24 |
| Finished | Aug 21 07:59:10 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3305656756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3305656756 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_bitstuff_err.1605122244 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 155069699 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:59:07 AM UTC 24 |
| Finished | Aug 21 07:59:10 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1605122244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.1605122244 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_data_toggle_clear.3671517037 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 187929502 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 07:59:07 AM UTC 24 |
| Finished | Aug 21 07:59:10 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3671517037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.3671517037 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_data_toggle_restore.1323957763 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 955542818 ps |
| CPU time | 4.86 seconds |
| Started | Aug 21 07:59:07 AM UTC 24 |
| Finished | Aug 21 07:59:13 AM UTC 24 |
| Peak memory | 218204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1323957763 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1323957763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_device_address.1814036744 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 48696539109 ps |
| CPU time | 84.29 seconds |
| Started | Aug 21 07:59:07 AM UTC 24 |
| Finished | Aug 21 08:00:34 AM UTC 24 |
| Peak memory | 218404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1814036744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.1814036744 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_device_timeout.1223549362 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 4329270018 ps |
| CPU time | 35.96 seconds |
| Started | Aug 21 07:59:08 AM UTC 24 |
| Finished | Aug 21 07:59:45 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1223549362 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.1223549362 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_disable_endpoint.2489889937 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 429106699 ps |
| CPU time | 1.86 seconds |
| Started | Aug 21 07:59:09 AM UTC 24 |
| Finished | Aug 21 07:59:12 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2489889937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.2489889937 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_disconnected.3870233031 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 143254637 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:59:09 AM UTC 24 |
| Finished | Aug 21 07:59:12 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3870233031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3870233031 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_enable.3512610048 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 34436151 ps |
| CPU time | 0.96 seconds |
| Started | Aug 21 07:59:09 AM UTC 24 |
| Finished | Aug 21 07:59:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3512610048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3512610048 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_endpoint_access.334031274 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 978985010 ps |
| CPU time | 3.31 seconds |
| Started | Aug 21 07:59:09 AM UTC 24 |
| Finished | Aug 21 07:59:14 AM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=334031274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.334031274 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_endpoint_types.3274820307 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 315066444 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:59:09 AM UTC 24 |
| Finished | Aug 21 07:59:12 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3274820307 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_types.3274820307 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_fifo_rst.1318049462 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 305696410 ps |
| CPU time | 3.19 seconds |
| Started | Aug 21 07:59:09 AM UTC 24 |
| Finished | Aug 21 07:59:14 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1318049462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1318049462 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_in_iso.3577645859 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 197585653 ps |
| CPU time | 1.69 seconds |
| Started | Aug 21 07:59:09 AM UTC 24 |
| Finished | Aug 21 07:59:12 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3577645859 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3577645859 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_in_stall.2221737036 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 138693065 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 07:59:11 AM UTC 24 |
| Finished | Aug 21 07:59:13 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2221737036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2221737036 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_in_trans.3233577827 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 190608184 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 07:59:11 AM UTC 24 |
| Finished | Aug 21 07:59:13 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3233577827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3233577827 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_invalid_sync.3800015532 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 3053022898 ps |
| CPU time | 77.74 seconds |
| Started | Aug 21 07:59:09 AM UTC 24 |
| Finished | Aug 21 08:00:29 AM UTC 24 |
| Peak memory | 235244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3800015532 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.3800015532 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_iso_retraction.3859092901 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 4138148273 ps |
| CPU time | 48.46 seconds |
| Started | Aug 21 07:59:11 AM UTC 24 |
| Finished | Aug 21 08:00:01 AM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3859092901 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.3859092901 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_link_in_err.1558763561 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 241007944 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:59:11 AM UTC 24 |
| Finished | Aug 21 07:59:13 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1558763561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1558763561 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_link_resume.1118226229 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 30260171401 ps |
| CPU time | 52.3 seconds |
| Started | Aug 21 07:59:11 AM UTC 24 |
| Finished | Aug 21 08:00:05 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1118226229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.1118226229 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_link_suspend.2069184977 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 11410592571 ps |
| CPU time | 15.49 seconds |
| Started | Aug 21 07:59:14 AM UTC 24 |
| Finished | Aug 21 07:59:30 AM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2069184977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.2069184977 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_low_speed_traffic.3530873084 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 5281404071 ps |
| CPU time | 51.18 seconds |
| Started | Aug 21 07:59:14 AM UTC 24 |
| Finished | Aug 21 08:00:06 AM UTC 24 |
| Peak memory | 235336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3530873084 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.3530873084 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_max_inter_pkt_delay.3325080047 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 2554822282 ps |
| CPU time | 28.18 seconds |
| Started | Aug 21 07:59:14 AM UTC 24 |
| Finished | Aug 21 07:59:43 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3325080047 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3325080047 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_max_length_in_transaction.2412489220 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 256877587 ps |
| CPU time | 1.71 seconds |
| Started | Aug 21 07:59:14 AM UTC 24 |
| Finished | Aug 21 07:59:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2412489220 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2412489220 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_max_length_out_transaction.1938030558 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 209263124 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 07:59:14 AM UTC 24 |
| Finished | Aug 21 07:59:16 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1938030558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1938030558 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_min_inter_pkt_delay.3951357691 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 4347565017 ps |
| CPU time | 38.46 seconds |
| Started | Aug 21 07:59:14 AM UTC 24 |
| Finished | Aug 21 07:59:54 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3951357691 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.3951357691 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_min_length_in_transaction.1623311410 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 153098794 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:59:14 AM UTC 24 |
| Finished | Aug 21 07:59:16 AM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1623311410 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.1623311410 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_min_length_out_transaction.1965531956 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 147392686 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:59:14 AM UTC 24 |
| Finished | Aug 21 07:59:16 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1965531956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1965531956 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_nak_trans.1727749369 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 211799084 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:59:14 AM UTC 24 |
| Finished | Aug 21 07:59:16 AM UTC 24 |
| Peak memory | 216376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1727749369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1727749369 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_out_iso.2188583153 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 182086127 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:59:14 AM UTC 24 |
| Finished | Aug 21 07:59:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2188583153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.2188583153 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_out_stall.4203742045 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 202616101 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:59:15 AM UTC 24 |
| Finished | Aug 21 07:59:18 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4203742045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.4203742045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_out_trans_nak.3882490572 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 181675330 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:59:15 AM UTC 24 |
| Finished | Aug 21 07:59:18 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3882490572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3882490572 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_pending_in_trans.974479932 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 166118766 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:59:15 AM UTC 24 |
| Finished | Aug 21 07:59:18 AM UTC 24 |
| Peak memory | 216152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=974479932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.974479932 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_phy_config_pinflip.1168440612 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 208567237 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:59:15 AM UTC 24 |
| Finished | Aug 21 07:59:18 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1168440612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.1168440612 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_phy_config_usb_ref_disable.558345971 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 177196633 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:59:15 AM UTC 24 |
| Finished | Aug 21 07:59:18 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=558345971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.558345971 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_phy_pins_sense.2866901345 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 101964969 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 07:59:17 AM UTC 24 |
| Finished | Aug 21 07:59:19 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2866901345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2866901345 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_pkt_buffer.2469046855 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 16402205015 ps |
| CPU time | 51.28 seconds |
| Started | Aug 21 07:59:17 AM UTC 24 |
| Finished | Aug 21 08:00:10 AM UTC 24 |
| Peak memory | 228448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2469046855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2469046855 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_pkt_received.2595600096 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 199894273 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:59:17 AM UTC 24 |
| Finished | Aug 21 07:59:19 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2595600096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2595600096 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_pkt_sent.2027786647 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 162791344 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 07:59:17 AM UTC 24 |
| Finished | Aug 21 07:59:19 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2027786647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2027786647 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_random_length_in_transaction.2003390795 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 197034808 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:59:17 AM UTC 24 |
| Finished | Aug 21 07:59:20 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2003390795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.2003390795 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_random_length_out_transaction.3119990762 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 144356106 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:59:19 AM UTC 24 |
| Finished | Aug 21 07:59:21 AM UTC 24 |
| Peak memory | 216492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3119990762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.3119990762 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_rx_crc_err.3638403455 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 176875727 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:59:19 AM UTC 24 |
| Finished | Aug 21 07:59:21 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3638403455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3638403455 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_rx_full.1915786992 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 262154595 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 07:59:19 AM UTC 24 |
| Finished | Aug 21 07:59:22 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1915786992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_full.1915786992 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_setup_stage.3058022356 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 153658018 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 07:59:19 AM UTC 24 |
| Finished | Aug 21 07:59:21 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3058022356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3058022356 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_setup_trans_ignored.2607914900 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 178455645 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:59:19 AM UTC 24 |
| Finished | Aug 21 07:59:21 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2607914900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2607914900 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_smoke.1270596499 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 237278889 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 07:59:19 AM UTC 24 |
| Finished | Aug 21 07:59:22 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1270596499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1270596499 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_spurious_pids_ignored.2814729088 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 2317986139 ps |
| CPU time | 17.61 seconds |
| Started | Aug 21 07:59:19 AM UTC 24 |
| Finished | Aug 21 07:59:38 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2814729088 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.2814729088 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_stall_priority_over_nak.1760847462 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 194399168 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:59:19 AM UTC 24 |
| Finished | Aug 21 07:59:21 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1760847462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1760847462 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_stall_trans.2263631669 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 188870615 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 07:59:21 AM UTC 24 |
| Finished | Aug 21 07:59:23 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2263631669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2263631669 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_stream_len_max.2064055685 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 1360735234 ps |
| CPU time | 3.84 seconds |
| Started | Aug 21 07:59:21 AM UTC 24 |
| Finished | Aug 21 07:59:26 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2064055685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.2064055685 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_streaming_out.7465940 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 4075685073 ps |
| CPU time | 103.2 seconds |
| Started | Aug 21 07:59:21 AM UTC 24 |
| Finished | Aug 21 08:01:06 AM UTC 24 |
| Peak memory | 228672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=7465940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.7465940 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_timeout_missing_host_handshake.86895853 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 1523204739 ps |
| CPU time | 34.78 seconds |
| Started | Aug 21 07:59:09 AM UTC 24 |
| Finished | Aug 21 07:59:45 AM UTC 24 |
| Peak memory | 218056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=86895853 -assert nop ostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_h ost_handshake.86895853 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/25.usbdev_tx_rx_disruption.866377638 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 546936289 ps |
| CPU time | 1.79 seconds |
| Started | Aug 21 07:59:21 AM UTC 24 |
| Finished | Aug 21 07:59:24 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=866377638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.usbdev_tx_rx_disruption.866377638 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/25.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/250.usbdev_tx_rx_disruption.2349878127 |
| Short name | T3350 |
| Test name | |
| Test status | |
| Simulation time | 489961882 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:06:31 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2349878127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 250.usbdev_tx_rx_disruption.2349878127 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/250.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/251.usbdev_tx_rx_disruption.405254639 |
| Short name | T3343 |
| Test name | |
| Test status | |
| Simulation time | 617355009 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:06:32 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=405254639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 251.usbdev_tx_rx_disruption.405254639 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/251.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/252.usbdev_tx_rx_disruption.520633570 |
| Short name | T3339 |
| Test name | |
| Test status | |
| Simulation time | 498708679 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:06:32 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=520633570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 252.usbdev_tx_rx_disruption.520633570 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/252.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/253.usbdev_tx_rx_disruption.1314639886 |
| Short name | T3341 |
| Test name | |
| Test status | |
| Simulation time | 618282521 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:06:32 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1314639886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 253.usbdev_tx_rx_disruption.1314639886 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/253.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/254.usbdev_tx_rx_disruption.2153822936 |
| Short name | T3338 |
| Test name | |
| Test status | |
| Simulation time | 479972828 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:06:32 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2153822936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 254.usbdev_tx_rx_disruption.2153822936 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/254.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/255.usbdev_tx_rx_disruption.3809044367 |
| Short name | T3340 |
| Test name | |
| Test status | |
| Simulation time | 475695539 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:06:32 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3809044367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 255.usbdev_tx_rx_disruption.3809044367 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/255.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/256.usbdev_tx_rx_disruption.1673100398 |
| Short name | T3342 |
| Test name | |
| Test status | |
| Simulation time | 465090879 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:06:32 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1673100398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 256.usbdev_tx_rx_disruption.1673100398 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/256.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/257.usbdev_tx_rx_disruption.4185402779 |
| Short name | T3344 |
| Test name | |
| Test status | |
| Simulation time | 537806248 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:06:32 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4185402779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 257.usbdev_tx_rx_disruption.4185402779 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/257.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/258.usbdev_tx_rx_disruption.477787521 |
| Short name | T3346 |
| Test name | |
| Test status | |
| Simulation time | 611512865 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:06:32 AM UTC 24 |
| Finished | Aug 21 08:06:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=477787521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 258.usbdev_tx_rx_disruption.477787521 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/258.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/259.usbdev_tx_rx_disruption.2604123290 |
| Short name | T3353 |
| Test name | |
| Test status | |
| Simulation time | 452415360 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:06:34 AM UTC 24 |
| Finished | Aug 21 08:06:37 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2604123290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 259.usbdev_tx_rx_disruption.2604123290 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/259.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_alert_test.19363764 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 42098524 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 07:59:35 AM UTC 24 |
| Finished | Aug 21 07:59:37 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19363764 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.19363764 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_aon_wake_disconnect.2129269547 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 5984209150 ps |
| CPU time | 13.84 seconds |
| Started | Aug 21 07:59:21 AM UTC 24 |
| Finished | Aug 21 07:59:36 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2129269547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbd ev_aon_wake_disconnect.2129269547 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_aon_wake_reset.414816032 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 16138110074 ps |
| CPU time | 23.07 seconds |
| Started | Aug 21 07:59:21 AM UTC 24 |
| Finished | Aug 21 07:59:46 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=414816032 -assert nopostp roc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.414816032 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_aon_wake_resume.2787795387 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 23806322236 ps |
| CPU time | 43.35 seconds |
| Started | Aug 21 07:59:21 AM UTC 24 |
| Finished | Aug 21 08:00:06 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2787795387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbd ev_aon_wake_resume.2787795387 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_av_buffer.134282939 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 169246202 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:59:21 AM UTC 24 |
| Finished | Aug 21 07:59:24 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=134282939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.134282939 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_bitstuff_err.107860145 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 141135044 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 07:59:23 AM UTC 24 |
| Finished | Aug 21 07:59:25 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=107860145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.107860145 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_data_toggle_clear.1518484810 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 470209658 ps |
| CPU time | 2.83 seconds |
| Started | Aug 21 07:59:23 AM UTC 24 |
| Finished | Aug 21 07:59:27 AM UTC 24 |
| Peak memory | 218012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1518484810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.1518484810 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_device_address.3153017192 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 29046281051 ps |
| CPU time | 57.27 seconds |
| Started | Aug 21 07:59:23 AM UTC 24 |
| Finished | Aug 21 08:00:22 AM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3153017192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.3153017192 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_device_timeout.1500391727 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 592175207 ps |
| CPU time | 11.28 seconds |
| Started | Aug 21 07:59:23 AM UTC 24 |
| Finished | Aug 21 07:59:36 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1500391727 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.1500391727 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_disable_endpoint.850193322 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 429436587 ps |
| CPU time | 2.35 seconds |
| Started | Aug 21 07:59:23 AM UTC 24 |
| Finished | Aug 21 07:59:27 AM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=850193322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.850193322 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_disconnected.2482005640 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 143637054 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:59:24 AM UTC 24 |
| Finished | Aug 21 07:59:26 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2482005640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2482005640 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_enable.3334928026 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 45743007 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 07:59:24 AM UTC 24 |
| Finished | Aug 21 07:59:25 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3334928026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3334928026 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_endpoint_access.3742656920 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 857946180 ps |
| CPU time | 2.82 seconds |
| Started | Aug 21 07:59:25 AM UTC 24 |
| Finished | Aug 21 07:59:29 AM UTC 24 |
| Peak memory | 218160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3742656920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3742656920 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_endpoint_types.2355898064 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 430512660 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:59:25 AM UTC 24 |
| Finished | Aug 21 07:59:27 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2355898064 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_types.2355898064 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_fifo_rst.3511541984 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 196805649 ps |
| CPU time | 2.47 seconds |
| Started | Aug 21 07:59:25 AM UTC 24 |
| Finished | Aug 21 07:59:28 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3511541984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3511541984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_in_iso.2956227962 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 237015787 ps |
| CPU time | 1.92 seconds |
| Started | Aug 21 07:59:25 AM UTC 24 |
| Finished | Aug 21 07:59:28 AM UTC 24 |
| Peak memory | 226388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2956227962 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2956227962 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_in_stall.1494817344 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 148022796 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:59:25 AM UTC 24 |
| Finished | Aug 21 07:59:28 AM UTC 24 |
| Peak memory | 216072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1494817344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1494817344 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_in_trans.2716680436 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 193534058 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:59:25 AM UTC 24 |
| Finished | Aug 21 07:59:27 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2716680436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2716680436 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_invalid_sync.3104687248 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 4746337433 ps |
| CPU time | 126.64 seconds |
| Started | Aug 21 07:59:25 AM UTC 24 |
| Finished | Aug 21 08:01:34 AM UTC 24 |
| Peak memory | 228620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3104687248 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.3104687248 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_iso_retraction.3579918006 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 5718012247 ps |
| CPU time | 57.35 seconds |
| Started | Aug 21 07:59:25 AM UTC 24 |
| Finished | Aug 21 08:00:24 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3579918006 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.3579918006 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_link_in_err.3888237121 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 157564189 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:59:27 AM UTC 24 |
| Finished | Aug 21 07:59:29 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3888237121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3888237121 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_link_resume.3896307821 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 28785008020 ps |
| CPU time | 48.03 seconds |
| Started | Aug 21 07:59:27 AM UTC 24 |
| Finished | Aug 21 08:00:16 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3896307821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3896307821 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_link_suspend.3370928483 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 4763392421 ps |
| CPU time | 9.46 seconds |
| Started | Aug 21 07:59:27 AM UTC 24 |
| Finished | Aug 21 07:59:37 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3370928483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.3370928483 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_low_speed_traffic.3421243260 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 4804278239 ps |
| CPU time | 124.22 seconds |
| Started | Aug 21 07:59:27 AM UTC 24 |
| Finished | Aug 21 08:01:33 AM UTC 24 |
| Peak memory | 230356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3421243260 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.3421243260 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_max_inter_pkt_delay.1752336272 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 3179771845 ps |
| CPU time | 83.56 seconds |
| Started | Aug 21 07:59:27 AM UTC 24 |
| Finished | Aug 21 08:00:52 AM UTC 24 |
| Peak memory | 228612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1752336272 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1752336272 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_max_length_in_transaction.2994811317 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 255552611 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 07:59:28 AM UTC 24 |
| Finished | Aug 21 07:59:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2994811317 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.2994811317 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_max_length_out_transaction.751437194 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 209023360 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 07:59:28 AM UTC 24 |
| Finished | Aug 21 07:59:31 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=751437194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.751437194 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_min_inter_pkt_delay.3053042002 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 2666501919 ps |
| CPU time | 70.68 seconds |
| Started | Aug 21 07:59:29 AM UTC 24 |
| Finished | Aug 21 08:00:41 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3053042002 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.3053042002 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_min_length_in_transaction.3731265262 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 170047018 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 07:59:29 AM UTC 24 |
| Finished | Aug 21 07:59:31 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3731265262 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3731265262 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_min_length_out_transaction.4091947703 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 191269959 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:59:29 AM UTC 24 |
| Finished | Aug 21 07:59:31 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4091947703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.4091947703 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_out_iso.612734480 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 166868649 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 07:59:29 AM UTC 24 |
| Finished | Aug 21 07:59:31 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=612734480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.612734480 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_out_stall.2421222816 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 155839290 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 07:59:29 AM UTC 24 |
| Finished | Aug 21 07:59:31 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2421222816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2421222816 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_out_trans_nak.3510503913 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 160702362 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:59:30 AM UTC 24 |
| Finished | Aug 21 07:59:33 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3510503913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3510503913 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_pending_in_trans.1562159439 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 215757605 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:59:30 AM UTC 24 |
| Finished | Aug 21 07:59:33 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1562159439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1562159439 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_phy_config_pinflip.905188820 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 217102352 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 07:59:30 AM UTC 24 |
| Finished | Aug 21 07:59:32 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=905188820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.905188820 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_phy_config_usb_ref_disable.39111855 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 155157793 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 07:59:30 AM UTC 24 |
| Finished | Aug 21 07:59:32 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39111855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_ 2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.39111855 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_phy_pins_sense.4015630172 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 40013572 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 07:59:30 AM UTC 24 |
| Finished | Aug 21 07:59:32 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4015630172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.4015630172 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_pkt_buffer.342983767 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 19625731347 ps |
| CPU time | 55.38 seconds |
| Started | Aug 21 07:59:32 AM UTC 24 |
| Finished | Aug 21 08:00:29 AM UTC 24 |
| Peak memory | 228524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=342983767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.342983767 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_pkt_received.2981154137 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 151103922 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:59:32 AM UTC 24 |
| Finished | Aug 21 07:59:34 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2981154137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2981154137 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_pkt_sent.1372805215 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 187206089 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 07:59:32 AM UTC 24 |
| Finished | Aug 21 07:59:35 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1372805215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1372805215 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_random_length_in_transaction.991065036 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 178747763 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:59:32 AM UTC 24 |
| Finished | Aug 21 07:59:34 AM UTC 24 |
| Peak memory | 216544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=991065036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.991065036 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_random_length_out_transaction.2984342604 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 194882165 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:59:32 AM UTC 24 |
| Finished | Aug 21 07:59:35 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2984342604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.2984342604 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_rx_crc_err.2845196692 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 162999561 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 07:59:32 AM UTC 24 |
| Finished | Aug 21 07:59:35 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2845196692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.2845196692 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_rx_full.1747388444 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 386326286 ps |
| CPU time | 1.69 seconds |
| Started | Aug 21 07:59:32 AM UTC 24 |
| Finished | Aug 21 07:59:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1747388444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_full.1747388444 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_setup_stage.62574634 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 158468662 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:59:32 AM UTC 24 |
| Finished | Aug 21 07:59:34 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=62574634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.62574634 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_setup_trans_ignored.822938402 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 173043610 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 07:59:32 AM UTC 24 |
| Finished | Aug 21 07:59:36 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=822938402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.822938402 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_smoke.3665465209 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 255179596 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:59:32 AM UTC 24 |
| Finished | Aug 21 07:59:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3665465209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.3665465209 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_spurious_pids_ignored.1141132769 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 2100828115 ps |
| CPU time | 49.33 seconds |
| Started | Aug 21 07:59:32 AM UTC 24 |
| Finished | Aug 21 08:00:24 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1141132769 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1141132769 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_stall_priority_over_nak.320045333 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 222139376 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 07:59:34 AM UTC 24 |
| Finished | Aug 21 07:59:36 AM UTC 24 |
| Peak memory | 216084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=320045333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20 24_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.320045333 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_stall_trans.56588093 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 162226357 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 07:59:34 AM UTC 24 |
| Finished | Aug 21 07:59:36 AM UTC 24 |
| Peak memory | 216116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=56588093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.56588093 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_stream_len_max.4189820681 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 1260682337 ps |
| CPU time | 2.96 seconds |
| Started | Aug 21 07:59:34 AM UTC 24 |
| Finished | Aug 21 07:59:38 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4189820681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.4189820681 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_streaming_out.1700969867 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 2110086360 ps |
| CPU time | 14.11 seconds |
| Started | Aug 21 07:59:34 AM UTC 24 |
| Finished | Aug 21 07:59:49 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1700969867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.1700969867 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_timeout_missing_host_handshake.2589312703 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 1119846434 ps |
| CPU time | 22.6 seconds |
| Started | Aug 21 07:59:23 AM UTC 24 |
| Finished | Aug 21 07:59:47 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2589312703 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing _host_handshake.2589312703 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/26.usbdev_tx_rx_disruption.1662937859 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 564979790 ps |
| CPU time | 2.18 seconds |
| Started | Aug 21 07:59:34 AM UTC 24 |
| Finished | Aug 21 07:59:37 AM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1662937859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.usbdev_tx_rx_disruption.1662937859 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/26.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/260.usbdev_tx_rx_disruption.3009565130 |
| Short name | T3364 |
| Test name | |
| Test status | |
| Simulation time | 470010777 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3009565130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 260.usbdev_tx_rx_disruption.3009565130 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/260.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/261.usbdev_tx_rx_disruption.3877130045 |
| Short name | T3363 |
| Test name | |
| Test status | |
| Simulation time | 461672919 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:40 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3877130045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 261.usbdev_tx_rx_disruption.3877130045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/261.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/262.usbdev_tx_rx_disruption.4036206794 |
| Short name | T3369 |
| Test name | |
| Test status | |
| Simulation time | 547121965 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4036206794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 262.usbdev_tx_rx_disruption.4036206794 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/262.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/263.usbdev_tx_rx_disruption.2378837618 |
| Short name | T3368 |
| Test name | |
| Test status | |
| Simulation time | 474787709 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2378837618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 263.usbdev_tx_rx_disruption.2378837618 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/263.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/264.usbdev_tx_rx_disruption.994958691 |
| Short name | T3365 |
| Test name | |
| Test status | |
| Simulation time | 525615639 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:41 AM UTC 24 |
| Peak memory | 216372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=994958691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 264.usbdev_tx_rx_disruption.994958691 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/264.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/265.usbdev_tx_rx_disruption.2627744843 |
| Short name | T3366 |
| Test name | |
| Test status | |
| Simulation time | 493545559 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:41 AM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2627744843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 265.usbdev_tx_rx_disruption.2627744843 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/265.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/266.usbdev_tx_rx_disruption.12765367 |
| Short name | T3386 |
| Test name | |
| Test status | |
| Simulation time | 517013536 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=12765367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 266.usbdev_tx_rx_disruption.12765367 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/266.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/267.usbdev_tx_rx_disruption.1757813001 |
| Short name | T3367 |
| Test name | |
| Test status | |
| Simulation time | 500119743 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1757813001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 267.usbdev_tx_rx_disruption.1757813001 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/267.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/268.usbdev_tx_rx_disruption.3981220664 |
| Short name | T3361 |
| Test name | |
| Test status | |
| Simulation time | 612454133 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:40 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3981220664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 268.usbdev_tx_rx_disruption.3981220664 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/268.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/269.usbdev_tx_rx_disruption.2360102909 |
| Short name | T3387 |
| Test name | |
| Test status | |
| Simulation time | 489508925 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2360102909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 269.usbdev_tx_rx_disruption.2360102909 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/269.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_alert_test.2298041632 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 42344088 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 07:59:50 AM UTC 24 |
| Finished | Aug 21 07:59:52 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2298041632 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.2298041632 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_aon_wake_disconnect.3208750814 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 10819282303 ps |
| CPU time | 16.69 seconds |
| Started | Aug 21 07:59:35 AM UTC 24 |
| Finished | Aug 21 07:59:53 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3208750814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbd ev_aon_wake_disconnect.3208750814 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_aon_wake_reset.1129278013 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 14880703588 ps |
| CPU time | 21.3 seconds |
| Started | Aug 21 07:59:35 AM UTC 24 |
| Finished | Aug 21 07:59:58 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1129278013 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.1129278013 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_aon_wake_resume.24965912 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 30598681458 ps |
| CPU time | 48.77 seconds |
| Started | Aug 21 07:59:35 AM UTC 24 |
| Finished | Aug 21 08:00:25 AM UTC 24 |
| Peak memory | 218252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=24965912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev _aon_wake_resume.24965912 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_av_buffer.4226489368 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 173988797 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 07:59:37 AM UTC 24 |
| Finished | Aug 21 07:59:39 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4226489368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.4226489368 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_bitstuff_err.240515803 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 136061051 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 07:59:37 AM UTC 24 |
| Finished | Aug 21 07:59:39 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=240515803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.240515803 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_data_toggle_clear.3316180666 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 207540239 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 07:59:37 AM UTC 24 |
| Finished | Aug 21 07:59:40 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3316180666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.3316180666 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_data_toggle_restore.291849413 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 1198746562 ps |
| CPU time | 4.53 seconds |
| Started | Aug 21 07:59:37 AM UTC 24 |
| Finished | Aug 21 07:59:43 AM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=291849413 -assert nopostproc +UVM_TESTNAME=us bdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.291849413 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_device_address.3274292073 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 17426730360 ps |
| CPU time | 32.52 seconds |
| Started | Aug 21 07:59:37 AM UTC 24 |
| Finished | Aug 21 08:00:11 AM UTC 24 |
| Peak memory | 218444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3274292073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.3274292073 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_device_timeout.140282934 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 1003326236 ps |
| CPU time | 21.6 seconds |
| Started | Aug 21 07:59:37 AM UTC 24 |
| Finished | Aug 21 08:00:00 AM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=140282934 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.140282934 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_disable_endpoint.641209683 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 851933459 ps |
| CPU time | 2.97 seconds |
| Started | Aug 21 07:59:37 AM UTC 24 |
| Finished | Aug 21 07:59:41 AM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=641209683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.641209683 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_disconnected.2360859007 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 161217940 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:59:37 AM UTC 24 |
| Finished | Aug 21 07:59:40 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2360859007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.2360859007 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_enable.2428623228 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 49017276 ps |
| CPU time | 0.85 seconds |
| Started | Aug 21 07:59:37 AM UTC 24 |
| Finished | Aug 21 07:59:39 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2428623228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2428623228 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_endpoint_access.2347935751 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 959221855 ps |
| CPU time | 3.68 seconds |
| Started | Aug 21 07:59:37 AM UTC 24 |
| Finished | Aug 21 07:59:42 AM UTC 24 |
| Peak memory | 218352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2347935751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.2347935751 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_endpoint_types.1419105275 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 278468624 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 07:59:39 AM UTC 24 |
| Finished | Aug 21 07:59:41 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1419105275 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_types.1419105275 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_fifo_rst.3271698650 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 179544230 ps |
| CPU time | 2.23 seconds |
| Started | Aug 21 07:59:39 AM UTC 24 |
| Finished | Aug 21 07:59:42 AM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3271698650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3271698650 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_in_iso.3097308833 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 220727628 ps |
| CPU time | 1.9 seconds |
| Started | Aug 21 07:59:39 AM UTC 24 |
| Finished | Aug 21 07:59:42 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3097308833 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3097308833 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_in_stall.141727632 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 142294669 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:59:39 AM UTC 24 |
| Finished | Aug 21 07:59:41 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=141727632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.141727632 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_in_trans.3064167955 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 224245311 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 07:59:39 AM UTC 24 |
| Finished | Aug 21 07:59:42 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3064167955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3064167955 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_invalid_sync.4257829765 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 4875627449 ps |
| CPU time | 33.2 seconds |
| Started | Aug 21 07:59:39 AM UTC 24 |
| Finished | Aug 21 08:00:13 AM UTC 24 |
| Peak memory | 235180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4257829765 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.4257829765 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_iso_retraction.330920540 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 8529144864 ps |
| CPU time | 98.17 seconds |
| Started | Aug 21 07:59:39 AM UTC 24 |
| Finished | Aug 21 08:01:19 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=330920540 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.330920540 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_link_in_err.557212763 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 234651641 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 07:59:40 AM UTC 24 |
| Finished | Aug 21 07:59:43 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=557212763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.557212763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_link_resume.1339447503 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 30175009388 ps |
| CPU time | 50.72 seconds |
| Started | Aug 21 07:59:40 AM UTC 24 |
| Finished | Aug 21 08:00:33 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1339447503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.1339447503 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_link_suspend.1019202605 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 4978212903 ps |
| CPU time | 12.05 seconds |
| Started | Aug 21 07:59:41 AM UTC 24 |
| Finished | Aug 21 07:59:54 AM UTC 24 |
| Peak memory | 218364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1019202605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1019202605 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_low_speed_traffic.3882044886 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 4209433751 ps |
| CPU time | 40.86 seconds |
| Started | Aug 21 07:59:41 AM UTC 24 |
| Finished | Aug 21 08:00:23 AM UTC 24 |
| Peak memory | 230724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3882044886 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3882044886 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_max_inter_pkt_delay.2334200655 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 3989963309 ps |
| CPU time | 103.41 seconds |
| Started | Aug 21 07:59:41 AM UTC 24 |
| Finished | Aug 21 08:01:26 AM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2334200655 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.2334200655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_max_length_in_transaction.4130221150 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 258576153 ps |
| CPU time | 1.74 seconds |
| Started | Aug 21 07:59:41 AM UTC 24 |
| Finished | Aug 21 07:59:43 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4130221150 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.4130221150 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_max_length_out_transaction.940210492 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 197999264 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 07:59:42 AM UTC 24 |
| Finished | Aug 21 07:59:45 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=940210492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.940210492 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_min_inter_pkt_delay.3362391880 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 3713453684 ps |
| CPU time | 94.29 seconds |
| Started | Aug 21 07:59:42 AM UTC 24 |
| Finished | Aug 21 08:01:19 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3362391880 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.3362391880 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_min_length_in_transaction.4007613006 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 174714844 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:59:43 AM UTC 24 |
| Finished | Aug 21 07:59:45 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4007613006 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.4007613006 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_min_length_out_transaction.3843002109 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 146427929 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:59:43 AM UTC 24 |
| Finished | Aug 21 07:59:45 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3843002109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3843002109 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_nak_trans.3732096865 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 209711478 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 07:59:43 AM UTC 24 |
| Finished | Aug 21 07:59:45 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3732096865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3732096865 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_out_iso.2972776078 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 232817204 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 07:59:43 AM UTC 24 |
| Finished | Aug 21 07:59:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2972776078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.2972776078 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_out_stall.2630594420 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 186194325 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:59:44 AM UTC 24 |
| Finished | Aug 21 07:59:47 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2630594420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2630594420 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_out_trans_nak.678411648 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 167267440 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 07:59:44 AM UTC 24 |
| Finished | Aug 21 07:59:46 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=678411648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.678411648 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_pending_in_trans.896032054 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 157068023 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:59:44 AM UTC 24 |
| Finished | Aug 21 07:59:47 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=896032054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.896032054 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_phy_config_pinflip.1928603545 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 274607540 ps |
| CPU time | 1.94 seconds |
| Started | Aug 21 07:59:44 AM UTC 24 |
| Finished | Aug 21 07:59:47 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1928603545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.1928603545 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_phy_config_usb_ref_disable.3549967605 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 150157917 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:59:44 AM UTC 24 |
| Finished | Aug 21 07:59:47 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3549967605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3549967605 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_phy_pins_sense.1052969141 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 47721611 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 07:59:44 AM UTC 24 |
| Finished | Aug 21 07:59:46 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1052969141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1052969141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_pkt_buffer.433375083 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 12188623698 ps |
| CPU time | 28.89 seconds |
| Started | Aug 21 07:59:45 AM UTC 24 |
| Finished | Aug 21 08:00:15 AM UTC 24 |
| Peak memory | 228584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=433375083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.433375083 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_pkt_received.2900181012 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 152269499 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:59:46 AM UTC 24 |
| Finished | Aug 21 07:59:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2900181012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2900181012 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_pkt_sent.3663604124 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 196828007 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 07:59:46 AM UTC 24 |
| Finished | Aug 21 07:59:49 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3663604124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3663604124 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_random_length_in_transaction.2586537178 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 246154379 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 07:59:46 AM UTC 24 |
| Finished | Aug 21 07:59:49 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2586537178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.2586537178 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_random_length_out_transaction.172573197 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 198363305 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:59:46 AM UTC 24 |
| Finished | Aug 21 07:59:49 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=172573197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.172573197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_rx_crc_err.1260311784 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 150304147 ps |
| CPU time | 0.87 seconds |
| Started | Aug 21 07:59:46 AM UTC 24 |
| Finished | Aug 21 07:59:48 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1260311784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1260311784 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_rx_full.887657524 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 252362542 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 07:59:46 AM UTC 24 |
| Finished | Aug 21 07:59:49 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=887657524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_full.887657524 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_setup_stage.1308681874 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 159790919 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:59:46 AM UTC 24 |
| Finished | Aug 21 07:59:49 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1308681874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1308681874 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_setup_trans_ignored.1133888943 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 151426737 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 07:59:46 AM UTC 24 |
| Finished | Aug 21 07:59:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1133888943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1133888943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_smoke.667984980 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 352320662 ps |
| CPU time | 1.9 seconds |
| Started | Aug 21 07:59:48 AM UTC 24 |
| Finished | Aug 21 07:59:51 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=667984980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.667984980 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_spurious_pids_ignored.2321263357 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 3150127163 ps |
| CPU time | 79.92 seconds |
| Started | Aug 21 07:59:48 AM UTC 24 |
| Finished | Aug 21 08:01:10 AM UTC 24 |
| Peak memory | 228492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2321263357 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2321263357 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_stall_priority_over_nak.2530475421 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 223940649 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 07:59:48 AM UTC 24 |
| Finished | Aug 21 07:59:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2530475421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2530475421 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_stall_trans.3208699506 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 217553278 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 07:59:48 AM UTC 24 |
| Finished | Aug 21 07:59:51 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3208699506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3208699506 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_stream_len_max.380812531 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 318687512 ps |
| CPU time | 1.95 seconds |
| Started | Aug 21 07:59:48 AM UTC 24 |
| Finished | Aug 21 07:59:51 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=380812531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.380812531 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_streaming_out.1967548130 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 3298404872 ps |
| CPU time | 34.42 seconds |
| Started | Aug 21 07:59:48 AM UTC 24 |
| Finished | Aug 21 08:00:24 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1967548130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1967548130 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_timeout_missing_host_handshake.21937149 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 3902820199 ps |
| CPU time | 31.36 seconds |
| Started | Aug 21 07:59:37 AM UTC 24 |
| Finished | Aug 21 08:00:10 AM UTC 24 |
| Peak memory | 218376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=21937149 -assert nop ostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_h ost_handshake.21937149 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/27.usbdev_tx_rx_disruption.659948021 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 501244186 ps |
| CPU time | 2.61 seconds |
| Started | Aug 21 07:59:48 AM UTC 24 |
| Finished | Aug 21 07:59:52 AM UTC 24 |
| Peak memory | 218004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=659948021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.usbdev_tx_rx_disruption.659948021 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/27.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/270.usbdev_tx_rx_disruption.1561647213 |
| Short name | T3391 |
| Test name | |
| Test status | |
| Simulation time | 514426172 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1561647213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 270.usbdev_tx_rx_disruption.1561647213 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/270.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/271.usbdev_tx_rx_disruption.1487619131 |
| Short name | T3370 |
| Test name | |
| Test status | |
| Simulation time | 593175811 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1487619131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 271.usbdev_tx_rx_disruption.1487619131 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/271.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/272.usbdev_tx_rx_disruption.3762174666 |
| Short name | T3362 |
| Test name | |
| Test status | |
| Simulation time | 714465253 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:40 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3762174666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 272.usbdev_tx_rx_disruption.3762174666 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/272.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/273.usbdev_tx_rx_disruption.1646728160 |
| Short name | T3371 |
| Test name | |
| Test status | |
| Simulation time | 542642415 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:06:37 AM UTC 24 |
| Finished | Aug 21 08:06:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1646728160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 273.usbdev_tx_rx_disruption.1646728160 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/273.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/274.usbdev_tx_rx_disruption.798402676 |
| Short name | T3400 |
| Test name | |
| Test status | |
| Simulation time | 503937708 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:06:39 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=798402676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 274.usbdev_tx_rx_disruption.798402676 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/274.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/275.usbdev_tx_rx_disruption.3373615243 |
| Short name | T3410 |
| Test name | |
| Test status | |
| Simulation time | 626443449 ps |
| CPU time | 1.79 seconds |
| Started | Aug 21 08:06:39 AM UTC 24 |
| Finished | Aug 21 08:06:49 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3373615243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 275.usbdev_tx_rx_disruption.3373615243 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/275.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/276.usbdev_tx_rx_disruption.469944120 |
| Short name | T3412 |
| Test name | |
| Test status | |
| Simulation time | 543374460 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 08:06:39 AM UTC 24 |
| Finished | Aug 21 08:06:49 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=469944120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 276.usbdev_tx_rx_disruption.469944120 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/276.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/277.usbdev_tx_rx_disruption.2978644652 |
| Short name | T3402 |
| Test name | |
| Test status | |
| Simulation time | 504746132 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:06:39 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2978644652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 277.usbdev_tx_rx_disruption.2978644652 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/277.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/278.usbdev_tx_rx_disruption.1847375478 |
| Short name | T3406 |
| Test name | |
| Test status | |
| Simulation time | 425855803 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:06:39 AM UTC 24 |
| Finished | Aug 21 08:06:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1847375478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 278.usbdev_tx_rx_disruption.1847375478 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/278.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/279.usbdev_tx_rx_disruption.2644366208 |
| Short name | T3425 |
| Test name | |
| Test status | |
| Simulation time | 430272298 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:06:39 AM UTC 24 |
| Finished | Aug 21 08:06:55 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2644366208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 279.usbdev_tx_rx_disruption.2644366208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/279.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_alert_test.2871878738 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 32790321 ps |
| CPU time | 0.89 seconds |
| Started | Aug 21 08:00:08 AM UTC 24 |
| Finished | Aug 21 08:00:10 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2871878738 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.2871878738 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_aon_wake_disconnect.1273062921 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 8813494339 ps |
| CPU time | 16.7 seconds |
| Started | Aug 21 07:59:50 AM UTC 24 |
| Finished | Aug 21 08:00:08 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1273062921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbd ev_aon_wake_disconnect.1273062921 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_aon_wake_reset.3996594162 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 19633465931 ps |
| CPU time | 24.92 seconds |
| Started | Aug 21 07:59:50 AM UTC 24 |
| Finished | Aug 21 08:00:16 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3996594162 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.3996594162 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_aon_wake_resume.202805234 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 24830508754 ps |
| CPU time | 38.7 seconds |
| Started | Aug 21 07:59:50 AM UTC 24 |
| Finished | Aug 21 08:00:30 AM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=202805234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbde v_aon_wake_resume.202805234 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_av_buffer.1904084435 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 201107031 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 07:59:50 AM UTC 24 |
| Finished | Aug 21 07:59:53 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1904084435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1904084435 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_bitstuff_err.3820073920 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 186230553 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 07:59:50 AM UTC 24 |
| Finished | Aug 21 07:59:52 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3820073920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3820073920 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_data_toggle_clear.3480454787 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 257750998 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 07:59:50 AM UTC 24 |
| Finished | Aug 21 07:59:53 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3480454787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.3480454787 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_data_toggle_restore.3733648173 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 809911144 ps |
| CPU time | 2.66 seconds |
| Started | Aug 21 07:59:50 AM UTC 24 |
| Finished | Aug 21 07:59:54 AM UTC 24 |
| Peak memory | 218136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3733648173 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.3733648173 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_device_address.180437317 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 29196136591 ps |
| CPU time | 53.32 seconds |
| Started | Aug 21 07:59:50 AM UTC 24 |
| Finished | Aug 21 08:00:45 AM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=180437317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.180437317 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_device_timeout.3717693696 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 461837145 ps |
| CPU time | 7.84 seconds |
| Started | Aug 21 07:59:52 AM UTC 24 |
| Finished | Aug 21 08:00:00 AM UTC 24 |
| Peak memory | 217944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3717693696 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.3717693696 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_disable_endpoint.2836363095 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 1097177817 ps |
| CPU time | 2.56 seconds |
| Started | Aug 21 07:59:52 AM UTC 24 |
| Finished | Aug 21 07:59:55 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2836363095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.2836363095 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_disconnected.1103233099 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 192319907 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:59:52 AM UTC 24 |
| Finished | Aug 21 07:59:54 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1103233099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1103233099 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_enable.2048127219 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 38951213 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 07:59:52 AM UTC 24 |
| Finished | Aug 21 07:59:54 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2048127219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2048127219 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_endpoint_access.109020079 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 813741153 ps |
| CPU time | 3.62 seconds |
| Started | Aug 21 07:59:54 AM UTC 24 |
| Finished | Aug 21 07:59:58 AM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=109020079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.109020079 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_endpoint_types.1207522954 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 565930969 ps |
| CPU time | 2.54 seconds |
| Started | Aug 21 07:59:54 AM UTC 24 |
| Finished | Aug 21 07:59:57 AM UTC 24 |
| Peak memory | 218104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1207522954 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_types.1207522954 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_fifo_rst.2228693534 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 223120885 ps |
| CPU time | 1.83 seconds |
| Started | Aug 21 07:59:54 AM UTC 24 |
| Finished | Aug 21 07:59:57 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2228693534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2228693534 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_in_iso.3580881030 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 210571875 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:59:54 AM UTC 24 |
| Finished | Aug 21 07:59:56 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3580881030 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3580881030 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_in_stall.2056074322 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 153917513 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:59:54 AM UTC 24 |
| Finished | Aug 21 07:59:56 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2056074322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2056074322 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_in_trans.119972246 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 189747494 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:59:54 AM UTC 24 |
| Finished | Aug 21 07:59:56 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=119972246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.119972246 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_invalid_sync.285712328 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 5039316300 ps |
| CPU time | 130.7 seconds |
| Started | Aug 21 07:59:54 AM UTC 24 |
| Finished | Aug 21 08:02:07 AM UTC 24 |
| Peak memory | 230724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=285712328 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.285712328 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_iso_retraction.496583834 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 9653594242 ps |
| CPU time | 64.1 seconds |
| Started | Aug 21 07:59:54 AM UTC 24 |
| Finished | Aug 21 08:01:00 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=496583834 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.496583834 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_link_in_err.1546753300 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 197716429 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:59:55 AM UTC 24 |
| Finished | Aug 21 07:59:58 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1546753300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.1546753300 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_link_resume.2359019251 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 11232036812 ps |
| CPU time | 16.07 seconds |
| Started | Aug 21 07:59:56 AM UTC 24 |
| Finished | Aug 21 08:00:13 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2359019251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.2359019251 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_link_suspend.1185268947 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 9624786163 ps |
| CPU time | 14.78 seconds |
| Started | Aug 21 07:59:56 AM UTC 24 |
| Finished | Aug 21 08:00:11 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1185268947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1185268947 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_low_speed_traffic.2674048244 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 2920514770 ps |
| CPU time | 72.32 seconds |
| Started | Aug 21 07:59:56 AM UTC 24 |
| Finished | Aug 21 08:01:10 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2674048244 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.2674048244 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_max_inter_pkt_delay.3071964430 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 2475329259 ps |
| CPU time | 20.43 seconds |
| Started | Aug 21 07:59:56 AM UTC 24 |
| Finished | Aug 21 08:00:17 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3071964430 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3071964430 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_max_length_in_transaction.3182260593 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 277397145 ps |
| CPU time | 1.71 seconds |
| Started | Aug 21 07:59:56 AM UTC 24 |
| Finished | Aug 21 07:59:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3182260593 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.3182260593 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_max_length_out_transaction.3501029312 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 212960994 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 07:59:57 AM UTC 24 |
| Finished | Aug 21 08:00:00 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3501029312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3501029312 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_min_inter_pkt_delay.3613040191 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 2005114480 ps |
| CPU time | 51.93 seconds |
| Started | Aug 21 07:59:57 AM UTC 24 |
| Finished | Aug 21 08:00:50 AM UTC 24 |
| Peak memory | 228352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3613040191 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.3613040191 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_min_length_in_transaction.3046550808 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 162982331 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:59:57 AM UTC 24 |
| Finished | Aug 21 07:59:59 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3046550808 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.3046550808 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_min_length_out_transaction.2202663429 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 156298268 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:59:57 AM UTC 24 |
| Finished | Aug 21 08:00:00 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2202663429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2202663429 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_nak_trans.2304934172 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 226206123 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 07:59:58 AM UTC 24 |
| Finished | Aug 21 08:00:01 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2304934172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2304934172 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_out_iso.3196350099 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 194435148 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 07:59:58 AM UTC 24 |
| Finished | Aug 21 08:00:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3196350099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3196350099 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_out_stall.2185806355 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 177625499 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:59:58 AM UTC 24 |
| Finished | Aug 21 08:00:01 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2185806355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2185806355 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_out_trans_nak.984139119 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 188355945 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 07:59:59 AM UTC 24 |
| Finished | Aug 21 08:00:01 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=984139119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.984139119 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_pending_in_trans.2204903522 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 196657559 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 08:00:00 AM UTC 24 |
| Finished | Aug 21 08:00:02 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2204903522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2204903522 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_phy_config_pinflip.3476392946 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 238593188 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:00:00 AM UTC 24 |
| Finished | Aug 21 08:00:03 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3476392946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3476392946 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_phy_config_usb_ref_disable.1164206223 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 146682178 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 08:00:00 AM UTC 24 |
| Finished | Aug 21 08:00:02 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1164206223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1164206223 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_phy_pins_sense.680210315 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 35827191 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 08:00:01 AM UTC 24 |
| Finished | Aug 21 08:00:07 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=680210315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.680210315 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_pkt_buffer.4101248852 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 7970565545 ps |
| CPU time | 21.52 seconds |
| Started | Aug 21 08:00:01 AM UTC 24 |
| Finished | Aug 21 08:00:28 AM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4101248852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.4101248852 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_pkt_received.331791021 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 159491982 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:00:01 AM UTC 24 |
| Finished | Aug 21 08:00:08 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=331791021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.331791021 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_pkt_sent.478419530 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 195246637 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:00:01 AM UTC 24 |
| Finished | Aug 21 08:00:08 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=478419530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.478419530 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_random_length_in_transaction.1878832890 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 250698102 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 08:00:01 AM UTC 24 |
| Finished | Aug 21 08:00:08 AM UTC 24 |
| Peak memory | 215964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1878832890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1878832890 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_random_length_out_transaction.525596682 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 164941125 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:00:02 AM UTC 24 |
| Finished | Aug 21 08:00:08 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=525596682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.525596682 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_rx_crc_err.3438535585 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 178887948 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:00:02 AM UTC 24 |
| Finished | Aug 21 08:00:07 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3438535585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3438535585 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_rx_full.1897855367 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 260089840 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:00:03 AM UTC 24 |
| Finished | Aug 21 08:00:08 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1897855367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_full.1897855367 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_setup_stage.3799011708 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 168091537 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:00:03 AM UTC 24 |
| Finished | Aug 21 08:00:08 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3799011708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.3799011708 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_setup_trans_ignored.1936773821 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 159461819 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:00:03 AM UTC 24 |
| Finished | Aug 21 08:00:08 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1936773821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1936773821 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_smoke.1761526816 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 276451693 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:00:06 AM UTC 24 |
| Finished | Aug 21 08:00:09 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1761526816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1761526816 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_spurious_pids_ignored.2445210071 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 3693302639 ps |
| CPU time | 27.74 seconds |
| Started | Aug 21 08:00:06 AM UTC 24 |
| Finished | Aug 21 08:00:36 AM UTC 24 |
| Peak memory | 228492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2445210071 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.2445210071 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_stall_priority_over_nak.2661927952 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 143778021 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:00:07 AM UTC 24 |
| Finished | Aug 21 08:00:09 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2661927952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2661927952 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_stall_trans.1506730130 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 174700147 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 08:00:07 AM UTC 24 |
| Finished | Aug 21 08:00:09 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1506730130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1506730130 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_stream_len_max.2470654705 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 283251547 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 08:00:08 AM UTC 24 |
| Finished | Aug 21 08:00:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2470654705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.2470654705 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_streaming_out.283156803 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 2071850720 ps |
| CPU time | 51.68 seconds |
| Started | Aug 21 08:00:07 AM UTC 24 |
| Finished | Aug 21 08:01:00 AM UTC 24 |
| Peak memory | 228292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=283156803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.283156803 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_timeout_missing_host_handshake.1543446656 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 436964712 ps |
| CPU time | 7.53 seconds |
| Started | Aug 21 07:59:52 AM UTC 24 |
| Finished | Aug 21 08:00:00 AM UTC 24 |
| Peak memory | 217868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1543446656 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing _host_handshake.1543446656 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/28.usbdev_tx_rx_disruption.1463957614 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 479005638 ps |
| CPU time | 1.81 seconds |
| Started | Aug 21 08:00:08 AM UTC 24 |
| Finished | Aug 21 08:00:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1463957614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.usbdev_tx_rx_disruption.1463957614 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/28.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/280.usbdev_tx_rx_disruption.4173348470 |
| Short name | T3430 |
| Test name | |
| Test status | |
| Simulation time | 604371827 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:06:39 AM UTC 24 |
| Finished | Aug 21 08:06:56 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4173348470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 280.usbdev_tx_rx_disruption.4173348470 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/280.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/282.usbdev_tx_rx_disruption.3737886183 |
| Short name | T3469 |
| Test name | |
| Test status | |
| Simulation time | 513963335 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:06:40 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3737886183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 282.usbdev_tx_rx_disruption.3737886183 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/282.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/283.usbdev_tx_rx_disruption.3298528524 |
| Short name | T3377 |
| Test name | |
| Test status | |
| Simulation time | 544751193 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:06:41 AM UTC 24 |
| Finished | Aug 21 08:06:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3298528524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 283.usbdev_tx_rx_disruption.3298528524 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/283.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/284.usbdev_tx_rx_disruption.1533684133 |
| Short name | T3379 |
| Test name | |
| Test status | |
| Simulation time | 490891982 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:06:41 AM UTC 24 |
| Finished | Aug 21 08:06:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1533684133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 284.usbdev_tx_rx_disruption.1533684133 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/284.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/285.usbdev_tx_rx_disruption.3456767172 |
| Short name | T3376 |
| Test name | |
| Test status | |
| Simulation time | 472653400 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:06:41 AM UTC 24 |
| Finished | Aug 21 08:06:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3456767172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 285.usbdev_tx_rx_disruption.3456767172 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/285.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/286.usbdev_tx_rx_disruption.118911919 |
| Short name | T3380 |
| Test name | |
| Test status | |
| Simulation time | 513212842 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:06:41 AM UTC 24 |
| Finished | Aug 21 08:06:47 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=118911919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 286.usbdev_tx_rx_disruption.118911919 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/286.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/287.usbdev_tx_rx_disruption.330057023 |
| Short name | T3381 |
| Test name | |
| Test status | |
| Simulation time | 586741291 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:06:41 AM UTC 24 |
| Finished | Aug 21 08:06:47 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=330057023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 287.usbdev_tx_rx_disruption.330057023 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/287.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/288.usbdev_tx_rx_disruption.2499931393 |
| Short name | T3378 |
| Test name | |
| Test status | |
| Simulation time | 630305596 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:06:41 AM UTC 24 |
| Finished | Aug 21 08:06:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2499931393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 288.usbdev_tx_rx_disruption.2499931393 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/288.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/289.usbdev_tx_rx_disruption.2082408695 |
| Short name | T3384 |
| Test name | |
| Test status | |
| Simulation time | 635762114 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:06:41 AM UTC 24 |
| Finished | Aug 21 08:06:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2082408695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 289.usbdev_tx_rx_disruption.2082408695 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/289.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_alert_test.195436240 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 50755331 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 08:00:22 AM UTC 24 |
| Finished | Aug 21 08:00:24 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=195436240 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.195436240 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_aon_wake_disconnect.1123691290 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 4755599588 ps |
| CPU time | 8.95 seconds |
| Started | Aug 21 08:00:10 AM UTC 24 |
| Finished | Aug 21 08:00:20 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1123691290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbd ev_aon_wake_disconnect.1123691290 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_aon_wake_reset.4111813925 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 18429171438 ps |
| CPU time | 31.55 seconds |
| Started | Aug 21 08:00:10 AM UTC 24 |
| Finished | Aug 21 08:00:43 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4111813925 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.4111813925 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_aon_wake_resume.2522537453 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 23615191135 ps |
| CPU time | 30.59 seconds |
| Started | Aug 21 08:00:10 AM UTC 24 |
| Finished | Aug 21 08:00:42 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2522537453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbd ev_aon_wake_resume.2522537453 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_av_buffer.3167882279 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 153912809 ps |
| CPU time | 0.96 seconds |
| Started | Aug 21 08:00:10 AM UTC 24 |
| Finished | Aug 21 08:00:12 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3167882279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3167882279 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_bitstuff_err.1407329023 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 159719747 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:00:10 AM UTC 24 |
| Finished | Aug 21 08:00:12 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1407329023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1407329023 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_data_toggle_clear.4123310575 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 221270546 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:00:10 AM UTC 24 |
| Finished | Aug 21 08:00:12 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4123310575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.4123310575 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_data_toggle_restore.4146535111 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 1221546829 ps |
| CPU time | 3.36 seconds |
| Started | Aug 21 08:00:10 AM UTC 24 |
| Finished | Aug 21 08:00:14 AM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4146535111 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.4146535111 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_device_address.3581802078 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 38106171684 ps |
| CPU time | 72.55 seconds |
| Started | Aug 21 08:00:10 AM UTC 24 |
| Finished | Aug 21 08:01:24 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3581802078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3581802078 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_device_timeout.2331721163 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 5727692006 ps |
| CPU time | 37.73 seconds |
| Started | Aug 21 08:00:10 AM UTC 24 |
| Finished | Aug 21 08:00:49 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2331721163 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.2331721163 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_disable_endpoint.3766916602 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 769628317 ps |
| CPU time | 3.21 seconds |
| Started | Aug 21 08:00:10 AM UTC 24 |
| Finished | Aug 21 08:00:14 AM UTC 24 |
| Peak memory | 217972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3766916602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.3766916602 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_disconnected.1403376942 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 146044412 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 08:00:12 AM UTC 24 |
| Finished | Aug 21 08:00:14 AM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1403376942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1403376942 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_enable.2097319821 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 47060583 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 08:00:12 AM UTC 24 |
| Finished | Aug 21 08:00:14 AM UTC 24 |
| Peak memory | 216068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2097319821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2097319821 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_endpoint_access.2402834207 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 1047663090 ps |
| CPU time | 4.1 seconds |
| Started | Aug 21 08:00:12 AM UTC 24 |
| Finished | Aug 21 08:00:17 AM UTC 24 |
| Peak memory | 218136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2402834207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.2402834207 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_endpoint_types.2653019195 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 561808548 ps |
| CPU time | 2.2 seconds |
| Started | Aug 21 08:00:12 AM UTC 24 |
| Finished | Aug 21 08:00:16 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2653019195 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_types.2653019195 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_fifo_rst.1358924911 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 177591816 ps |
| CPU time | 2.83 seconds |
| Started | Aug 21 08:00:12 AM UTC 24 |
| Finished | Aug 21 08:00:16 AM UTC 24 |
| Peak memory | 218048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1358924911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1358924911 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_in_iso.3961657104 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 236644709 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:00:12 AM UTC 24 |
| Finished | Aug 21 08:00:15 AM UTC 24 |
| Peak memory | 226696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3961657104 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3961657104 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_in_stall.2505262695 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 156873850 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:00:12 AM UTC 24 |
| Finished | Aug 21 08:00:15 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2505262695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2505262695 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_in_trans.2558752192 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 239652020 ps |
| CPU time | 1.69 seconds |
| Started | Aug 21 08:00:13 AM UTC 24 |
| Finished | Aug 21 08:00:15 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2558752192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2558752192 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_invalid_sync.3483344713 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 5420097269 ps |
| CPU time | 39.37 seconds |
| Started | Aug 21 08:00:12 AM UTC 24 |
| Finished | Aug 21 08:00:53 AM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3483344713 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.3483344713 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_iso_retraction.1733815956 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 8207317547 ps |
| CPU time | 54.66 seconds |
| Started | Aug 21 08:00:13 AM UTC 24 |
| Finished | Aug 21 08:01:09 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1733815956 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.1733815956 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_link_in_err.2851527345 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 154819601 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:00:13 AM UTC 24 |
| Finished | Aug 21 08:00:15 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2851527345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2851527345 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_link_resume.4234312166 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 13747599497 ps |
| CPU time | 21.81 seconds |
| Started | Aug 21 08:00:14 AM UTC 24 |
| Finished | Aug 21 08:00:37 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4234312166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.4234312166 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_link_suspend.3726595071 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 3655509724 ps |
| CPU time | 7.67 seconds |
| Started | Aug 21 08:00:14 AM UTC 24 |
| Finished | Aug 21 08:00:23 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3726595071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3726595071 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_low_speed_traffic.1737561782 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 4759180662 ps |
| CPU time | 123.61 seconds |
| Started | Aug 21 08:00:14 AM UTC 24 |
| Finished | Aug 21 08:02:20 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1737561782 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.1737561782 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_max_inter_pkt_delay.3181747859 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 2396777609 ps |
| CPU time | 61.43 seconds |
| Started | Aug 21 08:00:16 AM UTC 24 |
| Finished | Aug 21 08:01:19 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3181747859 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.3181747859 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_max_length_in_transaction.2241511748 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 277097804 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:00:16 AM UTC 24 |
| Finished | Aug 21 08:00:18 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2241511748 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.2241511748 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_max_length_out_transaction.764759744 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 249686305 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:00:16 AM UTC 24 |
| Finished | Aug 21 08:00:18 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=764759744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.764759744 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_min_inter_pkt_delay.873596323 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 2631399486 ps |
| CPU time | 66.79 seconds |
| Started | Aug 21 08:00:16 AM UTC 24 |
| Finished | Aug 21 08:01:24 AM UTC 24 |
| Peak memory | 228616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=873596323 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.873596323 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_min_length_in_transaction.2882908590 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 156777765 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:00:16 AM UTC 24 |
| Finished | Aug 21 08:00:18 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2882908590 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2882908590 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_min_length_out_transaction.1593129239 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 212257582 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:00:16 AM UTC 24 |
| Finished | Aug 21 08:00:18 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1593129239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1593129239 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_nak_trans.1543805723 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 285527986 ps |
| CPU time | 1.77 seconds |
| Started | Aug 21 08:00:16 AM UTC 24 |
| Finished | Aug 21 08:00:19 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1543805723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1543805723 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_out_iso.2240967374 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 235809238 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:00:16 AM UTC 24 |
| Finished | Aug 21 08:00:18 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2240967374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2240967374 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_out_stall.3574086292 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 159128097 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:00:16 AM UTC 24 |
| Finished | Aug 21 08:00:18 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3574086292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3574086292 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_out_trans_nak.3841352174 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 167071905 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:00:16 AM UTC 24 |
| Finished | Aug 21 08:00:18 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3841352174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3841352174 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_pending_in_trans.3760985481 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 179458608 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:00:17 AM UTC 24 |
| Finished | Aug 21 08:00:19 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3760985481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3760985481 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_phy_config_pinflip.3705579054 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 230590332 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:00:17 AM UTC 24 |
| Finished | Aug 21 08:00:20 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3705579054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.3705579054 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_phy_config_usb_ref_disable.1519744285 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 159603059 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:00:17 AM UTC 24 |
| Finished | Aug 21 08:00:20 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1519744285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1519744285 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_phy_pins_sense.2919927503 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 30780151 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 08:00:17 AM UTC 24 |
| Finished | Aug 21 08:00:19 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2919927503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2919927503 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_pkt_buffer.857191987 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 12025542668 ps |
| CPU time | 33.84 seconds |
| Started | Aug 21 08:00:19 AM UTC 24 |
| Finished | Aug 21 08:00:54 AM UTC 24 |
| Peak memory | 228584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=857191987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.857191987 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_pkt_received.2716256996 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 200704583 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:00:19 AM UTC 24 |
| Finished | Aug 21 08:00:22 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2716256996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2716256996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_pkt_sent.1917825007 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 249659461 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:00:19 AM UTC 24 |
| Finished | Aug 21 08:00:21 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1917825007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1917825007 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_random_length_in_transaction.3397417699 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 151470151 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:00:19 AM UTC 24 |
| Finished | Aug 21 08:00:21 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3397417699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.3397417699 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_random_length_out_transaction.578625434 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 202280201 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:00:19 AM UTC 24 |
| Finished | Aug 21 08:00:22 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=578625434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.578625434 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_rx_crc_err.3206665995 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 140391837 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:00:19 AM UTC 24 |
| Finished | Aug 21 08:00:22 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3206665995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.3206665995 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_rx_full.2935242267 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 300595534 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 08:00:19 AM UTC 24 |
| Finished | Aug 21 08:00:22 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2935242267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_full.2935242267 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_setup_stage.2628581562 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 149503926 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:00:19 AM UTC 24 |
| Finished | Aug 21 08:00:22 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2628581562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2628581562 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_setup_trans_ignored.953811111 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 143262374 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 08:00:19 AM UTC 24 |
| Finished | Aug 21 08:00:21 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=953811111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.953811111 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_smoke.3707468539 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 221430306 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 08:00:21 AM UTC 24 |
| Finished | Aug 21 08:00:23 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3707468539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3707468539 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_spurious_pids_ignored.2942359457 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 1796793246 ps |
| CPU time | 43.14 seconds |
| Started | Aug 21 08:00:21 AM UTC 24 |
| Finished | Aug 21 08:01:05 AM UTC 24 |
| Peak memory | 230484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2942359457 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.2942359457 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_stall_priority_over_nak.2805964289 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 195874664 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:00:21 AM UTC 24 |
| Finished | Aug 21 08:00:23 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2805964289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2805964289 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_stall_trans.2172161603 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 173611229 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 08:00:21 AM UTC 24 |
| Finished | Aug 21 08:00:23 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2172161603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2172161603 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_stream_len_max.158964190 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 1114680004 ps |
| CPU time | 3.52 seconds |
| Started | Aug 21 08:00:21 AM UTC 24 |
| Finished | Aug 21 08:00:25 AM UTC 24 |
| Peak memory | 218136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=158964190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.158964190 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_streaming_out.3502429833 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 3162674019 ps |
| CPU time | 28.28 seconds |
| Started | Aug 21 08:00:21 AM UTC 24 |
| Finished | Aug 21 08:00:50 AM UTC 24 |
| Peak memory | 230432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3502429833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3502429833 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_timeout_missing_host_handshake.2247323561 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 1677657437 ps |
| CPU time | 35.79 seconds |
| Started | Aug 21 08:00:10 AM UTC 24 |
| Finished | Aug 21 08:00:47 AM UTC 24 |
| Peak memory | 218056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2247323561 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing _host_handshake.2247323561 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/29.usbdev_tx_rx_disruption.2895805724 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 419446709 ps |
| CPU time | 2.36 seconds |
| Started | Aug 21 08:00:22 AM UTC 24 |
| Finished | Aug 21 08:00:26 AM UTC 24 |
| Peak memory | 218048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2895805724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 29.usbdev_tx_rx_disruption.2895805724 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/29.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/290.usbdev_tx_rx_disruption.3633174293 |
| Short name | T3382 |
| Test name | |
| Test status | |
| Simulation time | 581337683 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:06:41 AM UTC 24 |
| Finished | Aug 21 08:06:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3633174293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 290.usbdev_tx_rx_disruption.3633174293 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/290.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/291.usbdev_tx_rx_disruption.4090447867 |
| Short name | T3383 |
| Test name | |
| Test status | |
| Simulation time | 589267421 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:06:41 AM UTC 24 |
| Finished | Aug 21 08:06:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4090447867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 291.usbdev_tx_rx_disruption.4090447867 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/291.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/292.usbdev_tx_rx_disruption.799307577 |
| Short name | T3375 |
| Test name | |
| Test status | |
| Simulation time | 557534805 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:06:43 AM UTC 24 |
| Finished | Aug 21 08:06:46 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=799307577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 292.usbdev_tx_rx_disruption.799307577 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/292.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/293.usbdev_tx_rx_disruption.3974305984 |
| Short name | T3374 |
| Test name | |
| Test status | |
| Simulation time | 607566362 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:06:43 AM UTC 24 |
| Finished | Aug 21 08:06:46 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3974305984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 293.usbdev_tx_rx_disruption.3974305984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/293.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/294.usbdev_tx_rx_disruption.1458942331 |
| Short name | T3411 |
| Test name | |
| Test status | |
| Simulation time | 640232994 ps |
| CPU time | 1.81 seconds |
| Started | Aug 21 08:06:46 AM UTC 24 |
| Finished | Aug 21 08:06:49 AM UTC 24 |
| Peak memory | 216420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1458942331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 294.usbdev_tx_rx_disruption.1458942331 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/294.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/295.usbdev_tx_rx_disruption.762189331 |
| Short name | T3398 |
| Test name | |
| Test status | |
| Simulation time | 520181147 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:06:46 AM UTC 24 |
| Finished | Aug 21 08:06:48 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=762189331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 295.usbdev_tx_rx_disruption.762189331 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/295.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/296.usbdev_tx_rx_disruption.3789453087 |
| Short name | T3522 |
| Test name | |
| Test status | |
| Simulation time | 529385075 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:06:47 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3789453087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 296.usbdev_tx_rx_disruption.3789453087 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/296.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/297.usbdev_tx_rx_disruption.2422328510 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 541223294 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:06:47 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2422328510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 297.usbdev_tx_rx_disruption.2422328510 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/297.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/298.usbdev_tx_rx_disruption.4173348810 |
| Short name | T3523 |
| Test name | |
| Test status | |
| Simulation time | 490116260 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:06:47 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4173348810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 298.usbdev_tx_rx_disruption.4173348810 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/298.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/299.usbdev_tx_rx_disruption.204907164 |
| Short name | T3419 |
| Test name | |
| Test status | |
| Simulation time | 536709263 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:06:48 AM UTC 24 |
| Finished | Aug 21 08:06:51 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=204907164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 299.usbdev_tx_rx_disruption.204907164 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/299.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_alert_test.3329654777 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 38897649 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 07:51:40 AM UTC 24 |
| Finished | Aug 21 07:51:42 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3329654777 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.3329654777 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_disconnect.106009894 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6155874818 ps |
| CPU time | 9.89 seconds |
| Started | Aug 21 07:51:01 AM UTC 24 |
| Finished | Aug 21 07:51:12 AM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=106009894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev _aon_wake_disconnect.106009894 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_reset.1422781139 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 18706930129 ps |
| CPU time | 23.33 seconds |
| Started | Aug 21 07:51:01 AM UTC 24 |
| Finished | Aug 21 07:51:26 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1422781139 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1422781139 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_resume.2946031885 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 24151547886 ps |
| CPU time | 41.2 seconds |
| Started | Aug 21 07:51:02 AM UTC 24 |
| Finished | Aug 21 07:51:45 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2946031885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbde v_aon_wake_resume.2946031885 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_av_buffer.2025551084 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 208390123 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 07:51:02 AM UTC 24 |
| Finished | Aug 21 07:51:05 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2025551084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2025551084 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_av_overflow.3276599619 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 154591707 ps |
| CPU time | 0.96 seconds |
| Started | Aug 21 07:51:04 AM UTC 24 |
| Finished | Aug 21 07:51:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3276599619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.3276599619 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_av_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_bitstuff_err.2799001652 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 218331704 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:51:04 AM UTC 24 |
| Finished | Aug 21 07:51:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2799001652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.2799001652 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_clear.863659167 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 314208423 ps |
| CPU time | 1.93 seconds |
| Started | Aug 21 07:51:04 AM UTC 24 |
| Finished | Aug 21 07:51:07 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=863659167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.863659167 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_restore.3152055933 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 877010856 ps |
| CPU time | 4.2 seconds |
| Started | Aug 21 07:51:04 AM UTC 24 |
| Finished | Aug 21 07:51:09 AM UTC 24 |
| Peak memory | 218284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3152055933 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3152055933 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_device_timeout.2318501698 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1367501958 ps |
| CPU time | 35.72 seconds |
| Started | Aug 21 07:51:04 AM UTC 24 |
| Finished | Aug 21 07:51:41 AM UTC 24 |
| Peak memory | 218124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2318501698 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.2318501698 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_disable_endpoint.3214754144 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 450114418 ps |
| CPU time | 1.71 seconds |
| Started | Aug 21 07:51:05 AM UTC 24 |
| Finished | Aug 21 07:51:08 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3214754144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3214754144 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_disconnected.1321474351 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 152905429 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 07:51:06 AM UTC 24 |
| Finished | Aug 21 07:51:08 AM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1321474351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1321474351 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_enable.3624599877 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 44195348 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 07:51:06 AM UTC 24 |
| Finished | Aug 21 07:51:08 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3624599877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3624599877 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_access.4294672309 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 771065863 ps |
| CPU time | 2.37 seconds |
| Started | Aug 21 07:51:06 AM UTC 24 |
| Finished | Aug 21 07:51:09 AM UTC 24 |
| Peak memory | 218140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4294672309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.4294672309 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_rst.1624093116 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 187913346 ps |
| CPU time | 2.93 seconds |
| Started | Aug 21 07:51:07 AM UTC 24 |
| Finished | Aug 21 07:51:11 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1624093116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1624093116 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_freq_hiclk.1575854795 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 85187321417 ps |
| CPU time | 153.42 seconds |
| Started | Aug 21 07:51:07 AM UTC 24 |
| Finished | Aug 21 07:53:43 AM UTC 24 |
| Peak memory | 218288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1575854795 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.1575854795 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_freq_hiclk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_freq_hiclk_max.3213014333 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 116418507405 ps |
| CPU time | 190.77 seconds |
| Started | Aug 21 07:51:07 AM UTC 24 |
| Finished | Aug 21 07:54:21 AM UTC 24 |
| Peak memory | 218324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_ freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3213014333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_p hase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.3213014333 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_freq_hiclk_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_freq_loclk.614055214 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 106125846262 ps |
| CPU time | 199.14 seconds |
| Started | Aug 21 07:51:08 AM UTC 24 |
| Finished | Aug 21 07:54:30 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=614055214 -assert nopostproc +UVM_TESTNAME=usbdev _base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.614055214 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_freq_loclk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_freq_loclk_max.462767189 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 86102198405 ps |
| CPU time | 168.44 seconds |
| Started | Aug 21 07:51:08 AM UTC 24 |
| Finished | Aug 21 07:53:59 AM UTC 24 |
| Peak memory | 218464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_d rifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=462767189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_ph ase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.462767189 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_freq_loclk_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_freq_phase.266647180 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 104175490290 ps |
| CPU time | 186.67 seconds |
| Started | Aug 21 07:51:08 AM UTC 24 |
| Finished | Aug 21 07:54:18 AM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=266647180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.266647180 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_freq_phase/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_in_iso.2578570300 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 260475251 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 07:51:10 AM UTC 24 |
| Finished | Aug 21 07:51:12 AM UTC 24 |
| Peak memory | 234064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2578570300 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.2578570300 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_in_stall.3973363888 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 144720938 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:51:10 AM UTC 24 |
| Finished | Aug 21 07:51:12 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3973363888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3973363888 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_in_trans.3987824196 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 167290585 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:51:10 AM UTC 24 |
| Finished | Aug 21 07:51:12 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3987824196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3987824196 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_invalid_sync.3816733565 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 3242799780 ps |
| CPU time | 39.35 seconds |
| Started | Aug 21 07:51:08 AM UTC 24 |
| Finished | Aug 21 07:51:49 AM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3816733565 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3816733565 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_iso_retraction.3691928195 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 7981670657 ps |
| CPU time | 55.77 seconds |
| Started | Aug 21 07:51:10 AM UTC 24 |
| Finished | Aug 21 07:52:07 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3691928195 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.3691928195 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_link_in_err.347064190 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 159044057 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:51:11 AM UTC 24 |
| Finished | Aug 21 07:51:13 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=347064190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.347064190 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_link_resume.3509814459 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 30358325359 ps |
| CPU time | 59.88 seconds |
| Started | Aug 21 07:51:12 AM UTC 24 |
| Finished | Aug 21 07:52:13 AM UTC 24 |
| Peak memory | 218204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3509814459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.3509814459 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_link_suspend.454376884 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 9113131183 ps |
| CPU time | 22.33 seconds |
| Started | Aug 21 07:51:13 AM UTC 24 |
| Finished | Aug 21 07:51:37 AM UTC 24 |
| Peak memory | 218204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=454376884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.454376884 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_low_speed_traffic.795264980 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 3768818223 ps |
| CPU time | 45.49 seconds |
| Started | Aug 21 07:51:13 AM UTC 24 |
| Finished | Aug 21 07:52:00 AM UTC 24 |
| Peak memory | 230640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=795264980 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.795264980 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_max_inter_pkt_delay.69142921 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1712925370 ps |
| CPU time | 43.42 seconds |
| Started | Aug 21 07:51:13 AM UTC 24 |
| Finished | Aug 21 07:51:58 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=69142921 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.69142921 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_in_transaction.3592501179 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 242419130 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 07:51:13 AM UTC 24 |
| Finished | Aug 21 07:51:16 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3592501179 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3592501179 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_out_transaction.2430827495 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 214023314 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 07:51:14 AM UTC 24 |
| Finished | Aug 21 07:51:17 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2430827495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2430827495 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_max_non_iso_usb_traffic.2362603656 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1723260535 ps |
| CPU time | 15.8 seconds |
| Started | Aug 21 07:51:17 AM UTC 24 |
| Finished | Aug 21 07:51:34 AM UTC 24 |
| Peak memory | 228488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2362603656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_non_iso_usb_traffic.2362603656 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_max_usb_traffic.2202828817 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1934592547 ps |
| CPU time | 21.12 seconds |
| Started | Aug 21 07:51:17 AM UTC 24 |
| Finished | Aug 21 07:51:40 AM UTC 24 |
| Peak memory | 217540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2202828817 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.2202828817 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_min_inter_pkt_delay.942512512 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2957546309 ps |
| CPU time | 30.37 seconds |
| Started | Aug 21 07:51:17 AM UTC 24 |
| Finished | Aug 21 07:51:49 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=942512512 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.942512512 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_in_transaction.2887896845 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 188281981 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:51:17 AM UTC 24 |
| Finished | Aug 21 07:51:20 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2887896845 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.2887896845 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_out_transaction.1439065761 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 183246311 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:51:18 AM UTC 24 |
| Finished | Aug 21 07:51:21 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1439065761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1439065761 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_nak_trans.1150227421 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 207671563 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:51:20 AM UTC 24 |
| Finished | Aug 21 07:51:22 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1150227421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1150227421 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_out_iso.498416989 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 149208751 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:51:21 AM UTC 24 |
| Finished | Aug 21 07:51:23 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=498416989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.498416989 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_out_stall.3442975808 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 189289104 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:51:21 AM UTC 24 |
| Finished | Aug 21 07:51:23 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3442975808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3442975808 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_out_trans_nak.2538899966 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 178569408 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:51:22 AM UTC 24 |
| Finished | Aug 21 07:51:24 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2538899966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2538899966 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_pending_in_trans.551633354 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 202219498 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 07:51:22 AM UTC 24 |
| Finished | Aug 21 07:51:25 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=551633354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.551633354 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_pinflip.575661724 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 211921948 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 07:51:23 AM UTC 24 |
| Finished | Aug 21 07:51:26 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=575661724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.575661724 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_rand_bus_type.723935333 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 229711598 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 07:51:24 AM UTC 24 |
| Finished | Aug 21 07:51:27 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=723935333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.723935333 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_phy_config_rand_bus_type/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_usb_ref_disable.3447666004 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 145853780 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:51:24 AM UTC 24 |
| Finished | Aug 21 07:51:27 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3447666004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3447666004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_phy_pins_sense.343456010 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 29034817 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 07:51:25 AM UTC 24 |
| Finished | Aug 21 07:51:27 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=343456010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.343456010 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_buffer.926951427 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 17546281557 ps |
| CPU time | 51.15 seconds |
| Started | Aug 21 07:51:26 AM UTC 24 |
| Finished | Aug 21 07:52:18 AM UTC 24 |
| Peak memory | 228576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=926951427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.926951427 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_received.334528856 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 154316533 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 07:51:27 AM UTC 24 |
| Finished | Aug 21 07:51:29 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=334528856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.334528856 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_sent.3711693313 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 253287694 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:51:27 AM UTC 24 |
| Finished | Aug 21 07:51:29 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3711693313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3711693313 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_rand_bus_disconnects.2257374247 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 6071952896 ps |
| CPU time | 70.88 seconds |
| Started | Aug 21 07:51:28 AM UTC 24 |
| Finished | Aug 21 07:52:41 AM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2257374247 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.2257374247 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_rand_bus_resets.2681546552 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 6859788370 ps |
| CPU time | 26.38 seconds |
| Started | Aug 21 07:51:28 AM UTC 24 |
| Finished | Aug 21 07:51:56 AM UTC 24 |
| Peak memory | 235192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2681546552 -assert nopostproc +UVM_TESTNAME=usbdev_ base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2681546552 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_rand_suspends.1919556202 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 6651782822 ps |
| CPU time | 37.38 seconds |
| Started | Aug 21 07:51:28 AM UTC 24 |
| Finished | Aug 21 07:52:07 AM UTC 24 |
| Peak memory | 230632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1919556202 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.1919556202 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_rand_suspends/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_random_length_in_transaction.1994838269 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 232852382 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 07:51:28 AM UTC 24 |
| Finished | Aug 21 07:51:31 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1994838269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.1994838269 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_random_length_out_transaction.2868617323 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 180376142 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 07:51:28 AM UTC 24 |
| Finished | Aug 21 07:51:30 AM UTC 24 |
| Peak memory | 216592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2868617323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.2868617323 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_resume_link_active.2192575751 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 20181069112 ps |
| CPU time | 41.58 seconds |
| Started | Aug 21 07:51:29 AM UTC 24 |
| Finished | Aug 21 07:52:12 AM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2192575751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_resume_link_active.2192575751 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_rx_crc_err.1619188262 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 207332818 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 07:51:30 AM UTC 24 |
| Finished | Aug 21 07:51:33 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1619188262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1619188262 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_rx_full.1855168767 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 361494269 ps |
| CPU time | 2.22 seconds |
| Started | Aug 21 07:51:31 AM UTC 24 |
| Finished | Aug 21 07:51:35 AM UTC 24 |
| Peak memory | 218056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1855168767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_full.1855168767 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_rx_pid_err.2030171750 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 172316160 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:51:31 AM UTC 24 |
| Finished | Aug 21 07:51:34 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2030171750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.2030171750 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_rx_pid_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_sec_cm.2302363806 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 592357557 ps |
| CPU time | 2.31 seconds |
| Started | Aug 21 07:51:40 AM UTC 24 |
| Finished | Aug 21 07:51:44 AM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2302363806 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2302363806 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_setup_priority.3915407119 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 372240949 ps |
| CPU time | 2.23 seconds |
| Started | Aug 21 07:51:33 AM UTC 24 |
| Finished | Aug 21 07:51:37 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3915407119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.3915407119 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_setup_priority/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_setup_priority_over_stall_response.911405751 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 297986360 ps |
| CPU time | 1.82 seconds |
| Started | Aug 21 07:51:35 AM UTC 24 |
| Finished | Aug 21 07:51:38 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=911405751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.911405751 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_setup_priority_over_stall_response/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_setup_stage.3629126082 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 150661681 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:51:35 AM UTC 24 |
| Finished | Aug 21 07:51:37 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3629126082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3629126082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_setup_trans_ignored.3979193616 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 173350301 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 07:51:35 AM UTC 24 |
| Finished | Aug 21 07:51:37 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3979193616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3979193616 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_smoke.2465629791 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 210268578 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 07:51:36 AM UTC 24 |
| Finished | Aug 21 07:51:39 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2465629791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2465629791 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_spurious_pids_ignored.2631432332 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 3868867273 ps |
| CPU time | 40.68 seconds |
| Started | Aug 21 07:51:36 AM UTC 24 |
| Finished | Aug 21 07:52:18 AM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2631432332 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.2631432332 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_stall_priority_over_nak.4027353747 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 150895208 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:51:37 AM UTC 24 |
| Finished | Aug 21 07:51:39 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4027353747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.4027353747 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_stall_trans.458779526 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 176776279 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:51:37 AM UTC 24 |
| Finished | Aug 21 07:51:40 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=458779526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.458779526 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_stream_len_max.1120080739 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 634001535 ps |
| CPU time | 2.73 seconds |
| Started | Aug 21 07:51:38 AM UTC 24 |
| Finished | Aug 21 07:51:42 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1120080739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.1120080739 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_streaming_out.1954149634 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2076655825 ps |
| CPU time | 56.75 seconds |
| Started | Aug 21 07:51:38 AM UTC 24 |
| Finished | Aug 21 07:52:37 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1954149634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.1954149634 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_stress_usb_traffic.1905448985 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 5207886716 ps |
| CPU time | 18.8 seconds |
| Started | Aug 21 07:51:40 AM UTC 24 |
| Finished | Aug 21 07:52:00 AM UTC 24 |
| Peak memory | 228556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_ disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1905448985 -assert nopo stproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.1905448985 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_stress_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_timeout_missing_host_handshake.2042569378 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 2896026574 ps |
| CPU time | 21.17 seconds |
| Started | Aug 21 07:51:04 AM UTC 24 |
| Finished | Aug 21 07:51:27 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2042569378 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_ host_handshake.2042569378 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/3.usbdev_tx_rx_disruption.861481163 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 543912949 ps |
| CPU time | 2.69 seconds |
| Started | Aug 21 07:51:40 AM UTC 24 |
| Finished | Aug 21 07:51:44 AM UTC 24 |
| Peak memory | 218068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=861481163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.usbdev_tx_rx_disruption.861481163 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/3.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_alert_test.1462400265 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 45538356 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 08:00:39 AM UTC 24 |
| Finished | Aug 21 08:00:41 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1462400265 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.1462400265 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_aon_wake_disconnect.315858062 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 9379047502 ps |
| CPU time | 14.32 seconds |
| Started | Aug 21 08:00:22 AM UTC 24 |
| Finished | Aug 21 08:00:38 AM UTC 24 |
| Peak memory | 218396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=315858062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbde v_aon_wake_disconnect.315858062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_aon_wake_reset.654886224 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 20556103216 ps |
| CPU time | 25.68 seconds |
| Started | Aug 21 08:00:23 AM UTC 24 |
| Finished | Aug 21 08:00:49 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=654886224 -assert nopostp roc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.654886224 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_aon_wake_resume.2544874000 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 31331263910 ps |
| CPU time | 42.12 seconds |
| Started | Aug 21 08:00:23 AM UTC 24 |
| Finished | Aug 21 08:01:06 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2544874000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbd ev_aon_wake_resume.2544874000 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_av_buffer.1324657326 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 149634083 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 08:00:23 AM UTC 24 |
| Finished | Aug 21 08:00:25 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1324657326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1324657326 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_bitstuff_err.3496425370 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 155904652 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 08:00:23 AM UTC 24 |
| Finished | Aug 21 08:00:25 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3496425370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.3496425370 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_data_toggle_clear.136937643 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 332005043 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:00:23 AM UTC 24 |
| Finished | Aug 21 08:00:25 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=136937643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.136937643 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_data_toggle_restore.734981231 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 989741614 ps |
| CPU time | 3.44 seconds |
| Started | Aug 21 08:00:25 AM UTC 24 |
| Finished | Aug 21 08:00:29 AM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=734981231 -assert nopostproc +UVM_TESTNAME=us bdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.734981231 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_device_timeout.2963529320 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 271335990 ps |
| CPU time | 4.57 seconds |
| Started | Aug 21 08:00:25 AM UTC 24 |
| Finished | Aug 21 08:00:31 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2963529320 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.2963529320 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_disable_endpoint.3698348957 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 577990927 ps |
| CPU time | 2.1 seconds |
| Started | Aug 21 08:00:25 AM UTC 24 |
| Finished | Aug 21 08:00:28 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3698348957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3698348957 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_disconnected.2209247958 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 143150931 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:00:25 AM UTC 24 |
| Finished | Aug 21 08:00:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2209247958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2209247958 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_enable.3970614107 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 57120569 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 08:00:25 AM UTC 24 |
| Finished | Aug 21 08:00:27 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3970614107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.3970614107 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_endpoint_access.3218119109 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 781696087 ps |
| CPU time | 2.95 seconds |
| Started | Aug 21 08:00:25 AM UTC 24 |
| Finished | Aug 21 08:00:29 AM UTC 24 |
| Peak memory | 218136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3218119109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3218119109 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_endpoint_types.1308950490 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 509071574 ps |
| CPU time | 2.28 seconds |
| Started | Aug 21 08:00:25 AM UTC 24 |
| Finished | Aug 21 08:00:29 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1308950490 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_types.1308950490 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_fifo_rst.150180799 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 351487766 ps |
| CPU time | 2.67 seconds |
| Started | Aug 21 08:00:32 AM UTC 24 |
| Finished | Aug 21 08:00:35 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=150180799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.150180799 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_in_iso.2448293404 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 242864058 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:00:32 AM UTC 24 |
| Finished | Aug 21 08:00:34 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2448293404 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.2448293404 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_in_stall.1041547424 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 144269363 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 08:00:32 AM UTC 24 |
| Finished | Aug 21 08:00:34 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1041547424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1041547424 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_in_trans.3458474968 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 214905359 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:00:32 AM UTC 24 |
| Finished | Aug 21 08:00:34 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3458474968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3458474968 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_invalid_sync.1869796660 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 2841780262 ps |
| CPU time | 20.61 seconds |
| Started | Aug 21 08:00:32 AM UTC 24 |
| Finished | Aug 21 08:00:54 AM UTC 24 |
| Peak memory | 228492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1869796660 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.1869796660 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_iso_retraction.1553318156 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 8396157852 ps |
| CPU time | 87.36 seconds |
| Started | Aug 21 08:00:32 AM UTC 24 |
| Finished | Aug 21 08:02:01 AM UTC 24 |
| Peak memory | 218312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1553318156 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.1553318156 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_link_in_err.219531381 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 196237127 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 08:00:32 AM UTC 24 |
| Finished | Aug 21 08:00:34 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=219531381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.219531381 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_link_resume.3174949735 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 4733846901 ps |
| CPU time | 8.05 seconds |
| Started | Aug 21 08:00:32 AM UTC 24 |
| Finished | Aug 21 08:00:41 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3174949735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.3174949735 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_link_suspend.923114502 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 11017404846 ps |
| CPU time | 17.5 seconds |
| Started | Aug 21 08:00:32 AM UTC 24 |
| Finished | Aug 21 08:00:51 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=923114502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.923114502 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_low_speed_traffic.1613049069 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 4037781850 ps |
| CPU time | 99.96 seconds |
| Started | Aug 21 08:00:34 AM UTC 24 |
| Finished | Aug 21 08:02:17 AM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1613049069 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1613049069 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_max_inter_pkt_delay.2246897979 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 3775999194 ps |
| CPU time | 97.43 seconds |
| Started | Aug 21 08:00:34 AM UTC 24 |
| Finished | Aug 21 08:02:14 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2246897979 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.2246897979 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_max_length_in_transaction.876602300 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 279300718 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 08:00:34 AM UTC 24 |
| Finished | Aug 21 08:00:37 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=876602300 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.876602300 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_max_length_out_transaction.3779507311 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 203165141 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:00:34 AM UTC 24 |
| Finished | Aug 21 08:00:37 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3779507311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3779507311 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_min_inter_pkt_delay.941982997 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 1979801554 ps |
| CPU time | 15.09 seconds |
| Started | Aug 21 08:00:34 AM UTC 24 |
| Finished | Aug 21 08:00:51 AM UTC 24 |
| Peak memory | 235120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=941982997 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.941982997 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_min_length_in_transaction.1380010859 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 158786257 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 08:00:34 AM UTC 24 |
| Finished | Aug 21 08:00:37 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1380010859 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1380010859 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_min_length_out_transaction.957684164 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 162585231 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 08:00:34 AM UTC 24 |
| Finished | Aug 21 08:00:37 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=957684164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.957684164 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_out_iso.2821216777 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 192061543 ps |
| CPU time | 1 seconds |
| Started | Aug 21 08:00:35 AM UTC 24 |
| Finished | Aug 21 08:00:37 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2821216777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.2821216777 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_out_stall.2572234488 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 162764744 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:00:35 AM UTC 24 |
| Finished | Aug 21 08:00:38 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2572234488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2572234488 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_out_trans_nak.2771396889 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 192859930 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:00:35 AM UTC 24 |
| Finished | Aug 21 08:00:38 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2771396889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2771396889 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_pending_in_trans.3636007903 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 164321127 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:00:35 AM UTC 24 |
| Finished | Aug 21 08:00:38 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3636007903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3636007903 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_phy_config_pinflip.3910393050 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 234019437 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:00:35 AM UTC 24 |
| Finished | Aug 21 08:00:38 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3910393050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.3910393050 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_phy_config_usb_ref_disable.904475507 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 152393804 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 08:00:35 AM UTC 24 |
| Finished | Aug 21 08:00:37 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=904475507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.904475507 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_phy_pins_sense.736420075 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 34613839 ps |
| CPU time | 0.87 seconds |
| Started | Aug 21 08:00:35 AM UTC 24 |
| Finished | Aug 21 08:00:37 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=736420075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.736420075 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_pkt_buffer.2727627246 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 11490781568 ps |
| CPU time | 32.81 seconds |
| Started | Aug 21 08:00:37 AM UTC 24 |
| Finished | Aug 21 08:01:12 AM UTC 24 |
| Peak memory | 235140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2727627246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2727627246 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_pkt_received.2134638995 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 150380192 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 08:00:37 AM UTC 24 |
| Finished | Aug 21 08:00:39 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2134638995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2134638995 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_pkt_sent.108862943 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 173198067 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:00:37 AM UTC 24 |
| Finished | Aug 21 08:00:40 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=108862943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.108862943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_random_length_in_transaction.2495278505 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 186005194 ps |
| CPU time | 0.96 seconds |
| Started | Aug 21 08:00:37 AM UTC 24 |
| Finished | Aug 21 08:00:39 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2495278505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.2495278505 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_random_length_out_transaction.3018740684 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 192389130 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:00:37 AM UTC 24 |
| Finished | Aug 21 08:00:40 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3018740684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.3018740684 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_rx_crc_err.3137426064 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 140456922 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 08:00:37 AM UTC 24 |
| Finished | Aug 21 08:00:40 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3137426064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3137426064 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_rx_full.2859220259 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 299170340 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:00:38 AM UTC 24 |
| Finished | Aug 21 08:00:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2859220259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_full.2859220259 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_setup_stage.2643999455 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 154744294 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 08:00:38 AM UTC 24 |
| Finished | Aug 21 08:00:41 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2643999455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2643999455 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_setup_trans_ignored.711245489 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 179528226 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 08:00:38 AM UTC 24 |
| Finished | Aug 21 08:00:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=711245489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.711245489 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_smoke.416660418 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 260827495 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:00:38 AM UTC 24 |
| Finished | Aug 21 08:00:41 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=416660418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.416660418 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_spurious_pids_ignored.3374823050 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 2019170447 ps |
| CPU time | 14.5 seconds |
| Started | Aug 21 08:00:38 AM UTC 24 |
| Finished | Aug 21 08:00:55 AM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3374823050 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.3374823050 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_stall_priority_over_nak.3028603227 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 204547068 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:00:39 AM UTC 24 |
| Finished | Aug 21 08:00:41 AM UTC 24 |
| Peak memory | 216268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3028603227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3028603227 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_stall_trans.2769034483 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 149880135 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 08:00:39 AM UTC 24 |
| Finished | Aug 21 08:00:41 AM UTC 24 |
| Peak memory | 216236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2769034483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2769034483 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_stream_len_max.3366866402 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 329080255 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:00:39 AM UTC 24 |
| Finished | Aug 21 08:00:42 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3366866402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3366866402 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_streaming_out.3920839945 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 2187503641 ps |
| CPU time | 19.57 seconds |
| Started | Aug 21 08:00:39 AM UTC 24 |
| Finished | Aug 21 08:01:00 AM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3920839945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.3920839945 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_timeout_missing_host_handshake.2777072889 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 647860585 ps |
| CPU time | 4.83 seconds |
| Started | Aug 21 08:00:25 AM UTC 24 |
| Finished | Aug 21 08:00:31 AM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2777072889 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing _host_handshake.2777072889 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/30.usbdev_tx_rx_disruption.1968292510 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 519546428 ps |
| CPU time | 1.99 seconds |
| Started | Aug 21 08:00:39 AM UTC 24 |
| Finished | Aug 21 08:00:42 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1968292510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.usbdev_tx_rx_disruption.1968292510 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/30.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/300.usbdev_tx_rx_disruption.768992002 |
| Short name | T3418 |
| Test name | |
| Test status | |
| Simulation time | 465759560 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:06:48 AM UTC 24 |
| Finished | Aug 21 08:06:51 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=768992002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 300.usbdev_tx_rx_disruption.768992002 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/300.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/301.usbdev_tx_rx_disruption.4173495447 |
| Short name | T3417 |
| Test name | |
| Test status | |
| Simulation time | 458586824 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:06:48 AM UTC 24 |
| Finished | Aug 21 08:06:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4173495447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 301.usbdev_tx_rx_disruption.4173495447 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/301.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/302.usbdev_tx_rx_disruption.3087927677 |
| Short name | T3420 |
| Test name | |
| Test status | |
| Simulation time | 488676987 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:06:48 AM UTC 24 |
| Finished | Aug 21 08:06:51 AM UTC 24 |
| Peak memory | 216156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3087927677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 302.usbdev_tx_rx_disruption.3087927677 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/302.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/303.usbdev_tx_rx_disruption.3984063484 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 584091165 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:06:48 AM UTC 24 |
| Finished | Aug 21 08:06:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3984063484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 303.usbdev_tx_rx_disruption.3984063484 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/303.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/304.usbdev_tx_rx_disruption.230037860 |
| Short name | T3416 |
| Test name | |
| Test status | |
| Simulation time | 385800333 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 08:06:48 AM UTC 24 |
| Finished | Aug 21 08:06:51 AM UTC 24 |
| Peak memory | 216120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=230037860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 304.usbdev_tx_rx_disruption.230037860 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/304.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/305.usbdev_tx_rx_disruption.272922521 |
| Short name | T3421 |
| Test name | |
| Test status | |
| Simulation time | 510060936 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:06:48 AM UTC 24 |
| Finished | Aug 21 08:06:51 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=272922521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 305.usbdev_tx_rx_disruption.272922521 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/305.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/306.usbdev_tx_rx_disruption.1410074119 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 557340200 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:06:48 AM UTC 24 |
| Finished | Aug 21 08:06:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1410074119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 306.usbdev_tx_rx_disruption.1410074119 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/306.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/307.usbdev_tx_rx_disruption.405456083 |
| Short name | T3423 |
| Test name | |
| Test status | |
| Simulation time | 484551811 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:06:49 AM UTC 24 |
| Finished | Aug 21 08:06:51 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=405456083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 307.usbdev_tx_rx_disruption.405456083 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/307.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/308.usbdev_tx_rx_disruption.782536316 |
| Short name | T3422 |
| Test name | |
| Test status | |
| Simulation time | 499875929 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:06:49 AM UTC 24 |
| Finished | Aug 21 08:06:51 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=782536316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 308.usbdev_tx_rx_disruption.782536316 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/308.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/309.usbdev_tx_rx_disruption.2541460343 |
| Short name | T3500 |
| Test name | |
| Test status | |
| Simulation time | 535372270 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:26 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2541460343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 309.usbdev_tx_rx_disruption.2541460343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/309.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_alert_test.3985875519 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 71470300 ps |
| CPU time | 0.91 seconds |
| Started | Aug 21 08:00:53 AM UTC 24 |
| Finished | Aug 21 08:00:55 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3985875519 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.3985875519 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_aon_wake_disconnect.3294364332 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 11652452346 ps |
| CPU time | 18.15 seconds |
| Started | Aug 21 08:00:40 AM UTC 24 |
| Finished | Aug 21 08:01:00 AM UTC 24 |
| Peak memory | 218372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3294364332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbd ev_aon_wake_disconnect.3294364332 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_aon_wake_reset.1382805140 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 20523137423 ps |
| CPU time | 25.62 seconds |
| Started | Aug 21 08:00:40 AM UTC 24 |
| Finished | Aug 21 08:01:07 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1382805140 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1382805140 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_aon_wake_resume.2145938555 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 26119926208 ps |
| CPU time | 35.23 seconds |
| Started | Aug 21 08:00:40 AM UTC 24 |
| Finished | Aug 21 08:01:17 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2145938555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbd ev_aon_wake_resume.2145938555 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_av_buffer.1429401206 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 186320849 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 08:00:40 AM UTC 24 |
| Finished | Aug 21 08:00:42 AM UTC 24 |
| Peak memory | 216416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1429401206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1429401206 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_bitstuff_err.2352146633 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 147193225 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:00:40 AM UTC 24 |
| Finished | Aug 21 08:00:42 AM UTC 24 |
| Peak memory | 216416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2352146633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.2352146633 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_data_toggle_clear.1249156155 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 438463578 ps |
| CPU time | 1.86 seconds |
| Started | Aug 21 08:00:40 AM UTC 24 |
| Finished | Aug 21 08:00:43 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1249156155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.1249156155 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_data_toggle_restore.2834299795 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 459069594 ps |
| CPU time | 2.39 seconds |
| Started | Aug 21 08:00:42 AM UTC 24 |
| Finished | Aug 21 08:00:45 AM UTC 24 |
| Peak memory | 217920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2834299795 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2834299795 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_device_address.2081511804 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 29261648111 ps |
| CPU time | 51.09 seconds |
| Started | Aug 21 08:00:42 AM UTC 24 |
| Finished | Aug 21 08:01:35 AM UTC 24 |
| Peak memory | 218356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2081511804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.2081511804 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_device_timeout.3713576516 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 1032895020 ps |
| CPU time | 20.71 seconds |
| Started | Aug 21 08:00:42 AM UTC 24 |
| Finished | Aug 21 08:01:04 AM UTC 24 |
| Peak memory | 218192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3713576516 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.3713576516 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_disable_endpoint.4017288592 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 615715877 ps |
| CPU time | 1.86 seconds |
| Started | Aug 21 08:00:42 AM UTC 24 |
| Finished | Aug 21 08:00:45 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4017288592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.4017288592 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_disconnected.1175875855 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 159095742 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:00:42 AM UTC 24 |
| Finished | Aug 21 08:00:44 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1175875855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.1175875855 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_enable.281457736 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 40902122 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:00:42 AM UTC 24 |
| Finished | Aug 21 08:00:44 AM UTC 24 |
| Peak memory | 216308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=281457736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.281457736 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_endpoint_access.1308930215 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 819797492 ps |
| CPU time | 3.22 seconds |
| Started | Aug 21 08:00:42 AM UTC 24 |
| Finished | Aug 21 08:00:46 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1308930215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1308930215 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_endpoint_types.39702538 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 175641488 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:00:42 AM UTC 24 |
| Finished | Aug 21 08:00:44 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39702538 -assert nopostproc +UVM_TESTNAME=usbdev _base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.39702538 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_fifo_rst.172194311 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 351693265 ps |
| CPU time | 2.82 seconds |
| Started | Aug 21 08:00:42 AM UTC 24 |
| Finished | Aug 21 08:00:46 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=172194311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.172194311 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_in_iso.877590951 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 199881577 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:00:44 AM UTC 24 |
| Finished | Aug 21 08:00:46 AM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=877590951 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.877590951 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_in_stall.3230387298 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 147612658 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:00:44 AM UTC 24 |
| Finished | Aug 21 08:00:46 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3230387298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3230387298 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_in_trans.266385283 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 255276808 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 08:00:44 AM UTC 24 |
| Finished | Aug 21 08:00:46 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=266385283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.266385283 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_invalid_sync.1877233785 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 5592378587 ps |
| CPU time | 145.25 seconds |
| Started | Aug 21 08:00:44 AM UTC 24 |
| Finished | Aug 21 08:03:11 AM UTC 24 |
| Peak memory | 235244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1877233785 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.1877233785 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_iso_retraction.1129709872 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 12290346392 ps |
| CPU time | 82.17 seconds |
| Started | Aug 21 08:00:44 AM UTC 24 |
| Finished | Aug 21 08:02:08 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1129709872 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.1129709872 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_link_in_err.2259915501 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 164245982 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:00:44 AM UTC 24 |
| Finished | Aug 21 08:00:46 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2259915501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.2259915501 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_link_resume.3609073538 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 28762879406 ps |
| CPU time | 47.97 seconds |
| Started | Aug 21 08:00:44 AM UTC 24 |
| Finished | Aug 21 08:01:33 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3609073538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3609073538 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_link_suspend.3509966753 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 4515998305 ps |
| CPU time | 7.02 seconds |
| Started | Aug 21 08:00:44 AM UTC 24 |
| Finished | Aug 21 08:00:52 AM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3509966753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3509966753 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_low_speed_traffic.2401587920 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 5012212602 ps |
| CPU time | 127.66 seconds |
| Started | Aug 21 08:00:44 AM UTC 24 |
| Finished | Aug 21 08:02:54 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2401587920 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2401587920 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_max_inter_pkt_delay.1965219893 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 2485876334 ps |
| CPU time | 23.24 seconds |
| Started | Aug 21 08:00:45 AM UTC 24 |
| Finished | Aug 21 08:01:10 AM UTC 24 |
| Peak memory | 228676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1965219893 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1965219893 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_max_length_in_transaction.133912046 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 268452460 ps |
| CPU time | 1.83 seconds |
| Started | Aug 21 08:00:45 AM UTC 24 |
| Finished | Aug 21 08:00:48 AM UTC 24 |
| Peak memory | 216348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=133912046 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.133912046 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_max_length_out_transaction.89746933 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 203699390 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:00:45 AM UTC 24 |
| Finished | Aug 21 08:00:48 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=89746933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_ 2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.89746933 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_min_inter_pkt_delay.2544582128 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 1739278285 ps |
| CPU time | 14.89 seconds |
| Started | Aug 21 08:00:47 AM UTC 24 |
| Finished | Aug 21 08:01:03 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2544582128 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2544582128 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_min_length_in_transaction.52483019 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 156672274 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:00:47 AM UTC 24 |
| Finished | Aug 21 08:00:49 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=52483019 -assert nopostproc +UVM_TESTNAME=usbdev_base_tes t +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.52483019 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_min_length_out_transaction.1077213954 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 179115259 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:00:47 AM UTC 24 |
| Finished | Aug 21 08:00:49 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1077213954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1077213954 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_nak_trans.1234673981 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 201464387 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:00:47 AM UTC 24 |
| Finished | Aug 21 08:00:50 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1234673981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1234673981 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_out_iso.1583895074 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 210583986 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:00:47 AM UTC 24 |
| Finished | Aug 21 08:00:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1583895074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.1583895074 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_out_stall.1771659948 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 156783618 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:00:47 AM UTC 24 |
| Finished | Aug 21 08:00:49 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1771659948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1771659948 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_out_trans_nak.1790475759 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 158956203 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:00:47 AM UTC 24 |
| Finished | Aug 21 08:00:50 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1790475759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1790475759 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_pending_in_trans.3374053920 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 191597999 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:00:47 AM UTC 24 |
| Finished | Aug 21 08:00:50 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3374053920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3374053920 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_phy_config_pinflip.2834300604 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 181032325 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:00:48 AM UTC 24 |
| Finished | Aug 21 08:00:51 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2834300604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.2834300604 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_phy_config_usb_ref_disable.637910976 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 143740935 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:00:48 AM UTC 24 |
| Finished | Aug 21 08:00:51 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=637910976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.637910976 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_phy_pins_sense.2140633038 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 78621694 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 08:00:48 AM UTC 24 |
| Finished | Aug 21 08:00:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2140633038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2140633038 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_pkt_buffer.2486129216 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 16868391875 ps |
| CPU time | 46.53 seconds |
| Started | Aug 21 08:00:50 AM UTC 24 |
| Finished | Aug 21 08:01:38 AM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2486129216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2486129216 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_pkt_received.1049744361 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 184155159 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:00:51 AM UTC 24 |
| Finished | Aug 21 08:00:54 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1049744361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1049744361 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_pkt_sent.2149612609 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 211737915 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:00:51 AM UTC 24 |
| Finished | Aug 21 08:00:54 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2149612609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2149612609 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_random_length_in_transaction.1393788196 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 168106223 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 08:00:51 AM UTC 24 |
| Finished | Aug 21 08:00:53 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1393788196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1393788196 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_random_length_out_transaction.1349891257 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 235330068 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:00:51 AM UTC 24 |
| Finished | Aug 21 08:00:54 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1349891257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.1349891257 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_rx_crc_err.1361801265 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 145721931 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:00:51 AM UTC 24 |
| Finished | Aug 21 08:00:54 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1361801265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.1361801265 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_setup_stage.4294798493 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 154745246 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:00:51 AM UTC 24 |
| Finished | Aug 21 08:00:54 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4294798493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.4294798493 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_setup_trans_ignored.2121450156 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 155612874 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:00:51 AM UTC 24 |
| Finished | Aug 21 08:00:54 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2121450156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2121450156 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_smoke.640995664 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 221109271 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:00:51 AM UTC 24 |
| Finished | Aug 21 08:00:54 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=640995664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.640995664 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_spurious_pids_ignored.1556433225 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 2359313666 ps |
| CPU time | 20.62 seconds |
| Started | Aug 21 08:00:51 AM UTC 24 |
| Finished | Aug 21 08:01:14 AM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1556433225 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1556433225 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_stall_priority_over_nak.525512123 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 166991439 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:00:52 AM UTC 24 |
| Finished | Aug 21 08:00:54 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=525512123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20 24_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.525512123 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_stall_trans.3159794230 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 155455168 ps |
| CPU time | 0.88 seconds |
| Started | Aug 21 08:00:52 AM UTC 24 |
| Finished | Aug 21 08:00:54 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3159794230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3159794230 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_stream_len_max.4020362341 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 714102899 ps |
| CPU time | 2.06 seconds |
| Started | Aug 21 08:00:53 AM UTC 24 |
| Finished | Aug 21 08:00:56 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4020362341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.4020362341 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_streaming_out.1176697348 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 2169936764 ps |
| CPU time | 55.77 seconds |
| Started | Aug 21 08:00:53 AM UTC 24 |
| Finished | Aug 21 08:01:51 AM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1176697348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1176697348 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_timeout_missing_host_handshake.3573746876 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 5639064460 ps |
| CPU time | 37.15 seconds |
| Started | Aug 21 08:00:42 AM UTC 24 |
| Finished | Aug 21 08:01:21 AM UTC 24 |
| Peak memory | 218384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3573746876 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing _host_handshake.3573746876 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/31.usbdev_tx_rx_disruption.864413076 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 466601901 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 08:00:53 AM UTC 24 |
| Finished | Aug 21 08:00:56 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=864413076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.usbdev_tx_rx_disruption.864413076 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/31.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/310.usbdev_tx_rx_disruption.3094628498 |
| Short name | T3503 |
| Test name | |
| Test status | |
| Simulation time | 469465523 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:26 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3094628498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 310.usbdev_tx_rx_disruption.3094628498 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/310.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/311.usbdev_tx_rx_disruption.4199367251 |
| Short name | T3501 |
| Test name | |
| Test status | |
| Simulation time | 606443941 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:26 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4199367251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 311.usbdev_tx_rx_disruption.4199367251 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/311.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/312.usbdev_tx_rx_disruption.1014120850 |
| Short name | T3510 |
| Test name | |
| Test status | |
| Simulation time | 529290389 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1014120850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 312.usbdev_tx_rx_disruption.1014120850 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/312.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/313.usbdev_tx_rx_disruption.3899031335 |
| Short name | T3511 |
| Test name | |
| Test status | |
| Simulation time | 502163125 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3899031335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 313.usbdev_tx_rx_disruption.3899031335 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/313.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/314.usbdev_tx_rx_disruption.4043273351 |
| Short name | T3515 |
| Test name | |
| Test status | |
| Simulation time | 477620187 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4043273351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 314.usbdev_tx_rx_disruption.4043273351 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/314.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/315.usbdev_tx_rx_disruption.4004460583 |
| Short name | T3440 |
| Test name | |
| Test status | |
| Simulation time | 517794947 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:01 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4004460583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 315.usbdev_tx_rx_disruption.4004460583 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/315.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/316.usbdev_tx_rx_disruption.3682847948 |
| Short name | T3435 |
| Test name | |
| Test status | |
| Simulation time | 477038147 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3682847948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 316.usbdev_tx_rx_disruption.3682847948 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/316.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/317.usbdev_tx_rx_disruption.3069652982 |
| Short name | T3436 |
| Test name | |
| Test status | |
| Simulation time | 482473243 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3069652982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 317.usbdev_tx_rx_disruption.3069652982 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/317.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/318.usbdev_tx_rx_disruption.2271807860 |
| Short name | T3434 |
| Test name | |
| Test status | |
| Simulation time | 487645360 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2271807860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 318.usbdev_tx_rx_disruption.2271807860 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/318.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/319.usbdev_tx_rx_disruption.314460675 |
| Short name | T3438 |
| Test name | |
| Test status | |
| Simulation time | 572601580 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:01 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=314460675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 319.usbdev_tx_rx_disruption.314460675 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/319.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_alert_test.232209956 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 52699679 ps |
| CPU time | 0.89 seconds |
| Started | Aug 21 08:01:07 AM UTC 24 |
| Finished | Aug 21 08:01:09 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=232209956 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.232209956 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_aon_wake_disconnect.1742456900 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 4251162897 ps |
| CPU time | 7.48 seconds |
| Started | Aug 21 08:00:55 AM UTC 24 |
| Finished | Aug 21 08:01:04 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1742456900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbd ev_aon_wake_disconnect.1742456900 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_aon_wake_reset.2265326784 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 20121569245 ps |
| CPU time | 31.42 seconds |
| Started | Aug 21 08:00:55 AM UTC 24 |
| Finished | Aug 21 08:01:28 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2265326784 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.2265326784 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_aon_wake_resume.3550688576 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 23365931981 ps |
| CPU time | 32.54 seconds |
| Started | Aug 21 08:00:55 AM UTC 24 |
| Finished | Aug 21 08:01:29 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3550688576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbd ev_aon_wake_resume.3550688576 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_av_buffer.2173023851 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 152204129 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:00:55 AM UTC 24 |
| Finished | Aug 21 08:00:58 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2173023851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2173023851 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_bitstuff_err.2795344142 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 193411587 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 08:00:55 AM UTC 24 |
| Finished | Aug 21 08:00:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2795344142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2795344142 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_data_toggle_clear.109757251 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 169496750 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 08:00:55 AM UTC 24 |
| Finished | Aug 21 08:00:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=109757251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.109757251 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_data_toggle_restore.3525776237 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 323784462 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:00:55 AM UTC 24 |
| Finished | Aug 21 08:00:58 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3525776237 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3525776237 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_device_address.376618444 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 29174120509 ps |
| CPU time | 51.78 seconds |
| Started | Aug 21 08:00:56 AM UTC 24 |
| Finished | Aug 21 08:01:49 AM UTC 24 |
| Peak memory | 218252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=376618444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.376618444 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_device_timeout.3163075388 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 309937903 ps |
| CPU time | 4.84 seconds |
| Started | Aug 21 08:00:56 AM UTC 24 |
| Finished | Aug 21 08:01:02 AM UTC 24 |
| Peak memory | 218128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3163075388 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.3163075388 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_disable_endpoint.3730332694 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 497616410 ps |
| CPU time | 1.96 seconds |
| Started | Aug 21 08:00:56 AM UTC 24 |
| Finished | Aug 21 08:00:59 AM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3730332694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3730332694 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_disconnected.2324373094 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 151505560 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 08:00:56 AM UTC 24 |
| Finished | Aug 21 08:00:58 AM UTC 24 |
| Peak memory | 216124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2324373094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.2324373094 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_enable.3558883364 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 49946627 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 08:00:56 AM UTC 24 |
| Finished | Aug 21 08:00:58 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3558883364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3558883364 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_endpoint_access.3783605438 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 922379901 ps |
| CPU time | 3.43 seconds |
| Started | Aug 21 08:00:56 AM UTC 24 |
| Finished | Aug 21 08:01:01 AM UTC 24 |
| Peak memory | 218352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3783605438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3783605438 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_endpoint_types.3857927824 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 551638024 ps |
| CPU time | 1.76 seconds |
| Started | Aug 21 08:00:56 AM UTC 24 |
| Finished | Aug 21 08:00:59 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3857927824 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_types.3857927824 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_fifo_rst.3009227269 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 187653149 ps |
| CPU time | 2.39 seconds |
| Started | Aug 21 08:00:57 AM UTC 24 |
| Finished | Aug 21 08:01:01 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3009227269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3009227269 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_in_iso.1752902471 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 234680979 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:00:57 AM UTC 24 |
| Finished | Aug 21 08:00:59 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1752902471 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1752902471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_in_stall.716747706 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 163704030 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:00:57 AM UTC 24 |
| Finished | Aug 21 08:01:00 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=716747706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.716747706 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_in_trans.2302128579 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 211635681 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:00:57 AM UTC 24 |
| Finished | Aug 21 08:00:59 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2302128579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2302128579 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_invalid_sync.355327608 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 3050251245 ps |
| CPU time | 78.2 seconds |
| Started | Aug 21 08:00:57 AM UTC 24 |
| Finished | Aug 21 08:02:17 AM UTC 24 |
| Peak memory | 228612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=355327608 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.355327608 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_iso_retraction.2510628260 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 12816861604 ps |
| CPU time | 99.29 seconds |
| Started | Aug 21 08:00:59 AM UTC 24 |
| Finished | Aug 21 08:02:40 AM UTC 24 |
| Peak memory | 218376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2510628260 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.2510628260 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_link_in_err.1476802565 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 253421936 ps |
| CPU time | 1.71 seconds |
| Started | Aug 21 08:00:59 AM UTC 24 |
| Finished | Aug 21 08:01:01 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1476802565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1476802565 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_link_resume.3283204338 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 6420471525 ps |
| CPU time | 12.96 seconds |
| Started | Aug 21 08:00:59 AM UTC 24 |
| Finished | Aug 21 08:01:13 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3283204338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.3283204338 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_link_suspend.2415991182 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 11054283232 ps |
| CPU time | 15.56 seconds |
| Started | Aug 21 08:00:59 AM UTC 24 |
| Finished | Aug 21 08:01:16 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2415991182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2415991182 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_low_speed_traffic.1697754854 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 4921536972 ps |
| CPU time | 132.97 seconds |
| Started | Aug 21 08:00:59 AM UTC 24 |
| Finished | Aug 21 08:03:14 AM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1697754854 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.1697754854 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_max_inter_pkt_delay.3713461177 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 3089829314 ps |
| CPU time | 79.6 seconds |
| Started | Aug 21 08:00:59 AM UTC 24 |
| Finished | Aug 21 08:02:20 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3713461177 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3713461177 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_max_length_in_transaction.1186725218 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 267629753 ps |
| CPU time | 1.73 seconds |
| Started | Aug 21 08:01:01 AM UTC 24 |
| Finished | Aug 21 08:01:03 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1186725218 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1186725218 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_max_length_out_transaction.2167745697 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 192710139 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:01:01 AM UTC 24 |
| Finished | Aug 21 08:01:03 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2167745697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2167745697 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_min_inter_pkt_delay.2639781029 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 3270478611 ps |
| CPU time | 30.76 seconds |
| Started | Aug 21 08:01:01 AM UTC 24 |
| Finished | Aug 21 08:01:33 AM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2639781029 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.2639781029 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_min_length_in_transaction.3465364609 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 151087757 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:01:01 AM UTC 24 |
| Finished | Aug 21 08:01:03 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3465364609 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3465364609 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_min_length_out_transaction.966708509 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 226238959 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:01:01 AM UTC 24 |
| Finished | Aug 21 08:01:03 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=966708509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.966708509 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_nak_trans.3330826864 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 161416776 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:01:01 AM UTC 24 |
| Finished | Aug 21 08:01:03 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3330826864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3330826864 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_out_iso.3663910224 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 147263718 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:01:01 AM UTC 24 |
| Finished | Aug 21 08:01:03 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3663910224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3663910224 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_out_stall.2690435485 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 159049077 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:01:01 AM UTC 24 |
| Finished | Aug 21 08:01:03 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2690435485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2690435485 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_out_trans_nak.2647013438 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 157358301 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:01:01 AM UTC 24 |
| Finished | Aug 21 08:01:03 AM UTC 24 |
| Peak memory | 216344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2647013438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2647013438 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_pending_in_trans.2914782310 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 150234859 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:01:02 AM UTC 24 |
| Finished | Aug 21 08:01:05 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2914782310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2914782310 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_phy_config_pinflip.1550899313 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 275835187 ps |
| CPU time | 2.06 seconds |
| Started | Aug 21 08:01:02 AM UTC 24 |
| Finished | Aug 21 08:01:05 AM UTC 24 |
| Peak memory | 218008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1550899313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.1550899313 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_phy_config_usb_ref_disable.1017365674 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 158039273 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:01:02 AM UTC 24 |
| Finished | Aug 21 08:01:05 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1017365674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.1017365674 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_phy_pins_sense.3021154896 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 94006417 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 08:01:02 AM UTC 24 |
| Finished | Aug 21 08:01:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3021154896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3021154896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_pkt_buffer.1474156398 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 8134679648 ps |
| CPU time | 23.08 seconds |
| Started | Aug 21 08:01:04 AM UTC 24 |
| Finished | Aug 21 08:01:28 AM UTC 24 |
| Peak memory | 228584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1474156398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1474156398 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_pkt_received.3557221615 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 178864228 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:01:04 AM UTC 24 |
| Finished | Aug 21 08:01:06 AM UTC 24 |
| Peak memory | 216408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3557221615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3557221615 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_pkt_sent.1378582908 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 250319766 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 08:01:04 AM UTC 24 |
| Finished | Aug 21 08:01:06 AM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1378582908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1378582908 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_random_length_in_transaction.3876464506 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 324777190 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 08:01:04 AM UTC 24 |
| Finished | Aug 21 08:01:07 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3876464506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.3876464506 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_random_length_out_transaction.1110596263 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 175407257 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:01:04 AM UTC 24 |
| Finished | Aug 21 08:01:07 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1110596263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.1110596263 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_rx_crc_err.3468919286 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 215991352 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:01:04 AM UTC 24 |
| Finished | Aug 21 08:01:07 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3468919286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3468919286 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_rx_full.2838125762 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 352662575 ps |
| CPU time | 2.05 seconds |
| Started | Aug 21 08:01:04 AM UTC 24 |
| Finished | Aug 21 08:01:07 AM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2838125762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_full.2838125762 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_setup_stage.3208390153 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 172793432 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:01:04 AM UTC 24 |
| Finished | Aug 21 08:01:07 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3208390153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3208390153 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_setup_trans_ignored.2089113002 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 162405353 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:01:06 AM UTC 24 |
| Finished | Aug 21 08:01:08 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2089113002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2089113002 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_smoke.3155592763 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 208122962 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 08:01:06 AM UTC 24 |
| Finished | Aug 21 08:01:08 AM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3155592763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3155592763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_spurious_pids_ignored.96664083 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 1607123634 ps |
| CPU time | 39.46 seconds |
| Started | Aug 21 08:01:06 AM UTC 24 |
| Finished | Aug 21 08:01:47 AM UTC 24 |
| Peak memory | 228400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=96664083 -assert nopostproc +UVM_TESTNAME=usbdev_base _test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.96664083 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_stall_priority_over_nak.361490790 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 203929322 ps |
| CPU time | 1.16 seconds |
| Started | Aug 21 08:01:06 AM UTC 24 |
| Finished | Aug 21 08:01:08 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=361490790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20 24_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.361490790 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_stall_trans.3197198961 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 180677382 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:01:06 AM UTC 24 |
| Finished | Aug 21 08:01:08 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3197198961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3197198961 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_stream_len_max.2885003497 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 348298016 ps |
| CPU time | 1.78 seconds |
| Started | Aug 21 08:01:07 AM UTC 24 |
| Finished | Aug 21 08:01:10 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2885003497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.2885003497 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_streaming_out.3744109287 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 3415363975 ps |
| CPU time | 93.05 seconds |
| Started | Aug 21 08:01:06 AM UTC 24 |
| Finished | Aug 21 08:02:41 AM UTC 24 |
| Peak memory | 228532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3744109287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3744109287 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_timeout_missing_host_handshake.3607259977 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 2911949166 ps |
| CPU time | 18.1 seconds |
| Started | Aug 21 08:00:56 AM UTC 24 |
| Finished | Aug 21 08:01:15 AM UTC 24 |
| Peak memory | 218296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3607259977 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing _host_handshake.3607259977 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/32.usbdev_tx_rx_disruption.1631094545 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 480678440 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 08:01:07 AM UTC 24 |
| Finished | Aug 21 08:01:10 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1631094545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 32.usbdev_tx_rx_disruption.1631094545 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/32.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/320.usbdev_tx_rx_disruption.466988414 |
| Short name | T3437 |
| Test name | |
| Test status | |
| Simulation time | 484862233 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:01 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=466988414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 320.usbdev_tx_rx_disruption.466988414 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/320.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/321.usbdev_tx_rx_disruption.3788798665 |
| Short name | T3439 |
| Test name | |
| Test status | |
| Simulation time | 614145493 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:01 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3788798665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 321.usbdev_tx_rx_disruption.3788798665 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/321.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/322.usbdev_tx_rx_disruption.612969430 |
| Short name | T3448 |
| Test name | |
| Test status | |
| Simulation time | 497659371 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=612969430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 322.usbdev_tx_rx_disruption.612969430 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/322.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/323.usbdev_tx_rx_disruption.1324515136 |
| Short name | T3449 |
| Test name | |
| Test status | |
| Simulation time | 538233732 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1324515136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 323.usbdev_tx_rx_disruption.1324515136 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/323.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/324.usbdev_tx_rx_disruption.365178439 |
| Short name | T3452 |
| Test name | |
| Test status | |
| Simulation time | 513385724 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=365178439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 324.usbdev_tx_rx_disruption.365178439 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/324.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/325.usbdev_tx_rx_disruption.77445260 |
| Short name | T3460 |
| Test name | |
| Test status | |
| Simulation time | 621080963 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=77445260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 325.usbdev_tx_rx_disruption.77445260 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/325.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/326.usbdev_tx_rx_disruption.2743217996 |
| Short name | T3454 |
| Test name | |
| Test status | |
| Simulation time | 546641229 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2743217996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 326.usbdev_tx_rx_disruption.2743217996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/326.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/327.usbdev_tx_rx_disruption.1468221563 |
| Short name | T3447 |
| Test name | |
| Test status | |
| Simulation time | 453878764 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1468221563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 327.usbdev_tx_rx_disruption.1468221563 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/327.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/328.usbdev_tx_rx_disruption.4285695461 |
| Short name | T3453 |
| Test name | |
| Test status | |
| Simulation time | 643601515 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4285695461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 328.usbdev_tx_rx_disruption.4285695461 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/328.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/329.usbdev_tx_rx_disruption.2072693190 |
| Short name | T3450 |
| Test name | |
| Test status | |
| Simulation time | 498568092 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2072693190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 329.usbdev_tx_rx_disruption.2072693190 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/329.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_alert_test.3901221471 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 43826491 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:01:21 AM UTC 24 |
| Finished | Aug 21 08:01:23 AM UTC 24 |
| Peak memory | 216508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3901221471 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.3901221471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_aon_wake_disconnect.2719345072 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 3983887270 ps |
| CPU time | 9.91 seconds |
| Started | Aug 21 08:01:07 AM UTC 24 |
| Finished | Aug 21 08:01:19 AM UTC 24 |
| Peak memory | 228352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2719345072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbd ev_aon_wake_disconnect.2719345072 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_aon_wake_reset.3453153416 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 19035249111 ps |
| CPU time | 26.12 seconds |
| Started | Aug 21 08:01:08 AM UTC 24 |
| Finished | Aug 21 08:01:35 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3453153416 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3453153416 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_aon_wake_resume.4013160287 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 30127945400 ps |
| CPU time | 38.66 seconds |
| Started | Aug 21 08:01:08 AM UTC 24 |
| Finished | Aug 21 08:01:48 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4013160287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbd ev_aon_wake_resume.4013160287 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_av_buffer.3076929527 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 173786312 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:01:08 AM UTC 24 |
| Finished | Aug 21 08:01:10 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3076929527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3076929527 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_bitstuff_err.3725800393 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 149351097 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 08:01:08 AM UTC 24 |
| Finished | Aug 21 08:01:10 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3725800393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3725800393 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_data_toggle_clear.4158228435 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 224682275 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:01:08 AM UTC 24 |
| Finished | Aug 21 08:01:10 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4158228435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.4158228435 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_data_toggle_restore.2318055858 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 401841956 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:01:09 AM UTC 24 |
| Finished | Aug 21 08:01:11 AM UTC 24 |
| Peak memory | 216440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2318055858 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2318055858 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_device_address.2054031991 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 28013122591 ps |
| CPU time | 47.39 seconds |
| Started | Aug 21 08:01:09 AM UTC 24 |
| Finished | Aug 21 08:01:58 AM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2054031991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2054031991 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_device_timeout.229987339 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 3387397438 ps |
| CPU time | 26.5 seconds |
| Started | Aug 21 08:01:09 AM UTC 24 |
| Finished | Aug 21 08:01:37 AM UTC 24 |
| Peak memory | 218372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=229987339 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.229987339 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_disable_endpoint.2608211972 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 760667934 ps |
| CPU time | 2.23 seconds |
| Started | Aug 21 08:01:09 AM UTC 24 |
| Finished | Aug 21 08:01:12 AM UTC 24 |
| Peak memory | 218096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2608211972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.2608211972 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_disconnected.1470121059 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 191228180 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:01:09 AM UTC 24 |
| Finished | Aug 21 08:01:12 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1470121059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.1470121059 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_enable.785148290 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 56997621 ps |
| CPU time | 0.94 seconds |
| Started | Aug 21 08:01:11 AM UTC 24 |
| Finished | Aug 21 08:01:13 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=785148290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.785148290 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_endpoint_access.3844233290 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 999013277 ps |
| CPU time | 4.64 seconds |
| Started | Aug 21 08:01:11 AM UTC 24 |
| Finished | Aug 21 08:01:16 AM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3844233290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.3844233290 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_endpoint_types.927021151 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 505150533 ps |
| CPU time | 2.5 seconds |
| Started | Aug 21 08:01:11 AM UTC 24 |
| Finished | Aug 21 08:01:14 AM UTC 24 |
| Peak memory | 217980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=927021151 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_types.927021151 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_fifo_rst.1285318748 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 357659303 ps |
| CPU time | 2.45 seconds |
| Started | Aug 21 08:01:11 AM UTC 24 |
| Finished | Aug 21 08:01:14 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1285318748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1285318748 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_in_iso.2184186156 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 211273477 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:01:11 AM UTC 24 |
| Finished | Aug 21 08:01:13 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2184186156 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2184186156 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_in_stall.2216418595 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 137594087 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:01:11 AM UTC 24 |
| Finished | Aug 21 08:01:13 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2216418595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2216418595 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_in_trans.3318918405 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 195633130 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 08:01:11 AM UTC 24 |
| Finished | Aug 21 08:01:13 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3318918405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3318918405 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_invalid_sync.3543543962 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 4482692841 ps |
| CPU time | 117.01 seconds |
| Started | Aug 21 08:01:11 AM UTC 24 |
| Finished | Aug 21 08:03:10 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3543543962 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.3543543962 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_iso_retraction.1036505565 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 5358232682 ps |
| CPU time | 61.68 seconds |
| Started | Aug 21 08:01:11 AM UTC 24 |
| Finished | Aug 21 08:02:15 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1036505565 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.1036505565 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_link_in_err.1692321252 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 243371141 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:01:11 AM UTC 24 |
| Finished | Aug 21 08:01:14 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1692321252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.1692321252 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_link_resume.809144736 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 8920161344 ps |
| CPU time | 13.33 seconds |
| Started | Aug 21 08:01:11 AM UTC 24 |
| Finished | Aug 21 08:01:26 AM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=809144736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.809144736 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_link_suspend.734184221 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 6258246163 ps |
| CPU time | 13.78 seconds |
| Started | Aug 21 08:01:13 AM UTC 24 |
| Finished | Aug 21 08:01:28 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=734184221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.734184221 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_low_speed_traffic.4035026648 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 2736180130 ps |
| CPU time | 20.65 seconds |
| Started | Aug 21 08:01:13 AM UTC 24 |
| Finished | Aug 21 08:01:35 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4035026648 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.4035026648 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_max_inter_pkt_delay.2880560707 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 2921416000 ps |
| CPU time | 26.86 seconds |
| Started | Aug 21 08:01:13 AM UTC 24 |
| Finished | Aug 21 08:01:41 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2880560707 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.2880560707 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_max_length_in_transaction.3443376683 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 234433566 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 08:01:14 AM UTC 24 |
| Finished | Aug 21 08:01:17 AM UTC 24 |
| Peak memory | 216248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3443376683 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.3443376683 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_max_length_out_transaction.3863976883 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 206104904 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:01:14 AM UTC 24 |
| Finished | Aug 21 08:01:17 AM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3863976883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3863976883 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_min_inter_pkt_delay.2640742160 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 3437864262 ps |
| CPU time | 89.01 seconds |
| Started | Aug 21 08:01:14 AM UTC 24 |
| Finished | Aug 21 08:02:45 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2640742160 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.2640742160 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_min_length_in_transaction.1053396157 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 160005938 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 08:01:14 AM UTC 24 |
| Finished | Aug 21 08:01:16 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1053396157 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.1053396157 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_min_length_out_transaction.1704873887 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 153443268 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:01:14 AM UTC 24 |
| Finished | Aug 21 08:01:17 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1704873887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1704873887 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_nak_trans.1159462966 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 227992916 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:01:14 AM UTC 24 |
| Finished | Aug 21 08:01:17 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1159462966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.1159462966 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_out_iso.145800391 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 182921925 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:01:14 AM UTC 24 |
| Finished | Aug 21 08:01:17 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=145800391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.145800391 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_out_stall.4246295209 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 147964719 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:01:16 AM UTC 24 |
| Finished | Aug 21 08:01:18 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4246295209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.4246295209 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_out_trans_nak.1545778042 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 175608978 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:01:16 AM UTC 24 |
| Finished | Aug 21 08:01:18 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1545778042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1545778042 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_pending_in_trans.3425534482 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 167603928 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:01:16 AM UTC 24 |
| Finished | Aug 21 08:01:18 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3425534482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3425534482 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_phy_config_pinflip.2273714197 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 210888688 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:01:16 AM UTC 24 |
| Finished | Aug 21 08:01:18 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2273714197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2273714197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_phy_config_usb_ref_disable.1460886212 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 144383001 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:01:17 AM UTC 24 |
| Finished | Aug 21 08:01:20 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1460886212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1460886212 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_phy_pins_sense.1960262640 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 33994942 ps |
| CPU time | 0.89 seconds |
| Started | Aug 21 08:01:17 AM UTC 24 |
| Finished | Aug 21 08:01:19 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1960262640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1960262640 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_pkt_buffer.3499642786 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 9687513977 ps |
| CPU time | 25.96 seconds |
| Started | Aug 21 08:01:17 AM UTC 24 |
| Finished | Aug 21 08:01:45 AM UTC 24 |
| Peak memory | 228576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3499642786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3499642786 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_pkt_received.1706879160 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 196530356 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:01:17 AM UTC 24 |
| Finished | Aug 21 08:01:20 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1706879160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1706879160 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_pkt_sent.1555863325 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 240830919 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:01:17 AM UTC 24 |
| Finished | Aug 21 08:01:20 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1555863325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1555863325 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_random_length_in_transaction.1633168004 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 192681891 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 08:01:17 AM UTC 24 |
| Finished | Aug 21 08:01:20 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1633168004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.1633168004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_random_length_out_transaction.202328722 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 179016023 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:01:19 AM UTC 24 |
| Finished | Aug 21 08:01:21 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=202328722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.202328722 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_rx_crc_err.3397075352 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 140310898 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:01:19 AM UTC 24 |
| Finished | Aug 21 08:01:21 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3397075352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.3397075352 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_rx_full.2243221935 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 387990869 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 08:01:19 AM UTC 24 |
| Finished | Aug 21 08:01:22 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2243221935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_full.2243221935 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_setup_stage.804451483 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 160663019 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 08:01:19 AM UTC 24 |
| Finished | Aug 21 08:01:21 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=804451483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.804451483 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_setup_trans_ignored.1936607582 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 149365377 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 08:01:19 AM UTC 24 |
| Finished | Aug 21 08:01:21 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1936607582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1936607582 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_smoke.2943841489 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 223845199 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:01:19 AM UTC 24 |
| Finished | Aug 21 08:01:21 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2943841489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2943841489 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_spurious_pids_ignored.1053550819 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 2799007214 ps |
| CPU time | 19.09 seconds |
| Started | Aug 21 08:01:19 AM UTC 24 |
| Finished | Aug 21 08:01:39 AM UTC 24 |
| Peak memory | 235344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1053550819 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1053550819 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_stall_priority_over_nak.1088263342 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 218040895 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:01:21 AM UTC 24 |
| Finished | Aug 21 08:01:23 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1088263342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1088263342 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_stall_trans.3107319891 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 170676345 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:01:21 AM UTC 24 |
| Finished | Aug 21 08:01:23 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3107319891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3107319891 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_stream_len_max.503488519 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 1192036085 ps |
| CPU time | 2.87 seconds |
| Started | Aug 21 08:01:21 AM UTC 24 |
| Finished | Aug 21 08:01:25 AM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=503488519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.503488519 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_streaming_out.2175352593 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 3035736970 ps |
| CPU time | 30.22 seconds |
| Started | Aug 21 08:01:21 AM UTC 24 |
| Finished | Aug 21 08:01:52 AM UTC 24 |
| Peak memory | 228612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2175352593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.2175352593 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_timeout_missing_host_handshake.1018950302 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 442103121 ps |
| CPU time | 8.06 seconds |
| Started | Aug 21 08:01:09 AM UTC 24 |
| Finished | Aug 21 08:01:18 AM UTC 24 |
| Peak memory | 218120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1018950302 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing _host_handshake.1018950302 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/33.usbdev_tx_rx_disruption.1536550729 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 532861387 ps |
| CPU time | 2.68 seconds |
| Started | Aug 21 08:01:21 AM UTC 24 |
| Finished | Aug 21 08:01:25 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1536550729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.usbdev_tx_rx_disruption.1536550729 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/33.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/330.usbdev_tx_rx_disruption.935640868 |
| Short name | T3451 |
| Test name | |
| Test status | |
| Simulation time | 531298753 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=935640868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 330.usbdev_tx_rx_disruption.935640868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/330.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/331.usbdev_tx_rx_disruption.3294137196 |
| Short name | T3455 |
| Test name | |
| Test status | |
| Simulation time | 507262951 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3294137196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 331.usbdev_tx_rx_disruption.3294137196 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/331.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/332.usbdev_tx_rx_disruption.1625874253 |
| Short name | T3456 |
| Test name | |
| Test status | |
| Simulation time | 514478545 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1625874253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 332.usbdev_tx_rx_disruption.1625874253 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/332.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/333.usbdev_tx_rx_disruption.3496701209 |
| Short name | T3462 |
| Test name | |
| Test status | |
| Simulation time | 474308381 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3496701209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 333.usbdev_tx_rx_disruption.3496701209 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/333.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/334.usbdev_tx_rx_disruption.16334657 |
| Short name | T3457 |
| Test name | |
| Test status | |
| Simulation time | 451804608 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=16334657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 334.usbdev_tx_rx_disruption.16334657 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/334.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/335.usbdev_tx_rx_disruption.1362144566 |
| Short name | T3458 |
| Test name | |
| Test status | |
| Simulation time | 518601850 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1362144566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 335.usbdev_tx_rx_disruption.1362144566 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/335.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/337.usbdev_tx_rx_disruption.3682279602 |
| Short name | T3459 |
| Test name | |
| Test status | |
| Simulation time | 461391373 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3682279602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 337.usbdev_tx_rx_disruption.3682279602 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/337.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/338.usbdev_tx_rx_disruption.1881776805 |
| Short name | T3465 |
| Test name | |
| Test status | |
| Simulation time | 553119302 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:06:51 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1881776805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 338.usbdev_tx_rx_disruption.1881776805 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/338.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_alert_test.876856965 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 37270828 ps |
| CPU time | 0.87 seconds |
| Started | Aug 21 08:01:37 AM UTC 24 |
| Finished | Aug 21 08:01:39 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=876856965 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.876856965 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_aon_wake_disconnect.2513896598 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 5979168551 ps |
| CPU time | 9.69 seconds |
| Started | Aug 21 08:01:21 AM UTC 24 |
| Finished | Aug 21 08:01:32 AM UTC 24 |
| Peak memory | 228180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2513896598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbd ev_aon_wake_disconnect.2513896598 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_aon_wake_reset.1940011305 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 14470136556 ps |
| CPU time | 18.43 seconds |
| Started | Aug 21 08:01:21 AM UTC 24 |
| Finished | Aug 21 08:01:41 AM UTC 24 |
| Peak memory | 228476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1940011305 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.1940011305 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_aon_wake_resume.373378727 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 30331868529 ps |
| CPU time | 46.69 seconds |
| Started | Aug 21 08:01:21 AM UTC 24 |
| Finished | Aug 21 08:02:09 AM UTC 24 |
| Peak memory | 218284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=373378727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbde v_aon_wake_resume.373378727 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_av_buffer.3443429905 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 162784460 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:01:23 AM UTC 24 |
| Finished | Aug 21 08:01:25 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3443429905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3443429905 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_bitstuff_err.2787803294 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 161939844 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:01:23 AM UTC 24 |
| Finished | Aug 21 08:01:25 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2787803294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.2787803294 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_data_toggle_clear.3212437652 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 391339755 ps |
| CPU time | 2.23 seconds |
| Started | Aug 21 08:01:23 AM UTC 24 |
| Finished | Aug 21 08:01:26 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3212437652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.3212437652 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_data_toggle_restore.156560918 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 1234042849 ps |
| CPU time | 3.46 seconds |
| Started | Aug 21 08:01:23 AM UTC 24 |
| Finished | Aug 21 08:01:27 AM UTC 24 |
| Peak memory | 218012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=156560918 -assert nopostproc +UVM_TESTNAME=us bdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.156560918 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_device_address.919473005 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 40311749345 ps |
| CPU time | 93.13 seconds |
| Started | Aug 21 08:01:23 AM UTC 24 |
| Finished | Aug 21 08:02:58 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=919473005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.919473005 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_device_timeout.3183126006 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 5702975259 ps |
| CPU time | 34.07 seconds |
| Started | Aug 21 08:01:23 AM UTC 24 |
| Finished | Aug 21 08:01:58 AM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3183126006 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.3183126006 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_disable_endpoint.3334325688 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 748186680 ps |
| CPU time | 2.75 seconds |
| Started | Aug 21 08:01:24 AM UTC 24 |
| Finished | Aug 21 08:01:28 AM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3334325688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.3334325688 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_disconnected.2342980967 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 173381563 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:01:24 AM UTC 24 |
| Finished | Aug 21 08:01:26 AM UTC 24 |
| Peak memory | 216432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2342980967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2342980967 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_enable.3771198601 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 36283430 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 08:01:24 AM UTC 24 |
| Finished | Aug 21 08:01:26 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3771198601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3771198601 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_endpoint_access.2256116045 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 965519902 ps |
| CPU time | 4.27 seconds |
| Started | Aug 21 08:01:24 AM UTC 24 |
| Finished | Aug 21 08:01:29 AM UTC 24 |
| Peak memory | 218132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2256116045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2256116045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_endpoint_types.335667790 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 207781642 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 08:01:26 AM UTC 24 |
| Finished | Aug 21 08:01:29 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=335667790 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_types.335667790 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_fifo_rst.2695314259 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 176313762 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 08:01:26 AM UTC 24 |
| Finished | Aug 21 08:01:29 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2695314259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2695314259 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_in_iso.150644311 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 195478299 ps |
| CPU time | 1.7 seconds |
| Started | Aug 21 08:01:27 AM UTC 24 |
| Finished | Aug 21 08:01:29 AM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=150644311 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.150644311 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_in_stall.2066430861 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 139793547 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:01:27 AM UTC 24 |
| Finished | Aug 21 08:01:29 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2066430861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2066430861 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_in_trans.576077819 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 261527611 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:01:27 AM UTC 24 |
| Finished | Aug 21 08:01:29 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=576077819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.576077819 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_invalid_sync.1078766608 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 2921542000 ps |
| CPU time | 76.93 seconds |
| Started | Aug 21 08:01:26 AM UTC 24 |
| Finished | Aug 21 08:02:45 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1078766608 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.1078766608 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_iso_retraction.3910946697 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 14015237396 ps |
| CPU time | 104.59 seconds |
| Started | Aug 21 08:01:27 AM UTC 24 |
| Finished | Aug 21 08:03:13 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3910946697 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.3910946697 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_link_in_err.936991884 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 191984393 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:01:27 AM UTC 24 |
| Finished | Aug 21 08:01:29 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=936991884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.936991884 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_link_resume.2012309226 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 13664905324 ps |
| CPU time | 20.85 seconds |
| Started | Aug 21 08:01:28 AM UTC 24 |
| Finished | Aug 21 08:01:50 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2012309226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.2012309226 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_link_suspend.894453507 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 4416287248 ps |
| CPU time | 8.98 seconds |
| Started | Aug 21 08:01:28 AM UTC 24 |
| Finished | Aug 21 08:01:38 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=894453507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.894453507 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_low_speed_traffic.3785975855 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 3553660906 ps |
| CPU time | 94.85 seconds |
| Started | Aug 21 08:01:28 AM UTC 24 |
| Finished | Aug 21 08:03:05 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3785975855 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.3785975855 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_max_inter_pkt_delay.4053842384 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 3539518064 ps |
| CPU time | 28.13 seconds |
| Started | Aug 21 08:01:28 AM UTC 24 |
| Finished | Aug 21 08:01:58 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4053842384 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.4053842384 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_max_length_in_transaction.1576623175 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 235135775 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 08:01:30 AM UTC 24 |
| Finished | Aug 21 08:01:33 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1576623175 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1576623175 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_max_length_out_transaction.3779538042 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 237305016 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:01:30 AM UTC 24 |
| Finished | Aug 21 08:01:33 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3779538042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3779538042 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_min_inter_pkt_delay.2979370682 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 1990518329 ps |
| CPU time | 51.77 seconds |
| Started | Aug 21 08:01:30 AM UTC 24 |
| Finished | Aug 21 08:02:24 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2979370682 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.2979370682 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_min_length_in_transaction.2580183761 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 160200385 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:01:30 AM UTC 24 |
| Finished | Aug 21 08:01:33 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2580183761 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.2580183761 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_min_length_out_transaction.1377559285 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 150205037 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:01:30 AM UTC 24 |
| Finished | Aug 21 08:01:33 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1377559285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1377559285 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_nak_trans.2141126796 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 217034050 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:01:30 AM UTC 24 |
| Finished | Aug 21 08:01:33 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2141126796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2141126796 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_out_iso.1236342878 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 206006769 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:01:30 AM UTC 24 |
| Finished | Aug 21 08:01:33 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1236342878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1236342878 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_out_stall.811566730 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 179855174 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:01:30 AM UTC 24 |
| Finished | Aug 21 08:01:33 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=811566730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.811566730 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_out_trans_nak.1073430136 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 154459252 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:01:30 AM UTC 24 |
| Finished | Aug 21 08:01:33 AM UTC 24 |
| Peak memory | 216240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1073430136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1073430136 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_pending_in_trans.2945681913 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 164340666 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:01:30 AM UTC 24 |
| Finished | Aug 21 08:01:33 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2945681913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2945681913 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_phy_config_pinflip.74473306 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 215140211 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:01:32 AM UTC 24 |
| Finished | Aug 21 08:01:34 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=74473306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.74473306 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_phy_config_usb_ref_disable.1832102226 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 141346908 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:01:32 AM UTC 24 |
| Finished | Aug 21 08:01:34 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1832102226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1832102226 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_phy_pins_sense.426234636 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 88942009 ps |
| CPU time | 1 seconds |
| Started | Aug 21 08:01:33 AM UTC 24 |
| Finished | Aug 21 08:01:35 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=426234636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.426234636 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_pkt_buffer.2618685888 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 14032602127 ps |
| CPU time | 41.19 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:02:17 AM UTC 24 |
| Peak memory | 232544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2618685888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2618685888 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_pkt_received.2467390670 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 171123745 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:01:37 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2467390670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2467390670 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_pkt_sent.730074001 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 161958162 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:01:37 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=730074001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.730074001 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_random_length_in_transaction.1508457025 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 219516279 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:01:38 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1508457025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.1508457025 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_random_length_out_transaction.1728041242 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 181084523 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:01:38 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1728041242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.1728041242 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_rx_crc_err.725867615 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 168989071 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:01:38 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=725867615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.725867615 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_rx_full.494938245 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 334286800 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:01:38 AM UTC 24 |
| Peak memory | 216444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=494938245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_full.494938245 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_setup_stage.2607350321 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 152369020 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:01:37 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2607350321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.2607350321 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_setup_trans_ignored.161708453 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 152088345 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:01:37 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=161708453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.161708453 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_smoke.3497463576 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 244840255 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:01:37 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3497463576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3497463576 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_spurious_pids_ignored.2350065144 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 3597407486 ps |
| CPU time | 24.19 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:02:01 AM UTC 24 |
| Peak memory | 230424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2350065144 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.2350065144 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_stall_priority_over_nak.2465184638 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 186181908 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:01:37 AM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2465184638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2465184638 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_stall_trans.1137695164 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 186870249 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:01:38 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1137695164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1137695164 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_stream_len_max.2438641240 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 558431671 ps |
| CPU time | 1.82 seconds |
| Started | Aug 21 08:01:37 AM UTC 24 |
| Finished | Aug 21 08:01:40 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2438641240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.2438641240 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_streaming_out.3229043001 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 2694873920 ps |
| CPU time | 18.9 seconds |
| Started | Aug 21 08:01:35 AM UTC 24 |
| Finished | Aug 21 08:01:55 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3229043001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.3229043001 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_timeout_missing_host_handshake.136712478 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 3595207441 ps |
| CPU time | 24.8 seconds |
| Started | Aug 21 08:01:23 AM UTC 24 |
| Finished | Aug 21 08:01:49 AM UTC 24 |
| Peak memory | 218372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=136712478 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_ host_handshake.136712478 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/34.usbdev_tx_rx_disruption.3612244271 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 632321486 ps |
| CPU time | 2.91 seconds |
| Started | Aug 21 08:01:37 AM UTC 24 |
| Finished | Aug 21 08:01:41 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3612244271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.usbdev_tx_rx_disruption.3612244271 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/34.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/341.usbdev_tx_rx_disruption.2617691574 |
| Short name | T3467 |
| Test name | |
| Test status | |
| Simulation time | 490011225 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:06:52 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2617691574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 341.usbdev_tx_rx_disruption.2617691574 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/341.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/342.usbdev_tx_rx_disruption.1077027708 |
| Short name | T3517 |
| Test name | |
| Test status | |
| Simulation time | 558009752 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:06:53 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1077027708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 342.usbdev_tx_rx_disruption.1077027708 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/342.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/343.usbdev_tx_rx_disruption.3252349254 |
| Short name | T3525 |
| Test name | |
| Test status | |
| Simulation time | 605532666 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:06:53 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3252349254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 343.usbdev_tx_rx_disruption.3252349254 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/343.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/344.usbdev_tx_rx_disruption.1062072203 |
| Short name | T3521 |
| Test name | |
| Test status | |
| Simulation time | 456752276 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:06:53 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1062072203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 344.usbdev_tx_rx_disruption.1062072203 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/344.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/345.usbdev_tx_rx_disruption.1874006127 |
| Short name | T3427 |
| Test name | |
| Test status | |
| Simulation time | 594484434 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:06:53 AM UTC 24 |
| Finished | Aug 21 08:06:55 AM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1874006127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 345.usbdev_tx_rx_disruption.1874006127 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/345.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/346.usbdev_tx_rx_disruption.1666103897 |
| Short name | T3432 |
| Test name | |
| Test status | |
| Simulation time | 642815314 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 08:06:53 AM UTC 24 |
| Finished | Aug 21 08:06:56 AM UTC 24 |
| Peak memory | 215624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1666103897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 346.usbdev_tx_rx_disruption.1666103897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/346.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/347.usbdev_tx_rx_disruption.1258729436 |
| Short name | T3431 |
| Test name | |
| Test status | |
| Simulation time | 603914368 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:06:53 AM UTC 24 |
| Finished | Aug 21 08:06:56 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1258729436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 347.usbdev_tx_rx_disruption.1258729436 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/347.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/348.usbdev_tx_rx_disruption.2914958565 |
| Short name | T3426 |
| Test name | |
| Test status | |
| Simulation time | 468539346 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:06:53 AM UTC 24 |
| Finished | Aug 21 08:06:55 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2914958565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 348.usbdev_tx_rx_disruption.2914958565 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/348.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/349.usbdev_tx_rx_disruption.643265679 |
| Short name | T3429 |
| Test name | |
| Test status | |
| Simulation time | 508244474 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:06:53 AM UTC 24 |
| Finished | Aug 21 08:06:56 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=643265679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 349.usbdev_tx_rx_disruption.643265679 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/349.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_alert_test.3903909629 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 51705344 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:01:50 AM UTC 24 |
| Finished | Aug 21 08:01:52 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3903909629 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.3903909629 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_aon_wake_disconnect.2382261993 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 4588812016 ps |
| CPU time | 6.69 seconds |
| Started | Aug 21 08:01:37 AM UTC 24 |
| Finished | Aug 21 08:01:45 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2382261993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbd ev_aon_wake_disconnect.2382261993 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_aon_wake_reset.2294169277 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 20076153436 ps |
| CPU time | 31.51 seconds |
| Started | Aug 21 08:01:38 AM UTC 24 |
| Finished | Aug 21 08:02:11 AM UTC 24 |
| Peak memory | 218192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2294169277 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2294169277 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_aon_wake_resume.1784926326 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 28742995347 ps |
| CPU time | 37.03 seconds |
| Started | Aug 21 08:01:38 AM UTC 24 |
| Finished | Aug 21 08:02:17 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1784926326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbd ev_aon_wake_resume.1784926326 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_av_buffer.225840260 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 178759749 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:01:38 AM UTC 24 |
| Finished | Aug 21 08:01:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=225840260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.225840260 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_bitstuff_err.3717736253 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 158303956 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:01:38 AM UTC 24 |
| Finished | Aug 21 08:01:40 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3717736253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.3717736253 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_data_toggle_clear.1038489905 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 249731942 ps |
| CPU time | 1.76 seconds |
| Started | Aug 21 08:01:38 AM UTC 24 |
| Finished | Aug 21 08:01:41 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1038489905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.1038489905 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_data_toggle_restore.1800388643 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 552133068 ps |
| CPU time | 2.52 seconds |
| Started | Aug 21 08:01:39 AM UTC 24 |
| Finished | Aug 21 08:01:42 AM UTC 24 |
| Peak memory | 218072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1800388643 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1800388643 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_device_address.2432184379 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 31594790961 ps |
| CPU time | 50.93 seconds |
| Started | Aug 21 08:01:39 AM UTC 24 |
| Finished | Aug 21 08:02:31 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2432184379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.2432184379 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_device_timeout.2687809496 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 265932682 ps |
| CPU time | 4.47 seconds |
| Started | Aug 21 08:01:39 AM UTC 24 |
| Finished | Aug 21 08:01:44 AM UTC 24 |
| Peak memory | 218056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2687809496 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.2687809496 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_disable_endpoint.1435134988 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 595827318 ps |
| CPU time | 1.84 seconds |
| Started | Aug 21 08:01:39 AM UTC 24 |
| Finished | Aug 21 08:01:42 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1435134988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1435134988 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_disconnected.1551293900 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 149118848 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 08:01:39 AM UTC 24 |
| Finished | Aug 21 08:01:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1551293900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1551293900 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_enable.362704838 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 31278758 ps |
| CPU time | 0.91 seconds |
| Started | Aug 21 08:01:39 AM UTC 24 |
| Finished | Aug 21 08:01:41 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=362704838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.362704838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_endpoint_access.228609627 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 938304686 ps |
| CPU time | 2.94 seconds |
| Started | Aug 21 08:01:40 AM UTC 24 |
| Finished | Aug 21 08:01:44 AM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=228609627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.228609627 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_endpoint_types.3866094655 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 302545709 ps |
| CPU time | 1.95 seconds |
| Started | Aug 21 08:01:41 AM UTC 24 |
| Finished | Aug 21 08:01:43 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3866094655 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_types.3866094655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_fifo_rst.3623289895 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 289423252 ps |
| CPU time | 2.77 seconds |
| Started | Aug 21 08:01:41 AM UTC 24 |
| Finished | Aug 21 08:01:44 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3623289895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3623289895 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_in_iso.4061343689 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 195269912 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 08:01:41 AM UTC 24 |
| Finished | Aug 21 08:01:43 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4061343689 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.4061343689 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_in_stall.1497811348 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 153478565 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:01:41 AM UTC 24 |
| Finished | Aug 21 08:01:43 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1497811348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1497811348 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_in_trans.1978798070 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 247626077 ps |
| CPU time | 1.81 seconds |
| Started | Aug 21 08:01:41 AM UTC 24 |
| Finished | Aug 21 08:01:44 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1978798070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1978798070 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_invalid_sync.1663420904 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 4037016860 ps |
| CPU time | 37.13 seconds |
| Started | Aug 21 08:01:41 AM UTC 24 |
| Finished | Aug 21 08:02:19 AM UTC 24 |
| Peak memory | 235120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1663420904 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.1663420904 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_iso_retraction.1682469960 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 13111918915 ps |
| CPU time | 143.34 seconds |
| Started | Aug 21 08:01:42 AM UTC 24 |
| Finished | Aug 21 08:04:08 AM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1682469960 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.1682469960 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_link_in_err.3892269200 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 235478097 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:01:42 AM UTC 24 |
| Finished | Aug 21 08:01:45 AM UTC 24 |
| Peak memory | 216032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3892269200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3892269200 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_link_resume.3103773449 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 8481844307 ps |
| CPU time | 14.79 seconds |
| Started | Aug 21 08:01:42 AM UTC 24 |
| Finished | Aug 21 08:01:58 AM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3103773449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.3103773449 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_link_suspend.3584406823 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 5116668910 ps |
| CPU time | 8.02 seconds |
| Started | Aug 21 08:01:42 AM UTC 24 |
| Finished | Aug 21 08:01:51 AM UTC 24 |
| Peak memory | 228512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3584406823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.3584406823 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_low_speed_traffic.3451150358 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 5211504694 ps |
| CPU time | 129.58 seconds |
| Started | Aug 21 08:01:42 AM UTC 24 |
| Finished | Aug 21 08:03:54 AM UTC 24 |
| Peak memory | 228440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3451150358 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.3451150358 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_max_inter_pkt_delay.2360575496 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 1527252872 ps |
| CPU time | 11.94 seconds |
| Started | Aug 21 08:01:42 AM UTC 24 |
| Finished | Aug 21 08:01:55 AM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2360575496 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2360575496 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_max_length_in_transaction.4105598337 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 243978835 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 08:01:42 AM UTC 24 |
| Finished | Aug 21 08:01:44 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4105598337 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.4105598337 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_max_length_out_transaction.3868205776 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 211765510 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 08:01:42 AM UTC 24 |
| Finished | Aug 21 08:01:44 AM UTC 24 |
| Peak memory | 216428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3868205776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3868205776 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_min_inter_pkt_delay.2737989727 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 2613173913 ps |
| CPU time | 72.52 seconds |
| Started | Aug 21 08:01:42 AM UTC 24 |
| Finished | Aug 21 08:02:57 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2737989727 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2737989727 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_min_length_in_transaction.2069793658 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 168432791 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:01:44 AM UTC 24 |
| Finished | Aug 21 08:01:46 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2069793658 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.2069793658 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_min_length_out_transaction.1502668617 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 144169224 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:01:44 AM UTC 24 |
| Finished | Aug 21 08:01:46 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1502668617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1502668617 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_nak_trans.1252586739 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 212756883 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:01:44 AM UTC 24 |
| Finished | Aug 21 08:01:46 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1252586739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1252586739 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_out_iso.3965318465 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 203297268 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:01:45 AM UTC 24 |
| Finished | Aug 21 08:01:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3965318465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3965318465 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_out_stall.3068370646 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 154083380 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:01:45 AM UTC 24 |
| Finished | Aug 21 08:01:47 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3068370646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3068370646 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_out_trans_nak.472233174 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 198643864 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:01:45 AM UTC 24 |
| Finished | Aug 21 08:01:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=472233174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.472233174 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_pending_in_trans.358260882 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 166869339 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:01:45 AM UTC 24 |
| Finished | Aug 21 08:01:47 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=358260882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.358260882 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_phy_config_pinflip.2950410348 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 198236117 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:01:45 AM UTC 24 |
| Finished | Aug 21 08:01:47 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2950410348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.2950410348 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_phy_config_usb_ref_disable.2497220677 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 146959406 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:01:45 AM UTC 24 |
| Finished | Aug 21 08:01:48 AM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2497220677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2497220677 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_phy_pins_sense.3565786229 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 77866461 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 08:01:45 AM UTC 24 |
| Finished | Aug 21 08:01:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3565786229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3565786229 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_pkt_buffer.1078592045 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 14743596543 ps |
| CPU time | 37.77 seconds |
| Started | Aug 21 08:01:47 AM UTC 24 |
| Finished | Aug 21 08:02:26 AM UTC 24 |
| Peak memory | 235308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1078592045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1078592045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_pkt_received.323785282 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 184794897 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:01:47 AM UTC 24 |
| Finished | Aug 21 08:01:49 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=323785282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.323785282 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_pkt_sent.1980647893 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 203238575 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:01:47 AM UTC 24 |
| Finished | Aug 21 08:01:49 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1980647893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1980647893 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_random_length_in_transaction.2076381343 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 233315664 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:01:47 AM UTC 24 |
| Finished | Aug 21 08:01:49 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2076381343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2076381343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_random_length_out_transaction.3987318680 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 209296649 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:01:47 AM UTC 24 |
| Finished | Aug 21 08:01:49 AM UTC 24 |
| Peak memory | 216116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3987318680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3987318680 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_rx_crc_err.317645874 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 182066804 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:01:47 AM UTC 24 |
| Finished | Aug 21 08:01:49 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=317645874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.317645874 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_rx_full.1983447840 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 255623240 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:01:48 AM UTC 24 |
| Finished | Aug 21 08:01:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1983447840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_full.1983447840 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_setup_stage.3995504759 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 179593755 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:01:48 AM UTC 24 |
| Finished | Aug 21 08:01:50 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3995504759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3995504759 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_setup_trans_ignored.3829962506 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 156242284 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 08:01:48 AM UTC 24 |
| Finished | Aug 21 08:01:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3829962506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3829962506 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_smoke.138719325 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 233214207 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 08:01:48 AM UTC 24 |
| Finished | Aug 21 08:01:51 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=138719325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.138719325 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_spurious_pids_ignored.3233477430 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 2709075076 ps |
| CPU time | 72.23 seconds |
| Started | Aug 21 08:01:48 AM UTC 24 |
| Finished | Aug 21 08:03:02 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3233477430 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.3233477430 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_stall_priority_over_nak.1642928707 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 187796605 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:01:48 AM UTC 24 |
| Finished | Aug 21 08:01:51 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1642928707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1642928707 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_stall_trans.2959399395 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 157879138 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:01:48 AM UTC 24 |
| Finished | Aug 21 08:01:51 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2959399395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.2959399395 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_stream_len_max.1255553341 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 472649555 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 08:01:50 AM UTC 24 |
| Finished | Aug 21 08:01:52 AM UTC 24 |
| Peak memory | 216124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1255553341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.1255553341 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_streaming_out.756287534 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 2636250578 ps |
| CPU time | 67.62 seconds |
| Started | Aug 21 08:01:48 AM UTC 24 |
| Finished | Aug 21 08:02:58 AM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=756287534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.756287534 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_timeout_missing_host_handshake.1400425103 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 3875319066 ps |
| CPU time | 31.48 seconds |
| Started | Aug 21 08:01:39 AM UTC 24 |
| Finished | Aug 21 08:02:12 AM UTC 24 |
| Peak memory | 218252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1400425103 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing _host_handshake.1400425103 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/35.usbdev_tx_rx_disruption.2714963908 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 681890095 ps |
| CPU time | 2.06 seconds |
| Started | Aug 21 08:01:50 AM UTC 24 |
| Finished | Aug 21 08:01:53 AM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2714963908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 35.usbdev_tx_rx_disruption.2714963908 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/35.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/350.usbdev_tx_rx_disruption.188366815 |
| Short name | T3433 |
| Test name | |
| Test status | |
| Simulation time | 546277776 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:06:53 AM UTC 24 |
| Finished | Aug 21 08:06:56 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=188366815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 350.usbdev_tx_rx_disruption.188366815 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/350.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/351.usbdev_tx_rx_disruption.794584895 |
| Short name | T3373 |
| Test name | |
| Test status | |
| Simulation time | 556928943 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:06:53 AM UTC 24 |
| Finished | Aug 21 08:06:56 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=794584895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 351.usbdev_tx_rx_disruption.794584895 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/351.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/352.usbdev_tx_rx_disruption.1601949552 |
| Short name | T3491 |
| Test name | |
| Test status | |
| Simulation time | 609934375 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:06:57 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1601949552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 352.usbdev_tx_rx_disruption.1601949552 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/352.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/353.usbdev_tx_rx_disruption.4089287062 |
| Short name | T3494 |
| Test name | |
| Test status | |
| Simulation time | 662552228 ps |
| CPU time | 1.71 seconds |
| Started | Aug 21 08:06:57 AM UTC 24 |
| Finished | Aug 21 08:07:17 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4089287062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 353.usbdev_tx_rx_disruption.4089287062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/353.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/354.usbdev_tx_rx_disruption.1798274875 |
| Short name | T3499 |
| Test name | |
| Test status | |
| Simulation time | 566579441 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:06:57 AM UTC 24 |
| Finished | Aug 21 08:07:26 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1798274875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 354.usbdev_tx_rx_disruption.1798274875 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/354.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/355.usbdev_tx_rx_disruption.407511486 |
| Short name | T3504 |
| Test name | |
| Test status | |
| Simulation time | 494915125 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:06:57 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=407511486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 355.usbdev_tx_rx_disruption.407511486 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/355.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/356.usbdev_tx_rx_disruption.3930194061 |
| Short name | T3502 |
| Test name | |
| Test status | |
| Simulation time | 620663558 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:06:57 AM UTC 24 |
| Finished | Aug 21 08:07:26 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3930194061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 356.usbdev_tx_rx_disruption.3930194061 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/356.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/357.usbdev_tx_rx_disruption.4197214934 |
| Short name | T3492 |
| Test name | |
| Test status | |
| Simulation time | 617255784 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:06:57 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4197214934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 357.usbdev_tx_rx_disruption.4197214934 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/357.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/358.usbdev_tx_rx_disruption.407488103 |
| Short name | T3506 |
| Test name | |
| Test status | |
| Simulation time | 493921659 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:06:57 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=407488103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 358.usbdev_tx_rx_disruption.407488103 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/358.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/359.usbdev_tx_rx_disruption.984981757 |
| Short name | T3516 |
| Test name | |
| Test status | |
| Simulation time | 714598396 ps |
| CPU time | 1.67 seconds |
| Started | Aug 21 08:06:57 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=984981757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 359.usbdev_tx_rx_disruption.984981757 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/359.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_alert_test.368360984 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 46088809 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 08:02:06 AM UTC 24 |
| Finished | Aug 21 08:02:08 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=368360984 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.368360984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_aon_wake_disconnect.3204532896 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 5682373991 ps |
| CPU time | 10.78 seconds |
| Started | Aug 21 08:01:50 AM UTC 24 |
| Finished | Aug 21 08:02:02 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3204532896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbd ev_aon_wake_disconnect.3204532896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_aon_wake_reset.41257692 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 15985846473 ps |
| CPU time | 24.75 seconds |
| Started | Aug 21 08:01:50 AM UTC 24 |
| Finished | Aug 21 08:02:16 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41257692 -assert nopostpr oc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.41257692 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_aon_wake_resume.1389405715 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 30588232937 ps |
| CPU time | 43.71 seconds |
| Started | Aug 21 08:01:52 AM UTC 24 |
| Finished | Aug 21 08:02:37 AM UTC 24 |
| Peak memory | 218136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1389405715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbd ev_aon_wake_resume.1389405715 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_av_buffer.778474379 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 184968746 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:01:52 AM UTC 24 |
| Finished | Aug 21 08:01:55 AM UTC 24 |
| Peak memory | 216244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=778474379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.778474379 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_bitstuff_err.3172141703 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 149844947 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:01:52 AM UTC 24 |
| Finished | Aug 21 08:01:55 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3172141703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3172141703 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_data_toggle_clear.3298746013 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 232038013 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:01:52 AM UTC 24 |
| Finished | Aug 21 08:01:55 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3298746013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3298746013 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_data_toggle_restore.1278709699 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 991251690 ps |
| CPU time | 3.76 seconds |
| Started | Aug 21 08:01:52 AM UTC 24 |
| Finished | Aug 21 08:01:57 AM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1278709699 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1278709699 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_device_address.3238284222 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 49422529364 ps |
| CPU time | 85.65 seconds |
| Started | Aug 21 08:01:52 AM UTC 24 |
| Finished | Aug 21 08:03:20 AM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3238284222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.3238284222 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_device_timeout.896080415 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 2493845386 ps |
| CPU time | 20.93 seconds |
| Started | Aug 21 08:01:52 AM UTC 24 |
| Finished | Aug 21 08:02:15 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=896080415 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.896080415 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_disable_endpoint.4086512868 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 372702886 ps |
| CPU time | 1.74 seconds |
| Started | Aug 21 08:01:53 AM UTC 24 |
| Finished | Aug 21 08:01:55 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4086512868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.4086512868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_disconnected.3093208820 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 152164084 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:01:53 AM UTC 24 |
| Finished | Aug 21 08:01:55 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3093208820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.3093208820 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_enable.2760524444 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 72280122 ps |
| CPU time | 1.16 seconds |
| Started | Aug 21 08:01:53 AM UTC 24 |
| Finished | Aug 21 08:01:55 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2760524444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2760524444 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_endpoint_access.2821056181 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 912738224 ps |
| CPU time | 3.51 seconds |
| Started | Aug 21 08:01:53 AM UTC 24 |
| Finished | Aug 21 08:01:57 AM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2821056181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2821056181 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_endpoint_types.371747825 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 300299997 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:01:53 AM UTC 24 |
| Finished | Aug 21 08:01:55 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=371747825 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_types.371747825 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_fifo_rst.624873045 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 160873241 ps |
| CPU time | 1.92 seconds |
| Started | Aug 21 08:01:54 AM UTC 24 |
| Finished | Aug 21 08:01:57 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=624873045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.624873045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_in_iso.3207208723 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 159950610 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:01:54 AM UTC 24 |
| Finished | Aug 21 08:01:56 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3207208723 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3207208723 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_in_stall.30161220 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 146119259 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:01:55 AM UTC 24 |
| Finished | Aug 21 08:01:58 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30161220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.30161220 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_in_trans.3088099663 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 231845119 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 08:01:55 AM UTC 24 |
| Finished | Aug 21 08:01:58 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3088099663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3088099663 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_invalid_sync.4080560998 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 5049460366 ps |
| CPU time | 46.18 seconds |
| Started | Aug 21 08:01:54 AM UTC 24 |
| Finished | Aug 21 08:02:42 AM UTC 24 |
| Peak memory | 235320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4080560998 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.4080560998 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_iso_retraction.3126005023 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 6496653397 ps |
| CPU time | 74.98 seconds |
| Started | Aug 21 08:01:55 AM UTC 24 |
| Finished | Aug 21 08:03:12 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3126005023 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.3126005023 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_link_in_err.156684410 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 233580369 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:01:56 AM UTC 24 |
| Finished | Aug 21 08:01:58 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=156684410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.156684410 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_link_resume.269457568 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 5166427745 ps |
| CPU time | 9.45 seconds |
| Started | Aug 21 08:01:56 AM UTC 24 |
| Finished | Aug 21 08:02:06 AM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=269457568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.269457568 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_link_suspend.3327593391 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 4639626413 ps |
| CPU time | 13.9 seconds |
| Started | Aug 21 08:01:56 AM UTC 24 |
| Finished | Aug 21 08:02:11 AM UTC 24 |
| Peak memory | 218176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3327593391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3327593391 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_low_speed_traffic.1054145920 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 3457026460 ps |
| CPU time | 37.59 seconds |
| Started | Aug 21 08:01:57 AM UTC 24 |
| Finished | Aug 21 08:02:36 AM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1054145920 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.1054145920 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_max_inter_pkt_delay.144931471 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 3212156788 ps |
| CPU time | 25.44 seconds |
| Started | Aug 21 08:01:57 AM UTC 24 |
| Finished | Aug 21 08:02:24 AM UTC 24 |
| Peak memory | 230668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=144931471 -assert nopostproc +UVM _TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.144931471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_max_length_in_transaction.3374201911 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 234070173 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 08:01:57 AM UTC 24 |
| Finished | Aug 21 08:02:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3374201911 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.3374201911 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_max_length_out_transaction.278449987 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 201107231 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:01:57 AM UTC 24 |
| Finished | Aug 21 08:02:00 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=278449987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.278449987 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_min_inter_pkt_delay.969066830 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 2422152881 ps |
| CPU time | 17.11 seconds |
| Started | Aug 21 08:01:59 AM UTC 24 |
| Finished | Aug 21 08:02:17 AM UTC 24 |
| Peak memory | 228536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=969066830 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.969066830 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_min_length_in_transaction.3675344570 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 155055768 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:01:59 AM UTC 24 |
| Finished | Aug 21 08:02:01 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3675344570 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.3675344570 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_min_length_out_transaction.466216193 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 147779009 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 08:01:59 AM UTC 24 |
| Finished | Aug 21 08:02:01 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=466216193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.466216193 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_nak_trans.635558555 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 195369458 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:01:59 AM UTC 24 |
| Finished | Aug 21 08:02:01 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=635558555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.635558555 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_out_iso.2326548423 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 223485222 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:01:59 AM UTC 24 |
| Finished | Aug 21 08:02:01 AM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2326548423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.2326548423 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_out_stall.3318388016 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 162933498 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:01:59 AM UTC 24 |
| Finished | Aug 21 08:02:01 AM UTC 24 |
| Peak memory | 216296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3318388016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3318388016 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_out_trans_nak.686434655 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 183534411 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:01:59 AM UTC 24 |
| Finished | Aug 21 08:02:01 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=686434655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.686434655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_pending_in_trans.1160412632 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 152578039 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:02:01 AM UTC 24 |
| Finished | Aug 21 08:02:03 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1160412632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1160412632 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_phy_config_pinflip.1698528077 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 185422767 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:02:01 AM UTC 24 |
| Finished | Aug 21 08:02:03 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1698528077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1698528077 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_phy_config_usb_ref_disable.1030129250 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 195643224 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:02:01 AM UTC 24 |
| Finished | Aug 21 08:02:03 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1030129250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1030129250 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_phy_pins_sense.2157649950 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 52636726 ps |
| CPU time | 0.96 seconds |
| Started | Aug 21 08:02:01 AM UTC 24 |
| Finished | Aug 21 08:02:03 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2157649950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2157649950 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_pkt_buffer.2277174708 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 7438948771 ps |
| CPU time | 18.16 seconds |
| Started | Aug 21 08:02:01 AM UTC 24 |
| Finished | Aug 21 08:02:20 AM UTC 24 |
| Peak memory | 228512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2277174708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2277174708 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_pkt_received.2982859328 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 217979707 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:02:02 AM UTC 24 |
| Finished | Aug 21 08:02:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2982859328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2982859328 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_pkt_sent.2841245225 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 188654707 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:02:02 AM UTC 24 |
| Finished | Aug 21 08:02:05 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2841245225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2841245225 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_random_length_in_transaction.2135728010 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 259224756 ps |
| CPU time | 1.72 seconds |
| Started | Aug 21 08:02:02 AM UTC 24 |
| Finished | Aug 21 08:02:05 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2135728010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.2135728010 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_random_length_out_transaction.374840731 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 167374588 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:02:03 AM UTC 24 |
| Finished | Aug 21 08:02:05 AM UTC 24 |
| Peak memory | 216480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=374840731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.374840731 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_rx_crc_err.2729286181 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 162574949 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:02:03 AM UTC 24 |
| Finished | Aug 21 08:02:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2729286181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2729286181 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_rx_full.146546857 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 311230941 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 08:02:03 AM UTC 24 |
| Finished | Aug 21 08:02:05 AM UTC 24 |
| Peak memory | 216408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=146546857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_full.146546857 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_setup_stage.189099189 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 154596015 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:02:03 AM UTC 24 |
| Finished | Aug 21 08:02:05 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=189099189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.189099189 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_setup_trans_ignored.2045876798 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 145586514 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:02:03 AM UTC 24 |
| Finished | Aug 21 08:02:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2045876798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2045876798 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_smoke.2925235075 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 221304128 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 08:02:03 AM UTC 24 |
| Finished | Aug 21 08:02:05 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2925235075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2925235075 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_spurious_pids_ignored.3641568386 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 2446964037 ps |
| CPU time | 17.64 seconds |
| Started | Aug 21 08:02:04 AM UTC 24 |
| Finished | Aug 21 08:02:23 AM UTC 24 |
| Peak memory | 230668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3641568386 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.3641568386 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_stall_priority_over_nak.824490880 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 172157374 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:02:04 AM UTC 24 |
| Finished | Aug 21 08:02:06 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=824490880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20 24_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.824490880 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_stall_trans.2277512141 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 172866782 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:02:04 AM UTC 24 |
| Finished | Aug 21 08:02:07 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2277512141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2277512141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_stream_len_max.685771741 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 579590259 ps |
| CPU time | 3.13 seconds |
| Started | Aug 21 08:02:06 AM UTC 24 |
| Finished | Aug 21 08:02:10 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=685771741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.685771741 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_streaming_out.2119208523 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 2152378621 ps |
| CPU time | 56.62 seconds |
| Started | Aug 21 08:02:04 AM UTC 24 |
| Finished | Aug 21 08:03:02 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2119208523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.2119208523 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_timeout_missing_host_handshake.3577716396 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 1567437839 ps |
| CPU time | 32.05 seconds |
| Started | Aug 21 08:01:52 AM UTC 24 |
| Finished | Aug 21 08:02:26 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3577716396 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing _host_handshake.3577716396 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/36.usbdev_tx_rx_disruption.2725778474 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 632329539 ps |
| CPU time | 2.74 seconds |
| Started | Aug 21 08:02:06 AM UTC 24 |
| Finished | Aug 21 08:02:09 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2725778474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 36.usbdev_tx_rx_disruption.2725778474 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/36.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/360.usbdev_tx_rx_disruption.2607392612 |
| Short name | T3519 |
| Test name | |
| Test status | |
| Simulation time | 498009697 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:06:57 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2607392612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 360.usbdev_tx_rx_disruption.2607392612 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/360.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/361.usbdev_tx_rx_disruption.2934972520 |
| Short name | T3507 |
| Test name | |
| Test status | |
| Simulation time | 551304066 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:06:57 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2934972520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 361.usbdev_tx_rx_disruption.2934972520 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/361.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/362.usbdev_tx_rx_disruption.603501294 |
| Short name | T3524 |
| Test name | |
| Test status | |
| Simulation time | 575289045 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:06:57 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=603501294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 362.usbdev_tx_rx_disruption.603501294 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/362.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/363.usbdev_tx_rx_disruption.3185972842 |
| Short name | T3443 |
| Test name | |
| Test status | |
| Simulation time | 603180542 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:07:00 AM UTC 24 |
| Finished | Aug 21 08:07:06 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3185972842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 363.usbdev_tx_rx_disruption.3185972842 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/363.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/364.usbdev_tx_rx_disruption.2908142423 |
| Short name | T3446 |
| Test name | |
| Test status | |
| Simulation time | 692813735 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 08:07:00 AM UTC 24 |
| Finished | Aug 21 08:07:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2908142423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 364.usbdev_tx_rx_disruption.2908142423 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/364.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/365.usbdev_tx_rx_disruption.1739848652 |
| Short name | T3441 |
| Test name | |
| Test status | |
| Simulation time | 443249733 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:07:00 AM UTC 24 |
| Finished | Aug 21 08:07:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1739848652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 365.usbdev_tx_rx_disruption.1739848652 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/365.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/366.usbdev_tx_rx_disruption.117102102 |
| Short name | T3444 |
| Test name | |
| Test status | |
| Simulation time | 580695109 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:07:00 AM UTC 24 |
| Finished | Aug 21 08:07:06 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=117102102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 366.usbdev_tx_rx_disruption.117102102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/366.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/367.usbdev_tx_rx_disruption.2088586228 |
| Short name | T3442 |
| Test name | |
| Test status | |
| Simulation time | 514022947 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:07:00 AM UTC 24 |
| Finished | Aug 21 08:07:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2088586228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 367.usbdev_tx_rx_disruption.2088586228 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/367.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/368.usbdev_tx_rx_disruption.1668283367 |
| Short name | T3445 |
| Test name | |
| Test status | |
| Simulation time | 573784619 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:07:00 AM UTC 24 |
| Finished | Aug 21 08:07:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1668283367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 368.usbdev_tx_rx_disruption.1668283367 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/368.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/369.usbdev_tx_rx_disruption.437460467 |
| Short name | T3461 |
| Test name | |
| Test status | |
| Simulation time | 597432249 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:07:01 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=437460467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 369.usbdev_tx_rx_disruption.437460467 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/369.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_alert_test.1159380693 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 48409027 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 08:02:22 AM UTC 24 |
| Finished | Aug 21 08:02:24 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1159380693 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.1159380693 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_aon_wake_disconnect.2051406672 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 5448029887 ps |
| CPU time | 8.27 seconds |
| Started | Aug 21 08:02:06 AM UTC 24 |
| Finished | Aug 21 08:02:15 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2051406672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbd ev_aon_wake_disconnect.2051406672 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_aon_wake_reset.4004048270 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 13933500416 ps |
| CPU time | 23.28 seconds |
| Started | Aug 21 08:02:06 AM UTC 24 |
| Finished | Aug 21 08:02:30 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4004048270 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.4004048270 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_aon_wake_resume.1357133504 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 30255662587 ps |
| CPU time | 47.03 seconds |
| Started | Aug 21 08:02:07 AM UTC 24 |
| Finished | Aug 21 08:02:56 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1357133504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbd ev_aon_wake_resume.1357133504 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_av_buffer.4184984262 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 153478130 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 08:02:07 AM UTC 24 |
| Finished | Aug 21 08:02:09 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4184984262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.4184984262 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_bitstuff_err.1494151846 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 167668344 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:02:07 AM UTC 24 |
| Finished | Aug 21 08:02:09 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1494151846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1494151846 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_data_toggle_clear.1197140097 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 596621420 ps |
| CPU time | 2.45 seconds |
| Started | Aug 21 08:02:07 AM UTC 24 |
| Finished | Aug 21 08:02:11 AM UTC 24 |
| Peak memory | 218076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1197140097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.1197140097 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_data_toggle_restore.3148346519 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 364155373 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:02:07 AM UTC 24 |
| Finished | Aug 21 08:02:10 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3148346519 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3148346519 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_device_address.161476066 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 27743346774 ps |
| CPU time | 48.69 seconds |
| Started | Aug 21 08:02:07 AM UTC 24 |
| Finished | Aug 21 08:02:58 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=161476066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.161476066 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_device_timeout.2132490024 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 584973531 ps |
| CPU time | 11.77 seconds |
| Started | Aug 21 08:02:09 AM UTC 24 |
| Finished | Aug 21 08:02:22 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2132490024 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.2132490024 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_disable_endpoint.4279720107 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 845988043 ps |
| CPU time | 3.36 seconds |
| Started | Aug 21 08:02:09 AM UTC 24 |
| Finished | Aug 21 08:02:13 AM UTC 24 |
| Peak memory | 217972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4279720107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.4279720107 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_disconnected.519225990 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 138487900 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:02:09 AM UTC 24 |
| Finished | Aug 21 08:02:11 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=519225990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.519225990 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_enable.2396722196 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 112388380 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:02:10 AM UTC 24 |
| Finished | Aug 21 08:02:13 AM UTC 24 |
| Peak memory | 216376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2396722196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2396722196 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_endpoint_access.97197796 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 945596438 ps |
| CPU time | 3.49 seconds |
| Started | Aug 21 08:02:10 AM UTC 24 |
| Finished | Aug 21 08:02:15 AM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=97197796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.97197796 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_endpoint_types.2618961087 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 409086382 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:02:11 AM UTC 24 |
| Finished | Aug 21 08:02:13 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2618961087 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_types.2618961087 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_fifo_rst.2380056869 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 184636577 ps |
| CPU time | 2.18 seconds |
| Started | Aug 21 08:02:11 AM UTC 24 |
| Finished | Aug 21 08:02:14 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2380056869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2380056869 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_in_iso.1371800487 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 167510384 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:02:11 AM UTC 24 |
| Finished | Aug 21 08:02:13 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1371800487 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1371800487 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_in_stall.3865538732 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 144576346 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:02:12 AM UTC 24 |
| Finished | Aug 21 08:02:14 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3865538732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3865538732 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_in_trans.1160416123 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 170003349 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:02:12 AM UTC 24 |
| Finished | Aug 21 08:02:14 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1160416123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1160416123 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_invalid_sync.836870821 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 3895526128 ps |
| CPU time | 27.03 seconds |
| Started | Aug 21 08:02:11 AM UTC 24 |
| Finished | Aug 21 08:02:39 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=836870821 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.836870821 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_iso_retraction.4002681945 |
| Short name | T2948 |
| Test name | |
| Test status | |
| Simulation time | 12388334727 ps |
| CPU time | 142.18 seconds |
| Started | Aug 21 08:02:12 AM UTC 24 |
| Finished | Aug 21 08:04:37 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4002681945 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.4002681945 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_link_in_err.4140916720 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 204208332 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:02:12 AM UTC 24 |
| Finished | Aug 21 08:02:15 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4140916720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.4140916720 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_link_resume.3577253796 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 9602272387 ps |
| CPU time | 14.2 seconds |
| Started | Aug 21 08:02:13 AM UTC 24 |
| Finished | Aug 21 08:02:29 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3577253796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.3577253796 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_link_suspend.4270512527 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 10354643883 ps |
| CPU time | 14.69 seconds |
| Started | Aug 21 08:02:13 AM UTC 24 |
| Finished | Aug 21 08:02:29 AM UTC 24 |
| Peak memory | 218404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4270512527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.4270512527 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_low_speed_traffic.797048696 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 3435345996 ps |
| CPU time | 31.55 seconds |
| Started | Aug 21 08:02:13 AM UTC 24 |
| Finished | Aug 21 08:02:46 AM UTC 24 |
| Peak memory | 235136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=797048696 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.797048696 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_max_inter_pkt_delay.2736460312 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 1597473472 ps |
| CPU time | 42.45 seconds |
| Started | Aug 21 08:02:15 AM UTC 24 |
| Finished | Aug 21 08:02:59 AM UTC 24 |
| Peak memory | 230404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2736460312 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.2736460312 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_max_length_in_transaction.874014409 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 237113782 ps |
| CPU time | 1.7 seconds |
| Started | Aug 21 08:02:15 AM UTC 24 |
| Finished | Aug 21 08:02:18 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=874014409 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.874014409 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_max_length_out_transaction.121793153 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 198737367 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:02:15 AM UTC 24 |
| Finished | Aug 21 08:02:17 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=121793153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.121793153 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_min_inter_pkt_delay.2268876635 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 3732520503 ps |
| CPU time | 96.16 seconds |
| Started | Aug 21 08:02:15 AM UTC 24 |
| Finished | Aug 21 08:03:53 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2268876635 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.2268876635 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_min_length_in_transaction.1831565077 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 163948135 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:02:15 AM UTC 24 |
| Finished | Aug 21 08:02:17 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1831565077 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1831565077 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_min_length_out_transaction.148295545 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 209990641 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 08:02:15 AM UTC 24 |
| Finished | Aug 21 08:02:17 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=148295545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.148295545 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_nak_trans.3559027575 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 173294255 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:02:17 AM UTC 24 |
| Finished | Aug 21 08:02:19 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3559027575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3559027575 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_out_iso.3725944444 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 164693432 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:02:17 AM UTC 24 |
| Finished | Aug 21 08:02:19 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3725944444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.3725944444 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_out_stall.329951929 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 225887239 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:02:17 AM UTC 24 |
| Finished | Aug 21 08:02:19 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=329951929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.329951929 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_out_trans_nak.3561041421 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 263952853 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 08:02:17 AM UTC 24 |
| Finished | Aug 21 08:02:19 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3561041421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3561041421 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_pending_in_trans.986135845 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 148908615 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 08:02:17 AM UTC 24 |
| Finished | Aug 21 08:02:19 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=986135845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.986135845 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_phy_config_pinflip.1479920631 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 253397386 ps |
| CPU time | 1.75 seconds |
| Started | Aug 21 08:02:17 AM UTC 24 |
| Finished | Aug 21 08:02:20 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1479920631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.1479920631 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_phy_config_usb_ref_disable.517649195 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 147687463 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:02:19 AM UTC 24 |
| Finished | Aug 21 08:02:21 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=517649195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.517649195 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_phy_pins_sense.62199800 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 36843875 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:02:19 AM UTC 24 |
| Finished | Aug 21 08:02:21 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=62199800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.62199800 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_pkt_buffer.867166705 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 24024101649 ps |
| CPU time | 57.12 seconds |
| Started | Aug 21 08:02:19 AM UTC 24 |
| Finished | Aug 21 08:03:18 AM UTC 24 |
| Peak memory | 228512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=867166705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.867166705 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_pkt_received.2359526730 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 152791708 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:02:19 AM UTC 24 |
| Finished | Aug 21 08:02:21 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2359526730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2359526730 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_pkt_sent.1362740873 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 166440934 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:02:19 AM UTC 24 |
| Finished | Aug 21 08:02:22 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1362740873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1362740873 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_random_length_in_transaction.746282233 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 228677153 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 08:02:19 AM UTC 24 |
| Finished | Aug 21 08:02:21 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=746282233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.746282233 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_random_length_out_transaction.543655541 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 162873314 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 08:02:19 AM UTC 24 |
| Finished | Aug 21 08:02:21 AM UTC 24 |
| Peak memory | 216528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=543655541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.543655541 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_rx_crc_err.976631133 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 172307011 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 08:02:19 AM UTC 24 |
| Finished | Aug 21 08:02:21 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=976631133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.976631133 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_rx_full.685335290 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 252143475 ps |
| CPU time | 1.85 seconds |
| Started | Aug 21 08:02:19 AM UTC 24 |
| Finished | Aug 21 08:02:22 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=685335290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_full.685335290 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_setup_stage.2286911257 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 162098456 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:02:21 AM UTC 24 |
| Finished | Aug 21 08:02:23 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2286911257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2286911257 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_setup_trans_ignored.463600466 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 230099894 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:02:21 AM UTC 24 |
| Finished | Aug 21 08:02:23 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=463600466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.463600466 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_smoke.146150399 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 232455519 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 08:02:21 AM UTC 24 |
| Finished | Aug 21 08:02:23 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=146150399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.146150399 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_spurious_pids_ignored.4275188287 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 1603471801 ps |
| CPU time | 38.52 seconds |
| Started | Aug 21 08:02:21 AM UTC 24 |
| Finished | Aug 21 08:03:01 AM UTC 24 |
| Peak memory | 230420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4275188287 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.4275188287 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_stall_priority_over_nak.605452919 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 183642118 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:02:21 AM UTC 24 |
| Finished | Aug 21 08:02:23 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=605452919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20 24_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.605452919 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_stall_trans.413505830 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 188393666 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:02:21 AM UTC 24 |
| Finished | Aug 21 08:02:23 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=413505830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.413505830 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_stream_len_max.819834050 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 950576246 ps |
| CPU time | 2.72 seconds |
| Started | Aug 21 08:02:21 AM UTC 24 |
| Finished | Aug 21 08:02:25 AM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=819834050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.819834050 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_streaming_out.3302710057 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 2434368110 ps |
| CPU time | 60.16 seconds |
| Started | Aug 21 08:02:21 AM UTC 24 |
| Finished | Aug 21 08:03:23 AM UTC 24 |
| Peak memory | 228612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3302710057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3302710057 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_timeout_missing_host_handshake.3386215049 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 844230227 ps |
| CPU time | 17.06 seconds |
| Started | Aug 21 08:02:09 AM UTC 24 |
| Finished | Aug 21 08:02:27 AM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3386215049 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing _host_handshake.3386215049 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/37.usbdev_tx_rx_disruption.3984559264 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 528016410 ps |
| CPU time | 1.94 seconds |
| Started | Aug 21 08:02:22 AM UTC 24 |
| Finished | Aug 21 08:02:25 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3984559264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.usbdev_tx_rx_disruption.3984559264 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/37.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/370.usbdev_tx_rx_disruption.1481619344 |
| Short name | T3463 |
| Test name | |
| Test status | |
| Simulation time | 601276597 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:07:01 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1481619344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 370.usbdev_tx_rx_disruption.1481619344 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/370.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/371.usbdev_tx_rx_disruption.2870506271 |
| Short name | T3466 |
| Test name | |
| Test status | |
| Simulation time | 592104910 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:07:01 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2870506271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 371.usbdev_tx_rx_disruption.2870506271 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/371.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/372.usbdev_tx_rx_disruption.942833191 |
| Short name | T3468 |
| Test name | |
| Test status | |
| Simulation time | 522983870 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:07:01 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=942833191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 372.usbdev_tx_rx_disruption.942833191 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/372.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/373.usbdev_tx_rx_disruption.30317606 |
| Short name | T3464 |
| Test name | |
| Test status | |
| Simulation time | 482652356 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:07:02 AM UTC 24 |
| Finished | Aug 21 08:07:11 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=30317606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 373.usbdev_tx_rx_disruption.30317606 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/373.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/374.usbdev_tx_rx_disruption.3488122196 |
| Short name | T3575 |
| Test name | |
| Test status | |
| Simulation time | 522390772 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 08:07:02 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 216300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3488122196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 374.usbdev_tx_rx_disruption.3488122196 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/374.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/375.usbdev_tx_rx_disruption.3886502585 |
| Short name | T3571 |
| Test name | |
| Test status | |
| Simulation time | 530517931 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:07:02 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 217688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3886502585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 375.usbdev_tx_rx_disruption.3886502585 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/375.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/376.usbdev_tx_rx_disruption.3458505135 |
| Short name | T3520 |
| Test name | |
| Test status | |
| Simulation time | 501422365 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:07:07 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3458505135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 376.usbdev_tx_rx_disruption.3458505135 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/376.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/377.usbdev_tx_rx_disruption.3343991045 |
| Short name | T3512 |
| Test name | |
| Test status | |
| Simulation time | 482167265 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:07:07 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3343991045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 377.usbdev_tx_rx_disruption.3343991045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/377.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/378.usbdev_tx_rx_disruption.450159260 |
| Short name | T3514 |
| Test name | |
| Test status | |
| Simulation time | 506701771 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:07:07 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=450159260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 378.usbdev_tx_rx_disruption.450159260 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/378.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/379.usbdev_tx_rx_disruption.2396859551 |
| Short name | T3513 |
| Test name | |
| Test status | |
| Simulation time | 571746887 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:07:07 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2396859551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 379.usbdev_tx_rx_disruption.2396859551 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/379.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_alert_test.94981477 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 63509608 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:02:35 AM UTC 24 |
| Finished | Aug 21 08:02:38 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=94981477 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.94981477 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_aon_wake_disconnect.2838239016 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 4769769796 ps |
| CPU time | 10.13 seconds |
| Started | Aug 21 08:02:22 AM UTC 24 |
| Finished | Aug 21 08:02:34 AM UTC 24 |
| Peak memory | 228448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2838239016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbd ev_aon_wake_disconnect.2838239016 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_aon_wake_reset.1498799793 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 19452575960 ps |
| CPU time | 29.89 seconds |
| Started | Aug 21 08:02:22 AM UTC 24 |
| Finished | Aug 21 08:02:54 AM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1498799793 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1498799793 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_aon_wake_resume.4042287694 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 25618806933 ps |
| CPU time | 39.37 seconds |
| Started | Aug 21 08:02:23 AM UTC 24 |
| Finished | Aug 21 08:03:03 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4042287694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbd ev_aon_wake_resume.4042287694 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_av_buffer.2553150021 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 151825633 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:02:23 AM UTC 24 |
| Finished | Aug 21 08:02:25 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2553150021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2553150021 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_bitstuff_err.2876945412 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 142897688 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 08:02:23 AM UTC 24 |
| Finished | Aug 21 08:02:25 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2876945412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2876945412 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_data_toggle_clear.786416184 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 206087805 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 08:02:23 AM UTC 24 |
| Finished | Aug 21 08:02:25 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=786416184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.786416184 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_data_toggle_restore.1192398287 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 1209801243 ps |
| CPU time | 3.86 seconds |
| Started | Aug 21 08:02:23 AM UTC 24 |
| Finished | Aug 21 08:02:28 AM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1192398287 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1192398287 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_device_address.3419050343 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 32493295330 ps |
| CPU time | 57.86 seconds |
| Started | Aug 21 08:02:24 AM UTC 24 |
| Finished | Aug 21 08:03:24 AM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3419050343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3419050343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_device_timeout.1892658633 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 1092240163 ps |
| CPU time | 8.65 seconds |
| Started | Aug 21 08:02:24 AM UTC 24 |
| Finished | Aug 21 08:02:34 AM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1892658633 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.1892658633 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_disable_endpoint.1213973039 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 681433010 ps |
| CPU time | 2.29 seconds |
| Started | Aug 21 08:02:24 AM UTC 24 |
| Finished | Aug 21 08:02:28 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1213973039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.1213973039 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_disconnected.153124689 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 152729481 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:02:24 AM UTC 24 |
| Finished | Aug 21 08:02:27 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=153124689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.153124689 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_enable.4071711925 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 33663959 ps |
| CPU time | 1 seconds |
| Started | Aug 21 08:02:24 AM UTC 24 |
| Finished | Aug 21 08:02:26 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4071711925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.4071711925 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_endpoint_access.916007365 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 980415640 ps |
| CPU time | 2.8 seconds |
| Started | Aug 21 08:02:24 AM UTC 24 |
| Finished | Aug 21 08:02:28 AM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=916007365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.916007365 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_endpoint_types.2834328631 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 195192636 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:02:26 AM UTC 24 |
| Finished | Aug 21 08:02:28 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2834328631 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_types.2834328631 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_fifo_rst.1883453789 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 171672809 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:02:26 AM UTC 24 |
| Finished | Aug 21 08:02:28 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1883453789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1883453789 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_in_iso.2827343686 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 221113146 ps |
| CPU time | 1.78 seconds |
| Started | Aug 21 08:02:26 AM UTC 24 |
| Finished | Aug 21 08:02:29 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2827343686 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2827343686 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_in_stall.1249084343 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 139623162 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:02:26 AM UTC 24 |
| Finished | Aug 21 08:02:28 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1249084343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1249084343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_in_trans.3733587127 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 223799423 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 08:02:26 AM UTC 24 |
| Finished | Aug 21 08:02:28 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3733587127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3733587127 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_invalid_sync.3598492340 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 4223315122 ps |
| CPU time | 28.61 seconds |
| Started | Aug 21 08:02:26 AM UTC 24 |
| Finished | Aug 21 08:02:56 AM UTC 24 |
| Peak memory | 230724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3598492340 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.3598492340 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_iso_retraction.4182644494 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 10047816532 ps |
| CPU time | 66.69 seconds |
| Started | Aug 21 08:02:26 AM UTC 24 |
| Finished | Aug 21 08:03:34 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4182644494 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.4182644494 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_link_in_err.315908730 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 238773129 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:02:27 AM UTC 24 |
| Finished | Aug 21 08:02:30 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=315908730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.315908730 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_link_resume.2944904542 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 12874695052 ps |
| CPU time | 21.27 seconds |
| Started | Aug 21 08:02:27 AM UTC 24 |
| Finished | Aug 21 08:02:50 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2944904542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.2944904542 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_link_suspend.1661900360 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 9810960538 ps |
| CPU time | 15.13 seconds |
| Started | Aug 21 08:02:27 AM UTC 24 |
| Finished | Aug 21 08:02:44 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1661900360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1661900360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_low_speed_traffic.1428504193 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 3054874159 ps |
| CPU time | 28.27 seconds |
| Started | Aug 21 08:02:28 AM UTC 24 |
| Finished | Aug 21 08:02:57 AM UTC 24 |
| Peak memory | 230512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1428504193 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1428504193 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_max_inter_pkt_delay.1518660979 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 3212051769 ps |
| CPU time | 24.31 seconds |
| Started | Aug 21 08:02:28 AM UTC 24 |
| Finished | Aug 21 08:02:53 AM UTC 24 |
| Peak memory | 235120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1518660979 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.1518660979 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_max_length_in_transaction.1012595755 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 237896343 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:02:28 AM UTC 24 |
| Finished | Aug 21 08:02:30 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1012595755 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1012595755 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_max_length_out_transaction.892736221 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 198477078 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 08:02:29 AM UTC 24 |
| Finished | Aug 21 08:02:31 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=892736221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.892736221 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_min_inter_pkt_delay.1387910729 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 2288523982 ps |
| CPU time | 21.56 seconds |
| Started | Aug 21 08:02:29 AM UTC 24 |
| Finished | Aug 21 08:02:52 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1387910729 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1387910729 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_min_length_in_transaction.2845929206 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 172032425 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:02:29 AM UTC 24 |
| Finished | Aug 21 08:02:32 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2845929206 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.2845929206 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_min_length_out_transaction.2552432248 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 197320239 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 08:02:29 AM UTC 24 |
| Finished | Aug 21 08:02:31 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2552432248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2552432248 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_nak_trans.3685025194 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 216458043 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:02:29 AM UTC 24 |
| Finished | Aug 21 08:02:32 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3685025194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3685025194 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_out_iso.2575270336 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 157992842 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 08:02:29 AM UTC 24 |
| Finished | Aug 21 08:02:32 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2575270336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2575270336 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_out_stall.3091947242 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 166876424 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:02:29 AM UTC 24 |
| Finished | Aug 21 08:02:32 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3091947242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3091947242 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_out_trans_nak.2854658512 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 218617596 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:02:29 AM UTC 24 |
| Finished | Aug 21 08:02:31 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2854658512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2854658512 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_pending_in_trans.706856136 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 150507610 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:02:30 AM UTC 24 |
| Finished | Aug 21 08:02:33 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=706856136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.706856136 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_phy_config_pinflip.2213367223 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 243810516 ps |
| CPU time | 1.7 seconds |
| Started | Aug 21 08:02:30 AM UTC 24 |
| Finished | Aug 21 08:02:33 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2213367223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2213367223 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_phy_config_usb_ref_disable.4074938053 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 145406857 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:02:31 AM UTC 24 |
| Finished | Aug 21 08:02:33 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4074938053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.4074938053 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_phy_pins_sense.1583009132 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 60331266 ps |
| CPU time | 0.88 seconds |
| Started | Aug 21 08:02:32 AM UTC 24 |
| Finished | Aug 21 08:02:34 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1583009132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1583009132 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_pkt_buffer.18855345 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 7866714138 ps |
| CPU time | 24.02 seconds |
| Started | Aug 21 08:02:32 AM UTC 24 |
| Finished | Aug 21 08:02:58 AM UTC 24 |
| Peak memory | 228512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18855345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.18855345 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_pkt_received.4235126805 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 206210914 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:02:32 AM UTC 24 |
| Finished | Aug 21 08:02:35 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4235126805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.4235126805 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_pkt_sent.4155395574 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 240780265 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 08:02:32 AM UTC 24 |
| Finished | Aug 21 08:02:35 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4155395574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.4155395574 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_random_length_in_transaction.3356628592 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 198815031 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:02:32 AM UTC 24 |
| Finished | Aug 21 08:02:35 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3356628592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.3356628592 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_random_length_out_transaction.3282581418 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 250393050 ps |
| CPU time | 1.72 seconds |
| Started | Aug 21 08:02:32 AM UTC 24 |
| Finished | Aug 21 08:02:35 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3282581418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3282581418 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_rx_crc_err.3048378752 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 184473220 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:02:32 AM UTC 24 |
| Finished | Aug 21 08:02:35 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3048378752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3048378752 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_rx_full.3809034260 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 430572128 ps |
| CPU time | 2.04 seconds |
| Started | Aug 21 08:02:32 AM UTC 24 |
| Finished | Aug 21 08:02:36 AM UTC 24 |
| Peak memory | 218068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3809034260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_full.3809034260 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_setup_stage.1146892486 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 157075736 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:02:33 AM UTC 24 |
| Finished | Aug 21 08:02:35 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1146892486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1146892486 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_setup_trans_ignored.249304127 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 164855868 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:02:33 AM UTC 24 |
| Finished | Aug 21 08:02:35 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=249304127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.249304127 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_smoke.3232439483 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 205854454 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 08:02:33 AM UTC 24 |
| Finished | Aug 21 08:02:35 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3232439483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3232439483 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_spurious_pids_ignored.3113673045 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 2146775146 ps |
| CPU time | 18.68 seconds |
| Started | Aug 21 08:02:34 AM UTC 24 |
| Finished | Aug 21 08:02:54 AM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3113673045 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.3113673045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_stall_priority_over_nak.1218143855 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 153368742 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:02:34 AM UTC 24 |
| Finished | Aug 21 08:02:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1218143855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1218143855 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_stall_trans.3170969422 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 169490684 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:02:34 AM UTC 24 |
| Finished | Aug 21 08:02:36 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3170969422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3170969422 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_stream_len_max.16714727 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 1222175419 ps |
| CPU time | 4.65 seconds |
| Started | Aug 21 08:02:35 AM UTC 24 |
| Finished | Aug 21 08:02:41 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16714727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.16714727 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_streaming_out.3657209228 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 2686283206 ps |
| CPU time | 26.27 seconds |
| Started | Aug 21 08:02:35 AM UTC 24 |
| Finished | Aug 21 08:03:03 AM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3657209228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.3657209228 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_timeout_missing_host_handshake.3599065089 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 2047406104 ps |
| CPU time | 17.04 seconds |
| Started | Aug 21 08:02:24 AM UTC 24 |
| Finished | Aug 21 08:02:42 AM UTC 24 |
| Peak memory | 218040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3599065089 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing _host_handshake.3599065089 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/38.usbdev_tx_rx_disruption.3935152630 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 562666327 ps |
| CPU time | 2.15 seconds |
| Started | Aug 21 08:02:35 AM UTC 24 |
| Finished | Aug 21 08:02:38 AM UTC 24 |
| Peak memory | 218128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3935152630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 38.usbdev_tx_rx_disruption.3935152630 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/38.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/380.usbdev_tx_rx_disruption.3846298284 |
| Short name | T3526 |
| Test name | |
| Test status | |
| Simulation time | 625718685 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 08:07:07 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3846298284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 380.usbdev_tx_rx_disruption.3846298284 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/380.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/381.usbdev_tx_rx_disruption.1259046080 |
| Short name | T3518 |
| Test name | |
| Test status | |
| Simulation time | 450052755 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:07:07 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1259046080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 381.usbdev_tx_rx_disruption.1259046080 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/381.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/382.usbdev_tx_rx_disruption.2615696152 |
| Short name | T3477 |
| Test name | |
| Test status | |
| Simulation time | 512741218 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:07:10 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2615696152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 382.usbdev_tx_rx_disruption.2615696152 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/382.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/383.usbdev_tx_rx_disruption.1675466719 |
| Short name | T3480 |
| Test name | |
| Test status | |
| Simulation time | 486010189 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:07:10 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1675466719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 383.usbdev_tx_rx_disruption.1675466719 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/383.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/384.usbdev_tx_rx_disruption.889464785 |
| Short name | T3528 |
| Test name | |
| Test status | |
| Simulation time | 612455135 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:28 AM UTC 24 |
| Peak memory | 216080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=889464785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 384.usbdev_tx_rx_disruption.889464785 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/384.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/385.usbdev_tx_rx_disruption.982435091 |
| Short name | T3527 |
| Test name | |
| Test status | |
| Simulation time | 459832467 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:28 AM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=982435091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 385.usbdev_tx_rx_disruption.982435091 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/385.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/386.usbdev_tx_rx_disruption.2454164577 |
| Short name | T3530 |
| Test name | |
| Test status | |
| Simulation time | 504521836 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:28 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2454164577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 386.usbdev_tx_rx_disruption.2454164577 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/386.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/387.usbdev_tx_rx_disruption.1777763675 |
| Short name | T3529 |
| Test name | |
| Test status | |
| Simulation time | 584100026 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:28 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1777763675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 387.usbdev_tx_rx_disruption.1777763675 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/387.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/388.usbdev_tx_rx_disruption.3524044163 |
| Short name | T3532 |
| Test name | |
| Test status | |
| Simulation time | 621773759 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:28 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3524044163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 388.usbdev_tx_rx_disruption.3524044163 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/388.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/389.usbdev_tx_rx_disruption.3302378092 |
| Short name | T3475 |
| Test name | |
| Test status | |
| Simulation time | 522611416 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3302378092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 389.usbdev_tx_rx_disruption.3302378092 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/389.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_alert_test.3064696985 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 107997064 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 08:02:54 AM UTC 24 |
| Finished | Aug 21 08:02:56 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3064696985 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.3064696985 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_aon_wake_disconnect.4185587838 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 10009703450 ps |
| CPU time | 16.74 seconds |
| Started | Aug 21 08:02:37 AM UTC 24 |
| Finished | Aug 21 08:02:56 AM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4185587838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbd ev_aon_wake_disconnect.4185587838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_aon_wake_reset.410129595 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 13900851505 ps |
| CPU time | 21.13 seconds |
| Started | Aug 21 08:02:37 AM UTC 24 |
| Finished | Aug 21 08:03:00 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=410129595 -assert nopostp roc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.410129595 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_aon_wake_resume.197958060 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 28502177488 ps |
| CPU time | 34.31 seconds |
| Started | Aug 21 08:02:37 AM UTC 24 |
| Finished | Aug 21 08:03:14 AM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=197958060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbde v_aon_wake_resume.197958060 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_av_buffer.1140858229 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 164951219 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:02:37 AM UTC 24 |
| Finished | Aug 21 08:02:41 AM UTC 24 |
| Peak memory | 215884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1140858229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1140858229 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_bitstuff_err.3581772556 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 149014168 ps |
| CPU time | 0.94 seconds |
| Started | Aug 21 08:02:37 AM UTC 24 |
| Finished | Aug 21 08:02:40 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3581772556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.3581772556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_data_toggle_clear.2082103469 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 550333180 ps |
| CPU time | 2.8 seconds |
| Started | Aug 21 08:02:37 AM UTC 24 |
| Finished | Aug 21 08:02:42 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2082103469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.2082103469 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_data_toggle_restore.4288385061 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 1283404563 ps |
| CPU time | 5.58 seconds |
| Started | Aug 21 08:02:37 AM UTC 24 |
| Finished | Aug 21 08:02:45 AM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4288385061 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.4288385061 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_device_address.148229278 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 48523751928 ps |
| CPU time | 83.11 seconds |
| Started | Aug 21 08:02:37 AM UTC 24 |
| Finished | Aug 21 08:04:03 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=148229278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.148229278 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_device_timeout.394826490 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 166827192 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:02:37 AM UTC 24 |
| Finished | Aug 21 08:02:41 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=394826490 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.394826490 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_disable_endpoint.2865024008 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 605172558 ps |
| CPU time | 1.87 seconds |
| Started | Aug 21 08:02:39 AM UTC 24 |
| Finished | Aug 21 08:02:42 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2865024008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2865024008 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_disconnected.2183458017 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 168241088 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:02:39 AM UTC 24 |
| Finished | Aug 21 08:02:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2183458017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2183458017 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_enable.33976161 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 55441850 ps |
| CPU time | 0.91 seconds |
| Started | Aug 21 08:02:39 AM UTC 24 |
| Finished | Aug 21 08:02:41 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33976161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.33976161 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_endpoint_access.4104469730 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 806510986 ps |
| CPU time | 2.69 seconds |
| Started | Aug 21 08:02:40 AM UTC 24 |
| Finished | Aug 21 08:02:44 AM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4104469730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.4104469730 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_endpoint_types.3328588436 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 310415304 ps |
| CPU time | 1.92 seconds |
| Started | Aug 21 08:02:40 AM UTC 24 |
| Finished | Aug 21 08:02:43 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3328588436 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_types.3328588436 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_fifo_rst.1670151773 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 291082685 ps |
| CPU time | 2.16 seconds |
| Started | Aug 21 08:02:42 AM UTC 24 |
| Finished | Aug 21 08:02:45 AM UTC 24 |
| Peak memory | 218240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1670151773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1670151773 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_in_iso.1514025864 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 285398421 ps |
| CPU time | 1.72 seconds |
| Started | Aug 21 08:02:42 AM UTC 24 |
| Finished | Aug 21 08:02:45 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1514025864 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1514025864 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_in_stall.659369991 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 147806420 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:02:42 AM UTC 24 |
| Finished | Aug 21 08:02:45 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=659369991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.659369991 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_in_trans.2860795428 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 206736933 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:02:42 AM UTC 24 |
| Finished | Aug 21 08:02:45 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2860795428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2860795428 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_invalid_sync.3489145088 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 2335868413 ps |
| CPU time | 16.32 seconds |
| Started | Aug 21 08:02:42 AM UTC 24 |
| Finished | Aug 21 08:03:00 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3489145088 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.3489145088 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_iso_retraction.1607101341 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 13341494872 ps |
| CPU time | 93.05 seconds |
| Started | Aug 21 08:02:42 AM UTC 24 |
| Finished | Aug 21 08:04:18 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1607101341 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.1607101341 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_link_in_err.1591124152 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 287642599 ps |
| CPU time | 1.76 seconds |
| Started | Aug 21 08:02:42 AM UTC 24 |
| Finished | Aug 21 08:02:45 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1591124152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.1591124152 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_link_resume.756289 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 8312541218 ps |
| CPU time | 13.4 seconds |
| Started | Aug 21 08:02:42 AM UTC 24 |
| Finished | Aug 21 08:02:57 AM UTC 24 |
| Peak memory | 228412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=756289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.756289 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_link_suspend.2989221824 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 8810834163 ps |
| CPU time | 12.49 seconds |
| Started | Aug 21 08:02:43 AM UTC 24 |
| Finished | Aug 21 08:02:57 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2989221824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.2989221824 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_low_speed_traffic.1260106549 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 3718347122 ps |
| CPU time | 95.26 seconds |
| Started | Aug 21 08:02:43 AM UTC 24 |
| Finished | Aug 21 08:04:21 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1260106549 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.1260106549 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_max_inter_pkt_delay.2979337360 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 1451708829 ps |
| CPU time | 35.96 seconds |
| Started | Aug 21 08:02:43 AM UTC 24 |
| Finished | Aug 21 08:03:21 AM UTC 24 |
| Peak memory | 228276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2979337360 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.2979337360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_max_length_in_transaction.3753676521 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 241005313 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:02:44 AM UTC 24 |
| Finished | Aug 21 08:02:46 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3753676521 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.3753676521 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_max_length_out_transaction.187366486 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 199107470 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:02:44 AM UTC 24 |
| Finished | Aug 21 08:02:46 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=187366486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.187366486 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_min_inter_pkt_delay.2443740487 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 2174640113 ps |
| CPU time | 20.47 seconds |
| Started | Aug 21 08:02:45 AM UTC 24 |
| Finished | Aug 21 08:03:07 AM UTC 24 |
| Peak memory | 228488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2443740487 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.2443740487 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_min_length_in_transaction.3864414383 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 162122731 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:02:45 AM UTC 24 |
| Finished | Aug 21 08:02:47 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3864414383 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3864414383 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_min_length_out_transaction.3502298539 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 142939202 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:02:47 AM UTC 24 |
| Finished | Aug 21 08:02:49 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3502298539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3502298539 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_nak_trans.823386767 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 202645866 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 08:02:47 AM UTC 24 |
| Finished | Aug 21 08:02:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=823386767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.823386767 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_out_iso.1826028654 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 171526664 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:02:47 AM UTC 24 |
| Finished | Aug 21 08:02:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1826028654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1826028654 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_out_stall.2224526963 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 169274772 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:02:47 AM UTC 24 |
| Finished | Aug 21 08:02:49 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2224526963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2224526963 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_out_trans_nak.2245970419 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 164822065 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 08:02:47 AM UTC 24 |
| Finished | Aug 21 08:02:49 AM UTC 24 |
| Peak memory | 216344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2245970419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2245970419 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_pending_in_trans.1220626984 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 152735975 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:02:47 AM UTC 24 |
| Finished | Aug 21 08:02:49 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1220626984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1220626984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_phy_config_pinflip.3020782068 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 218600396 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 08:02:47 AM UTC 24 |
| Finished | Aug 21 08:02:49 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3020782068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3020782068 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_phy_config_usb_ref_disable.2268200964 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 169277225 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:02:47 AM UTC 24 |
| Finished | Aug 21 08:02:49 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2268200964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2268200964 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_phy_pins_sense.1970346532 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 37635276 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:02:47 AM UTC 24 |
| Finished | Aug 21 08:02:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1970346532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1970346532 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_pkt_buffer.2623566884 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 18684462886 ps |
| CPU time | 45.86 seconds |
| Started | Aug 21 08:02:48 AM UTC 24 |
| Finished | Aug 21 08:03:36 AM UTC 24 |
| Peak memory | 228576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2623566884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2623566884 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_pkt_received.1836861055 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 210162420 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:02:48 AM UTC 24 |
| Finished | Aug 21 08:02:51 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1836861055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1836861055 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_pkt_sent.3589540844 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 187277509 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:02:48 AM UTC 24 |
| Finished | Aug 21 08:02:51 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3589540844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3589540844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_random_length_in_transaction.3400988508 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 243234043 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:02:49 AM UTC 24 |
| Finished | Aug 21 08:02:52 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3400988508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3400988508 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_random_length_out_transaction.125030395 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 173840631 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:02:51 AM UTC 24 |
| Finished | Aug 21 08:02:53 AM UTC 24 |
| Peak memory | 216528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=125030395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.125030395 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_rx_crc_err.3681492406 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 133209320 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:02:51 AM UTC 24 |
| Finished | Aug 21 08:02:53 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3681492406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3681492406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_rx_full.2153308397 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 285076449 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:02:51 AM UTC 24 |
| Finished | Aug 21 08:02:53 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2153308397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_full.2153308397 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_setup_stage.3922650092 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 213766695 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:02:51 AM UTC 24 |
| Finished | Aug 21 08:02:53 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3922650092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3922650092 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_setup_trans_ignored.4048091651 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 149814448 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 08:02:51 AM UTC 24 |
| Finished | Aug 21 08:02:53 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4048091651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.4048091651 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_smoke.1741405324 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 204282611 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 08:02:51 AM UTC 24 |
| Finished | Aug 21 08:02:54 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1741405324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1741405324 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_spurious_pids_ignored.2185061604 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 1760993277 ps |
| CPU time | 41.1 seconds |
| Started | Aug 21 08:02:51 AM UTC 24 |
| Finished | Aug 21 08:03:34 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2185061604 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.2185061604 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_stall_priority_over_nak.2744448998 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 240040134 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:02:51 AM UTC 24 |
| Finished | Aug 21 08:02:54 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2744448998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2744448998 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_stall_trans.2067032732 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 247574365 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:02:52 AM UTC 24 |
| Finished | Aug 21 08:02:55 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2067032732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2067032732 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_stream_len_max.4085918675 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 1000611050 ps |
| CPU time | 3.41 seconds |
| Started | Aug 21 08:02:52 AM UTC 24 |
| Finished | Aug 21 08:02:57 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4085918675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.4085918675 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_streaming_out.3208426864 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 2962097461 ps |
| CPU time | 26.88 seconds |
| Started | Aug 21 08:02:52 AM UTC 24 |
| Finished | Aug 21 08:03:20 AM UTC 24 |
| Peak memory | 230516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3208426864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.3208426864 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_timeout_missing_host_handshake.755291960 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 2213291302 ps |
| CPU time | 14.87 seconds |
| Started | Aug 21 08:02:37 AM UTC 24 |
| Finished | Aug 21 08:02:55 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=755291960 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_ host_handshake.755291960 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/39.usbdev_tx_rx_disruption.2341209730 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 512583486 ps |
| CPU time | 1.9 seconds |
| Started | Aug 21 08:02:52 AM UTC 24 |
| Finished | Aug 21 08:02:55 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2341209730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.usbdev_tx_rx_disruption.2341209730 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/39.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/390.usbdev_tx_rx_disruption.2976602806 |
| Short name | T3470 |
| Test name | |
| Test status | |
| Simulation time | 526846932 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2976602806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 390.usbdev_tx_rx_disruption.2976602806 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/390.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/391.usbdev_tx_rx_disruption.49496842 |
| Short name | T3476 |
| Test name | |
| Test status | |
| Simulation time | 530406288 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=49496842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 391.usbdev_tx_rx_disruption.49496842 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/391.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/392.usbdev_tx_rx_disruption.1069484962 |
| Short name | T3472 |
| Test name | |
| Test status | |
| Simulation time | 484502111 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1069484962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 392.usbdev_tx_rx_disruption.1069484962 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/392.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/393.usbdev_tx_rx_disruption.1879483335 |
| Short name | T3473 |
| Test name | |
| Test status | |
| Simulation time | 539076017 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1879483335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 393.usbdev_tx_rx_disruption.1879483335 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/393.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/394.usbdev_tx_rx_disruption.1371464865 |
| Short name | T3471 |
| Test name | |
| Test status | |
| Simulation time | 563974024 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1371464865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 394.usbdev_tx_rx_disruption.1371464865 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/394.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/395.usbdev_tx_rx_disruption.3266515747 |
| Short name | T3474 |
| Test name | |
| Test status | |
| Simulation time | 465651299 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3266515747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 395.usbdev_tx_rx_disruption.3266515747 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/395.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/396.usbdev_tx_rx_disruption.2470988771 |
| Short name | T3481 |
| Test name | |
| Test status | |
| Simulation time | 558019038 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2470988771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 396.usbdev_tx_rx_disruption.2470988771 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/396.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/397.usbdev_tx_rx_disruption.2596079816 |
| Short name | T3482 |
| Test name | |
| Test status | |
| Simulation time | 522251776 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2596079816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 397.usbdev_tx_rx_disruption.2596079816 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/397.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/398.usbdev_tx_rx_disruption.3007559553 |
| Short name | T3479 |
| Test name | |
| Test status | |
| Simulation time | 487677829 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3007559553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 398.usbdev_tx_rx_disruption.3007559553 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/398.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/399.usbdev_tx_rx_disruption.2067088630 |
| Short name | T3485 |
| Test name | |
| Test status | |
| Simulation time | 534916050 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2067088630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 399.usbdev_tx_rx_disruption.2067088630 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/399.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_alert_test.1955137813 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 56850096 ps |
| CPU time | 1 seconds |
| Started | Aug 21 07:52:20 AM UTC 24 |
| Finished | Aug 21 07:52:22 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1955137813 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.1955137813 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_aon_wake_disconnect.4158558911 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 10700061207 ps |
| CPU time | 24.98 seconds |
| Started | Aug 21 07:51:41 AM UTC 24 |
| Finished | Aug 21 07:52:08 AM UTC 24 |
| Peak memory | 218240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4158558911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbde v_aon_wake_disconnect.4158558911 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_aon_wake_reset.3875142556 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 19593580925 ps |
| CPU time | 25.49 seconds |
| Started | Aug 21 07:51:41 AM UTC 24 |
| Finished | Aug 21 07:52:08 AM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3875142556 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.3875142556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_aon_wake_resume.246166556 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 30333633559 ps |
| CPU time | 47.99 seconds |
| Started | Aug 21 07:51:43 AM UTC 24 |
| Finished | Aug 21 07:52:32 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=246166556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev _aon_wake_resume.246166556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_av_buffer.440012247 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 170737944 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:51:43 AM UTC 24 |
| Finished | Aug 21 07:51:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=440012247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.440012247 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_av_empty.454474015 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 194240575 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 07:51:43 AM UTC 24 |
| Finished | Aug 21 07:51:45 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=454474015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.454474015 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_av_empty/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_av_overflow.2860261218 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 140760028 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:51:44 AM UTC 24 |
| Finished | Aug 21 07:51:46 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2860261218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2860261218 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_av_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_bitstuff_err.3825508023 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 145464146 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:51:45 AM UTC 24 |
| Finished | Aug 21 07:51:48 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3825508023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3825508023 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_data_toggle_clear.1063314672 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 378960165 ps |
| CPU time | 2.45 seconds |
| Started | Aug 21 07:51:45 AM UTC 24 |
| Finished | Aug 21 07:51:49 AM UTC 24 |
| Peak memory | 218076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1063314672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.1063314672 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_data_toggle_restore.159886780 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 524369677 ps |
| CPU time | 2.51 seconds |
| Started | Aug 21 07:51:46 AM UTC 24 |
| Finished | Aug 21 07:51:49 AM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=159886780 -assert nopostproc +UVM_TESTNAME=us bdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.159886780 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_device_address.1495283443 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 46574308802 ps |
| CPU time | 95.05 seconds |
| Started | Aug 21 07:51:46 AM UTC 24 |
| Finished | Aug 21 07:53:23 AM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1495283443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.1495283443 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_device_timeout.1321227030 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 6721705899 ps |
| CPU time | 48.81 seconds |
| Started | Aug 21 07:51:46 AM UTC 24 |
| Finished | Aug 21 07:52:37 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1321227030 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.1321227030 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_disable_endpoint.1224919301 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 683689574 ps |
| CPU time | 2.85 seconds |
| Started | Aug 21 07:51:48 AM UTC 24 |
| Finished | Aug 21 07:51:52 AM UTC 24 |
| Peak memory | 218040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1224919301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1224919301 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_disconnected.783442046 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 146407493 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:51:49 AM UTC 24 |
| Finished | Aug 21 07:51:52 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=783442046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.783442046 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_enable.3239428860 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 43274210 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 07:51:51 AM UTC 24 |
| Finished | Aug 21 07:51:53 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3239428860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3239428860 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_endpoint_access.2011374021 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 896138265 ps |
| CPU time | 3.11 seconds |
| Started | Aug 21 07:51:51 AM UTC 24 |
| Finished | Aug 21 07:51:55 AM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2011374021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2011374021 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_endpoint_types.434749644 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 337276856 ps |
| CPU time | 2.09 seconds |
| Started | Aug 21 07:51:51 AM UTC 24 |
| Finished | Aug 21 07:51:54 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=434749644 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_types.434749644 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_fifo_rst.1612756051 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 251017621 ps |
| CPU time | 2.22 seconds |
| Started | Aug 21 07:51:53 AM UTC 24 |
| Finished | Aug 21 07:51:56 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1612756051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1612756051 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_freq_hiclk.2119260611 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 117181965189 ps |
| CPU time | 204.09 seconds |
| Started | Aug 21 07:51:53 AM UTC 24 |
| Finished | Aug 21 07:55:20 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2119260611 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2119260611 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_freq_hiclk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_freq_hiclk_max.3903091772 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 95032905270 ps |
| CPU time | 203.3 seconds |
| Started | Aug 21 07:51:55 AM UTC 24 |
| Finished | Aug 21 07:55:22 AM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_ freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3903091772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_p hase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.3903091772 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_freq_hiclk_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_freq_loclk.1228203082 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 117094575139 ps |
| CPU time | 225.02 seconds |
| Started | Aug 21 07:51:55 AM UTC 24 |
| Finished | Aug 21 07:55:44 AM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1228203082 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1228203082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_freq_loclk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_freq_loclk_max.2104071698 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 96187365391 ps |
| CPU time | 176.55 seconds |
| Started | Aug 21 07:51:55 AM UTC 24 |
| Finished | Aug 21 07:54:54 AM UTC 24 |
| Peak memory | 218372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_d rifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2104071698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_p hase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.2104071698 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_freq_loclk_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_freq_phase.3246071149 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 88241005318 ps |
| CPU time | 152.4 seconds |
| Started | Aug 21 07:51:55 AM UTC 24 |
| Finished | Aug 21 07:54:30 AM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3246071149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.3246071149 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_freq_phase/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_in_iso.2000095799 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 252062287 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:51:56 AM UTC 24 |
| Finished | Aug 21 07:51:59 AM UTC 24 |
| Peak memory | 226632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2000095799 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.2000095799 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_in_stall.630981591 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 142742582 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:51:56 AM UTC 24 |
| Finished | Aug 21 07:51:59 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=630981591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.630981591 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_in_trans.3296681730 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 228383367 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:51:58 AM UTC 24 |
| Finished | Aug 21 07:52:00 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3296681730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3296681730 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_invalid_sync.2778413838 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3836376850 ps |
| CPU time | 104.39 seconds |
| Started | Aug 21 07:51:55 AM UTC 24 |
| Finished | Aug 21 07:53:42 AM UTC 24 |
| Peak memory | 235324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2778413838 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.2778413838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_iso_retraction.936453166 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 6358153636 ps |
| CPU time | 51.59 seconds |
| Started | Aug 21 07:51:58 AM UTC 24 |
| Finished | Aug 21 07:52:51 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=936453166 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.936453166 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_link_in_err.2585097795 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 190675470 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 07:51:59 AM UTC 24 |
| Finished | Aug 21 07:52:01 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2585097795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.2585097795 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_link_suspend.1209719290 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 5372663631 ps |
| CPU time | 8.21 seconds |
| Started | Aug 21 07:52:00 AM UTC 24 |
| Finished | Aug 21 07:52:09 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1209719290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1209719290 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_low_speed_traffic.3454591696 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 3530045927 ps |
| CPU time | 26.26 seconds |
| Started | Aug 21 07:52:01 AM UTC 24 |
| Finished | Aug 21 07:52:29 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3454591696 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3454591696 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_max_inter_pkt_delay.802639953 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 2070307804 ps |
| CPU time | 20.64 seconds |
| Started | Aug 21 07:52:01 AM UTC 24 |
| Finished | Aug 21 07:52:23 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=802639953 -assert nopostproc +UVM _TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.802639953 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_max_length_in_transaction.1615722700 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 250923545 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:52:01 AM UTC 24 |
| Finished | Aug 21 07:52:04 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1615722700 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.1615722700 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_max_length_out_transaction.1306762398 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 195243068 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:52:01 AM UTC 24 |
| Finished | Aug 21 07:52:04 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1306762398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1306762398 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_max_non_iso_usb_traffic.680534706 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3172742288 ps |
| CPU time | 26.33 seconds |
| Started | Aug 21 07:52:01 AM UTC 24 |
| Finished | Aug 21 07:52:29 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=680534706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20 24_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_non_iso_usb_traffic.680534706 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_max_usb_traffic.3406732675 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2502500384 ps |
| CPU time | 78.7 seconds |
| Started | Aug 21 07:52:02 AM UTC 24 |
| Finished | Aug 21 07:53:22 AM UTC 24 |
| Peak memory | 230676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3406732675 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3406732675 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_min_inter_pkt_delay.1067542098 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 2109109085 ps |
| CPU time | 56.35 seconds |
| Started | Aug 21 07:52:05 AM UTC 24 |
| Finished | Aug 21 07:53:03 AM UTC 24 |
| Peak memory | 235116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1067542098 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.1067542098 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_min_length_in_transaction.317139756 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 148525127 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:52:05 AM UTC 24 |
| Finished | Aug 21 07:52:07 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=317139756 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.317139756 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_min_length_out_transaction.732899102 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 146506031 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:52:08 AM UTC 24 |
| Finished | Aug 21 07:52:11 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=732899102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.732899102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_nak_trans.3732500554 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 220504670 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 07:52:08 AM UTC 24 |
| Finished | Aug 21 07:52:11 AM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3732500554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3732500554 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_out_iso.1739934180 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 256552920 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 07:52:08 AM UTC 24 |
| Finished | Aug 21 07:52:11 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1739934180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1739934180 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_out_stall.3577996435 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 193780527 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:52:08 AM UTC 24 |
| Finished | Aug 21 07:52:11 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3577996435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3577996435 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_out_trans_nak.138009247 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 181181156 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:52:10 AM UTC 24 |
| Finished | Aug 21 07:52:12 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=138009247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.138009247 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_pending_in_trans.3279854487 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 178922003 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:52:10 AM UTC 24 |
| Finished | Aug 21 07:52:12 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3279854487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3279854487 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_phy_config_pinflip.1525835218 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 235326473 ps |
| CPU time | 1.72 seconds |
| Started | Aug 21 07:52:10 AM UTC 24 |
| Finished | Aug 21 07:52:13 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1525835218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.1525835218 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_phy_config_rand_bus_type.587730683 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 292286146 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 07:52:11 AM UTC 24 |
| Finished | Aug 21 07:52:14 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=587730683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.587730683 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_phy_config_rand_bus_type/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_phy_config_usb_ref_disable.2859167659 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 156480593 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:52:11 AM UTC 24 |
| Finished | Aug 21 07:52:13 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2859167659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2859167659 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_phy_pins_sense.2489326681 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 35448609 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 07:52:13 AM UTC 24 |
| Finished | Aug 21 07:52:15 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2489326681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2489326681 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_pkt_buffer.1350595842 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 14882215978 ps |
| CPU time | 39.21 seconds |
| Started | Aug 21 07:52:13 AM UTC 24 |
| Finished | Aug 21 07:52:53 AM UTC 24 |
| Peak memory | 232616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1350595842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1350595842 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_pkt_received.2278865189 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 167375451 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:52:13 AM UTC 24 |
| Finished | Aug 21 07:52:15 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2278865189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2278865189 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_pkt_sent.81028525 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 201348662 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 07:52:13 AM UTC 24 |
| Finished | Aug 21 07:52:15 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=81028525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.81028525 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_rand_bus_resets.634703289 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 9082874435 ps |
| CPU time | 210.91 seconds |
| Started | Aug 21 07:52:14 AM UTC 24 |
| Finished | Aug 21 07:55:48 AM UTC 24 |
| Peak memory | 228488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=634703289 -assert nopostproc +UVM_TESTNAME=usbdev_b ase_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.634703289 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_rand_suspends.3848030729 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 10069145866 ps |
| CPU time | 52.69 seconds |
| Started | Aug 21 07:52:14 AM UTC 24 |
| Finished | Aug 21 07:53:08 AM UTC 24 |
| Peak memory | 230668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3848030729 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.3848030729 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_rand_suspends/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_random_length_in_transaction.2437246831 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 234788511 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:52:13 AM UTC 24 |
| Finished | Aug 21 07:52:15 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2437246831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.2437246831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_random_length_out_transaction.283749929 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 191138644 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:52:13 AM UTC 24 |
| Finished | Aug 21 07:52:15 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=283749929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.283749929 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_resume_link_active.3545879218 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 20161899517 ps |
| CPU time | 32.16 seconds |
| Started | Aug 21 07:52:14 AM UTC 24 |
| Finished | Aug 21 07:52:48 AM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3545879218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_resume_link_active.3545879218 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_rx_crc_err.3714288251 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 194306895 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:52:14 AM UTC 24 |
| Finished | Aug 21 07:52:17 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3714288251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.3714288251 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_rx_full.901145242 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 415285687 ps |
| CPU time | 2.13 seconds |
| Started | Aug 21 07:52:15 AM UTC 24 |
| Finished | Aug 21 07:52:18 AM UTC 24 |
| Peak memory | 217996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=901145242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_full.901145242 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_rx_pid_err.883030542 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 159780591 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:52:16 AM UTC 24 |
| Finished | Aug 21 07:52:18 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=883030542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.883030542 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_rx_pid_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_sec_cm.1589476863 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 663003361 ps |
| CPU time | 2.54 seconds |
| Started | Aug 21 07:52:20 AM UTC 24 |
| Finished | Aug 21 07:52:24 AM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1589476863 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1589476863 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_setup_priority.3297978135 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 439557605 ps |
| CPU time | 2.27 seconds |
| Started | Aug 21 07:52:16 AM UTC 24 |
| Finished | Aug 21 07:52:19 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3297978135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.3297978135 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_setup_priority/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_setup_priority_over_stall_response.3413329914 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 305257643 ps |
| CPU time | 1.72 seconds |
| Started | Aug 21 07:52:17 AM UTC 24 |
| Finished | Aug 21 07:52:20 AM UTC 24 |
| Peak memory | 216304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3413329914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.3413329914 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_setup_priority_over_stall_response/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_setup_stage.2341064561 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 157466095 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:52:17 AM UTC 24 |
| Finished | Aug 21 07:52:19 AM UTC 24 |
| Peak memory | 216196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2341064561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2341064561 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_setup_trans_ignored.1729401810 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 159265710 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 07:52:17 AM UTC 24 |
| Finished | Aug 21 07:52:19 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1729401810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1729401810 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_smoke.1426914745 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 281864428 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:52:17 AM UTC 24 |
| Finished | Aug 21 07:52:20 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1426914745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1426914745 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_spurious_pids_ignored.4278958083 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 3136751793 ps |
| CPU time | 82.71 seconds |
| Started | Aug 21 07:52:18 AM UTC 24 |
| Finished | Aug 21 07:53:43 AM UTC 24 |
| Peak memory | 230672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4278958083 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.4278958083 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_stall_priority_over_nak.1680507854 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 178573338 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:52:18 AM UTC 24 |
| Finished | Aug 21 07:52:21 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1680507854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1680507854 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_stall_trans.987078502 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 180978601 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:52:18 AM UTC 24 |
| Finished | Aug 21 07:52:21 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=987078502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.987078502 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_stream_len_max.3597074732 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 1262474225 ps |
| CPU time | 5.5 seconds |
| Started | Aug 21 07:52:18 AM UTC 24 |
| Finished | Aug 21 07:52:25 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3597074732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.3597074732 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_streaming_out.1983860572 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3920796357 ps |
| CPU time | 32.17 seconds |
| Started | Aug 21 07:52:18 AM UTC 24 |
| Finished | Aug 21 07:52:52 AM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1983860572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1983860572 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_timeout_missing_host_handshake.464844595 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 469837286 ps |
| CPU time | 8.56 seconds |
| Started | Aug 21 07:51:47 AM UTC 24 |
| Finished | Aug 21 07:51:57 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=464844595 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_h ost_handshake.464844595 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/4.usbdev_tx_rx_disruption.3441997416 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 576464196 ps |
| CPU time | 2.73 seconds |
| Started | Aug 21 07:52:20 AM UTC 24 |
| Finished | Aug 21 07:52:24 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3441997416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.usbdev_tx_rx_disruption.3441997416 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/4.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_alert_test.1338824013 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 42232040 ps |
| CPU time | 0.92 seconds |
| Started | Aug 21 08:03:04 AM UTC 24 |
| Finished | Aug 21 08:03:06 AM UTC 24 |
| Peak memory | 216552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1338824013 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.1338824013 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_aon_wake_disconnect.3790973558 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 5747761931 ps |
| CPU time | 8.56 seconds |
| Started | Aug 21 08:02:54 AM UTC 24 |
| Finished | Aug 21 08:03:03 AM UTC 24 |
| Peak memory | 228352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3790973558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbd ev_aon_wake_disconnect.3790973558 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_aon_wake_reset.643808984 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 20594589098 ps |
| CPU time | 27.06 seconds |
| Started | Aug 21 08:02:54 AM UTC 24 |
| Finished | Aug 21 08:03:22 AM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=643808984 -assert nopostp roc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.643808984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_aon_wake_resume.358836361 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 25837686511 ps |
| CPU time | 35.73 seconds |
| Started | Aug 21 08:02:54 AM UTC 24 |
| Finished | Aug 21 08:03:31 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=358836361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbde v_aon_wake_resume.358836361 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_av_buffer.4142552214 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 183365261 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:02:56 AM UTC 24 |
| Finished | Aug 21 08:02:58 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4142552214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.4142552214 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_bitstuff_err.3503180004 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 142578696 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 08:02:56 AM UTC 24 |
| Finished | Aug 21 08:02:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3503180004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.3503180004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_data_toggle_clear.550990656 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 347655369 ps |
| CPU time | 1.78 seconds |
| Started | Aug 21 08:02:56 AM UTC 24 |
| Finished | Aug 21 08:02:59 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=550990656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.550990656 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_data_toggle_restore.2642426289 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 286690201 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 08:02:56 AM UTC 24 |
| Finished | Aug 21 08:02:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2642426289 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2642426289 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_device_address.3924411728 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 20600538057 ps |
| CPU time | 32.11 seconds |
| Started | Aug 21 08:02:56 AM UTC 24 |
| Finished | Aug 21 08:03:29 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3924411728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.3924411728 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_device_timeout.4099732828 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 1173716208 ps |
| CPU time | 23.68 seconds |
| Started | Aug 21 08:02:56 AM UTC 24 |
| Finished | Aug 21 08:03:21 AM UTC 24 |
| Peak memory | 218120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4099732828 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.4099732828 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_disable_endpoint.3394093802 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 691162236 ps |
| CPU time | 2.08 seconds |
| Started | Aug 21 08:02:56 AM UTC 24 |
| Finished | Aug 21 08:02:59 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3394093802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.3394093802 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_disconnected.423858107 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 164828536 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 08:02:56 AM UTC 24 |
| Finished | Aug 21 08:02:58 AM UTC 24 |
| Peak memory | 215508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=423858107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.423858107 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_enable.3668185486 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 66035004 ps |
| CPU time | 0.84 seconds |
| Started | Aug 21 08:02:56 AM UTC 24 |
| Finished | Aug 21 08:02:58 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3668185486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3668185486 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_endpoint_access.772197467 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 805005132 ps |
| CPU time | 2.55 seconds |
| Started | Aug 21 08:02:58 AM UTC 24 |
| Finished | Aug 21 08:03:01 AM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=772197467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.772197467 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_endpoint_types.1905667705 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 339377551 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:02:58 AM UTC 24 |
| Finished | Aug 21 08:03:00 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1905667705 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_types.1905667705 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_fifo_rst.1876854269 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 209843231 ps |
| CPU time | 1.7 seconds |
| Started | Aug 21 08:02:58 AM UTC 24 |
| Finished | Aug 21 08:03:00 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1876854269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1876854269 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_in_iso.2394314201 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 286335311 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:02:58 AM UTC 24 |
| Finished | Aug 21 08:03:00 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2394314201 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.2394314201 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_in_stall.1066783754 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 154121599 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:02:58 AM UTC 24 |
| Finished | Aug 21 08:03:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1066783754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1066783754 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_in_trans.2089172225 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 234061261 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 08:02:58 AM UTC 24 |
| Finished | Aug 21 08:03:00 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2089172225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2089172225 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_invalid_sync.479086851 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 2098350425 ps |
| CPU time | 18.08 seconds |
| Started | Aug 21 08:02:58 AM UTC 24 |
| Finished | Aug 21 08:03:17 AM UTC 24 |
| Peak memory | 235056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=479086851 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.479086851 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_iso_retraction.2445010817 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 7622067943 ps |
| CPU time | 49.53 seconds |
| Started | Aug 21 08:02:58 AM UTC 24 |
| Finished | Aug 21 08:03:49 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2445010817 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.2445010817 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_link_in_err.1565876972 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 208637678 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:02:58 AM UTC 24 |
| Finished | Aug 21 08:03:00 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1565876972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1565876972 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_link_resume.3504536893 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 12785039475 ps |
| CPU time | 18.64 seconds |
| Started | Aug 21 08:03:00 AM UTC 24 |
| Finished | Aug 21 08:03:20 AM UTC 24 |
| Peak memory | 218408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3504536893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3504536893 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_link_suspend.1536523127 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 4656448465 ps |
| CPU time | 6.89 seconds |
| Started | Aug 21 08:03:00 AM UTC 24 |
| Finished | Aug 21 08:03:08 AM UTC 24 |
| Peak memory | 218304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1536523127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.1536523127 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_low_speed_traffic.3834473716 |
| Short name | T2951 |
| Test name | |
| Test status | |
| Simulation time | 3985287513 ps |
| CPU time | 97.1 seconds |
| Started | Aug 21 08:03:00 AM UTC 24 |
| Finished | Aug 21 08:04:39 AM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3834473716 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.3834473716 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_max_inter_pkt_delay.522410289 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 2239031798 ps |
| CPU time | 53.7 seconds |
| Started | Aug 21 08:03:00 AM UTC 24 |
| Finished | Aug 21 08:03:56 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=522410289 -assert nopostproc +UVM _TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.522410289 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_max_length_in_transaction.254522057 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 230578139 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:03:00 AM UTC 24 |
| Finished | Aug 21 08:03:03 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=254522057 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.254522057 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_max_length_out_transaction.1238470448 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 238017383 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:03:00 AM UTC 24 |
| Finished | Aug 21 08:03:03 AM UTC 24 |
| Peak memory | 216360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1238470448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1238470448 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_min_inter_pkt_delay.192211561 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 1881525506 ps |
| CPU time | 45.08 seconds |
| Started | Aug 21 08:03:00 AM UTC 24 |
| Finished | Aug 21 08:03:47 AM UTC 24 |
| Peak memory | 228012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=192211561 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.192211561 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_min_length_in_transaction.1132736427 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 174187036 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 08:03:00 AM UTC 24 |
| Finished | Aug 21 08:03:02 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1132736427 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.1132736427 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_min_length_out_transaction.3444659984 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 143298725 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 08:03:00 AM UTC 24 |
| Finished | Aug 21 08:03:03 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3444659984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3444659984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_nak_trans.719591844 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 202266039 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:03:00 AM UTC 24 |
| Finished | Aug 21 08:03:03 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=719591844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.719591844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_out_iso.2729597724 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 169352575 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 08:03:00 AM UTC 24 |
| Finished | Aug 21 08:03:03 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2729597724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.2729597724 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_out_stall.2307271316 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 187554150 ps |
| CPU time | 1.16 seconds |
| Started | Aug 21 08:03:00 AM UTC 24 |
| Finished | Aug 21 08:03:03 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2307271316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2307271316 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_out_trans_nak.2701159903 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 211946116 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 08:03:00 AM UTC 24 |
| Finished | Aug 21 08:03:03 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2701159903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2701159903 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_pending_in_trans.891672896 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 222020345 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:03:01 AM UTC 24 |
| Finished | Aug 21 08:03:03 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=891672896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.891672896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_phy_config_pinflip.2711684753 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 259229012 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:03:02 AM UTC 24 |
| Finished | Aug 21 08:03:04 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2711684753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.2711684753 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_phy_config_usb_ref_disable.1662997777 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 169257453 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 08:03:02 AM UTC 24 |
| Finished | Aug 21 08:03:04 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1662997777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1662997777 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_phy_pins_sense.1262516280 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 47959494 ps |
| CPU time | 0.87 seconds |
| Started | Aug 21 08:03:02 AM UTC 24 |
| Finished | Aug 21 08:03:04 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1262516280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1262516280 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_pkt_buffer.45023265 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 19578016541 ps |
| CPU time | 50.09 seconds |
| Started | Aug 21 08:03:02 AM UTC 24 |
| Finished | Aug 21 08:03:54 AM UTC 24 |
| Peak memory | 228512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=45023265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.45023265 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_pkt_received.10999335 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 175608049 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 08:03:02 AM UTC 24 |
| Finished | Aug 21 08:03:04 AM UTC 24 |
| Peak memory | 215980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10999335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.10999335 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_pkt_sent.2868869259 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 221059088 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:03:02 AM UTC 24 |
| Finished | Aug 21 08:03:04 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2868869259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2868869259 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_random_length_in_transaction.647933350 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 206323463 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 08:03:02 AM UTC 24 |
| Finished | Aug 21 08:03:04 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=647933350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.647933350 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_random_length_out_transaction.2548112626 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 184156692 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 08:03:02 AM UTC 24 |
| Finished | Aug 21 08:03:04 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2548112626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.2548112626 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_rx_crc_err.354897225 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 139274824 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 08:03:02 AM UTC 24 |
| Finished | Aug 21 08:03:04 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=354897225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.354897225 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_rx_full.2879854166 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 258893977 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 08:03:02 AM UTC 24 |
| Finished | Aug 21 08:03:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2879854166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_full.2879854166 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_setup_stage.2605684557 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 156657048 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:03:04 AM UTC 24 |
| Finished | Aug 21 08:03:06 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2605684557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2605684557 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_setup_trans_ignored.476015384 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 146475855 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 08:03:04 AM UTC 24 |
| Finished | Aug 21 08:03:06 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=476015384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.476015384 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_smoke.257097252 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 249561130 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:03:04 AM UTC 24 |
| Finished | Aug 21 08:03:06 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=257097252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.257097252 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_spurious_pids_ignored.1578860079 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 1653132758 ps |
| CPU time | 14.64 seconds |
| Started | Aug 21 08:03:04 AM UTC 24 |
| Finished | Aug 21 08:03:20 AM UTC 24 |
| Peak memory | 230484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1578860079 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.1578860079 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_stall_priority_over_nak.2120706856 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 177652917 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:03:04 AM UTC 24 |
| Finished | Aug 21 08:03:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2120706856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2120706856 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_stall_trans.3814627422 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 200328819 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 08:03:04 AM UTC 24 |
| Finished | Aug 21 08:03:06 AM UTC 24 |
| Peak memory | 216068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3814627422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.3814627422 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_stream_len_max.3416194954 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 1236124693 ps |
| CPU time | 2.94 seconds |
| Started | Aug 21 08:03:04 AM UTC 24 |
| Finished | Aug 21 08:03:08 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3416194954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.3416194954 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_streaming_out.4132387780 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 3222051897 ps |
| CPU time | 21.7 seconds |
| Started | Aug 21 08:03:04 AM UTC 24 |
| Finished | Aug 21 08:03:27 AM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4132387780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.4132387780 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_timeout_missing_host_handshake.923757360 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 153699032 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:02:56 AM UTC 24 |
| Finished | Aug 21 08:02:58 AM UTC 24 |
| Peak memory | 216568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=923757360 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_ host_handshake.923757360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/40.usbdev_tx_rx_disruption.1546368950 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 577008242 ps |
| CPU time | 2.33 seconds |
| Started | Aug 21 08:03:04 AM UTC 24 |
| Finished | Aug 21 08:03:08 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1546368950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.usbdev_tx_rx_disruption.1546368950 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/40.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/400.usbdev_tx_rx_disruption.2582716407 |
| Short name | T3486 |
| Test name | |
| Test status | |
| Simulation time | 535740912 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2582716407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 400.usbdev_tx_rx_disruption.2582716407 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/400.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/401.usbdev_tx_rx_disruption.3669459660 |
| Short name | T3488 |
| Test name | |
| Test status | |
| Simulation time | 602012884 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3669459660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 401.usbdev_tx_rx_disruption.3669459660 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/401.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/402.usbdev_tx_rx_disruption.1054499850 |
| Short name | T3483 |
| Test name | |
| Test status | |
| Simulation time | 563157437 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1054499850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 402.usbdev_tx_rx_disruption.1054499850 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/402.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/403.usbdev_tx_rx_disruption.3202370246 |
| Short name | T3489 |
| Test name | |
| Test status | |
| Simulation time | 596455181 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3202370246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 403.usbdev_tx_rx_disruption.3202370246 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/403.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/404.usbdev_tx_rx_disruption.3668510779 |
| Short name | T3487 |
| Test name | |
| Test status | |
| Simulation time | 514535395 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:07:12 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 215500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3668510779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 404.usbdev_tx_rx_disruption.3668510779 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/404.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/405.usbdev_tx_rx_disruption.2543808240 |
| Short name | T3484 |
| Test name | |
| Test status | |
| Simulation time | 478019988 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:07:13 AM UTC 24 |
| Finished | Aug 21 08:07:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2543808240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 405.usbdev_tx_rx_disruption.2543808240 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/405.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/406.usbdev_tx_rx_disruption.2867348888 |
| Short name | T3533 |
| Test name | |
| Test status | |
| Simulation time | 505088531 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:28 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2867348888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 406.usbdev_tx_rx_disruption.2867348888 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/406.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/407.usbdev_tx_rx_disruption.1015682317 |
| Short name | T3496 |
| Test name | |
| Test status | |
| Simulation time | 625756854 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:21 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1015682317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 407.usbdev_tx_rx_disruption.1015682317 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/407.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/408.usbdev_tx_rx_disruption.2765770400 |
| Short name | T3537 |
| Test name | |
| Test status | |
| Simulation time | 613964650 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2765770400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 408.usbdev_tx_rx_disruption.2765770400 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/408.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/409.usbdev_tx_rx_disruption.2241060115 |
| Short name | T3495 |
| Test name | |
| Test status | |
| Simulation time | 575246334 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:21 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2241060115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 409.usbdev_tx_rx_disruption.2241060115 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/409.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_alert_test.907313450 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 84373749 ps |
| CPU time | 0.92 seconds |
| Started | Aug 21 08:03:20 AM UTC 24 |
| Finished | Aug 21 08:03:22 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=907313450 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.907313450 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_aon_wake_disconnect.607428997 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 6378785806 ps |
| CPU time | 8.92 seconds |
| Started | Aug 21 08:03:04 AM UTC 24 |
| Finished | Aug 21 08:03:14 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=607428997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbde v_aon_wake_disconnect.607428997 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_aon_wake_reset.3108590395 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 14355364297 ps |
| CPU time | 15.54 seconds |
| Started | Aug 21 08:03:06 AM UTC 24 |
| Finished | Aug 21 08:03:23 AM UTC 24 |
| Peak memory | 228608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3108590395 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3108590395 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_aon_wake_resume.780429129 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 30279326974 ps |
| CPU time | 40.87 seconds |
| Started | Aug 21 08:03:06 AM UTC 24 |
| Finished | Aug 21 08:03:48 AM UTC 24 |
| Peak memory | 218008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=780429129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbde v_aon_wake_resume.780429129 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_av_buffer.295224872 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 234004258 ps |
| CPU time | 1 seconds |
| Started | Aug 21 08:03:06 AM UTC 24 |
| Finished | Aug 21 08:03:08 AM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=295224872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.295224872 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_bitstuff_err.975133978 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 149061188 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:03:06 AM UTC 24 |
| Finished | Aug 21 08:03:08 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=975133978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.975133978 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_data_toggle_clear.1921176385 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 224343740 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:03:06 AM UTC 24 |
| Finished | Aug 21 08:03:08 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1921176385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.1921176385 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_data_toggle_restore.1696968943 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 895618397 ps |
| CPU time | 2.35 seconds |
| Started | Aug 21 08:03:06 AM UTC 24 |
| Finished | Aug 21 08:03:09 AM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1696968943 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1696968943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_device_address.857513129 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 29931046909 ps |
| CPU time | 48.74 seconds |
| Started | Aug 21 08:03:06 AM UTC 24 |
| Finished | Aug 21 08:03:56 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=857513129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.857513129 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_device_timeout.196400387 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 839016043 ps |
| CPU time | 16.22 seconds |
| Started | Aug 21 08:03:06 AM UTC 24 |
| Finished | Aug 21 08:03:23 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=196400387 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.196400387 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_disable_endpoint.2395343458 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 870956022 ps |
| CPU time | 2.33 seconds |
| Started | Aug 21 08:03:06 AM UTC 24 |
| Finished | Aug 21 08:03:10 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2395343458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.2395343458 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_disconnected.3343391175 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 168701007 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:03:06 AM UTC 24 |
| Finished | Aug 21 08:03:09 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3343391175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.3343391175 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_enable.1111537284 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 59596251 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 08:03:06 AM UTC 24 |
| Finished | Aug 21 08:03:08 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1111537284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.1111537284 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_endpoint_access.3330964766 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 1084033730 ps |
| CPU time | 2.63 seconds |
| Started | Aug 21 08:03:13 AM UTC 24 |
| Finished | Aug 21 08:03:17 AM UTC 24 |
| Peak memory | 218160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3330964766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3330964766 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_fifo_rst.1212697411 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 170656493 ps |
| CPU time | 1.95 seconds |
| Started | Aug 21 08:03:13 AM UTC 24 |
| Finished | Aug 21 08:03:16 AM UTC 24 |
| Peak memory | 216312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1212697411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1212697411 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_in_iso.703368333 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 228611798 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 08:03:13 AM UTC 24 |
| Finished | Aug 21 08:03:16 AM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=703368333 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.703368333 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_in_stall.3394026033 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 216042197 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 08:03:13 AM UTC 24 |
| Finished | Aug 21 08:03:16 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3394026033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3394026033 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_in_trans.82323435 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 247891532 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:03:13 AM UTC 24 |
| Finished | Aug 21 08:03:16 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=82323435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.82323435 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_invalid_sync.245372726 |
| Short name | T2937 |
| Test name | |
| Test status | |
| Simulation time | 2990064504 ps |
| CPU time | 78.36 seconds |
| Started | Aug 21 08:03:13 AM UTC 24 |
| Finished | Aug 21 08:04:34 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=245372726 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.245372726 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_iso_retraction.3623022272 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 4963673476 ps |
| CPU time | 31.01 seconds |
| Started | Aug 21 08:03:13 AM UTC 24 |
| Finished | Aug 21 08:03:46 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3623022272 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.3623022272 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_link_in_err.2617917290 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 214107633 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:03:14 AM UTC 24 |
| Finished | Aug 21 08:03:16 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2617917290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2617917290 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_link_resume.1177146 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 12422550163 ps |
| CPU time | 17.1 seconds |
| Started | Aug 21 08:03:15 AM UTC 24 |
| Finished | Aug 21 08:03:34 AM UTC 24 |
| Peak memory | 218400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1177146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.1177146 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_link_suspend.3963982091 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 8584455815 ps |
| CPU time | 12.46 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:29 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3963982091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.3963982091 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_low_speed_traffic.3321553740 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 2852013712 ps |
| CPU time | 21.39 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:38 AM UTC 24 |
| Peak memory | 230724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3321553740 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.3321553740 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_max_inter_pkt_delay.4184149307 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 3923921856 ps |
| CPU time | 36.03 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:53 AM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4184149307 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.4184149307 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_max_length_in_transaction.890413971 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 328366166 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:18 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=890413971 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.890413971 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_max_length_out_transaction.4089219277 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 194066443 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:18 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4089219277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.4089219277 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_min_inter_pkt_delay.845237778 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 2027300587 ps |
| CPU time | 49.54 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:04:07 AM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=845237778 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.845237778 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_min_length_in_transaction.1014025172 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 161529667 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:18 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1014025172 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.1014025172 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_min_length_out_transaction.292234189 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 158493255 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:18 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=292234189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.292234189 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_out_iso.3201554244 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 253428067 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:18 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3201554244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.3201554244 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_out_stall.2268524389 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 212645036 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:18 AM UTC 24 |
| Peak memory | 216348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2268524389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2268524389 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_out_trans_nak.1602822428 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 146110534 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:18 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1602822428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1602822428 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_pending_in_trans.2344810634 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 158590533 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:18 AM UTC 24 |
| Peak memory | 216240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2344810634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2344810634 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_phy_config_pinflip.838209869 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 275402229 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:18 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=838209869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.838209869 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_phy_config_usb_ref_disable.882478915 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 147527060 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:18 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=882478915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.882478915 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_phy_pins_sense.3374912838 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 86070154 ps |
| CPU time | 0.96 seconds |
| Started | Aug 21 08:03:16 AM UTC 24 |
| Finished | Aug 21 08:03:18 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3374912838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3374912838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_pkt_buffer.3711443364 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 10990053354 ps |
| CPU time | 27.01 seconds |
| Started | Aug 21 08:03:17 AM UTC 24 |
| Finished | Aug 21 08:03:46 AM UTC 24 |
| Peak memory | 228508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3711443364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3711443364 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_pkt_received.1004210822 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 262337946 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:03:17 AM UTC 24 |
| Finished | Aug 21 08:03:20 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1004210822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1004210822 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_pkt_sent.2365377881 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 217761632 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 08:03:17 AM UTC 24 |
| Finished | Aug 21 08:03:20 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2365377881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2365377881 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_random_length_in_transaction.4078040708 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 169055325 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 08:03:17 AM UTC 24 |
| Finished | Aug 21 08:03:19 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4078040708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.4078040708 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_random_length_out_transaction.3687222248 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 168802542 ps |
| CPU time | 0.84 seconds |
| Started | Aug 21 08:03:18 AM UTC 24 |
| Finished | Aug 21 08:03:19 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3687222248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3687222248 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_rx_crc_err.871580049 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 188456330 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:03:18 AM UTC 24 |
| Finished | Aug 21 08:03:20 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=871580049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.871580049 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_rx_full.4277980670 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 264198846 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 08:03:19 AM UTC 24 |
| Finished | Aug 21 08:03:22 AM UTC 24 |
| Peak memory | 216348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4277980670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_full.4277980670 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_setup_stage.1690112306 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 148086571 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 08:03:19 AM UTC 24 |
| Finished | Aug 21 08:03:21 AM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1690112306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1690112306 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_setup_trans_ignored.3068384970 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 164452962 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:03:19 AM UTC 24 |
| Finished | Aug 21 08:03:21 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3068384970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3068384970 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_smoke.4061844624 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 217975597 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 08:03:19 AM UTC 24 |
| Finished | Aug 21 08:03:22 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4061844624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.4061844624 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_spurious_pids_ignored.140647654 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 2157604649 ps |
| CPU time | 14.03 seconds |
| Started | Aug 21 08:03:19 AM UTC 24 |
| Finished | Aug 21 08:03:35 AM UTC 24 |
| Peak memory | 230456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=140647654 -assert nopostproc +UVM_TESTNAME=usbdev_bas e_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.140647654 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_stall_priority_over_nak.3353373186 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 159363786 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 08:03:19 AM UTC 24 |
| Finished | Aug 21 08:03:22 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3353373186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3353373186 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_stall_trans.2691905441 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 183203886 ps |
| CPU time | 0.89 seconds |
| Started | Aug 21 08:03:20 AM UTC 24 |
| Finished | Aug 21 08:03:21 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2691905441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2691905441 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_stream_len_max.3608921968 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 1082858218 ps |
| CPU time | 2.93 seconds |
| Started | Aug 21 08:03:20 AM UTC 24 |
| Finished | Aug 21 08:03:24 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3608921968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.3608921968 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_streaming_out.3987502357 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 2083832240 ps |
| CPU time | 52.27 seconds |
| Started | Aug 21 08:03:20 AM UTC 24 |
| Finished | Aug 21 08:04:13 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3987502357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.3987502357 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_timeout_missing_host_handshake.4029735157 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 1194425103 ps |
| CPU time | 23.6 seconds |
| Started | Aug 21 08:03:06 AM UTC 24 |
| Finished | Aug 21 08:03:31 AM UTC 24 |
| Peak memory | 218056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4029735157 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing _host_handshake.4029735157 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/41.usbdev_tx_rx_disruption.349476336 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 563006315 ps |
| CPU time | 2.01 seconds |
| Started | Aug 21 08:03:20 AM UTC 24 |
| Finished | Aug 21 08:03:23 AM UTC 24 |
| Peak memory | 217708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=349476336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.usbdev_tx_rx_disruption.349476336 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/41.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/410.usbdev_tx_rx_disruption.3788035986 |
| Short name | T3534 |
| Test name | |
| Test status | |
| Simulation time | 542910762 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:29 AM UTC 24 |
| Peak memory | 215980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3788035986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 410.usbdev_tx_rx_disruption.3788035986 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/410.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/411.usbdev_tx_rx_disruption.820813584 |
| Short name | T3531 |
| Test name | |
| Test status | |
| Simulation time | 493943848 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:28 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=820813584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 411.usbdev_tx_rx_disruption.820813584 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/411.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/412.usbdev_tx_rx_disruption.230105297 |
| Short name | T3535 |
| Test name | |
| Test status | |
| Simulation time | 453823656 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=230105297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 412.usbdev_tx_rx_disruption.230105297 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/412.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/413.usbdev_tx_rx_disruption.4140555527 |
| Short name | T3538 |
| Test name | |
| Test status | |
| Simulation time | 517949868 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4140555527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 413.usbdev_tx_rx_disruption.4140555527 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/413.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/414.usbdev_tx_rx_disruption.1198290431 |
| Short name | T3548 |
| Test name | |
| Test status | |
| Simulation time | 682832374 ps |
| CPU time | 1.76 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1198290431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 414.usbdev_tx_rx_disruption.1198290431 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/414.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/415.usbdev_tx_rx_disruption.1780197945 |
| Short name | T3497 |
| Test name | |
| Test status | |
| Simulation time | 476936335 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:21 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1780197945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 415.usbdev_tx_rx_disruption.1780197945 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/415.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/416.usbdev_tx_rx_disruption.2816527307 |
| Short name | T3551 |
| Test name | |
| Test status | |
| Simulation time | 674350705 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2816527307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 416.usbdev_tx_rx_disruption.2816527307 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/416.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/417.usbdev_tx_rx_disruption.1073091355 |
| Short name | T3543 |
| Test name | |
| Test status | |
| Simulation time | 500019894 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1073091355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 417.usbdev_tx_rx_disruption.1073091355 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/417.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/418.usbdev_tx_rx_disruption.2680984484 |
| Short name | T3558 |
| Test name | |
| Test status | |
| Simulation time | 672415003 ps |
| CPU time | 1.79 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:32 AM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2680984484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 418.usbdev_tx_rx_disruption.2680984484 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/418.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/419.usbdev_tx_rx_disruption.1765672493 |
| Short name | T3557 |
| Test name | |
| Test status | |
| Simulation time | 620262191 ps |
| CPU time | 1.74 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:32 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1765672493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 419.usbdev_tx_rx_disruption.1765672493 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/419.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_alert_test.1471894332 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 49512753 ps |
| CPU time | 0.94 seconds |
| Started | Aug 21 08:03:30 AM UTC 24 |
| Finished | Aug 21 08:03:36 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1471894332 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1471894332 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_aon_wake_disconnect.216000469 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 11032830267 ps |
| CPU time | 16.44 seconds |
| Started | Aug 21 08:03:20 AM UTC 24 |
| Finished | Aug 21 08:03:37 AM UTC 24 |
| Peak memory | 218344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=216000469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbde v_aon_wake_disconnect.216000469 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_aon_wake_reset.3957923457 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 19623835648 ps |
| CPU time | 25.51 seconds |
| Started | Aug 21 08:03:20 AM UTC 24 |
| Finished | Aug 21 08:03:47 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3957923457 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3957923457 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_aon_wake_resume.1703604356 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 31322341033 ps |
| CPU time | 41.64 seconds |
| Started | Aug 21 08:03:20 AM UTC 24 |
| Finished | Aug 21 08:04:03 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1703604356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbd ev_aon_wake_resume.1703604356 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_av_buffer.3715949486 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 184362607 ps |
| CPU time | 1 seconds |
| Started | Aug 21 08:03:22 AM UTC 24 |
| Finished | Aug 21 08:03:24 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3715949486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3715949486 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_bitstuff_err.133101382 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 188132262 ps |
| CPU time | 0.86 seconds |
| Started | Aug 21 08:03:22 AM UTC 24 |
| Finished | Aug 21 08:03:24 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=133101382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.133101382 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_data_toggle_clear.1721017042 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 566088292 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 08:03:22 AM UTC 24 |
| Finished | Aug 21 08:03:25 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1721017042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.1721017042 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_data_toggle_restore.3724319820 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 993544065 ps |
| CPU time | 2.6 seconds |
| Started | Aug 21 08:03:22 AM UTC 24 |
| Finished | Aug 21 08:03:26 AM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3724319820 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3724319820 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_device_address.1921443114 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 19379273259 ps |
| CPU time | 35.3 seconds |
| Started | Aug 21 08:03:22 AM UTC 24 |
| Finished | Aug 21 08:03:59 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1921443114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.1921443114 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_device_timeout.1374269590 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 5704655474 ps |
| CPU time | 35.05 seconds |
| Started | Aug 21 08:03:22 AM UTC 24 |
| Finished | Aug 21 08:03:59 AM UTC 24 |
| Peak memory | 218320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1374269590 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.1374269590 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_disable_endpoint.3526559821 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 685223619 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 08:03:22 AM UTC 24 |
| Finished | Aug 21 08:03:25 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3526559821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3526559821 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_disconnected.3542435043 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 144161997 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:03:22 AM UTC 24 |
| Finished | Aug 21 08:03:25 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3542435043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3542435043 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_enable.1953719640 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 59344207 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 08:03:22 AM UTC 24 |
| Finished | Aug 21 08:03:25 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1953719640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1953719640 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_endpoint_access.361162073 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 841965773 ps |
| CPU time | 2.41 seconds |
| Started | Aug 21 08:03:22 AM UTC 24 |
| Finished | Aug 21 08:03:26 AM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=361162073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.361162073 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_endpoint_types.625939689 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 442586017 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:03:23 AM UTC 24 |
| Finished | Aug 21 08:03:25 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=625939689 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_types.625939689 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_fifo_rst.2306898583 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 185729077 ps |
| CPU time | 1.96 seconds |
| Started | Aug 21 08:03:23 AM UTC 24 |
| Finished | Aug 21 08:03:26 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2306898583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2306898583 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_in_iso.532036654 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 200434944 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 08:03:23 AM UTC 24 |
| Finished | Aug 21 08:03:25 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=532036654 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.532036654 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_in_stall.3514629018 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 164780897 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:03:23 AM UTC 24 |
| Finished | Aug 21 08:03:25 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3514629018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3514629018 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_in_trans.1511344336 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 171587154 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:03:23 AM UTC 24 |
| Finished | Aug 21 08:03:25 AM UTC 24 |
| Peak memory | 216172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1511344336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1511344336 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_invalid_sync.2416218063 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 4537077997 ps |
| CPU time | 42.54 seconds |
| Started | Aug 21 08:03:23 AM UTC 24 |
| Finished | Aug 21 08:04:07 AM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2416218063 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.2416218063 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_iso_retraction.3854344038 |
| Short name | T2988 |
| Test name | |
| Test status | |
| Simulation time | 8517170881 ps |
| CPU time | 83.67 seconds |
| Started | Aug 21 08:03:23 AM UTC 24 |
| Finished | Aug 21 08:04:48 AM UTC 24 |
| Peak memory | 218140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3854344038 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.3854344038 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_link_in_err.1105907388 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 219484331 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:03:23 AM UTC 24 |
| Finished | Aug 21 08:03:25 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1105907388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.1105907388 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_link_resume.1957270319 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 28813292894 ps |
| CPU time | 50.82 seconds |
| Started | Aug 21 08:03:24 AM UTC 24 |
| Finished | Aug 21 08:04:17 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1957270319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1957270319 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_link_suspend.3614951444 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 10697705362 ps |
| CPU time | 15.76 seconds |
| Started | Aug 21 08:03:24 AM UTC 24 |
| Finished | Aug 21 08:03:41 AM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3614951444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.3614951444 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_low_speed_traffic.413897871 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 3620176453 ps |
| CPU time | 25.69 seconds |
| Started | Aug 21 08:03:25 AM UTC 24 |
| Finished | Aug 21 08:03:51 AM UTC 24 |
| Peak memory | 228592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=413897871 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.413897871 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_max_inter_pkt_delay.163293491 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 2040762084 ps |
| CPU time | 18.14 seconds |
| Started | Aug 21 08:03:25 AM UTC 24 |
| Finished | Aug 21 08:03:44 AM UTC 24 |
| Peak memory | 235196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=163293491 -assert nopostproc +UVM _TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.163293491 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_max_length_in_transaction.2724799211 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 270207347 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 08:03:25 AM UTC 24 |
| Finished | Aug 21 08:03:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2724799211 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2724799211 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_max_length_out_transaction.2875133198 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 207149080 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:03:25 AM UTC 24 |
| Finished | Aug 21 08:03:27 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2875133198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2875133198 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_min_inter_pkt_delay.1547053705 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 2173364165 ps |
| CPU time | 15.2 seconds |
| Started | Aug 21 08:03:25 AM UTC 24 |
| Finished | Aug 21 08:03:41 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1547053705 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.1547053705 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_min_length_in_transaction.2200195659 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 197214994 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:03:25 AM UTC 24 |
| Finished | Aug 21 08:03:27 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2200195659 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.2200195659 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_min_length_out_transaction.1108894403 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 167613837 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 08:03:25 AM UTC 24 |
| Finished | Aug 21 08:03:27 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1108894403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1108894403 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_nak_trans.1910152221 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 189332247 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:03:26 AM UTC 24 |
| Finished | Aug 21 08:03:29 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1910152221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1910152221 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_out_iso.754258347 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 196414806 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:03:26 AM UTC 24 |
| Finished | Aug 21 08:03:29 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=754258347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.754258347 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_out_stall.1130796843 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 196691436 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:03:26 AM UTC 24 |
| Finished | Aug 21 08:03:29 AM UTC 24 |
| Peak memory | 216260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1130796843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1130796843 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_out_trans_nak.2060942878 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 178865360 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:03:26 AM UTC 24 |
| Finished | Aug 21 08:03:29 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2060942878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2060942878 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_pending_in_trans.2288079370 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 215696088 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 08:03:26 AM UTC 24 |
| Finished | Aug 21 08:03:30 AM UTC 24 |
| Peak memory | 216368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2288079370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2288079370 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_phy_config_pinflip.2449879231 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 220336052 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:03:26 AM UTC 24 |
| Finished | Aug 21 08:03:29 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2449879231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.2449879231 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_phy_config_usb_ref_disable.350245002 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 135023015 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 08:03:26 AM UTC 24 |
| Finished | Aug 21 08:03:29 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=350245002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.350245002 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_phy_pins_sense.2155908931 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 47154039 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 08:03:27 AM UTC 24 |
| Finished | Aug 21 08:03:30 AM UTC 24 |
| Peak memory | 216432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2155908931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2155908931 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_pkt_buffer.2122563430 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 19866669451 ps |
| CPU time | 48.01 seconds |
| Started | Aug 21 08:03:27 AM UTC 24 |
| Finished | Aug 21 08:04:17 AM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2122563430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2122563430 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_pkt_received.3399152186 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 149489057 ps |
| CPU time | 1.16 seconds |
| Started | Aug 21 08:03:27 AM UTC 24 |
| Finished | Aug 21 08:03:29 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3399152186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3399152186 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_pkt_sent.1960506590 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 204750726 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 08:03:28 AM UTC 24 |
| Finished | Aug 21 08:03:30 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1960506590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1960506590 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_random_length_in_transaction.3873369267 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 161423824 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:03:28 AM UTC 24 |
| Finished | Aug 21 08:03:30 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3873369267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.3873369267 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_random_length_out_transaction.4284784028 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 149715481 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:03:28 AM UTC 24 |
| Finished | Aug 21 08:03:31 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4284784028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.4284784028 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_rx_crc_err.2176526092 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 153766026 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:03:28 AM UTC 24 |
| Finished | Aug 21 08:03:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2176526092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2176526092 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_rx_full.2122851575 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 250056531 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:03:28 AM UTC 24 |
| Finished | Aug 21 08:03:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2122851575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_full.2122851575 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_setup_stage.2420771073 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 174216580 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 08:03:28 AM UTC 24 |
| Finished | Aug 21 08:03:31 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2420771073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2420771073 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_setup_trans_ignored.2096072477 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 151202402 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 08:03:28 AM UTC 24 |
| Finished | Aug 21 08:03:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2096072477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2096072477 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_smoke.97817753 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 183666676 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:03:30 AM UTC 24 |
| Finished | Aug 21 08:03:32 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=97817753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.97817753 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_spurious_pids_ignored.2560614804 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 3035497563 ps |
| CPU time | 26.56 seconds |
| Started | Aug 21 08:03:30 AM UTC 24 |
| Finished | Aug 21 08:03:58 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2560614804 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.2560614804 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_stall_priority_over_nak.2553194117 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 149900394 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 08:03:30 AM UTC 24 |
| Finished | Aug 21 08:03:35 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2553194117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2553194117 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_stall_trans.2177823525 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 193595097 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 08:03:30 AM UTC 24 |
| Finished | Aug 21 08:03:32 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2177823525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2177823525 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_stream_len_max.833747681 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 672316154 ps |
| CPU time | 2.34 seconds |
| Started | Aug 21 08:03:30 AM UTC 24 |
| Finished | Aug 21 08:03:37 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=833747681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.833747681 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_streaming_out.1720236985 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 2988920706 ps |
| CPU time | 19.96 seconds |
| Started | Aug 21 08:03:30 AM UTC 24 |
| Finished | Aug 21 08:03:54 AM UTC 24 |
| Peak memory | 218348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1720236985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1720236985 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_timeout_missing_host_handshake.3614239157 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 2125470385 ps |
| CPU time | 46.12 seconds |
| Started | Aug 21 08:03:22 AM UTC 24 |
| Finished | Aug 21 08:04:10 AM UTC 24 |
| Peak memory | 218192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3614239157 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing _host_handshake.3614239157 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/42.usbdev_tx_rx_disruption.2275389985 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 489986565 ps |
| CPU time | 1.85 seconds |
| Started | Aug 21 08:03:30 AM UTC 24 |
| Finished | Aug 21 08:03:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2275389985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.usbdev_tx_rx_disruption.2275389985 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/42.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/420.usbdev_tx_rx_disruption.3161638120 |
| Short name | T3539 |
| Test name | |
| Test status | |
| Simulation time | 455437971 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3161638120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 420.usbdev_tx_rx_disruption.3161638120 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/420.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/421.usbdev_tx_rx_disruption.1205479865 |
| Short name | T3544 |
| Test name | |
| Test status | |
| Simulation time | 504061083 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:07:17 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1205479865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 421.usbdev_tx_rx_disruption.1205479865 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/421.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/422.usbdev_tx_rx_disruption.1813625864 |
| Short name | T3554 |
| Test name | |
| Test status | |
| Simulation time | 549872365 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:07:18 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1813625864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 422.usbdev_tx_rx_disruption.1813625864 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/422.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/423.usbdev_tx_rx_disruption.2904771134 |
| Short name | T3552 |
| Test name | |
| Test status | |
| Simulation time | 632795737 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:07:18 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2904771134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 423.usbdev_tx_rx_disruption.2904771134 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/423.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/424.usbdev_tx_rx_disruption.939324650 |
| Short name | T3546 |
| Test name | |
| Test status | |
| Simulation time | 492167994 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:07:18 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=939324650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 424.usbdev_tx_rx_disruption.939324650 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/424.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/425.usbdev_tx_rx_disruption.2017207889 |
| Short name | T3574 |
| Test name | |
| Test status | |
| Simulation time | 511475764 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 08:07:18 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2017207889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 425.usbdev_tx_rx_disruption.2017207889 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/425.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/426.usbdev_tx_rx_disruption.4011400042 |
| Short name | T3555 |
| Test name | |
| Test status | |
| Simulation time | 556343843 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:07:18 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4011400042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 426.usbdev_tx_rx_disruption.4011400042 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/426.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/427.usbdev_tx_rx_disruption.2164720613 |
| Short name | T3586 |
| Test name | |
| Test status | |
| Simulation time | 534369158 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:07:19 AM UTC 24 |
| Finished | Aug 21 08:07:42 AM UTC 24 |
| Peak memory | 216056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2164720613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 427.usbdev_tx_rx_disruption.2164720613 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/427.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/428.usbdev_tx_rx_disruption.2536573479 |
| Short name | T3580 |
| Test name | |
| Test status | |
| Simulation time | 567160960 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:07:19 AM UTC 24 |
| Finished | Aug 21 08:07:42 AM UTC 24 |
| Peak memory | 216148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2536573479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 428.usbdev_tx_rx_disruption.2536573479 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/428.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/429.usbdev_tx_rx_disruption.3426220436 |
| Short name | T3589 |
| Test name | |
| Test status | |
| Simulation time | 612333079 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:07:19 AM UTC 24 |
| Finished | Aug 21 08:07:42 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3426220436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 429.usbdev_tx_rx_disruption.3426220436 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/429.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_alert_test.4033305926 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 43352727 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 08:03:46 AM UTC 24 |
| Finished | Aug 21 08:03:48 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4033305926 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.4033305926 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_aon_wake_disconnect.3341036868 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 9924157168 ps |
| CPU time | 16.19 seconds |
| Started | Aug 21 08:03:32 AM UTC 24 |
| Finished | Aug 21 08:03:56 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3341036868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbd ev_aon_wake_disconnect.3341036868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_aon_wake_reset.1395358201 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 14885143128 ps |
| CPU time | 16.31 seconds |
| Started | Aug 21 08:03:32 AM UTC 24 |
| Finished | Aug 21 08:03:56 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1395358201 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1395358201 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_aon_wake_resume.4012715387 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 24341358513 ps |
| CPU time | 28.7 seconds |
| Started | Aug 21 08:03:32 AM UTC 24 |
| Finished | Aug 21 08:04:03 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4012715387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbd ev_aon_wake_resume.4012715387 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_av_buffer.2675758741 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 145450952 ps |
| CPU time | 0.96 seconds |
| Started | Aug 21 08:03:32 AM UTC 24 |
| Finished | Aug 21 08:03:35 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2675758741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2675758741 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_bitstuff_err.3939972549 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 141698056 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:03:32 AM UTC 24 |
| Finished | Aug 21 08:03:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3939972549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.3939972549 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_data_toggle_clear.205932122 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 338604859 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 08:03:32 AM UTC 24 |
| Finished | Aug 21 08:03:36 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=205932122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.205932122 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_data_toggle_restore.300711501 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 372734664 ps |
| CPU time | 1.73 seconds |
| Started | Aug 21 08:03:32 AM UTC 24 |
| Finished | Aug 21 08:03:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=300711501 -assert nopostproc +UVM_TESTNAME=us bdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.300711501 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_device_address.2085199430 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 34542736160 ps |
| CPU time | 56.15 seconds |
| Started | Aug 21 08:03:32 AM UTC 24 |
| Finished | Aug 21 08:04:31 AM UTC 24 |
| Peak memory | 218436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2085199430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.2085199430 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_device_timeout.1352971927 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 1338151496 ps |
| CPU time | 8.53 seconds |
| Started | Aug 21 08:03:32 AM UTC 24 |
| Finished | Aug 21 08:03:43 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1352971927 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.1352971927 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_disable_endpoint.2919401462 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 671422396 ps |
| CPU time | 2.35 seconds |
| Started | Aug 21 08:03:32 AM UTC 24 |
| Finished | Aug 21 08:03:37 AM UTC 24 |
| Peak memory | 218104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2919401462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.2919401462 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_disconnected.4143027541 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 138760459 ps |
| CPU time | 0.85 seconds |
| Started | Aug 21 08:03:33 AM UTC 24 |
| Finished | Aug 21 08:03:35 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4143027541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.4143027541 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_enable.2680000150 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 37528548 ps |
| CPU time | 0.85 seconds |
| Started | Aug 21 08:03:33 AM UTC 24 |
| Finished | Aug 21 08:03:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2680000150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2680000150 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_endpoint_access.4037467731 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 965785035 ps |
| CPU time | 3 seconds |
| Started | Aug 21 08:03:35 AM UTC 24 |
| Finished | Aug 21 08:03:46 AM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4037467731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.4037467731 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_endpoint_types.2579961925 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 421016222 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:03:35 AM UTC 24 |
| Finished | Aug 21 08:03:40 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2579961925 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_types.2579961925 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_fifo_rst.4272605434 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 259918105 ps |
| CPU time | 2.47 seconds |
| Started | Aug 21 08:03:37 AM UTC 24 |
| Finished | Aug 21 08:03:41 AM UTC 24 |
| Peak memory | 218096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4272605434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.4272605434 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_in_iso.261641270 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 204217389 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:03:37 AM UTC 24 |
| Finished | Aug 21 08:03:41 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=261641270 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.261641270 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_in_stall.2966939593 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 153815080 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:03:37 AM UTC 24 |
| Finished | Aug 21 08:03:41 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2966939593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2966939593 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_in_trans.919969405 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 176818580 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:03:37 AM UTC 24 |
| Finished | Aug 21 08:03:41 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=919969405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.919969405 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_invalid_sync.35162269 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 3595922924 ps |
| CPU time | 24.63 seconds |
| Started | Aug 21 08:03:37 AM UTC 24 |
| Finished | Aug 21 08:04:04 AM UTC 24 |
| Peak memory | 228508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35162269 -assert nopostproc +UVM_TESTNAME=usbdev_base_tes t +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.35162269 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_iso_retraction.3248660744 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 5228222976 ps |
| CPU time | 32.76 seconds |
| Started | Aug 21 08:03:37 AM UTC 24 |
| Finished | Aug 21 08:04:12 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3248660744 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.3248660744 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_link_in_err.1803559040 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 252286210 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 08:03:37 AM UTC 24 |
| Finished | Aug 21 08:03:40 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1803559040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.1803559040 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_link_resume.3039986624 |
| Short name | T2941 |
| Test name | |
| Test status | |
| Simulation time | 31939737707 ps |
| CPU time | 55.03 seconds |
| Started | Aug 21 08:03:37 AM UTC 24 |
| Finished | Aug 21 08:04:35 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3039986624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.3039986624 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_link_suspend.385680253 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 5684608827 ps |
| CPU time | 10.3 seconds |
| Started | Aug 21 08:03:37 AM UTC 24 |
| Finished | Aug 21 08:03:50 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=385680253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.385680253 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_low_speed_traffic.387276331 |
| Short name | T3099 |
| Test name | |
| Test status | |
| Simulation time | 4396489104 ps |
| CPU time | 101.54 seconds |
| Started | Aug 21 08:03:37 AM UTC 24 |
| Finished | Aug 21 08:05:22 AM UTC 24 |
| Peak memory | 235364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=387276331 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.387276331 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_max_inter_pkt_delay.1672368056 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 3939066580 ps |
| CPU time | 33.32 seconds |
| Started | Aug 21 08:03:37 AM UTC 24 |
| Finished | Aug 21 08:04:13 AM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1672368056 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.1672368056 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_max_length_in_transaction.3212716390 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 253205474 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 08:03:37 AM UTC 24 |
| Finished | Aug 21 08:03:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3212716390 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.3212716390 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_max_length_out_transaction.3380983550 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 233476395 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 08:03:39 AM UTC 24 |
| Finished | Aug 21 08:03:41 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3380983550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3380983550 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_min_inter_pkt_delay.3446466036 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 3412207420 ps |
| CPU time | 31.03 seconds |
| Started | Aug 21 08:03:39 AM UTC 24 |
| Finished | Aug 21 08:04:11 AM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3446466036 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3446466036 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_min_length_in_transaction.1594955459 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 196838490 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:03:39 AM UTC 24 |
| Finished | Aug 21 08:03:41 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1594955459 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.1594955459 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_min_length_out_transaction.1121362873 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 144323088 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 08:03:39 AM UTC 24 |
| Finished | Aug 21 08:03:41 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1121362873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1121362873 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_nak_trans.3285995318 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 221577530 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:03:39 AM UTC 24 |
| Finished | Aug 21 08:03:41 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3285995318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3285995318 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_out_iso.837228809 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 146531050 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:03:41 AM UTC 24 |
| Finished | Aug 21 08:03:43 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=837228809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.837228809 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_out_stall.3883438215 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 216547479 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:03:41 AM UTC 24 |
| Finished | Aug 21 08:03:44 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3883438215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3883438215 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_out_trans_nak.1162848461 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 235988239 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:03:41 AM UTC 24 |
| Finished | Aug 21 08:03:44 AM UTC 24 |
| Peak memory | 216344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1162848461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1162848461 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_pending_in_trans.3691778763 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 186786621 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:03:41 AM UTC 24 |
| Finished | Aug 21 08:03:44 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3691778763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3691778763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_phy_config_pinflip.898112723 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 261225240 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:03:41 AM UTC 24 |
| Finished | Aug 21 08:03:44 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=898112723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.898112723 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_phy_config_usb_ref_disable.3781498659 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 151372536 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:03:43 AM UTC 24 |
| Finished | Aug 21 08:03:45 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3781498659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3781498659 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_phy_pins_sense.2791133952 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 65111378 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 08:03:43 AM UTC 24 |
| Finished | Aug 21 08:03:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2791133952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2791133952 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_pkt_buffer.478321996 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 8434502901 ps |
| CPU time | 23.11 seconds |
| Started | Aug 21 08:03:43 AM UTC 24 |
| Finished | Aug 21 08:04:07 AM UTC 24 |
| Peak memory | 228448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=478321996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.478321996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_pkt_received.2616470244 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 174229413 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 08:03:43 AM UTC 24 |
| Finished | Aug 21 08:03:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2616470244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2616470244 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_pkt_sent.898147970 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 223729650 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:03:43 AM UTC 24 |
| Finished | Aug 21 08:03:46 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=898147970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.898147970 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_random_length_in_transaction.3301435542 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 170526602 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:03:43 AM UTC 24 |
| Finished | Aug 21 08:03:46 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3301435542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.3301435542 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_random_length_out_transaction.1808791661 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 236490342 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 08:03:43 AM UTC 24 |
| Finished | Aug 21 08:03:45 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1808791661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.1808791661 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_rx_crc_err.329009319 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 158162391 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:03:43 AM UTC 24 |
| Finished | Aug 21 08:03:46 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=329009319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.329009319 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_rx_full.3770905501 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 299385645 ps |
| CPU time | 1.74 seconds |
| Started | Aug 21 08:03:44 AM UTC 24 |
| Finished | Aug 21 08:03:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3770905501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_full.3770905501 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_setup_stage.1666747416 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 154590308 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:03:45 AM UTC 24 |
| Finished | Aug 21 08:03:47 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1666747416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1666747416 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_setup_trans_ignored.1592797096 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 148855572 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:03:45 AM UTC 24 |
| Finished | Aug 21 08:03:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1592797096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1592797096 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_smoke.2391306076 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 263797712 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:03:45 AM UTC 24 |
| Finished | Aug 21 08:03:47 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2391306076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2391306076 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_spurious_pids_ignored.927786217 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 2101912413 ps |
| CPU time | 15.55 seconds |
| Started | Aug 21 08:03:45 AM UTC 24 |
| Finished | Aug 21 08:04:01 AM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=927786217 -assert nopostproc +UVM_TESTNAME=usbdev_bas e_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.927786217 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_stall_priority_over_nak.1731607405 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 221454896 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:03:45 AM UTC 24 |
| Finished | Aug 21 08:03:47 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1731607405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1731607405 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_stall_trans.2156960819 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 176409021 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:03:45 AM UTC 24 |
| Finished | Aug 21 08:03:47 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2156960819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2156960819 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_stream_len_max.74795694 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 559325152 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 08:03:46 AM UTC 24 |
| Finished | Aug 21 08:03:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=74795694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.74795694 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_streaming_out.1430784670 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 2510817702 ps |
| CPU time | 21.19 seconds |
| Started | Aug 21 08:03:46 AM UTC 24 |
| Finished | Aug 21 08:04:08 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1430784670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1430784670 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_timeout_missing_host_handshake.1252995043 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 618245348 ps |
| CPU time | 10.5 seconds |
| Started | Aug 21 08:03:32 AM UTC 24 |
| Finished | Aug 21 08:03:45 AM UTC 24 |
| Peak memory | 218128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1252995043 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing _host_handshake.1252995043 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/43.usbdev_tx_rx_disruption.9767036 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 593889378 ps |
| CPU time | 2.78 seconds |
| Started | Aug 21 08:03:46 AM UTC 24 |
| Finished | Aug 21 08:03:50 AM UTC 24 |
| Peak memory | 218068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=9767036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 43.usbdev_tx_rx_disruption.9767036 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/43.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/430.usbdev_tx_rx_disruption.2326912066 |
| Short name | T3579 |
| Test name | |
| Test status | |
| Simulation time | 443228237 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:07:19 AM UTC 24 |
| Finished | Aug 21 08:07:42 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2326912066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 430.usbdev_tx_rx_disruption.2326912066 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/430.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/431.usbdev_tx_rx_disruption.1781156763 |
| Short name | T3578 |
| Test name | |
| Test status | |
| Simulation time | 423584758 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:07:19 AM UTC 24 |
| Finished | Aug 21 08:07:42 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1781156763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 431.usbdev_tx_rx_disruption.1781156763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/431.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/432.usbdev_tx_rx_disruption.2804687185 |
| Short name | T3498 |
| Test name | |
| Test status | |
| Simulation time | 601676866 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:07:20 AM UTC 24 |
| Finished | Aug 21 08:07:26 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2804687185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 432.usbdev_tx_rx_disruption.2804687185 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/432.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/433.usbdev_tx_rx_disruption.3100741134 |
| Short name | T3505 |
| Test name | |
| Test status | |
| Simulation time | 482263673 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:07:21 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3100741134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 433.usbdev_tx_rx_disruption.3100741134 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/433.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/434.usbdev_tx_rx_disruption.4251091828 |
| Short name | T3508 |
| Test name | |
| Test status | |
| Simulation time | 475910613 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:07:21 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4251091828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 434.usbdev_tx_rx_disruption.4251091828 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/434.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/435.usbdev_tx_rx_disruption.1017742054 |
| Short name | T3509 |
| Test name | |
| Test status | |
| Simulation time | 537401395 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:07:21 AM UTC 24 |
| Finished | Aug 21 08:07:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1017742054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 435.usbdev_tx_rx_disruption.1017742054 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/435.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/436.usbdev_tx_rx_disruption.2974450140 |
| Short name | T3563 |
| Test name | |
| Test status | |
| Simulation time | 624935765 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 08:07:26 AM UTC 24 |
| Finished | Aug 21 08:07:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2974450140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 436.usbdev_tx_rx_disruption.2974450140 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/436.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/437.usbdev_tx_rx_disruption.391891759 |
| Short name | T3545 |
| Test name | |
| Test status | |
| Simulation time | 602370827 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:07:28 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=391891759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 437.usbdev_tx_rx_disruption.391891759 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/437.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/438.usbdev_tx_rx_disruption.1775803129 |
| Short name | T3547 |
| Test name | |
| Test status | |
| Simulation time | 591349162 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:07:28 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1775803129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 438.usbdev_tx_rx_disruption.1775803129 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/438.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/439.usbdev_tx_rx_disruption.400773208 |
| Short name | T3550 |
| Test name | |
| Test status | |
| Simulation time | 596369587 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 08:07:28 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=400773208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 439.usbdev_tx_rx_disruption.400773208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/439.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_alert_test.3255790101 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 129254822 ps |
| CPU time | 0.94 seconds |
| Started | Aug 21 08:03:59 AM UTC 24 |
| Finished | Aug 21 08:04:02 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3255790101 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.3255790101 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_aon_wake_disconnect.4214233504 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 6793240196 ps |
| CPU time | 9.68 seconds |
| Started | Aug 21 08:03:46 AM UTC 24 |
| Finished | Aug 21 08:03:57 AM UTC 24 |
| Peak memory | 228508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4214233504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbd ev_aon_wake_disconnect.4214233504 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_aon_wake_reset.2181518722 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 15389448561 ps |
| CPU time | 21.15 seconds |
| Started | Aug 21 08:03:46 AM UTC 24 |
| Finished | Aug 21 08:04:09 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2181518722 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.2181518722 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_aon_wake_resume.1062126348 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 23672745682 ps |
| CPU time | 30.87 seconds |
| Started | Aug 21 08:03:46 AM UTC 24 |
| Finished | Aug 21 08:04:19 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1062126348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbd ev_aon_wake_resume.1062126348 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_av_buffer.3810021814 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 179832082 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:03:48 AM UTC 24 |
| Finished | Aug 21 08:03:51 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3810021814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3810021814 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_bitstuff_err.2306007295 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 152078831 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:03:48 AM UTC 24 |
| Finished | Aug 21 08:03:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2306007295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.2306007295 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_data_toggle_clear.544029073 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 332786884 ps |
| CPU time | 2.24 seconds |
| Started | Aug 21 08:03:49 AM UTC 24 |
| Finished | Aug 21 08:03:52 AM UTC 24 |
| Peak memory | 218008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=544029073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.544029073 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_data_toggle_restore.824452836 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 1211042609 ps |
| CPU time | 4.89 seconds |
| Started | Aug 21 08:03:49 AM UTC 24 |
| Finished | Aug 21 08:03:55 AM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=824452836 -assert nopostproc +UVM_TESTNAME=us bdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.824452836 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_device_address.2716603069 |
| Short name | T3018 |
| Test name | |
| Test status | |
| Simulation time | 44813434983 ps |
| CPU time | 68.87 seconds |
| Started | Aug 21 08:03:49 AM UTC 24 |
| Finished | Aug 21 08:04:59 AM UTC 24 |
| Peak memory | 218012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2716603069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.2716603069 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_device_timeout.1439365673 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 605549694 ps |
| CPU time | 4.86 seconds |
| Started | Aug 21 08:03:49 AM UTC 24 |
| Finished | Aug 21 08:03:55 AM UTC 24 |
| Peak memory | 218056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1439365673 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.1439365673 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_disable_endpoint.4151597222 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 570391256 ps |
| CPU time | 2.93 seconds |
| Started | Aug 21 08:03:49 AM UTC 24 |
| Finished | Aug 21 08:03:53 AM UTC 24 |
| Peak memory | 217972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4151597222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.4151597222 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_disconnected.1873516349 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 135631181 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:03:49 AM UTC 24 |
| Finished | Aug 21 08:03:51 AM UTC 24 |
| Peak memory | 216444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1873516349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.1873516349 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_enable.2701931232 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 73249056 ps |
| CPU time | 0.76 seconds |
| Started | Aug 21 08:03:49 AM UTC 24 |
| Finished | Aug 21 08:03:51 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2701931232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2701931232 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_endpoint_access.708018658 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 799515679 ps |
| CPU time | 2.97 seconds |
| Started | Aug 21 08:03:49 AM UTC 24 |
| Finished | Aug 21 08:03:53 AM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=708018658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.708018658 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_endpoint_types.1747993393 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 159344474 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:03:49 AM UTC 24 |
| Finished | Aug 21 08:03:51 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1747993393 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_types.1747993393 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_fifo_rst.2360924367 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 360797038 ps |
| CPU time | 2.87 seconds |
| Started | Aug 21 08:03:50 AM UTC 24 |
| Finished | Aug 21 08:03:54 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2360924367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2360924367 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_in_iso.2427958768 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 220313709 ps |
| CPU time | 1.87 seconds |
| Started | Aug 21 08:03:50 AM UTC 24 |
| Finished | Aug 21 08:03:53 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2427958768 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2427958768 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_in_stall.3252627649 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 153849894 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:03:50 AM UTC 24 |
| Finished | Aug 21 08:03:53 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3252627649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3252627649 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_in_trans.975625135 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 217079100 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 08:03:50 AM UTC 24 |
| Finished | Aug 21 08:03:53 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=975625135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.975625135 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_invalid_sync.91616785 |
| Short name | T3163 |
| Test name | |
| Test status | |
| Simulation time | 4192088388 ps |
| CPU time | 108.75 seconds |
| Started | Aug 21 08:03:50 AM UTC 24 |
| Finished | Aug 21 08:05:41 AM UTC 24 |
| Peak memory | 228704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=91616785 -assert nopostproc +UVM_TESTNAME=usbdev_base_tes t +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.91616785 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_iso_retraction.272859806 |
| Short name | T3069 |
| Test name | |
| Test status | |
| Simulation time | 13445036170 ps |
| CPU time | 77.79 seconds |
| Started | Aug 21 08:03:52 AM UTC 24 |
| Finished | Aug 21 08:05:11 AM UTC 24 |
| Peak memory | 218312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=272859806 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.272859806 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_link_in_err.1914322800 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 228435141 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:03:52 AM UTC 24 |
| Finished | Aug 21 08:03:54 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1914322800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1914322800 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_link_resume.2237090709 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 22059746762 ps |
| CPU time | 37.13 seconds |
| Started | Aug 21 08:03:52 AM UTC 24 |
| Finished | Aug 21 08:04:30 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2237090709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2237090709 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_link_suspend.4239230235 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 5461296152 ps |
| CPU time | 9.33 seconds |
| Started | Aug 21 08:03:52 AM UTC 24 |
| Finished | Aug 21 08:04:02 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4239230235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.4239230235 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_low_speed_traffic.2087665342 |
| Short name | T3104 |
| Test name | |
| Test status | |
| Simulation time | 3577259465 ps |
| CPU time | 89.64 seconds |
| Started | Aug 21 08:03:52 AM UTC 24 |
| Finished | Aug 21 08:05:24 AM UTC 24 |
| Peak memory | 228404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2087665342 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.2087665342 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_max_inter_pkt_delay.2309551748 |
| Short name | T3087 |
| Test name | |
| Test status | |
| Simulation time | 3475727084 ps |
| CPU time | 85.3 seconds |
| Started | Aug 21 08:03:52 AM UTC 24 |
| Finished | Aug 21 08:05:19 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2309551748 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.2309551748 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_max_length_in_transaction.2497995414 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 235877694 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:03:53 AM UTC 24 |
| Finished | Aug 21 08:03:56 AM UTC 24 |
| Peak memory | 216436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2497995414 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.2497995414 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_max_length_out_transaction.1675041269 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 198939239 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:03:53 AM UTC 24 |
| Finished | Aug 21 08:03:56 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1675041269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1675041269 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_min_inter_pkt_delay.377522159 |
| Short name | T3002 |
| Test name | |
| Test status | |
| Simulation time | 2407767943 ps |
| CPU time | 59.56 seconds |
| Started | Aug 21 08:03:53 AM UTC 24 |
| Finished | Aug 21 08:04:55 AM UTC 24 |
| Peak memory | 228616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=377522159 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.377522159 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_min_length_in_transaction.4173876385 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 157580768 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:03:53 AM UTC 24 |
| Finished | Aug 21 08:03:56 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4173876385 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.4173876385 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_min_length_out_transaction.4182670932 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 177196881 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 08:03:53 AM UTC 24 |
| Finished | Aug 21 08:03:56 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4182670932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.4182670932 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_nak_trans.3597259082 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 230115299 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:03:55 AM UTC 24 |
| Finished | Aug 21 08:03:58 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3597259082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3597259082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_out_iso.4205060101 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 194877461 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 08:03:55 AM UTC 24 |
| Finished | Aug 21 08:03:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4205060101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.4205060101 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_out_stall.541376528 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 178672106 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 08:03:55 AM UTC 24 |
| Finished | Aug 21 08:03:58 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=541376528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.541376528 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_out_trans_nak.2614232052 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 196050200 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:03:56 AM UTC 24 |
| Finished | Aug 21 08:03:58 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2614232052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2614232052 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_pending_in_trans.3197695563 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 149845859 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:03:56 AM UTC 24 |
| Finished | Aug 21 08:03:58 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3197695563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3197695563 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_phy_config_pinflip.4206689996 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 260227653 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:03:56 AM UTC 24 |
| Finished | Aug 21 08:03:58 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4206689996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.4206689996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_phy_config_usb_ref_disable.2153418512 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 141649577 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:03:56 AM UTC 24 |
| Finished | Aug 21 08:03:58 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2153418512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.2153418512 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_phy_pins_sense.1590437571 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 42682626 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:03:56 AM UTC 24 |
| Finished | Aug 21 08:03:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1590437571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1590437571 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_pkt_buffer.3460034922 |
| Short name | T2938 |
| Test name | |
| Test status | |
| Simulation time | 16153504569 ps |
| CPU time | 36.8 seconds |
| Started | Aug 21 08:03:56 AM UTC 24 |
| Finished | Aug 21 08:04:34 AM UTC 24 |
| Peak memory | 228448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3460034922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3460034922 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_pkt_received.2868821000 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 158481135 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:03:56 AM UTC 24 |
| Finished | Aug 21 08:03:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2868821000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2868821000 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_pkt_sent.2904468816 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 204817993 ps |
| CPU time | 0.87 seconds |
| Started | Aug 21 08:03:56 AM UTC 24 |
| Finished | Aug 21 08:03:58 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2904468816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2904468816 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_random_length_in_transaction.1041144822 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 225234548 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:03:57 AM UTC 24 |
| Finished | Aug 21 08:04:00 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1041144822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.1041144822 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_random_length_out_transaction.405227907 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 207451521 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:03:58 AM UTC 24 |
| Finished | Aug 21 08:04:00 AM UTC 24 |
| Peak memory | 216528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=405227907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.405227907 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_rx_crc_err.2795159387 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 163092996 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:03:58 AM UTC 24 |
| Finished | Aug 21 08:04:00 AM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2795159387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.2795159387 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_rx_full.557776776 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 356242385 ps |
| CPU time | 1.73 seconds |
| Started | Aug 21 08:03:58 AM UTC 24 |
| Finished | Aug 21 08:04:00 AM UTC 24 |
| Peak memory | 216364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=557776776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_full.557776776 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_setup_stage.771115734 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 170123904 ps |
| CPU time | 0.8 seconds |
| Started | Aug 21 08:03:58 AM UTC 24 |
| Finished | Aug 21 08:03:59 AM UTC 24 |
| Peak memory | 216064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=771115734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.771115734 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_setup_trans_ignored.136228751 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 176189535 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 08:03:58 AM UTC 24 |
| Finished | Aug 21 08:04:00 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=136228751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.136228751 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_smoke.446978480 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 237313581 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:03:58 AM UTC 24 |
| Finished | Aug 21 08:04:00 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=446978480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.446978480 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_spurious_pids_ignored.3741638355 |
| Short name | T3057 |
| Test name | |
| Test status | |
| Simulation time | 3041776157 ps |
| CPU time | 70.22 seconds |
| Started | Aug 21 08:03:58 AM UTC 24 |
| Finished | Aug 21 08:05:10 AM UTC 24 |
| Peak memory | 230668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3741638355 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.3741638355 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_stall_priority_over_nak.3008395073 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 159922838 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 08:03:58 AM UTC 24 |
| Finished | Aug 21 08:04:00 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3008395073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3008395073 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_stall_trans.2843800785 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 185797910 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:03:59 AM UTC 24 |
| Finished | Aug 21 08:04:02 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2843800785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2843800785 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_stream_len_max.4201629110 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 1285382117 ps |
| CPU time | 3.71 seconds |
| Started | Aug 21 08:03:59 AM UTC 24 |
| Finished | Aug 21 08:04:04 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4201629110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.4201629110 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_streaming_out.1398809688 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 1895933913 ps |
| CPU time | 12.62 seconds |
| Started | Aug 21 08:03:59 AM UTC 24 |
| Finished | Aug 21 08:04:13 AM UTC 24 |
| Peak memory | 235116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1398809688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1398809688 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_timeout_missing_host_handshake.2576022635 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 2558694622 ps |
| CPU time | 21.02 seconds |
| Started | Aug 21 08:03:49 AM UTC 24 |
| Finished | Aug 21 08:04:11 AM UTC 24 |
| Peak memory | 218368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2576022635 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing _host_handshake.2576022635 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/44.usbdev_tx_rx_disruption.2142296284 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 585733247 ps |
| CPU time | 2.71 seconds |
| Started | Aug 21 08:03:59 AM UTC 24 |
| Finished | Aug 21 08:04:03 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2142296284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 44.usbdev_tx_rx_disruption.2142296284 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/44.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/440.usbdev_tx_rx_disruption.1884309233 |
| Short name | T3542 |
| Test name | |
| Test status | |
| Simulation time | 587526027 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:07:28 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1884309233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 440.usbdev_tx_rx_disruption.1884309233 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/440.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/441.usbdev_tx_rx_disruption.2552698262 |
| Short name | T3536 |
| Test name | |
| Test status | |
| Simulation time | 494982259 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:07:28 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2552698262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 441.usbdev_tx_rx_disruption.2552698262 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/441.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/442.usbdev_tx_rx_disruption.171228585 |
| Short name | T3541 |
| Test name | |
| Test status | |
| Simulation time | 525557293 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:07:28 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=171228585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 442.usbdev_tx_rx_disruption.171228585 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/442.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/443.usbdev_tx_rx_disruption.247874702 |
| Short name | T3540 |
| Test name | |
| Test status | |
| Simulation time | 485160743 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:07:28 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=247874702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 443.usbdev_tx_rx_disruption.247874702 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/443.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/444.usbdev_tx_rx_disruption.1009427836 |
| Short name | T3553 |
| Test name | |
| Test status | |
| Simulation time | 516197256 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1009427836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 444.usbdev_tx_rx_disruption.1009427836 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/444.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/445.usbdev_tx_rx_disruption.1788816389 |
| Short name | T3549 |
| Test name | |
| Test status | |
| Simulation time | 623438342 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1788816389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 445.usbdev_tx_rx_disruption.1788816389 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/445.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/446.usbdev_tx_rx_disruption.2536971447 |
| Short name | T3556 |
| Test name | |
| Test status | |
| Simulation time | 576067144 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2536971447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 446.usbdev_tx_rx_disruption.2536971447 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/446.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/447.usbdev_tx_rx_disruption.3425638585 |
| Short name | T3572 |
| Test name | |
| Test status | |
| Simulation time | 591659966 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3425638585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 447.usbdev_tx_rx_disruption.3425638585 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/447.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/448.usbdev_tx_rx_disruption.348635479 |
| Short name | T3573 |
| Test name | |
| Test status | |
| Simulation time | 615375557 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 217776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=348635479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 448.usbdev_tx_rx_disruption.348635479 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/448.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/449.usbdev_tx_rx_disruption.1865770837 |
| Short name | T3569 |
| Test name | |
| Test status | |
| Simulation time | 469946065 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1865770837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 449.usbdev_tx_rx_disruption.1865770837 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/449.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_alert_test.2119819124 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 47038970 ps |
| CPU time | 0.69 seconds |
| Started | Aug 21 08:04:17 AM UTC 24 |
| Finished | Aug 21 08:04:19 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2119819124 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.2119819124 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_aon_wake_disconnect.193345094 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 12043468715 ps |
| CPU time | 15.6 seconds |
| Started | Aug 21 08:03:59 AM UTC 24 |
| Finished | Aug 21 08:04:17 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=193345094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbde v_aon_wake_disconnect.193345094 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_aon_wake_reset.2997929830 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 14793708221 ps |
| CPU time | 20.25 seconds |
| Started | Aug 21 08:04:00 AM UTC 24 |
| Finished | Aug 21 08:04:21 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2997929830 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.2997929830 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_aon_wake_resume.2236188081 |
| Short name | T2940 |
| Test name | |
| Test status | |
| Simulation time | 28605925534 ps |
| CPU time | 33.24 seconds |
| Started | Aug 21 08:04:00 AM UTC 24 |
| Finished | Aug 21 08:04:34 AM UTC 24 |
| Peak memory | 218372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2236188081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbd ev_aon_wake_resume.2236188081 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_av_buffer.617480312 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 185776505 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 08:04:00 AM UTC 24 |
| Finished | Aug 21 08:04:02 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=617480312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.617480312 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_bitstuff_err.821166173 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 210884319 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 08:04:00 AM UTC 24 |
| Finished | Aug 21 08:04:02 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=821166173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.821166173 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_data_toggle_clear.2226799680 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 479623541 ps |
| CPU time | 1.76 seconds |
| Started | Aug 21 08:04:01 AM UTC 24 |
| Finished | Aug 21 08:04:07 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2226799680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2226799680 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_data_toggle_restore.1697871253 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 389355206 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 08:04:01 AM UTC 24 |
| Finished | Aug 21 08:04:07 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1697871253 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1697871253 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_device_address.3954111426 |
| Short name | T3108 |
| Test name | |
| Test status | |
| Simulation time | 39114496206 ps |
| CPU time | 78.66 seconds |
| Started | Aug 21 08:04:01 AM UTC 24 |
| Finished | Aug 21 08:05:25 AM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3954111426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.3954111426 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_device_timeout.1451766782 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 839689794 ps |
| CPU time | 15.93 seconds |
| Started | Aug 21 08:04:01 AM UTC 24 |
| Finished | Aug 21 08:04:21 AM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1451766782 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.1451766782 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_disable_endpoint.2913683669 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 639238002 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 08:04:01 AM UTC 24 |
| Finished | Aug 21 08:04:10 AM UTC 24 |
| Peak memory | 216176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2913683669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.2913683669 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_disconnected.818644189 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 161668685 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:04:01 AM UTC 24 |
| Finished | Aug 21 08:04:10 AM UTC 24 |
| Peak memory | 216376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=818644189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.818644189 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_enable.629428062 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 53110856 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 08:04:01 AM UTC 24 |
| Finished | Aug 21 08:04:09 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=629428062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.629428062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_endpoint_access.2161038120 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 781457324 ps |
| CPU time | 2.28 seconds |
| Started | Aug 21 08:04:01 AM UTC 24 |
| Finished | Aug 21 08:04:11 AM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2161038120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.2161038120 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_fifo_rst.187494452 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 327280545 ps |
| CPU time | 1.96 seconds |
| Started | Aug 21 08:04:03 AM UTC 24 |
| Finished | Aug 21 08:04:07 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=187494452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.187494452 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_in_iso.412615535 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 181090363 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:04:03 AM UTC 24 |
| Finished | Aug 21 08:04:06 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=412615535 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.412615535 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_in_stall.636187905 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 132678422 ps |
| CPU time | 0.68 seconds |
| Started | Aug 21 08:04:03 AM UTC 24 |
| Finished | Aug 21 08:04:06 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=636187905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.636187905 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_in_trans.3660241901 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 208136122 ps |
| CPU time | 0.96 seconds |
| Started | Aug 21 08:04:03 AM UTC 24 |
| Finished | Aug 21 08:04:06 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3660241901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3660241901 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_invalid_sync.1052260128 |
| Short name | T2950 |
| Test name | |
| Test status | |
| Simulation time | 3796874380 ps |
| CPU time | 31.89 seconds |
| Started | Aug 21 08:04:03 AM UTC 24 |
| Finished | Aug 21 08:04:37 AM UTC 24 |
| Peak memory | 228404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1052260128 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.1052260128 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_iso_retraction.125426853 |
| Short name | T3102 |
| Test name | |
| Test status | |
| Simulation time | 7599311096 ps |
| CPU time | 77.45 seconds |
| Started | Aug 21 08:04:03 AM UTC 24 |
| Finished | Aug 21 08:05:23 AM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=125426853 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.125426853 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_link_in_err.998511456 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 241358634 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 08:04:05 AM UTC 24 |
| Finished | Aug 21 08:04:10 AM UTC 24 |
| Peak memory | 216236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=998511456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.998511456 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_link_resume.1026851242 |
| Short name | T2960 |
| Test name | |
| Test status | |
| Simulation time | 25410758805 ps |
| CPU time | 31.92 seconds |
| Started | Aug 21 08:04:05 AM UTC 24 |
| Finished | Aug 21 08:04:41 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1026851242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.1026851242 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_link_suspend.2681174880 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 10769103447 ps |
| CPU time | 14.89 seconds |
| Started | Aug 21 08:04:05 AM UTC 24 |
| Finished | Aug 21 08:04:24 AM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2681174880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2681174880 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_low_speed_traffic.1315018673 |
| Short name | T2976 |
| Test name | |
| Test status | |
| Simulation time | 3899122261 ps |
| CPU time | 35.23 seconds |
| Started | Aug 21 08:04:05 AM UTC 24 |
| Finished | Aug 21 08:04:44 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1315018673 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1315018673 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_max_inter_pkt_delay.950470725 |
| Short name | T3111 |
| Test name | |
| Test status | |
| Simulation time | 3042349433 ps |
| CPU time | 75.31 seconds |
| Started | Aug 21 08:04:05 AM UTC 24 |
| Finished | Aug 21 08:05:25 AM UTC 24 |
| Peak memory | 230524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=950470725 -assert nopostproc +UVM _TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.950470725 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_max_length_in_transaction.3348568399 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 245667550 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:04:05 AM UTC 24 |
| Finished | Aug 21 08:04:10 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3348568399 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3348568399 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_max_length_out_transaction.2154060801 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 225583778 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:04:06 AM UTC 24 |
| Finished | Aug 21 08:04:11 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2154060801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.2154060801 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_min_inter_pkt_delay.1007161875 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 2091094372 ps |
| CPU time | 14.74 seconds |
| Started | Aug 21 08:04:07 AM UTC 24 |
| Finished | Aug 21 08:04:24 AM UTC 24 |
| Peak memory | 228352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1007161875 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.1007161875 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_min_length_in_transaction.3706268767 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 163770785 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 08:04:07 AM UTC 24 |
| Finished | Aug 21 08:04:12 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3706268767 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3706268767 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_min_length_out_transaction.2314865989 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 147185182 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:04:07 AM UTC 24 |
| Finished | Aug 21 08:04:10 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2314865989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2314865989 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_nak_trans.3385511353 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 188534020 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 08:04:08 AM UTC 24 |
| Finished | Aug 21 08:04:11 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3385511353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3385511353 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_out_iso.504614320 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 206651871 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 08:04:08 AM UTC 24 |
| Finished | Aug 21 08:04:11 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=504614320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.504614320 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_out_stall.3322082799 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 168732885 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 08:04:08 AM UTC 24 |
| Finished | Aug 21 08:04:11 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3322082799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3322082799 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_out_trans_nak.807037918 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 187032777 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 08:04:08 AM UTC 24 |
| Finished | Aug 21 08:04:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=807037918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.807037918 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_pending_in_trans.2543692542 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 246008747 ps |
| CPU time | 0.91 seconds |
| Started | Aug 21 08:04:08 AM UTC 24 |
| Finished | Aug 21 08:04:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2543692542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2543692542 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_phy_config_pinflip.2308881507 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 226710774 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:04:09 AM UTC 24 |
| Finished | Aug 21 08:04:11 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2308881507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.2308881507 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_phy_config_usb_ref_disable.1054692272 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 208267499 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 08:04:10 AM UTC 24 |
| Finished | Aug 21 08:04:12 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1054692272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1054692272 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_phy_pins_sense.1677981767 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 47839848 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 08:04:10 AM UTC 24 |
| Finished | Aug 21 08:04:12 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1677981767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1677981767 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_pkt_buffer.1465411829 |
| Short name | T2936 |
| Test name | |
| Test status | |
| Simulation time | 9061399289 ps |
| CPU time | 21.79 seconds |
| Started | Aug 21 08:04:10 AM UTC 24 |
| Finished | Aug 21 08:04:33 AM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1465411829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1465411829 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_pkt_received.2958565423 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 187905330 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 08:04:10 AM UTC 24 |
| Finished | Aug 21 08:04:12 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2958565423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2958565423 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_pkt_sent.316540678 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 224743414 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 08:04:11 AM UTC 24 |
| Finished | Aug 21 08:04:14 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=316540678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.316540678 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_random_length_in_transaction.3861457433 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 190821702 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 08:04:11 AM UTC 24 |
| Finished | Aug 21 08:04:13 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3861457433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3861457433 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_random_length_out_transaction.1025253981 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 183799932 ps |
| CPU time | 0.89 seconds |
| Started | Aug 21 08:04:12 AM UTC 24 |
| Finished | Aug 21 08:04:13 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1025253981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.1025253981 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_rx_crc_err.2043986354 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 148172064 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:04:12 AM UTC 24 |
| Finished | Aug 21 08:04:14 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2043986354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2043986354 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_rx_full.2443177168 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 393407727 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:04:12 AM UTC 24 |
| Finished | Aug 21 08:04:14 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2443177168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_full.2443177168 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_setup_stage.1758197161 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 148569485 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 08:04:12 AM UTC 24 |
| Finished | Aug 21 08:04:14 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1758197161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1758197161 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_setup_trans_ignored.2640338766 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 173095616 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 08:04:12 AM UTC 24 |
| Finished | Aug 21 08:04:14 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2640338766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2640338766 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_smoke.4198795193 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 259158516 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:04:12 AM UTC 24 |
| Finished | Aug 21 08:04:14 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4198795193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.4198795193 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_spurious_pids_ignored.3504315198 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 2369545638 ps |
| CPU time | 15.38 seconds |
| Started | Aug 21 08:04:12 AM UTC 24 |
| Finished | Aug 21 08:04:29 AM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3504315198 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3504315198 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_stall_priority_over_nak.784844722 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 199921549 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 08:04:12 AM UTC 24 |
| Finished | Aug 21 08:04:15 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=784844722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20 24_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.784844722 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_stall_trans.3409923702 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 177937305 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 08:04:12 AM UTC 24 |
| Finished | Aug 21 08:04:15 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3409923702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3409923702 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_stream_len_max.530306029 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 1025443658 ps |
| CPU time | 2.38 seconds |
| Started | Aug 21 08:04:12 AM UTC 24 |
| Finished | Aug 21 08:04:16 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=530306029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.530306029 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_streaming_out.1719252007 |
| Short name | T3117 |
| Test name | |
| Test status | |
| Simulation time | 3081168148 ps |
| CPU time | 72.1 seconds |
| Started | Aug 21 08:04:12 AM UTC 24 |
| Finished | Aug 21 08:05:27 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1719252007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1719252007 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_timeout_missing_host_handshake.2571846834 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 560185235 ps |
| CPU time | 10.63 seconds |
| Started | Aug 21 08:04:01 AM UTC 24 |
| Finished | Aug 21 08:04:16 AM UTC 24 |
| Peak memory | 218240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2571846834 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing _host_handshake.2571846834 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/45.usbdev_tx_rx_disruption.2152127014 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 469359455 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:04:17 AM UTC 24 |
| Finished | Aug 21 08:04:20 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2152127014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 45.usbdev_tx_rx_disruption.2152127014 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/45.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/450.usbdev_tx_rx_disruption.1833294624 |
| Short name | T3567 |
| Test name | |
| Test status | |
| Simulation time | 574496350 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1833294624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 450.usbdev_tx_rx_disruption.1833294624 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/450.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/451.usbdev_tx_rx_disruption.204959187 |
| Short name | T3583 |
| Test name | |
| Test status | |
| Simulation time | 630270078 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:42 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=204959187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 451.usbdev_tx_rx_disruption.204959187 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/451.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/452.usbdev_tx_rx_disruption.1243955726 |
| Short name | T3584 |
| Test name | |
| Test status | |
| Simulation time | 619133807 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:42 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1243955726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 452.usbdev_tx_rx_disruption.1243955726 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/452.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/453.usbdev_tx_rx_disruption.2182199883 |
| Short name | T3570 |
| Test name | |
| Test status | |
| Simulation time | 499162081 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2182199883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 453.usbdev_tx_rx_disruption.2182199883 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/453.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/454.usbdev_tx_rx_disruption.3344059497 |
| Short name | T3585 |
| Test name | |
| Test status | |
| Simulation time | 515974955 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:42 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3344059497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 454.usbdev_tx_rx_disruption.3344059497 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/454.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/455.usbdev_tx_rx_disruption.2430454812 |
| Short name | T3590 |
| Test name | |
| Test status | |
| Simulation time | 701248732 ps |
| CPU time | 1.7 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:42 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2430454812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 455.usbdev_tx_rx_disruption.2430454812 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/455.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/456.usbdev_tx_rx_disruption.2652684939 |
| Short name | T3582 |
| Test name | |
| Test status | |
| Simulation time | 517807790 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:42 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2652684939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 456.usbdev_tx_rx_disruption.2652684939 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/456.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/457.usbdev_tx_rx_disruption.2416950355 |
| Short name | T3588 |
| Test name | |
| Test status | |
| Simulation time | 640148932 ps |
| CPU time | 1.62 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:42 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2416950355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 457.usbdev_tx_rx_disruption.2416950355 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/457.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/458.usbdev_tx_rx_disruption.2366677570 |
| Short name | T3577 |
| Test name | |
| Test status | |
| Simulation time | 508447182 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2366677570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 458.usbdev_tx_rx_disruption.2366677570 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/458.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/459.usbdev_tx_rx_disruption.3943266789 |
| Short name | T3576 |
| Test name | |
| Test status | |
| Simulation time | 422410911 ps |
| CPU time | 1.16 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3943266789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 459.usbdev_tx_rx_disruption.3943266789 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/459.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_alert_test.3563622243 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 43750840 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 08:04:28 AM UTC 24 |
| Finished | Aug 21 08:04:31 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3563622243 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.3563622243 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_aon_wake_disconnect.526524221 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 9359307484 ps |
| CPU time | 12.51 seconds |
| Started | Aug 21 08:04:17 AM UTC 24 |
| Finished | Aug 21 08:04:31 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=526524221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbde v_aon_wake_disconnect.526524221 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_aon_wake_reset.3161273659 |
| Short name | T2943 |
| Test name | |
| Test status | |
| Simulation time | 13798160526 ps |
| CPU time | 16.7 seconds |
| Started | Aug 21 08:04:18 AM UTC 24 |
| Finished | Aug 21 08:04:35 AM UTC 24 |
| Peak memory | 228476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3161273659 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.3161273659 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_aon_wake_resume.4197002822 |
| Short name | T3004 |
| Test name | |
| Test status | |
| Simulation time | 29086626769 ps |
| CPU time | 35.92 seconds |
| Started | Aug 21 08:04:18 AM UTC 24 |
| Finished | Aug 21 08:04:55 AM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4197002822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbd ev_aon_wake_resume.4197002822 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_av_buffer.1887585049 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 148485380 ps |
| CPU time | 0.75 seconds |
| Started | Aug 21 08:04:18 AM UTC 24 |
| Finished | Aug 21 08:04:19 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1887585049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1887585049 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_bitstuff_err.4184481992 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 145773846 ps |
| CPU time | 0.75 seconds |
| Started | Aug 21 08:04:18 AM UTC 24 |
| Finished | Aug 21 08:04:19 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4184481992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.4184481992 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_data_toggle_clear.1075128008 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 376989369 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:04:18 AM UTC 24 |
| Finished | Aug 21 08:04:20 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1075128008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.1075128008 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_data_toggle_restore.2084762309 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 1059107150 ps |
| CPU time | 2.66 seconds |
| Started | Aug 21 08:04:18 AM UTC 24 |
| Finished | Aug 21 08:04:22 AM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2084762309 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.2084762309 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_device_address.2160331161 |
| Short name | T3135 |
| Test name | |
| Test status | |
| Simulation time | 42218556696 ps |
| CPU time | 68.01 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:05:30 AM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2160331161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2160331161 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_device_timeout.3517348468 |
| Short name | T3017 |
| Test name | |
| Test status | |
| Simulation time | 6341191168 ps |
| CPU time | 35.59 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:58 AM UTC 24 |
| Peak memory | 218384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3517348468 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.3517348468 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_disable_endpoint.3203755446 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 870674089 ps |
| CPU time | 2 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:24 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3203755446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3203755446 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_disconnected.977886099 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 151906589 ps |
| CPU time | 0.86 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:23 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=977886099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.977886099 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_enable.3204161511 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 35380283 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:23 AM UTC 24 |
| Peak memory | 216376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3204161511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3204161511 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_endpoint_access.1751714325 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 975240554 ps |
| CPU time | 2.39 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:24 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1751714325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.1751714325 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_endpoint_types.1565968298 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 633041925 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:23 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1565968298 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_types.1565968298 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_fifo_rst.1014569555 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 452159473 ps |
| CPU time | 2.61 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:24 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1014569555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1014569555 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_in_iso.1401257884 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 169035306 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:23 AM UTC 24 |
| Peak memory | 216368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1401257884 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1401257884 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_in_stall.3494478791 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 145303967 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:23 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3494478791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3494478791 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_in_trans.4187516574 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 224135279 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:23 AM UTC 24 |
| Peak memory | 216364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4187516574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.4187516574 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_invalid_sync.3467005069 |
| Short name | T3160 |
| Test name | |
| Test status | |
| Simulation time | 3064860832 ps |
| CPU time | 77.07 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:05:40 AM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3467005069 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.3467005069 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_iso_retraction.1528132248 |
| Short name | T3134 |
| Test name | |
| Test status | |
| Simulation time | 10917015542 ps |
| CPU time | 63.94 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:05:30 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1528132248 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.1528132248 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_link_in_err.2267050611 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 206080656 ps |
| CPU time | 0.87 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:26 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2267050611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2267050611 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_link_resume.2488155635 |
| Short name | T3071 |
| Test name | |
| Test status | |
| Simulation time | 29452649168 ps |
| CPU time | 46.55 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:05:12 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2488155635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2488155635 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_link_suspend.3569454815 |
| Short name | T2944 |
| Test name | |
| Test status | |
| Simulation time | 8398958493 ps |
| CPU time | 10.32 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:35 AM UTC 24 |
| Peak memory | 218148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3569454815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.3569454815 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_low_speed_traffic.4201090633 |
| Short name | T3007 |
| Test name | |
| Test status | |
| Simulation time | 3362400644 ps |
| CPU time | 29.95 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:56 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4201090633 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.4201090633 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_max_inter_pkt_delay.4219101653 |
| Short name | T3233 |
| Test name | |
| Test status | |
| Simulation time | 3919743499 ps |
| CPU time | 94.98 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:06:01 AM UTC 24 |
| Peak memory | 228576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4219101653 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.4219101653 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_max_length_in_transaction.48008912 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 246612390 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:04:21 AM UTC 24 |
| Finished | Aug 21 08:04:27 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=48008912 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.48008912 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_max_length_out_transaction.1943010327 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 218205909 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 08:04:21 AM UTC 24 |
| Finished | Aug 21 08:04:27 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1943010327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1943010327 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_min_inter_pkt_delay.60595243 |
| Short name | T2975 |
| Test name | |
| Test status | |
| Simulation time | 2082396145 ps |
| CPU time | 17.49 seconds |
| Started | Aug 21 08:04:21 AM UTC 24 |
| Finished | Aug 21 08:04:43 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=60595243 -assert nopostproc +UVM_TE STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.60595243 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_min_length_in_transaction.837367243 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 165585210 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:04:21 AM UTC 24 |
| Finished | Aug 21 08:04:27 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=837367243 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.837367243 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_min_length_out_transaction.389705844 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 147485616 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:04:21 AM UTC 24 |
| Finished | Aug 21 08:04:27 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=389705844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.389705844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_nak_trans.1139359444 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 221139328 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 08:04:22 AM UTC 24 |
| Finished | Aug 21 08:04:25 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1139359444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1139359444 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_out_iso.3930795539 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 175976854 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 08:04:22 AM UTC 24 |
| Finished | Aug 21 08:04:25 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3930795539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3930795539 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_out_stall.186614054 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 228514820 ps |
| CPU time | 0.84 seconds |
| Started | Aug 21 08:04:22 AM UTC 24 |
| Finished | Aug 21 08:04:25 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=186614054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.186614054 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_out_trans_nak.2988363897 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 161675337 ps |
| CPU time | 0.8 seconds |
| Started | Aug 21 08:04:22 AM UTC 24 |
| Finished | Aug 21 08:04:25 AM UTC 24 |
| Peak memory | 216180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2988363897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2988363897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_pending_in_trans.299005139 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 162509201 ps |
| CPU time | 0.77 seconds |
| Started | Aug 21 08:04:22 AM UTC 24 |
| Finished | Aug 21 08:04:25 AM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=299005139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.299005139 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_phy_config_pinflip.3203408347 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 209000538 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 08:04:23 AM UTC 24 |
| Finished | Aug 21 08:04:26 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3203408347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3203408347 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_phy_config_usb_ref_disable.3558657084 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 156910174 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 08:04:23 AM UTC 24 |
| Finished | Aug 21 08:04:25 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3558657084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3558657084 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_phy_pins_sense.2581600182 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 36201191 ps |
| CPU time | 0.63 seconds |
| Started | Aug 21 08:04:23 AM UTC 24 |
| Finished | Aug 21 08:04:25 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2581600182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2581600182 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_pkt_buffer.42918141 |
| Short name | T3090 |
| Test name | |
| Test status | |
| Simulation time | 22387446230 ps |
| CPU time | 53.96 seconds |
| Started | Aug 21 08:04:25 AM UTC 24 |
| Finished | Aug 21 08:05:20 AM UTC 24 |
| Peak memory | 228476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42918141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.42918141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_pkt_received.3887203276 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 189846946 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:04:25 AM UTC 24 |
| Finished | Aug 21 08:04:27 AM UTC 24 |
| Peak memory | 216428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3887203276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3887203276 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_pkt_sent.3601366618 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 259947800 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 08:04:25 AM UTC 24 |
| Finished | Aug 21 08:04:27 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3601366618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3601366618 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_random_length_in_transaction.1813592199 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 159308623 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 08:04:25 AM UTC 24 |
| Finished | Aug 21 08:04:30 AM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1813592199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.1813592199 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_random_length_out_transaction.3864796316 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 163917228 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:04:25 AM UTC 24 |
| Finished | Aug 21 08:04:27 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3864796316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.3864796316 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_rx_crc_err.3931779873 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 185251492 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:04:25 AM UTC 24 |
| Finished | Aug 21 08:04:27 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3931779873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3931779873 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_rx_full.362931495 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 352591591 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:04:25 AM UTC 24 |
| Finished | Aug 21 08:04:28 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=362931495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_full.362931495 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_setup_stage.951878460 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 146811773 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 08:04:26 AM UTC 24 |
| Finished | Aug 21 08:04:31 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=951878460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.951878460 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_setup_trans_ignored.2154141231 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 168142760 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:04:26 AM UTC 24 |
| Finished | Aug 21 08:04:32 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2154141231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2154141231 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_smoke.2380824098 |
| Short name | T2934 |
| Test name | |
| Test status | |
| Simulation time | 215977853 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:04:26 AM UTC 24 |
| Finished | Aug 21 08:04:32 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2380824098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2380824098 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_spurious_pids_ignored.2401480517 |
| Short name | T3206 |
| Test name | |
| Test status | |
| Simulation time | 3365625506 ps |
| CPU time | 82.6 seconds |
| Started | Aug 21 08:04:26 AM UTC 24 |
| Finished | Aug 21 08:05:54 AM UTC 24 |
| Peak memory | 230572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2401480517 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.2401480517 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_stall_priority_over_nak.1680756769 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 205282874 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 08:04:26 AM UTC 24 |
| Finished | Aug 21 08:04:32 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1680756769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.1680756769 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_stall_trans.1681134730 |
| Short name | T2932 |
| Test name | |
| Test status | |
| Simulation time | 158514981 ps |
| CPU time | 1.16 seconds |
| Started | Aug 21 08:04:26 AM UTC 24 |
| Finished | Aug 21 08:04:32 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1681134730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1681134730 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_stream_len_max.2047558177 |
| Short name | T2947 |
| Test name | |
| Test status | |
| Simulation time | 948671077 ps |
| CPU time | 2.56 seconds |
| Started | Aug 21 08:04:26 AM UTC 24 |
| Finished | Aug 21 08:04:36 AM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2047558177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.2047558177 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_streaming_out.2154782905 |
| Short name | T3000 |
| Test name | |
| Test status | |
| Simulation time | 2576649077 ps |
| CPU time | 19.26 seconds |
| Started | Aug 21 08:04:26 AM UTC 24 |
| Finished | Aug 21 08:04:53 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2154782905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.2154782905 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_timeout_missing_host_handshake.2708597821 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 613310062 ps |
| CPU time | 9.74 seconds |
| Started | Aug 21 08:04:20 AM UTC 24 |
| Finished | Aug 21 08:04:32 AM UTC 24 |
| Peak memory | 218120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2708597821 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing _host_handshake.2708597821 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/46.usbdev_tx_rx_disruption.955119598 |
| Short name | T2942 |
| Test name | |
| Test status | |
| Simulation time | 540017887 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 08:04:26 AM UTC 24 |
| Finished | Aug 21 08:04:35 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=955119598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.usbdev_tx_rx_disruption.955119598 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/46.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/460.usbdev_tx_rx_disruption.2721680655 |
| Short name | T3587 |
| Test name | |
| Test status | |
| Simulation time | 540334142 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:42 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2721680655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 460.usbdev_tx_rx_disruption.2721680655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/460.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/461.usbdev_tx_rx_disruption.1808921752 |
| Short name | T3581 |
| Test name | |
| Test status | |
| Simulation time | 446179684 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:42 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1808921752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 461.usbdev_tx_rx_disruption.1808921752 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/461.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/462.usbdev_tx_rx_disruption.1842360312 |
| Short name | T3601 |
| Test name | |
| Test status | |
| Simulation time | 554331225 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:52 AM UTC 24 |
| Peak memory | 217692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1842360312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 462.usbdev_tx_rx_disruption.1842360312 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/462.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/463.usbdev_tx_rx_disruption.2052294274 |
| Short name | T3605 |
| Test name | |
| Test status | |
| Simulation time | 603908473 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:52 AM UTC 24 |
| Peak memory | 216148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2052294274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 463.usbdev_tx_rx_disruption.2052294274 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/463.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/464.usbdev_tx_rx_disruption.3224159300 |
| Short name | T3600 |
| Test name | |
| Test status | |
| Simulation time | 529596458 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:52 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3224159300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 464.usbdev_tx_rx_disruption.3224159300 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/464.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/465.usbdev_tx_rx_disruption.4215819369 |
| Short name | T3603 |
| Test name | |
| Test status | |
| Simulation time | 539805166 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:52 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4215819369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 465.usbdev_tx_rx_disruption.4215819369 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/465.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/466.usbdev_tx_rx_disruption.1161158612 |
| Short name | T3602 |
| Test name | |
| Test status | |
| Simulation time | 623139949 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:52 AM UTC 24 |
| Peak memory | 216084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1161158612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 466.usbdev_tx_rx_disruption.1161158612 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/466.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/467.usbdev_tx_rx_disruption.2940176973 |
| Short name | T3604 |
| Test name | |
| Test status | |
| Simulation time | 506806296 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 08:07:29 AM UTC 24 |
| Finished | Aug 21 08:07:52 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2940176973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 467.usbdev_tx_rx_disruption.2940176973 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/467.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/468.usbdev_tx_rx_disruption.2377542707 |
| Short name | T3562 |
| Test name | |
| Test status | |
| Simulation time | 574938023 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:07:30 AM UTC 24 |
| Finished | Aug 21 08:07:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2377542707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 468.usbdev_tx_rx_disruption.2377542707 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/468.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/469.usbdev_tx_rx_disruption.131152688 |
| Short name | T3597 |
| Test name | |
| Test status | |
| Simulation time | 568230281 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:07:30 AM UTC 24 |
| Finished | Aug 21 08:07:46 AM UTC 24 |
| Peak memory | 215992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=131152688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 469.usbdev_tx_rx_disruption.131152688 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/469.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_alert_test.2635483623 |
| Short name | T2979 |
| Test name | |
| Test status | |
| Simulation time | 44966607 ps |
| CPU time | 0.94 seconds |
| Started | Aug 21 08:04:43 AM UTC 24 |
| Finished | Aug 21 08:04:45 AM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2635483623 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.2635483623 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_aon_wake_disconnect.2132477493 |
| Short name | T2980 |
| Test name | |
| Test status | |
| Simulation time | 10827086999 ps |
| CPU time | 15.41 seconds |
| Started | Aug 21 08:04:28 AM UTC 24 |
| Finished | Aug 21 08:04:46 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2132477493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbd ev_aon_wake_disconnect.2132477493 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_aon_wake_reset.2336377814 |
| Short name | T2999 |
| Test name | |
| Test status | |
| Simulation time | 15744176905 ps |
| CPU time | 21.45 seconds |
| Started | Aug 21 08:04:28 AM UTC 24 |
| Finished | Aug 21 08:04:52 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2336377814 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.2336377814 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_aon_wake_resume.4001982413 |
| Short name | T3035 |
| Test name | |
| Test status | |
| Simulation time | 23922969042 ps |
| CPU time | 30.6 seconds |
| Started | Aug 21 08:04:28 AM UTC 24 |
| Finished | Aug 21 08:05:01 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4001982413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbd ev_aon_wake_resume.4001982413 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_av_buffer.1694894653 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 188482425 ps |
| CPU time | 0.87 seconds |
| Started | Aug 21 08:04:28 AM UTC 24 |
| Finished | Aug 21 08:04:31 AM UTC 24 |
| Peak memory | 216444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1694894653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1694894653 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_bitstuff_err.2727444956 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 144102603 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:04:29 AM UTC 24 |
| Finished | Aug 21 08:04:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2727444956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2727444956 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_data_toggle_clear.1293767908 |
| Short name | T2933 |
| Test name | |
| Test status | |
| Simulation time | 325757669 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 08:04:29 AM UTC 24 |
| Finished | Aug 21 08:04:32 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1293767908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.1293767908 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_data_toggle_restore.4068718129 |
| Short name | T2935 |
| Test name | |
| Test status | |
| Simulation time | 822562605 ps |
| CPU time | 2.62 seconds |
| Started | Aug 21 08:04:29 AM UTC 24 |
| Finished | Aug 21 08:04:33 AM UTC 24 |
| Peak memory | 218160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4068718129 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.4068718129 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_device_address.2774820975 |
| Short name | T3044 |
| Test name | |
| Test status | |
| Simulation time | 20141646716 ps |
| CPU time | 34.98 seconds |
| Started | Aug 21 08:04:29 AM UTC 24 |
| Finished | Aug 21 08:05:06 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2774820975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.2774820975 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_device_timeout.478041744 |
| Short name | T2985 |
| Test name | |
| Test status | |
| Simulation time | 846045752 ps |
| CPU time | 15.58 seconds |
| Started | Aug 21 08:04:29 AM UTC 24 |
| Finished | Aug 21 08:04:46 AM UTC 24 |
| Peak memory | 218124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=478041744 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.478041744 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_disable_endpoint.3599341594 |
| Short name | T2964 |
| Test name | |
| Test status | |
| Simulation time | 743798101 ps |
| CPU time | 2.06 seconds |
| Started | Aug 21 08:04:31 AM UTC 24 |
| Finished | Aug 21 08:04:42 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3599341594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.3599341594 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_disconnected.3399318342 |
| Short name | T2959 |
| Test name | |
| Test status | |
| Simulation time | 158798537 ps |
| CPU time | 0.79 seconds |
| Started | Aug 21 08:04:31 AM UTC 24 |
| Finished | Aug 21 08:04:40 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3399318342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3399318342 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_enable.2869838517 |
| Short name | T2968 |
| Test name | |
| Test status | |
| Simulation time | 37551097 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 08:04:33 AM UTC 24 |
| Finished | Aug 21 08:04:42 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2869838517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2869838517 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_endpoint_access.719739440 |
| Short name | T2949 |
| Test name | |
| Test status | |
| Simulation time | 908810287 ps |
| CPU time | 2.5 seconds |
| Started | Aug 21 08:04:33 AM UTC 24 |
| Finished | Aug 21 08:04:37 AM UTC 24 |
| Peak memory | 218284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=719739440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.719739440 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_endpoint_types.244861997 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 478724868 ps |
| CPU time | 1.85 seconds |
| Started | Aug 21 08:04:33 AM UTC 24 |
| Finished | Aug 21 08:04:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=244861997 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_types.244861997 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_fifo_rst.524732890 |
| Short name | T2946 |
| Test name | |
| Test status | |
| Simulation time | 214939016 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:04:33 AM UTC 24 |
| Finished | Aug 21 08:04:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=524732890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.524732890 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_in_iso.3497095835 |
| Short name | T2945 |
| Test name | |
| Test status | |
| Simulation time | 242757266 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:04:33 AM UTC 24 |
| Finished | Aug 21 08:04:36 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3497095835 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3497095835 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_in_stall.53173196 |
| Short name | T2972 |
| Test name | |
| Test status | |
| Simulation time | 141037250 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 08:04:33 AM UTC 24 |
| Finished | Aug 21 08:04:43 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=53173196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.53173196 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_in_trans.366126905 |
| Short name | T2973 |
| Test name | |
| Test status | |
| Simulation time | 227154442 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 08:04:33 AM UTC 24 |
| Finished | Aug 21 08:04:43 AM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=366126905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.366126905 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_invalid_sync.1018496817 |
| Short name | T3105 |
| Test name | |
| Test status | |
| Simulation time | 4688872289 ps |
| CPU time | 42.55 seconds |
| Started | Aug 21 08:04:33 AM UTC 24 |
| Finished | Aug 21 08:05:24 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1018496817 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.1018496817 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_iso_retraction.3884272724 |
| Short name | T2978 |
| Test name | |
| Test status | |
| Simulation time | 6043050136 ps |
| CPU time | 67.03 seconds |
| Started | Aug 21 08:04:33 AM UTC 24 |
| Finished | Aug 21 08:05:49 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3884272724 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.3884272724 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_link_in_err.3623993585 |
| Short name | T2974 |
| Test name | |
| Test status | |
| Simulation time | 155770601 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:04:33 AM UTC 24 |
| Finished | Aug 21 08:04:43 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3623993585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3623993585 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_link_resume.3654676431 |
| Short name | T3147 |
| Test name | |
| Test status | |
| Simulation time | 33878986087 ps |
| CPU time | 54.66 seconds |
| Started | Aug 21 08:04:33 AM UTC 24 |
| Finished | Aug 21 08:05:37 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3654676431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.3654676431 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_link_suspend.933045868 |
| Short name | T2989 |
| Test name | |
| Test status | |
| Simulation time | 5033498860 ps |
| CPU time | 6.76 seconds |
| Started | Aug 21 08:04:33 AM UTC 24 |
| Finished | Aug 21 08:04:49 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=933045868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.933045868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_low_speed_traffic.2641627599 |
| Short name | T3089 |
| Test name | |
| Test status | |
| Simulation time | 4652066780 ps |
| CPU time | 40.26 seconds |
| Started | Aug 21 08:04:35 AM UTC 24 |
| Finished | Aug 21 08:05:20 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2641627599 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.2641627599 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_max_inter_pkt_delay.3063176376 |
| Short name | T3235 |
| Test name | |
| Test status | |
| Simulation time | 3450883930 ps |
| CPU time | 85.2 seconds |
| Started | Aug 21 08:04:35 AM UTC 24 |
| Finished | Aug 21 08:06:02 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3063176376 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.3063176376 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_max_length_in_transaction.3905490524 |
| Short name | T2958 |
| Test name | |
| Test status | |
| Simulation time | 231430173 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 08:04:35 AM UTC 24 |
| Finished | Aug 21 08:04:40 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3905490524 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3905490524 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_max_length_out_transaction.247490708 |
| Short name | T2956 |
| Test name | |
| Test status | |
| Simulation time | 263108391 ps |
| CPU time | 0.91 seconds |
| Started | Aug 21 08:04:35 AM UTC 24 |
| Finished | Aug 21 08:04:40 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=247490708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.247490708 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_min_inter_pkt_delay.1462093099 |
| Short name | T3159 |
| Test name | |
| Test status | |
| Simulation time | 2364322426 ps |
| CPU time | 58.62 seconds |
| Started | Aug 21 08:04:35 AM UTC 24 |
| Finished | Aug 21 08:05:39 AM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1462093099 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.1462093099 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_min_length_in_transaction.643822634 |
| Short name | T2957 |
| Test name | |
| Test status | |
| Simulation time | 158381532 ps |
| CPU time | 0.88 seconds |
| Started | Aug 21 08:04:35 AM UTC 24 |
| Finished | Aug 21 08:04:40 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=643822634 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.643822634 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_min_length_out_transaction.1523938776 |
| Short name | T2952 |
| Test name | |
| Test status | |
| Simulation time | 193095958 ps |
| CPU time | 0.85 seconds |
| Started | Aug 21 08:04:36 AM UTC 24 |
| Finished | Aug 21 08:04:40 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1523938776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1523938776 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_nak_trans.1489038658 |
| Short name | T2965 |
| Test name | |
| Test status | |
| Simulation time | 217382397 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 08:04:36 AM UTC 24 |
| Finished | Aug 21 08:04:42 AM UTC 24 |
| Peak memory | 216444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1489038658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1489038658 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_out_iso.3554590771 |
| Short name | T2963 |
| Test name | |
| Test status | |
| Simulation time | 181830894 ps |
| CPU time | 0.89 seconds |
| Started | Aug 21 08:04:36 AM UTC 24 |
| Finished | Aug 21 08:04:42 AM UTC 24 |
| Peak memory | 216444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3554590771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3554590771 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_out_stall.3433733150 |
| Short name | T2962 |
| Test name | |
| Test status | |
| Simulation time | 172644174 ps |
| CPU time | 0.91 seconds |
| Started | Aug 21 08:04:37 AM UTC 24 |
| Finished | Aug 21 08:04:42 AM UTC 24 |
| Peak memory | 216432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3433733150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3433733150 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_out_trans_nak.840149860 |
| Short name | T2953 |
| Test name | |
| Test status | |
| Simulation time | 194898897 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 08:04:37 AM UTC 24 |
| Finished | Aug 21 08:04:40 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=840149860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.840149860 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_pending_in_trans.1151762222 |
| Short name | T2967 |
| Test name | |
| Test status | |
| Simulation time | 144298959 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 08:04:37 AM UTC 24 |
| Finished | Aug 21 08:04:42 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1151762222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.1151762222 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_phy_config_pinflip.1397459207 |
| Short name | T2966 |
| Test name | |
| Test status | |
| Simulation time | 225835193 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 08:04:37 AM UTC 24 |
| Finished | Aug 21 08:04:42 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1397459207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.1397459207 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_phy_config_usb_ref_disable.2358614549 |
| Short name | T2961 |
| Test name | |
| Test status | |
| Simulation time | 185238931 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 08:04:38 AM UTC 24 |
| Finished | Aug 21 08:04:41 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2358614549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2358614549 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_phy_pins_sense.674964545 |
| Short name | T2954 |
| Test name | |
| Test status | |
| Simulation time | 88768267 ps |
| CPU time | 0.71 seconds |
| Started | Aug 21 08:04:38 AM UTC 24 |
| Finished | Aug 21 08:04:40 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=674964545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.674964545 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_pkt_buffer.750217475 |
| Short name | T3014 |
| Test name | |
| Test status | |
| Simulation time | 6453902237 ps |
| CPU time | 16.04 seconds |
| Started | Aug 21 08:04:38 AM UTC 24 |
| Finished | Aug 21 08:04:57 AM UTC 24 |
| Peak memory | 228448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=750217475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.750217475 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_pkt_received.2930918819 |
| Short name | T2955 |
| Test name | |
| Test status | |
| Simulation time | 156761668 ps |
| CPU time | 0.8 seconds |
| Started | Aug 21 08:04:38 AM UTC 24 |
| Finished | Aug 21 08:04:40 AM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2930918819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2930918819 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_pkt_sent.1995600533 |
| Short name | T2971 |
| Test name | |
| Test status | |
| Simulation time | 215613267 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:04:40 AM UTC 24 |
| Finished | Aug 21 08:04:43 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1995600533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1995600533 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_random_length_in_transaction.1338846397 |
| Short name | T2970 |
| Test name | |
| Test status | |
| Simulation time | 193711274 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 08:04:40 AM UTC 24 |
| Finished | Aug 21 08:04:42 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1338846397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.1338846397 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_random_length_out_transaction.860509 |
| Short name | T2969 |
| Test name | |
| Test status | |
| Simulation time | 179348483 ps |
| CPU time | 0.86 seconds |
| Started | Aug 21 08:04:40 AM UTC 24 |
| Finished | Aug 21 08:04:42 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=860509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.860509 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_rx_crc_err.1270035016 |
| Short name | T2991 |
| Test name | |
| Test status | |
| Simulation time | 174438534 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 08:04:42 AM UTC 24 |
| Finished | Aug 21 08:04:50 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1270035016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1270035016 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_rx_full.1812176358 |
| Short name | T2977 |
| Test name | |
| Test status | |
| Simulation time | 334395782 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:04:42 AM UTC 24 |
| Finished | Aug 21 08:04:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1812176358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_full.1812176358 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_setup_stage.2754112441 |
| Short name | T2990 |
| Test name | |
| Test status | |
| Simulation time | 146956865 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:04:42 AM UTC 24 |
| Finished | Aug 21 08:04:50 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2754112441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2754112441 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_setup_trans_ignored.1739707011 |
| Short name | T2992 |
| Test name | |
| Test status | |
| Simulation time | 174332768 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 08:04:42 AM UTC 24 |
| Finished | Aug 21 08:04:50 AM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1739707011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1739707011 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_smoke.869182069 |
| Short name | T2994 |
| Test name | |
| Test status | |
| Simulation time | 210939751 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:04:42 AM UTC 24 |
| Finished | Aug 21 08:04:50 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=869182069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbde v-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.869182069 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_spurious_pids_ignored.1070624441 |
| Short name | T3098 |
| Test name | |
| Test status | |
| Simulation time | 3739316810 ps |
| CPU time | 32.52 seconds |
| Started | Aug 21 08:04:42 AM UTC 24 |
| Finished | Aug 21 08:05:22 AM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1070624441 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.1070624441 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_stall_priority_over_nak.1640521747 |
| Short name | T2997 |
| Test name | |
| Test status | |
| Simulation time | 183015243 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:04:42 AM UTC 24 |
| Finished | Aug 21 08:04:51 AM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1640521747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1640521747 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_stall_trans.3935293111 |
| Short name | T2993 |
| Test name | |
| Test status | |
| Simulation time | 159062292 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 08:04:42 AM UTC 24 |
| Finished | Aug 21 08:04:50 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3935293111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3935293111 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_stream_len_max.1965307942 |
| Short name | T2982 |
| Test name | |
| Test status | |
| Simulation time | 308959709 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:04:43 AM UTC 24 |
| Finished | Aug 21 08:04:46 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1965307942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1965307942 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_streaming_out.2514126919 |
| Short name | T3249 |
| Test name | |
| Test status | |
| Simulation time | 3592686758 ps |
| CPU time | 88.88 seconds |
| Started | Aug 21 08:04:43 AM UTC 24 |
| Finished | Aug 21 08:06:14 AM UTC 24 |
| Peak memory | 230696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2514126919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2514126919 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_timeout_missing_host_handshake.208567143 |
| Short name | T3054 |
| Test name | |
| Test status | |
| Simulation time | 4247719955 ps |
| CPU time | 25.61 seconds |
| Started | Aug 21 08:04:30 AM UTC 24 |
| Finished | Aug 21 08:05:07 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=208567143 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_ host_handshake.208567143 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/47.usbdev_tx_rx_disruption.224266051 |
| Short name | T2986 |
| Test name | |
| Test status | |
| Simulation time | 479350910 ps |
| CPU time | 1.86 seconds |
| Started | Aug 21 08:04:43 AM UTC 24 |
| Finished | Aug 21 08:04:46 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=224266051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.usbdev_tx_rx_disruption.224266051 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/47.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/470.usbdev_tx_rx_disruption.3839591777 |
| Short name | T3610 |
| Test name | |
| Test status | |
| Simulation time | 583907522 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:07:30 AM UTC 24 |
| Finished | Aug 21 08:07:53 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3839591777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 470.usbdev_tx_rx_disruption.3839591777 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/470.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/471.usbdev_tx_rx_disruption.2007965943 |
| Short name | T3561 |
| Test name | |
| Test status | |
| Simulation time | 516918499 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:07:30 AM UTC 24 |
| Finished | Aug 21 08:07:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2007965943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 471.usbdev_tx_rx_disruption.2007965943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/471.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/472.usbdev_tx_rx_disruption.172020608 |
| Short name | T3564 |
| Test name | |
| Test status | |
| Simulation time | 660235399 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:07:30 AM UTC 24 |
| Finished | Aug 21 08:07:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=172020608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 472.usbdev_tx_rx_disruption.172020608 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/472.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/473.usbdev_tx_rx_disruption.3043594793 |
| Short name | T3606 |
| Test name | |
| Test status | |
| Simulation time | 550223442 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:07:30 AM UTC 24 |
| Finished | Aug 21 08:07:53 AM UTC 24 |
| Peak memory | 216356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3043594793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 473.usbdev_tx_rx_disruption.3043594793 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/473.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/474.usbdev_tx_rx_disruption.3110149884 |
| Short name | T3598 |
| Test name | |
| Test status | |
| Simulation time | 539470124 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:07:32 AM UTC 24 |
| Finished | Aug 21 08:07:46 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3110149884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 474.usbdev_tx_rx_disruption.3110149884 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/474.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/475.usbdev_tx_rx_disruption.2129174067 |
| Short name | T3560 |
| Test name | |
| Test status | |
| Simulation time | 626529859 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:07:32 AM UTC 24 |
| Finished | Aug 21 08:07:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2129174067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 475.usbdev_tx_rx_disruption.2129174067 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/475.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/476.usbdev_tx_rx_disruption.355453227 |
| Short name | T3559 |
| Test name | |
| Test status | |
| Simulation time | 610809014 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:07:32 AM UTC 24 |
| Finished | Aug 21 08:07:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=355453227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 476.usbdev_tx_rx_disruption.355453227 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/476.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/477.usbdev_tx_rx_disruption.272035994 |
| Short name | T3607 |
| Test name | |
| Test status | |
| Simulation time | 430157675 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:07:32 AM UTC 24 |
| Finished | Aug 21 08:07:53 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=272035994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 477.usbdev_tx_rx_disruption.272035994 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/477.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/478.usbdev_tx_rx_disruption.894051573 |
| Short name | T3596 |
| Test name | |
| Test status | |
| Simulation time | 475324992 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:07:32 AM UTC 24 |
| Finished | Aug 21 08:07:46 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=894051573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 478.usbdev_tx_rx_disruption.894051573 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/478.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/479.usbdev_tx_rx_disruption.1627642178 |
| Short name | T3608 |
| Test name | |
| Test status | |
| Simulation time | 486509278 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:07:32 AM UTC 24 |
| Finished | Aug 21 08:07:53 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1627642178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 479.usbdev_tx_rx_disruption.1627642178 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/479.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_alert_test.2789261104 |
| Short name | T3047 |
| Test name | |
| Test status | |
| Simulation time | 35322532 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:07 AM UTC 24 |
| Peak memory | 216516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2789261104 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.2789261104 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_aon_wake_disconnect.2173989053 |
| Short name | T3037 |
| Test name | |
| Test status | |
| Simulation time | 11452250601 ps |
| CPU time | 19.12 seconds |
| Started | Aug 21 08:04:43 AM UTC 24 |
| Finished | Aug 21 08:05:04 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2173989053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbd ev_aon_wake_disconnect.2173989053 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_aon_wake_reset.3000551470 |
| Short name | T3075 |
| Test name | |
| Test status | |
| Simulation time | 20493044790 ps |
| CPU time | 28.48 seconds |
| Started | Aug 21 08:04:44 AM UTC 24 |
| Finished | Aug 21 08:05:13 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3000551470 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.3000551470 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_aon_wake_resume.3259586532 |
| Short name | T3109 |
| Test name | |
| Test status | |
| Simulation time | 29433362960 ps |
| CPU time | 39.74 seconds |
| Started | Aug 21 08:04:44 AM UTC 24 |
| Finished | Aug 21 08:05:25 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3259586532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbd ev_aon_wake_resume.3259586532 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_av_buffer.2888695796 |
| Short name | T2983 |
| Test name | |
| Test status | |
| Simulation time | 165024193 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 08:04:44 AM UTC 24 |
| Finished | Aug 21 08:04:46 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2888695796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2888695796 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_bitstuff_err.2989513447 |
| Short name | T2981 |
| Test name | |
| Test status | |
| Simulation time | 185299323 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 08:04:44 AM UTC 24 |
| Finished | Aug 21 08:04:46 AM UTC 24 |
| Peak memory | 216072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2989513447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.2989513447 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_data_toggle_clear.3833539826 |
| Short name | T2984 |
| Test name | |
| Test status | |
| Simulation time | 183515074 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 08:04:44 AM UTC 24 |
| Finished | Aug 21 08:04:46 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3833539826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.3833539826 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_data_toggle_restore.2937553377 |
| Short name | T2987 |
| Test name | |
| Test status | |
| Simulation time | 868304294 ps |
| CPU time | 2.88 seconds |
| Started | Aug 21 08:04:44 AM UTC 24 |
| Finished | Aug 21 08:04:48 AM UTC 24 |
| Peak memory | 218160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2937553377 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2937553377 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_device_address.3781464803 |
| Short name | T3222 |
| Test name | |
| Test status | |
| Simulation time | 45239144486 ps |
| CPU time | 69.85 seconds |
| Started | Aug 21 08:04:45 AM UTC 24 |
| Finished | Aug 21 08:05:59 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3781464803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.3781464803 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_device_timeout.1962569472 |
| Short name | T3001 |
| Test name | |
| Test status | |
| Simulation time | 728694576 ps |
| CPU time | 4.74 seconds |
| Started | Aug 21 08:04:45 AM UTC 24 |
| Finished | Aug 21 08:04:54 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1962569472 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.1962569472 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_disable_endpoint.3881535529 |
| Short name | T3010 |
| Test name | |
| Test status | |
| Simulation time | 417198270 ps |
| CPU time | 1.78 seconds |
| Started | Aug 21 08:04:46 AM UTC 24 |
| Finished | Aug 21 08:04:56 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3881535529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.3881535529 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_disconnected.1729056690 |
| Short name | T3003 |
| Test name | |
| Test status | |
| Simulation time | 174859185 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 08:04:46 AM UTC 24 |
| Finished | Aug 21 08:04:55 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1729056690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1729056690 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_enable.4212386444 |
| Short name | T2939 |
| Test name | |
| Test status | |
| Simulation time | 46485557 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 08:04:46 AM UTC 24 |
| Finished | Aug 21 08:04:54 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4212386444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.4212386444 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_endpoint_access.1782128805 |
| Short name | T3016 |
| Test name | |
| Test status | |
| Simulation time | 875310080 ps |
| CPU time | 2.87 seconds |
| Started | Aug 21 08:04:46 AM UTC 24 |
| Finished | Aug 21 08:04:57 AM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1782128805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1782128805 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_endpoint_types.700980317 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 292048980 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:04:46 AM UTC 24 |
| Finished | Aug 21 08:04:56 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=700980317 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_types.700980317 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_fifo_rst.2327379842 |
| Short name | T3015 |
| Test name | |
| Test status | |
| Simulation time | 188042977 ps |
| CPU time | 2.31 seconds |
| Started | Aug 21 08:04:46 AM UTC 24 |
| Finished | Aug 21 08:04:57 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2327379842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2327379842 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_in_iso.1040608741 |
| Short name | T3013 |
| Test name | |
| Test status | |
| Simulation time | 251292935 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 08:04:47 AM UTC 24 |
| Finished | Aug 21 08:04:56 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1040608741 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.1040608741 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_in_stall.929146102 |
| Short name | T2995 |
| Test name | |
| Test status | |
| Simulation time | 149207275 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 08:04:48 AM UTC 24 |
| Finished | Aug 21 08:04:51 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=929146102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.929146102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_in_trans.2637216710 |
| Short name | T2998 |
| Test name | |
| Test status | |
| Simulation time | 230289094 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:04:48 AM UTC 24 |
| Finished | Aug 21 08:04:51 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2637216710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2637216710 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_invalid_sync.1817989884 |
| Short name | T3146 |
| Test name | |
| Test status | |
| Simulation time | 4258669905 ps |
| CPU time | 40.66 seconds |
| Started | Aug 21 08:04:46 AM UTC 24 |
| Finished | Aug 21 08:05:36 AM UTC 24 |
| Peak memory | 235244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1817989884 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.1817989884 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_iso_retraction.582742834 |
| Short name | T3097 |
| Test name | |
| Test status | |
| Simulation time | 4897101815 ps |
| CPU time | 31.41 seconds |
| Started | Aug 21 08:04:49 AM UTC 24 |
| Finished | Aug 21 08:05:22 AM UTC 24 |
| Peak memory | 218312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=582742834 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.582742834 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_link_in_err.446467232 |
| Short name | T2996 |
| Test name | |
| Test status | |
| Simulation time | 163376691 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 08:04:49 AM UTC 24 |
| Finished | Aug 21 08:04:51 AM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=446467232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.446467232 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_link_resume.157797357 |
| Short name | T3142 |
| Test name | |
| Test status | |
| Simulation time | 24555475420 ps |
| CPU time | 41.33 seconds |
| Started | Aug 21 08:04:49 AM UTC 24 |
| Finished | Aug 21 08:05:32 AM UTC 24 |
| Peak memory | 228516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=157797357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.157797357 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_link_suspend.875106230 |
| Short name | T3074 |
| Test name | |
| Test status | |
| Simulation time | 9610891558 ps |
| CPU time | 14.31 seconds |
| Started | Aug 21 08:04:51 AM UTC 24 |
| Finished | Aug 21 08:05:13 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=875106230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.875106230 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_low_speed_traffic.3872440667 |
| Short name | T3165 |
| Test name | |
| Test status | |
| Simulation time | 5196870358 ps |
| CPU time | 46.76 seconds |
| Started | Aug 21 08:04:51 AM UTC 24 |
| Finished | Aug 21 08:05:43 AM UTC 24 |
| Peak memory | 230564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3872440667 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.3872440667 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_max_inter_pkt_delay.979766189 |
| Short name | T3192 |
| Test name | |
| Test status | |
| Simulation time | 2151845177 ps |
| CPU time | 50.86 seconds |
| Started | Aug 21 08:04:51 AM UTC 24 |
| Finished | Aug 21 08:05:50 AM UTC 24 |
| Peak memory | 228488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=979766189 -assert nopostproc +UVM _TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.979766189 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_max_length_in_transaction.2978601617 |
| Short name | T3024 |
| Test name | |
| Test status | |
| Simulation time | 246814239 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:04:52 AM UTC 24 |
| Finished | Aug 21 08:05:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2978601617 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.2978601617 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_max_length_out_transaction.2379283889 |
| Short name | T3019 |
| Test name | |
| Test status | |
| Simulation time | 198657290 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:04:52 AM UTC 24 |
| Finished | Aug 21 08:05:00 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2379283889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2379283889 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_min_inter_pkt_delay.405332346 |
| Short name | T3304 |
| Test name | |
| Test status | |
| Simulation time | 3454464731 ps |
| CPU time | 85.22 seconds |
| Started | Aug 21 08:04:52 AM UTC 24 |
| Finished | Aug 21 08:06:25 AM UTC 24 |
| Peak memory | 228640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=405332346 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.405332346 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_min_length_in_transaction.2369850903 |
| Short name | T3020 |
| Test name | |
| Test status | |
| Simulation time | 155331906 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:04:52 AM UTC 24 |
| Finished | Aug 21 08:05:00 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2369850903 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2369850903 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_min_length_out_transaction.1721234311 |
| Short name | T3006 |
| Test name | |
| Test status | |
| Simulation time | 149009116 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 08:04:53 AM UTC 24 |
| Finished | Aug 21 08:04:56 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1721234311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1721234311 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_nak_trans.3309159651 |
| Short name | T3005 |
| Test name | |
| Test status | |
| Simulation time | 195804129 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:04:53 AM UTC 24 |
| Finished | Aug 21 08:04:55 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3309159651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3309159651 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_out_iso.4147626355 |
| Short name | T3012 |
| Test name | |
| Test status | |
| Simulation time | 163304327 ps |
| CPU time | 1.16 seconds |
| Started | Aug 21 08:04:53 AM UTC 24 |
| Finished | Aug 21 08:04:56 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4147626355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.4147626355 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_out_stall.221391208 |
| Short name | T3009 |
| Test name | |
| Test status | |
| Simulation time | 149345251 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 08:04:54 AM UTC 24 |
| Finished | Aug 21 08:04:56 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=221391208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.221391208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_out_trans_nak.1467279492 |
| Short name | T3011 |
| Test name | |
| Test status | |
| Simulation time | 181948565 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:04:54 AM UTC 24 |
| Finished | Aug 21 08:04:56 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1467279492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1467279492 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_pending_in_trans.3560794292 |
| Short name | T3028 |
| Test name | |
| Test status | |
| Simulation time | 160607329 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 08:04:55 AM UTC 24 |
| Finished | Aug 21 08:05:01 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3560794292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.3560794292 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_phy_config_pinflip.798789915 |
| Short name | T3034 |
| Test name | |
| Test status | |
| Simulation time | 223804520 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:04:55 AM UTC 24 |
| Finished | Aug 21 08:05:01 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=798789915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.798789915 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_phy_config_usb_ref_disable.3828555757 |
| Short name | T3030 |
| Test name | |
| Test status | |
| Simulation time | 157745482 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 08:04:55 AM UTC 24 |
| Finished | Aug 21 08:05:01 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3828555757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3828555757 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_phy_pins_sense.324490706 |
| Short name | T3025 |
| Test name | |
| Test status | |
| Simulation time | 29980139 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 08:04:55 AM UTC 24 |
| Finished | Aug 21 08:05:00 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=324490706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.324490706 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_pkt_received.806973359 |
| Short name | T3042 |
| Test name | |
| Test status | |
| Simulation time | 168672214 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 08:04:57 AM UTC 24 |
| Finished | Aug 21 08:05:05 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=806973359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.806973359 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_pkt_sent.3724170036 |
| Short name | T3036 |
| Test name | |
| Test status | |
| Simulation time | 163111957 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:04:57 AM UTC 24 |
| Finished | Aug 21 08:05:02 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3724170036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3724170036 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_random_length_in_transaction.360566640 |
| Short name | T3031 |
| Test name | |
| Test status | |
| Simulation time | 266117643 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 08:04:57 AM UTC 24 |
| Finished | Aug 21 08:05:01 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=360566640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.360566640 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_random_length_out_transaction.2057030398 |
| Short name | T3022 |
| Test name | |
| Test status | |
| Simulation time | 169772938 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:04:57 AM UTC 24 |
| Finished | Aug 21 08:05:00 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2057030398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2057030398 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_rx_crc_err.2127818684 |
| Short name | T3027 |
| Test name | |
| Test status | |
| Simulation time | 138968032 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:04:57 AM UTC 24 |
| Finished | Aug 21 08:05:00 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2127818684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2127818684 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_rx_full.2987454543 |
| Short name | T3032 |
| Test name | |
| Test status | |
| Simulation time | 303979932 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 08:04:57 AM UTC 24 |
| Finished | Aug 21 08:05:01 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2987454543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_full.2987454543 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_setup_stage.3937849620 |
| Short name | T3023 |
| Test name | |
| Test status | |
| Simulation time | 144927783 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 08:04:57 AM UTC 24 |
| Finished | Aug 21 08:05:00 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3937849620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3937849620 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_setup_trans_ignored.1818635452 |
| Short name | T3021 |
| Test name | |
| Test status | |
| Simulation time | 187103359 ps |
| CPU time | 0.89 seconds |
| Started | Aug 21 08:04:57 AM UTC 24 |
| Finished | Aug 21 08:05:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1818635452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1818635452 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_smoke.1296090750 |
| Short name | T3029 |
| Test name | |
| Test status | |
| Simulation time | 194735626 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 08:04:57 AM UTC 24 |
| Finished | Aug 21 08:05:01 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1296090750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1296090750 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_spurious_pids_ignored.429118051 |
| Short name | T3204 |
| Test name | |
| Test status | |
| Simulation time | 2181129824 ps |
| CPU time | 52.07 seconds |
| Started | Aug 21 08:04:58 AM UTC 24 |
| Finished | Aug 21 08:05:52 AM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=429118051 -assert nopostproc +UVM_TESTNAME=usbdev_bas e_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.429118051 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_stall_priority_over_nak.3415129633 |
| Short name | T3026 |
| Test name | |
| Test status | |
| Simulation time | 160912038 ps |
| CPU time | 0.91 seconds |
| Started | Aug 21 08:04:58 AM UTC 24 |
| Finished | Aug 21 08:05:00 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3415129633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3415129633 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_stall_trans.205490360 |
| Short name | T3033 |
| Test name | |
| Test status | |
| Simulation time | 167991838 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:04:58 AM UTC 24 |
| Finished | Aug 21 08:05:01 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=205490360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.205490360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_stream_len_max.1927058357 |
| Short name | T3050 |
| Test name | |
| Test status | |
| Simulation time | 898321442 ps |
| CPU time | 2.71 seconds |
| Started | Aug 21 08:05:00 AM UTC 24 |
| Finished | Aug 21 08:05:07 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1927058357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.1927058357 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_streaming_out.2236189107 |
| Short name | T3080 |
| Test name | |
| Test status | |
| Simulation time | 2158491057 ps |
| CPU time | 15.91 seconds |
| Started | Aug 21 08:04:58 AM UTC 24 |
| Finished | Aug 21 08:05:16 AM UTC 24 |
| Peak memory | 230476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2236189107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.2236189107 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_timeout_missing_host_handshake.2392783094 |
| Short name | T3008 |
| Test name | |
| Test status | |
| Simulation time | 438523687 ps |
| CPU time | 6.84 seconds |
| Started | Aug 21 08:04:45 AM UTC 24 |
| Finished | Aug 21 08:04:56 AM UTC 24 |
| Peak memory | 218192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2392783094 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing _host_handshake.2392783094 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/48.usbdev_tx_rx_disruption.1593170092 |
| Short name | T3052 |
| Test name | |
| Test status | |
| Simulation time | 494492190 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:07 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1593170092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 48.usbdev_tx_rx_disruption.1593170092 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/48.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/480.usbdev_tx_rx_disruption.2839897653 |
| Short name | T3599 |
| Test name | |
| Test status | |
| Simulation time | 518259109 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 08:07:32 AM UTC 24 |
| Finished | Aug 21 08:07:46 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2839897653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 480.usbdev_tx_rx_disruption.2839897653 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/480.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/481.usbdev_tx_rx_disruption.3196989932 |
| Short name | T3609 |
| Test name | |
| Test status | |
| Simulation time | 501462504 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 08:07:32 AM UTC 24 |
| Finished | Aug 21 08:07:53 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3196989932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 481.usbdev_tx_rx_disruption.3196989932 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/481.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/482.usbdev_tx_rx_disruption.3634862343 |
| Short name | T3615 |
| Test name | |
| Test status | |
| Simulation time | 554303215 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:07:32 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3634862343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 482.usbdev_tx_rx_disruption.3634862343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/482.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/483.usbdev_tx_rx_disruption.769539186 |
| Short name | T3565 |
| Test name | |
| Test status | |
| Simulation time | 546654793 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:07:32 AM UTC 24 |
| Finished | Aug 21 08:07:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=769539186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 483.usbdev_tx_rx_disruption.769539186 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/483.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/484.usbdev_tx_rx_disruption.80589371 |
| Short name | T3612 |
| Test name | |
| Test status | |
| Simulation time | 511603614 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:07:32 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=80589371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 484.usbdev_tx_rx_disruption.80589371 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/484.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/485.usbdev_tx_rx_disruption.1855456463 |
| Short name | T3617 |
| Test name | |
| Test status | |
| Simulation time | 568252778 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:07:33 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1855456463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 485.usbdev_tx_rx_disruption.1855456463 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/485.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/486.usbdev_tx_rx_disruption.1314550065 |
| Short name | T3591 |
| Test name | |
| Test status | |
| Simulation time | 494497463 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:07:33 AM UTC 24 |
| Finished | Aug 21 08:07:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1314550065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 486.usbdev_tx_rx_disruption.1314550065 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/486.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/487.usbdev_tx_rx_disruption.2180696641 |
| Short name | T3595 |
| Test name | |
| Test status | |
| Simulation time | 630051713 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:07:33 AM UTC 24 |
| Finished | Aug 21 08:07:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2180696641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 487.usbdev_tx_rx_disruption.2180696641 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/487.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/488.usbdev_tx_rx_disruption.2502051833 |
| Short name | T3593 |
| Test name | |
| Test status | |
| Simulation time | 530130977 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:07:33 AM UTC 24 |
| Finished | Aug 21 08:07:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2502051833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 488.usbdev_tx_rx_disruption.2502051833 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/488.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/489.usbdev_tx_rx_disruption.1544720798 |
| Short name | T3592 |
| Test name | |
| Test status | |
| Simulation time | 462346824 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:07:33 AM UTC 24 |
| Finished | Aug 21 08:07:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1544720798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 489.usbdev_tx_rx_disruption.1544720798 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/489.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_alert_test.989163259 |
| Short name | T3091 |
| Test name | |
| Test status | |
| Simulation time | 52440961 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:05:16 AM UTC 24 |
| Finished | Aug 21 08:05:21 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=989163259 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.989163259 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_aon_wake_disconnect.2948760207 |
| Short name | T3112 |
| Test name | |
| Test status | |
| Simulation time | 11042786053 ps |
| CPU time | 19.07 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:25 AM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2948760207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbd ev_aon_wake_disconnect.2948760207 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_aon_wake_reset.3498298422 |
| Short name | T3123 |
| Test name | |
| Test status | |
| Simulation time | 19077064679 ps |
| CPU time | 22.5 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3498298422 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3498298422 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_aon_wake_resume.3386490843 |
| Short name | T3164 |
| Test name | |
| Test status | |
| Simulation time | 28531650384 ps |
| CPU time | 36.48 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:43 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3386490843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbd ev_aon_wake_resume.3386490843 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_av_buffer.2888517292 |
| Short name | T3049 |
| Test name | |
| Test status | |
| Simulation time | 156020318 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:07 AM UTC 24 |
| Peak memory | 216304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2888517292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.2888517292 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_bitstuff_err.3980512086 |
| Short name | T3041 |
| Test name | |
| Test status | |
| Simulation time | 166063409 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:05 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3980512086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.3980512086 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_data_toggle_clear.3749361549 |
| Short name | T3040 |
| Test name | |
| Test status | |
| Simulation time | 266539172 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:05 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3749361549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.3749361549 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_data_toggle_restore.1272970272 |
| Short name | T3043 |
| Test name | |
| Test status | |
| Simulation time | 392294751 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:06 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1272970272 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.1272970272 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_device_address.2946983666 |
| Short name | T3203 |
| Test name | |
| Test status | |
| Simulation time | 31416500302 ps |
| CPU time | 47.57 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:52 AM UTC 24 |
| Peak memory | 218436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2946983666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2946983666 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_device_timeout.880160740 |
| Short name | T3162 |
| Test name | |
| Test status | |
| Simulation time | 6390427715 ps |
| CPU time | 36.57 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:41 AM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=880160740 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.880160740 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_disable_endpoint.1646646112 |
| Short name | T3045 |
| Test name | |
| Test status | |
| Simulation time | 560565281 ps |
| CPU time | 1.82 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:06 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1646646112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1646646112 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_disconnected.1469331845 |
| Short name | T3039 |
| Test name | |
| Test status | |
| Simulation time | 154980874 ps |
| CPU time | 0.86 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:05 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1469331845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1469331845 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_enable.691756137 |
| Short name | T3038 |
| Test name | |
| Test status | |
| Simulation time | 72210342 ps |
| CPU time | 0.71 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:05 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=691756137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.691756137 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_endpoint_access.3682024168 |
| Short name | T3048 |
| Test name | |
| Test status | |
| Simulation time | 782885130 ps |
| CPU time | 2.38 seconds |
| Started | Aug 21 08:05:03 AM UTC 24 |
| Finished | Aug 21 08:05:07 AM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3682024168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3682024168 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_fifo_rst.4170116626 |
| Short name | T3053 |
| Test name | |
| Test status | |
| Simulation time | 183964236 ps |
| CPU time | 1.92 seconds |
| Started | Aug 21 08:05:04 AM UTC 24 |
| Finished | Aug 21 08:05:07 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4170116626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.4170116626 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_in_iso.3148066547 |
| Short name | T3055 |
| Test name | |
| Test status | |
| Simulation time | 181772096 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 08:05:06 AM UTC 24 |
| Finished | Aug 21 08:05:08 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3148066547 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3148066547 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_in_stall.1524708927 |
| Short name | T3060 |
| Test name | |
| Test status | |
| Simulation time | 160879031 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 08:05:07 AM UTC 24 |
| Finished | Aug 21 08:05:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1524708927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1524708927 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_in_trans.517752700 |
| Short name | T3061 |
| Test name | |
| Test status | |
| Simulation time | 187144819 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:05:07 AM UTC 24 |
| Finished | Aug 21 08:05:11 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=517752700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.517752700 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_invalid_sync.1794421588 |
| Short name | T3132 |
| Test name | |
| Test status | |
| Simulation time | 2674500390 ps |
| CPU time | 22.5 seconds |
| Started | Aug 21 08:05:06 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 235180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1794421588 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1794421588 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_iso_retraction.2927189801 |
| Short name | T3337 |
| Test name | |
| Test status | |
| Simulation time | 13236583424 ps |
| CPU time | 83.65 seconds |
| Started | Aug 21 08:05:07 AM UTC 24 |
| Finished | Aug 21 08:06:34 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2927189801 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.2927189801 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_link_in_err.40929410 |
| Short name | T3064 |
| Test name | |
| Test status | |
| Simulation time | 238542018 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 08:05:07 AM UTC 24 |
| Finished | Aug 21 08:05:11 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40929410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.40929410 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_link_resume.483137164 |
| Short name | T3205 |
| Test name | |
| Test status | |
| Simulation time | 28356165489 ps |
| CPU time | 43.08 seconds |
| Started | Aug 21 08:05:07 AM UTC 24 |
| Finished | Aug 21 08:05:53 AM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=483137164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.483137164 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_link_suspend.3514548450 |
| Short name | T3124 |
| Test name | |
| Test status | |
| Simulation time | 11228619325 ps |
| CPU time | 18.74 seconds |
| Started | Aug 21 08:05:08 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3514548450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3514548450 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_low_speed_traffic.3837212747 |
| Short name | T3145 |
| Test name | |
| Test status | |
| Simulation time | 3792813285 ps |
| CPU time | 25.75 seconds |
| Started | Aug 21 08:05:08 AM UTC 24 |
| Finished | Aug 21 08:05:36 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3837212747 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.3837212747 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_max_inter_pkt_delay.3400793453 |
| Short name | T3144 |
| Test name | |
| Test status | |
| Simulation time | 2641694700 ps |
| CPU time | 24 seconds |
| Started | Aug 21 08:05:08 AM UTC 24 |
| Finished | Aug 21 08:05:34 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3400793453 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.3400793453 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_max_length_in_transaction.4256391910 |
| Short name | T3062 |
| Test name | |
| Test status | |
| Simulation time | 309144685 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 08:05:08 AM UTC 24 |
| Finished | Aug 21 08:05:11 AM UTC 24 |
| Peak memory | 216264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4256391910 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.4256391910 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_max_length_out_transaction.2042497328 |
| Short name | T3063 |
| Test name | |
| Test status | |
| Simulation time | 199177068 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:05:08 AM UTC 24 |
| Finished | Aug 21 08:05:11 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2042497328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2042497328 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_min_inter_pkt_delay.1151172533 |
| Short name | T3143 |
| Test name | |
| Test status | |
| Simulation time | 2547146477 ps |
| CPU time | 22.89 seconds |
| Started | Aug 21 08:05:09 AM UTC 24 |
| Finished | Aug 21 08:05:33 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1151172533 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.1151172533 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_min_length_in_transaction.208719543 |
| Short name | T3068 |
| Test name | |
| Test status | |
| Simulation time | 167712220 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:05:09 AM UTC 24 |
| Finished | Aug 21 08:05:11 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=208719543 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.208719543 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_min_length_out_transaction.2403388440 |
| Short name | T3067 |
| Test name | |
| Test status | |
| Simulation time | 151869566 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 08:05:09 AM UTC 24 |
| Finished | Aug 21 08:05:11 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2403388440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2403388440 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_nak_trans.3659178661 |
| Short name | T3070 |
| Test name | |
| Test status | |
| Simulation time | 187803613 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:05:09 AM UTC 24 |
| Finished | Aug 21 08:05:12 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3659178661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3659178661 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_out_iso.3283638806 |
| Short name | T3065 |
| Test name | |
| Test status | |
| Simulation time | 205288739 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 08:05:09 AM UTC 24 |
| Finished | Aug 21 08:05:11 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3283638806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.3283638806 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_out_stall.2607656000 |
| Short name | T3066 |
| Test name | |
| Test status | |
| Simulation time | 155505191 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 08:05:09 AM UTC 24 |
| Finished | Aug 21 08:05:11 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2607656000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2607656000 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_out_trans_nak.502607668 |
| Short name | T3072 |
| Test name | |
| Test status | |
| Simulation time | 184083406 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:05:10 AM UTC 24 |
| Finished | Aug 21 08:05:13 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=502607668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.502607668 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_pending_in_trans.1444650169 |
| Short name | T3073 |
| Test name | |
| Test status | |
| Simulation time | 187501981 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:05:10 AM UTC 24 |
| Finished | Aug 21 08:05:13 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1444650169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1444650169 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_phy_config_pinflip.1567311099 |
| Short name | T3078 |
| Test name | |
| Test status | |
| Simulation time | 267002660 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 08:05:12 AM UTC 24 |
| Finished | Aug 21 08:05:14 AM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1567311099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1567311099 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_phy_config_usb_ref_disable.3654690282 |
| Short name | T3059 |
| Test name | |
| Test status | |
| Simulation time | 137771317 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 08:05:12 AM UTC 24 |
| Finished | Aug 21 08:05:14 AM UTC 24 |
| Peak memory | 215948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3654690282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3654690282 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_phy_pins_sense.4090078983 |
| Short name | T3058 |
| Test name | |
| Test status | |
| Simulation time | 37990790 ps |
| CPU time | 0.79 seconds |
| Started | Aug 21 08:05:12 AM UTC 24 |
| Finished | Aug 21 08:05:14 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4090078983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.4090078983 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_buffer.3655040852 |
| Short name | T3239 |
| Test name | |
| Test status | |
| Simulation time | 22112072648 ps |
| CPU time | 52.1 seconds |
| Started | Aug 21 08:05:12 AM UTC 24 |
| Finished | Aug 21 08:06:06 AM UTC 24 |
| Peak memory | 228512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3655040852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3655040852 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_received.630716831 |
| Short name | T3046 |
| Test name | |
| Test status | |
| Simulation time | 184187286 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 08:05:12 AM UTC 24 |
| Finished | Aug 21 08:05:14 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=630716831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.630716831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_sent.1840040128 |
| Short name | T3051 |
| Test name | |
| Test status | |
| Simulation time | 207448703 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 08:05:12 AM UTC 24 |
| Finished | Aug 21 08:05:14 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1840040128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1840040128 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_random_length_in_transaction.2967187970 |
| Short name | T3079 |
| Test name | |
| Test status | |
| Simulation time | 194291612 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:05:12 AM UTC 24 |
| Finished | Aug 21 08:05:15 AM UTC 24 |
| Peak memory | 216080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2967187970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.2967187970 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_random_length_out_transaction.1873448714 |
| Short name | T3077 |
| Test name | |
| Test status | |
| Simulation time | 163039762 ps |
| CPU time | 1.16 seconds |
| Started | Aug 21 08:05:12 AM UTC 24 |
| Finished | Aug 21 08:05:14 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1873448714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.1873448714 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_rx_crc_err.1677017614 |
| Short name | T3076 |
| Test name | |
| Test status | |
| Simulation time | 156408658 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 08:05:12 AM UTC 24 |
| Finished | Aug 21 08:05:14 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1677017614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.1677017614 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_rx_full.29118924 |
| Short name | T3084 |
| Test name | |
| Test status | |
| Simulation time | 327422065 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 08:05:14 AM UTC 24 |
| Finished | Aug 21 08:05:16 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29118924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_full.29118924 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_setup_stage.4271957171 |
| Short name | T3082 |
| Test name | |
| Test status | |
| Simulation time | 154254858 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:05:14 AM UTC 24 |
| Finished | Aug 21 08:05:16 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4271957171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.4271957171 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_setup_trans_ignored.515988572 |
| Short name | T3083 |
| Test name | |
| Test status | |
| Simulation time | 226098358 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:05:14 AM UTC 24 |
| Finished | Aug 21 08:05:16 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=515988572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.515988572 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_smoke.1097341819 |
| Short name | T3085 |
| Test name | |
| Test status | |
| Simulation time | 238001402 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 08:05:14 AM UTC 24 |
| Finished | Aug 21 08:05:16 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1097341819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1097341819 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_spurious_pids_ignored.315839177 |
| Short name | T3282 |
| Test name | |
| Test status | |
| Simulation time | 2710959762 ps |
| CPU time | 62.96 seconds |
| Started | Aug 21 08:05:14 AM UTC 24 |
| Finished | Aug 21 08:06:18 AM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=315839177 -assert nopostproc +UVM_TESTNAME=usbdev_bas e_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.315839177 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_stall_priority_over_nak.3734777677 |
| Short name | T3081 |
| Test name | |
| Test status | |
| Simulation time | 201092644 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 08:05:14 AM UTC 24 |
| Finished | Aug 21 08:05:16 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3734777677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3734777677 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_stall_trans.1649668063 |
| Short name | T3086 |
| Test name | |
| Test status | |
| Simulation time | 171117635 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:05:15 AM UTC 24 |
| Finished | Aug 21 08:05:18 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1649668063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1649668063 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_stream_len_max.3187228461 |
| Short name | T3103 |
| Test name | |
| Test status | |
| Simulation time | 1013781230 ps |
| CPU time | 3.69 seconds |
| Started | Aug 21 08:05:15 AM UTC 24 |
| Finished | Aug 21 08:05:23 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3187228461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.3187228461 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_streaming_out.4064739287 |
| Short name | T3161 |
| Test name | |
| Test status | |
| Simulation time | 3231876795 ps |
| CPU time | 23.13 seconds |
| Started | Aug 21 08:05:15 AM UTC 24 |
| Finished | Aug 21 08:05:40 AM UTC 24 |
| Peak memory | 230176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4064739287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.4064739287 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_timeout_missing_host_handshake.3742769825 |
| Short name | T3056 |
| Test name | |
| Test status | |
| Simulation time | 855466731 ps |
| CPU time | 4.93 seconds |
| Started | Aug 21 08:05:02 AM UTC 24 |
| Finished | Aug 21 08:05:09 AM UTC 24 |
| Peak memory | 218112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3742769825 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing _host_handshake.3742769825 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/49.usbdev_tx_rx_disruption.1293495271 |
| Short name | T3088 |
| Test name | |
| Test status | |
| Simulation time | 598439302 ps |
| CPU time | 2.89 seconds |
| Started | Aug 21 08:05:15 AM UTC 24 |
| Finished | Aug 21 08:05:19 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1293495271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 49.usbdev_tx_rx_disruption.1293495271 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/49.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/490.usbdev_tx_rx_disruption.3125863274 |
| Short name | T3594 |
| Test name | |
| Test status | |
| Simulation time | 485851608 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:07:33 AM UTC 24 |
| Finished | Aug 21 08:07:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3125863274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 490.usbdev_tx_rx_disruption.3125863274 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/490.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/491.usbdev_tx_rx_disruption.3148430318 |
| Short name | T3611 |
| Test name | |
| Test status | |
| Simulation time | 466434284 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:07:33 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3148430318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 491.usbdev_tx_rx_disruption.3148430318 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/491.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/492.usbdev_tx_rx_disruption.1497963015 |
| Short name | T3616 |
| Test name | |
| Test status | |
| Simulation time | 565744120 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:07:33 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1497963015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 492.usbdev_tx_rx_disruption.1497963015 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/492.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/493.usbdev_tx_rx_disruption.3909045743 |
| Short name | T3613 |
| Test name | |
| Test status | |
| Simulation time | 470011237 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:07:33 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3909045743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 493.usbdev_tx_rx_disruption.3909045743 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/493.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/494.usbdev_tx_rx_disruption.2726580426 |
| Short name | T3619 |
| Test name | |
| Test status | |
| Simulation time | 670956831 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 08:07:33 AM UTC 24 |
| Finished | Aug 21 08:07:57 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2726580426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 494.usbdev_tx_rx_disruption.2726580426 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/494.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/495.usbdev_tx_rx_disruption.66272164 |
| Short name | T3614 |
| Test name | |
| Test status | |
| Simulation time | 464670668 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:07:33 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=66272164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 495.usbdev_tx_rx_disruption.66272164 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/495.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/496.usbdev_tx_rx_disruption.2658063805 |
| Short name | T3620 |
| Test name | |
| Test status | |
| Simulation time | 639977919 ps |
| CPU time | 1.71 seconds |
| Started | Aug 21 08:07:34 AM UTC 24 |
| Finished | Aug 21 08:07:57 AM UTC 24 |
| Peak memory | 216156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2658063805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 496.usbdev_tx_rx_disruption.2658063805 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/496.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/497.usbdev_tx_rx_disruption.1118794252 |
| Short name | T3618 |
| Test name | |
| Test status | |
| Simulation time | 466114604 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:07:34 AM UTC 24 |
| Finished | Aug 21 08:07:56 AM UTC 24 |
| Peak memory | 216036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1118794252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 497.usbdev_tx_rx_disruption.1118794252 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/497.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/498.usbdev_tx_rx_disruption.3542736415 |
| Short name | T3566 |
| Test name | |
| Test status | |
| Simulation time | 591681576 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 08:07:37 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 216444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3542736415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 498.usbdev_tx_rx_disruption.3542736415 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/498.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/499.usbdev_tx_rx_disruption.269761197 |
| Short name | T3568 |
| Test name | |
| Test status | |
| Simulation time | 485541228 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:07:37 AM UTC 24 |
| Finished | Aug 21 08:07:41 AM UTC 24 |
| Peak memory | 216140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=269761197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 499.usbdev_tx_rx_disruption.269761197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/499.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_alert_test.3212952068 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 34639160 ps |
| CPU time | 0.94 seconds |
| Started | Aug 21 07:53:01 AM UTC 24 |
| Finished | Aug 21 07:53:03 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3212952068 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.3212952068 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_aon_wake_disconnect.2181740486 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 5307009271 ps |
| CPU time | 15.88 seconds |
| Started | Aug 21 07:52:20 AM UTC 24 |
| Finished | Aug 21 07:52:37 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2181740486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbde v_aon_wake_disconnect.2181740486 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_aon_wake_reset.4220925918 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 15585864235 ps |
| CPU time | 36.89 seconds |
| Started | Aug 21 07:52:22 AM UTC 24 |
| Finished | Aug 21 07:53:00 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4220925918 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.4220925918 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_aon_wake_resume.4128826747 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 24997359923 ps |
| CPU time | 42.37 seconds |
| Started | Aug 21 07:52:22 AM UTC 24 |
| Finished | Aug 21 07:53:05 AM UTC 24 |
| Peak memory | 228608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4128826747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbde v_aon_wake_resume.4128826747 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_av_buffer.1244793895 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 177727607 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:52:23 AM UTC 24 |
| Finished | Aug 21 07:52:26 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1244793895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1244793895 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_bitstuff_err.983413544 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 164126718 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:52:23 AM UTC 24 |
| Finished | Aug 21 07:52:26 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=983413544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.983413544 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_data_toggle_clear.981494369 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 145011034 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:52:23 AM UTC 24 |
| Finished | Aug 21 07:52:26 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=981494369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.981494369 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_data_toggle_restore.2378113136 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 411168747 ps |
| CPU time | 2.11 seconds |
| Started | Aug 21 07:52:23 AM UTC 24 |
| Finished | Aug 21 07:52:27 AM UTC 24 |
| Peak memory | 218196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2378113136 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2378113136 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_device_address.234653859 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 30012466780 ps |
| CPU time | 50.74 seconds |
| Started | Aug 21 07:52:25 AM UTC 24 |
| Finished | Aug 21 07:53:17 AM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=234653859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.234653859 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_device_timeout.1420263534 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4362348631 ps |
| CPU time | 40.39 seconds |
| Started | Aug 21 07:52:25 AM UTC 24 |
| Finished | Aug 21 07:53:07 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1420263534 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.1420263534 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_disable_endpoint.1845115115 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 618528983 ps |
| CPU time | 2.93 seconds |
| Started | Aug 21 07:52:26 AM UTC 24 |
| Finished | Aug 21 07:52:30 AM UTC 24 |
| Peak memory | 218040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1845115115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.1845115115 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_disconnected.593015007 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 143545814 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:52:27 AM UTC 24 |
| Finished | Aug 21 07:52:30 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=593015007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.593015007 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_enable.721101736 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 60456124 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 07:52:27 AM UTC 24 |
| Finished | Aug 21 07:52:29 AM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=721101736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.721101736 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_endpoint_access.3000516218 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1044836538 ps |
| CPU time | 4.4 seconds |
| Started | Aug 21 07:52:27 AM UTC 24 |
| Finished | Aug 21 07:52:33 AM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3000516218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3000516218 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_endpoint_types.817458992 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 819832903 ps |
| CPU time | 3.06 seconds |
| Started | Aug 21 07:52:28 AM UTC 24 |
| Finished | Aug 21 07:52:32 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=817458992 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_types.817458992 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_fifo_rst.4031772733 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 154150475 ps |
| CPU time | 2.12 seconds |
| Started | Aug 21 07:52:29 AM UTC 24 |
| Finished | Aug 21 07:52:33 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4031772733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.4031772733 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_in_iso.2609965950 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 236325694 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 07:52:31 AM UTC 24 |
| Finished | Aug 21 07:52:33 AM UTC 24 |
| Peak memory | 226632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2609965950 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2609965950 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_in_stall.3155809570 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 140269849 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:52:31 AM UTC 24 |
| Finished | Aug 21 07:52:33 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3155809570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3155809570 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_in_trans.906306089 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 165128536 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:52:31 AM UTC 24 |
| Finished | Aug 21 07:52:33 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=906306089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.906306089 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_invalid_sync.2641675077 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2475060008 ps |
| CPU time | 29.92 seconds |
| Started | Aug 21 07:52:31 AM UTC 24 |
| Finished | Aug 21 07:53:02 AM UTC 24 |
| Peak memory | 230616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2641675077 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.2641675077 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_iso_retraction.3816597843 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 10563121140 ps |
| CPU time | 74.4 seconds |
| Started | Aug 21 07:52:33 AM UTC 24 |
| Finished | Aug 21 07:53:49 AM UTC 24 |
| Peak memory | 218240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3816597843 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.3816597843 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_link_in_err.513575925 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 176296332 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:52:33 AM UTC 24 |
| Finished | Aug 21 07:52:35 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=513575925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.513575925 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_link_resume.573849897 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 30836679619 ps |
| CPU time | 53.16 seconds |
| Started | Aug 21 07:52:34 AM UTC 24 |
| Finished | Aug 21 07:53:29 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=573849897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.573849897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_link_suspend.807115742 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 4506420325 ps |
| CPU time | 12.2 seconds |
| Started | Aug 21 07:52:34 AM UTC 24 |
| Finished | Aug 21 07:52:47 AM UTC 24 |
| Peak memory | 218232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=807115742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.807115742 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_low_speed_traffic.1662649509 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3748111309 ps |
| CPU time | 37.12 seconds |
| Started | Aug 21 07:52:34 AM UTC 24 |
| Finished | Aug 21 07:53:13 AM UTC 24 |
| Peak memory | 230724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1662649509 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.1662649509 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_max_inter_pkt_delay.336471339 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 2262095592 ps |
| CPU time | 25.7 seconds |
| Started | Aug 21 07:52:34 AM UTC 24 |
| Finished | Aug 21 07:53:01 AM UTC 24 |
| Peak memory | 235272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=336471339 -assert nopostproc +UVM _TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.336471339 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_max_length_in_transaction.1211596435 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 248653242 ps |
| CPU time | 1.73 seconds |
| Started | Aug 21 07:52:34 AM UTC 24 |
| Finished | Aug 21 07:52:37 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1211596435 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.1211596435 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_max_length_out_transaction.174737760 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 196985470 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:52:36 AM UTC 24 |
| Finished | Aug 21 07:52:39 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=174737760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.174737760 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_max_non_iso_usb_traffic.2930621322 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 2438949934 ps |
| CPU time | 66.21 seconds |
| Started | Aug 21 07:52:37 AM UTC 24 |
| Finished | Aug 21 07:53:45 AM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2930621322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_non_iso_usb_traffic.2930621322 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_max_usb_traffic.4144325118 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1879451232 ps |
| CPU time | 18.91 seconds |
| Started | Aug 21 07:52:38 AM UTC 24 |
| Finished | Aug 21 07:52:58 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4144325118 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.4144325118 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_min_inter_pkt_delay.248241816 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2726552247 ps |
| CPU time | 29.11 seconds |
| Started | Aug 21 07:52:38 AM UTC 24 |
| Finished | Aug 21 07:53:08 AM UTC 24 |
| Peak memory | 230544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=248241816 -assert nopostproc +UVM_T ESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.248241816 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_min_length_in_transaction.860065073 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 154266739 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:52:38 AM UTC 24 |
| Finished | Aug 21 07:52:40 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=860065073 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.860065073 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_min_length_out_transaction.2317306425 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 149366048 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:52:39 AM UTC 24 |
| Finished | Aug 21 07:52:41 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2317306425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2317306425 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_nak_trans.1393858261 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 244580084 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 07:52:40 AM UTC 24 |
| Finished | Aug 21 07:52:42 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1393858261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1393858261 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_out_iso.1224012945 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 247988290 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 07:52:41 AM UTC 24 |
| Finished | Aug 21 07:52:43 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1224012945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.1224012945 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_out_stall.2791713938 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 180997723 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:52:42 AM UTC 24 |
| Finished | Aug 21 07:52:44 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2791713938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2791713938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_out_trans_nak.2384665792 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 166522161 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:52:42 AM UTC 24 |
| Finished | Aug 21 07:52:45 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2384665792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2384665792 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_pending_in_trans.579028905 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 139784884 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:52:43 AM UTC 24 |
| Finished | Aug 21 07:52:46 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=579028905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.579028905 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_phy_config_pinflip.1400618301 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 188820327 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:52:44 AM UTC 24 |
| Finished | Aug 21 07:52:47 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1400618301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.1400618301 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_phy_config_usb_ref_disable.3924053256 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 184696677 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:52:45 AM UTC 24 |
| Finished | Aug 21 07:52:48 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3924053256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3924053256 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_phy_pins_sense.1722908912 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 60622897 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 07:52:45 AM UTC 24 |
| Finished | Aug 21 07:52:47 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1722908912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1722908912 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_pkt_buffer.2433779106 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 11288588832 ps |
| CPU time | 34.36 seconds |
| Started | Aug 21 07:52:46 AM UTC 24 |
| Finished | Aug 21 07:53:22 AM UTC 24 |
| Peak memory | 228516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2433779106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2433779106 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_pkt_received.3672232851 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 194092018 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:52:48 AM UTC 24 |
| Finished | Aug 21 07:52:50 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3672232851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3672232851 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_pkt_sent.3947253909 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 200810400 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 07:52:49 AM UTC 24 |
| Finished | Aug 21 07:52:51 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3947253909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3947253909 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_rand_bus_disconnects.1474860497 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1881877058 ps |
| CPU time | 12.48 seconds |
| Started | Aug 21 07:52:49 AM UTC 24 |
| Finished | Aug 21 07:53:02 AM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1474860497 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1474860497 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_rand_bus_resets.2234408372 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 7267875862 ps |
| CPU time | 34.27 seconds |
| Started | Aug 21 07:52:51 AM UTC 24 |
| Finished | Aug 21 07:53:26 AM UTC 24 |
| Peak memory | 235180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2234408372 -assert nopostproc +UVM_TESTNAME=usbdev_ base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.2234408372 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_rand_suspends.3882714065 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 13024642823 ps |
| CPU time | 251.03 seconds |
| Started | Aug 21 07:52:52 AM UTC 24 |
| Finished | Aug 21 07:57:07 AM UTC 24 |
| Peak memory | 228660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3882714065 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3882714065 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_rand_suspends/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_random_length_in_transaction.1430737851 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 186792421 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:52:49 AM UTC 24 |
| Finished | Aug 21 07:52:51 AM UTC 24 |
| Peak memory | 216580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1430737851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.1430737851 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_random_length_out_transaction.3667769883 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 197568899 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 07:52:49 AM UTC 24 |
| Finished | Aug 21 07:52:51 AM UTC 24 |
| Peak memory | 216532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3667769883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.3667769883 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_resume_link_active.3977471158 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 20165563400 ps |
| CPU time | 31.71 seconds |
| Started | Aug 21 07:52:52 AM UTC 24 |
| Finished | Aug 21 07:53:25 AM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3977471158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_resume_link_active.3977471158 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_rx_crc_err.2231109333 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 159046939 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 07:52:52 AM UTC 24 |
| Finished | Aug 21 07:52:54 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2231109333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2231109333 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_rx_full.148770744 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 252384016 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 07:52:52 AM UTC 24 |
| Finished | Aug 21 07:52:55 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=148770744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_full.148770744 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_setup_stage.2022720484 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 167071568 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:52:53 AM UTC 24 |
| Finished | Aug 21 07:52:56 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2022720484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2022720484 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_setup_trans_ignored.3634430823 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 177201751 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 07:52:55 AM UTC 24 |
| Finished | Aug 21 07:52:57 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3634430823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3634430823 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_smoke.2463867167 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 216516727 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:52:55 AM UTC 24 |
| Finished | Aug 21 07:52:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2463867167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2463867167 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_spurious_pids_ignored.2163475408 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 2717170719 ps |
| CPU time | 75.96 seconds |
| Started | Aug 21 07:52:56 AM UTC 24 |
| Finished | Aug 21 07:54:14 AM UTC 24 |
| Peak memory | 234748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2163475408 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.2163475408 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_stall_priority_over_nak.1223318259 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 215911247 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 07:52:56 AM UTC 24 |
| Finished | Aug 21 07:52:59 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1223318259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1223318259 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_stall_trans.827820115 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 180643019 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:52:58 AM UTC 24 |
| Finished | Aug 21 07:53:01 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=827820115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.827820115 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_stream_len_max.643305386 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 1155663294 ps |
| CPU time | 5.04 seconds |
| Started | Aug 21 07:52:58 AM UTC 24 |
| Finished | Aug 21 07:53:04 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=643305386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.643305386 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_streaming_out.2221510016 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 2474224886 ps |
| CPU time | 22.15 seconds |
| Started | Aug 21 07:52:58 AM UTC 24 |
| Finished | Aug 21 07:53:22 AM UTC 24 |
| Peak memory | 235120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2221510016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2221510016 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_timeout_missing_host_handshake.1111061083 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 1582399485 ps |
| CPU time | 10.97 seconds |
| Started | Aug 21 07:52:25 AM UTC 24 |
| Finished | Aug 21 07:52:37 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1111061083 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_ host_handshake.1111061083 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/5.usbdev_tx_rx_disruption.4207697627 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 572245299 ps |
| CPU time | 1.87 seconds |
| Started | Aug 21 07:53:00 AM UTC 24 |
| Finished | Aug 21 07:53:03 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4207697627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 5.usbdev_tx_rx_disruption.4207697627 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/5.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/50.usbdev_endpoint_types.891745915 |
| Short name | T3092 |
| Test name | |
| Test status | |
| Simulation time | 230966149 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 08:05:16 AM UTC 24 |
| Finished | Aug 21 08:05:21 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=891745915 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_endpoint_types.891745915 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/50.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/50.usbdev_tx_rx_disruption.1824050095 |
| Short name | T3096 |
| Test name | |
| Test status | |
| Simulation time | 437772044 ps |
| CPU time | 2.01 seconds |
| Started | Aug 21 08:05:16 AM UTC 24 |
| Finished | Aug 21 08:05:22 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1824050095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 50.usbdev_tx_rx_disruption.1824050095 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/50.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/51.usbdev_endpoint_types.2005195124 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 382668495 ps |
| CPU time | 1.97 seconds |
| Started | Aug 21 08:05:16 AM UTC 24 |
| Finished | Aug 21 08:05:22 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2005195124 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_endpoint_types.2005195124 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/51.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/51.usbdev_tx_rx_disruption.1955734384 |
| Short name | T3093 |
| Test name | |
| Test status | |
| Simulation time | 541922742 ps |
| CPU time | 2.32 seconds |
| Started | Aug 21 08:05:17 AM UTC 24 |
| Finished | Aug 21 08:05:21 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1955734384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 51.usbdev_tx_rx_disruption.1955734384 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/51.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/52.usbdev_endpoint_types.3727664133 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 468232077 ps |
| CPU time | 2.2 seconds |
| Started | Aug 21 08:05:17 AM UTC 24 |
| Finished | Aug 21 08:05:21 AM UTC 24 |
| Peak memory | 218104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3727664133 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_endpoint_types.3727664133 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/52.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/52.usbdev_tx_rx_disruption.175588030 |
| Short name | T3094 |
| Test name | |
| Test status | |
| Simulation time | 481831668 ps |
| CPU time | 2.37 seconds |
| Started | Aug 21 08:05:17 AM UTC 24 |
| Finished | Aug 21 08:05:22 AM UTC 24 |
| Peak memory | 218068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=175588030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 52.usbdev_tx_rx_disruption.175588030 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/52.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/53.usbdev_endpoint_types.3224094142 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 533415136 ps |
| CPU time | 2.08 seconds |
| Started | Aug 21 08:05:17 AM UTC 24 |
| Finished | Aug 21 08:05:21 AM UTC 24 |
| Peak memory | 218104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3224094142 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_endpoint_types.3224094142 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/53.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/53.usbdev_tx_rx_disruption.2974831365 |
| Short name | T3095 |
| Test name | |
| Test status | |
| Simulation time | 404198374 ps |
| CPU time | 2.21 seconds |
| Started | Aug 21 08:05:17 AM UTC 24 |
| Finished | Aug 21 08:05:22 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2974831365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 53.usbdev_tx_rx_disruption.2974831365 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/53.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/54.usbdev_endpoint_types.952857983 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 803076541 ps |
| CPU time | 2.28 seconds |
| Started | Aug 21 08:05:17 AM UTC 24 |
| Finished | Aug 21 08:05:22 AM UTC 24 |
| Peak memory | 218040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=952857983 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_endpoint_types.952857983 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/54.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/54.usbdev_tx_rx_disruption.1429441885 |
| Short name | T3100 |
| Test name | |
| Test status | |
| Simulation time | 504430908 ps |
| CPU time | 2.66 seconds |
| Started | Aug 21 08:05:19 AM UTC 24 |
| Finished | Aug 21 08:05:22 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1429441885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 54.usbdev_tx_rx_disruption.1429441885 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/54.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/55.usbdev_endpoint_types.3860382908 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 233401464 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 08:05:19 AM UTC 24 |
| Finished | Aug 21 08:05:21 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3860382908 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_endpoint_types.3860382908 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/55.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/55.usbdev_tx_rx_disruption.3622487655 |
| Short name | T3101 |
| Test name | |
| Test status | |
| Simulation time | 652909565 ps |
| CPU time | 2.02 seconds |
| Started | Aug 21 08:05:20 AM UTC 24 |
| Finished | Aug 21 08:05:23 AM UTC 24 |
| Peak memory | 218128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3622487655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 55.usbdev_tx_rx_disruption.3622487655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/55.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/56.usbdev_endpoint_types.914408530 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 343476402 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:05:20 AM UTC 24 |
| Finished | Aug 21 08:05:22 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=914408530 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_endpoint_types.914408530 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/56.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/56.usbdev_tx_rx_disruption.3121058032 |
| Short name | T3106 |
| Test name | |
| Test status | |
| Simulation time | 585595017 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 08:05:22 AM UTC 24 |
| Finished | Aug 21 08:05:24 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3121058032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 56.usbdev_tx_rx_disruption.3121058032 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/56.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/57.usbdev_endpoint_types.3538198217 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 692169277 ps |
| CPU time | 2.33 seconds |
| Started | Aug 21 08:05:22 AM UTC 24 |
| Finished | Aug 21 08:05:25 AM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3538198217 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_endpoint_types.3538198217 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/57.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/57.usbdev_tx_rx_disruption.1221788152 |
| Short name | T3110 |
| Test name | |
| Test status | |
| Simulation time | 652300144 ps |
| CPU time | 1.88 seconds |
| Started | Aug 21 08:05:22 AM UTC 24 |
| Finished | Aug 21 08:05:25 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1221788152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 57.usbdev_tx_rx_disruption.1221788152 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/57.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/58.usbdev_tx_rx_disruption.1144861013 |
| Short name | T3113 |
| Test name | |
| Test status | |
| Simulation time | 615620126 ps |
| CPU time | 2.31 seconds |
| Started | Aug 21 08:05:22 AM UTC 24 |
| Finished | Aug 21 08:05:25 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1144861013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 58.usbdev_tx_rx_disruption.1144861013 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/58.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/59.usbdev_endpoint_types.1281178851 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 382769853 ps |
| CPU time | 1.52 seconds |
| Started | Aug 21 08:05:22 AM UTC 24 |
| Finished | Aug 21 08:05:24 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1281178851 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_endpoint_types.1281178851 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/59.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/59.usbdev_tx_rx_disruption.755952721 |
| Short name | T3107 |
| Test name | |
| Test status | |
| Simulation time | 596086402 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 08:05:22 AM UTC 24 |
| Finished | Aug 21 08:05:25 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=755952721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 59.usbdev_tx_rx_disruption.755952721 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/59.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_alert_test.2522209462 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 58571488 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 07:53:29 AM UTC 24 |
| Finished | Aug 21 07:53:31 AM UTC 24 |
| Peak memory | 216504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2522209462 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.2522209462 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_aon_wake_disconnect.3561124789 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 10682234143 ps |
| CPU time | 16.01 seconds |
| Started | Aug 21 07:53:03 AM UTC 24 |
| Finished | Aug 21 07:53:20 AM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3561124789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbde v_aon_wake_disconnect.3561124789 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_aon_wake_reset.3597136761 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 16258912473 ps |
| CPU time | 23.27 seconds |
| Started | Aug 21 07:53:03 AM UTC 24 |
| Finished | Aug 21 07:53:27 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3597136761 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3597136761 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_aon_wake_resume.2399634928 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 25449760275 ps |
| CPU time | 37.18 seconds |
| Started | Aug 21 07:53:03 AM UTC 24 |
| Finished | Aug 21 07:53:41 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2399634928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbde v_aon_wake_resume.2399634928 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_av_buffer.2047714684 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 176615344 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:53:10 AM UTC 24 |
| Finished | Aug 21 07:53:13 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2047714684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2047714684 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_bitstuff_err.924059379 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 178682034 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:53:10 AM UTC 24 |
| Finished | Aug 21 07:53:13 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=924059379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.924059379 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_data_toggle_clear.816364825 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 228754656 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 07:53:10 AM UTC 24 |
| Finished | Aug 21 07:53:13 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=816364825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.816364825 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_data_toggle_restore.2952584039 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 691791879 ps |
| CPU time | 2.41 seconds |
| Started | Aug 21 07:53:10 AM UTC 24 |
| Finished | Aug 21 07:53:14 AM UTC 24 |
| Peak memory | 218004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2952584039 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2952584039 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_device_address.3605289187 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 18438648881 ps |
| CPU time | 32.11 seconds |
| Started | Aug 21 07:53:10 AM UTC 24 |
| Finished | Aug 21 07:53:44 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3605289187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.3605289187 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_device_timeout.1569387103 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 9038089026 ps |
| CPU time | 54.35 seconds |
| Started | Aug 21 07:53:10 AM UTC 24 |
| Finished | Aug 21 07:54:06 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1569387103 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.1569387103 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_disable_endpoint.2833069363 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 732355846 ps |
| CPU time | 2.95 seconds |
| Started | Aug 21 07:53:14 AM UTC 24 |
| Finished | Aug 21 07:53:18 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2833069363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.2833069363 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_disconnected.163149404 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 162682451 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:53:14 AM UTC 24 |
| Finished | Aug 21 07:53:16 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=163149404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.163149404 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_enable.2833971039 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 38305070 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 07:53:14 AM UTC 24 |
| Finished | Aug 21 07:53:16 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2833971039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2833971039 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_endpoint_access.1044431627 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 863975966 ps |
| CPU time | 3.99 seconds |
| Started | Aug 21 07:53:14 AM UTC 24 |
| Finished | Aug 21 07:53:19 AM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1044431627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1044431627 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_endpoint_types.950957225 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 390421702 ps |
| CPU time | 1.95 seconds |
| Started | Aug 21 07:53:14 AM UTC 24 |
| Finished | Aug 21 07:53:17 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=950957225 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_types.950957225 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_fifo_rst.3118743423 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 164819533 ps |
| CPU time | 2.26 seconds |
| Started | Aug 21 07:53:14 AM UTC 24 |
| Finished | Aug 21 07:53:17 AM UTC 24 |
| Peak memory | 218144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3118743423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3118743423 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_in_iso.1967201420 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 215823196 ps |
| CPU time | 1.9 seconds |
| Started | Aug 21 07:53:14 AM UTC 24 |
| Finished | Aug 21 07:53:17 AM UTC 24 |
| Peak memory | 226632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1967201420 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1967201420 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_in_stall.2744762378 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 174486320 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:53:14 AM UTC 24 |
| Finished | Aug 21 07:53:16 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2744762378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2744762378 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_in_trans.111932065 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 195266389 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 07:53:14 AM UTC 24 |
| Finished | Aug 21 07:53:17 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=111932065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.111932065 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_invalid_sync.575043554 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 3582012139 ps |
| CPU time | 100.51 seconds |
| Started | Aug 21 07:53:14 AM UTC 24 |
| Finished | Aug 21 07:54:56 AM UTC 24 |
| Peak memory | 230564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=575043554 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.575043554 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_iso_retraction.2326297725 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 10723155484 ps |
| CPU time | 73.58 seconds |
| Started | Aug 21 07:53:14 AM UTC 24 |
| Finished | Aug 21 07:54:29 AM UTC 24 |
| Peak memory | 218304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2326297725 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.2326297725 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_link_in_err.1231463463 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 275839348 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 07:53:15 AM UTC 24 |
| Finished | Aug 21 07:53:18 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1231463463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.1231463463 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_link_resume.4291358835 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 6314704916 ps |
| CPU time | 10.03 seconds |
| Started | Aug 21 07:53:16 AM UTC 24 |
| Finished | Aug 21 07:53:27 AM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4291358835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.4291358835 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_link_suspend.1435172220 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 4932242345 ps |
| CPU time | 13.6 seconds |
| Started | Aug 21 07:53:18 AM UTC 24 |
| Finished | Aug 21 07:53:33 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1435172220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1435172220 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_low_speed_traffic.1587236556 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 3463705925 ps |
| CPU time | 22.13 seconds |
| Started | Aug 21 07:53:18 AM UTC 24 |
| Finished | Aug 21 07:53:41 AM UTC 24 |
| Peak memory | 235264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1587236556 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1587236556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_max_inter_pkt_delay.2916328762 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 3276632778 ps |
| CPU time | 91.65 seconds |
| Started | Aug 21 07:53:18 AM UTC 24 |
| Finished | Aug 21 07:54:52 AM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2916328762 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.2916328762 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_max_length_in_transaction.992258598 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 246374658 ps |
| CPU time | 1.56 seconds |
| Started | Aug 21 07:53:18 AM UTC 24 |
| Finished | Aug 21 07:53:21 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=992258598 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.992258598 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_max_length_out_transaction.3485723047 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 189383098 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 07:53:18 AM UTC 24 |
| Finished | Aug 21 07:53:21 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3485723047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3485723047 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_max_non_iso_usb_traffic.1581432158 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 3026584963 ps |
| CPU time | 76.16 seconds |
| Started | Aug 21 07:53:18 AM UTC 24 |
| Finished | Aug 21 07:54:36 AM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1581432158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_non_iso_usb_traffic.1581432158 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_max_usb_traffic.901062370 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 3435583760 ps |
| CPU time | 97.69 seconds |
| Started | Aug 21 07:53:18 AM UTC 24 |
| Finished | Aug 21 07:54:58 AM UTC 24 |
| Peak memory | 235308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=901062370 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.901062370 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_min_inter_pkt_delay.2842611037 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 2228936594 ps |
| CPU time | 23.28 seconds |
| Started | Aug 21 07:53:18 AM UTC 24 |
| Finished | Aug 21 07:53:43 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2842611037 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.2842611037 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_min_length_in_transaction.4288655183 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 206289314 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:53:19 AM UTC 24 |
| Finished | Aug 21 07:53:21 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4288655183 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.4288655183 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_min_length_out_transaction.3591967840 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 147022462 ps |
| CPU time | 1.21 seconds |
| Started | Aug 21 07:53:19 AM UTC 24 |
| Finished | Aug 21 07:53:21 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3591967840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3591967840 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_nak_trans.3391350163 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 216997001 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:53:21 AM UTC 24 |
| Finished | Aug 21 07:53:24 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3391350163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3391350163 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_out_iso.3865552857 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 171387184 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:53:21 AM UTC 24 |
| Finished | Aug 21 07:53:24 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3865552857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3865552857 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_out_stall.1045078543 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 194060099 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:53:21 AM UTC 24 |
| Finished | Aug 21 07:53:24 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1045078543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1045078543 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_out_trans_nak.2444182309 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 165904472 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:53:21 AM UTC 24 |
| Finished | Aug 21 07:53:24 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2444182309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2444182309 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_pending_in_trans.4059386974 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 150000350 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:53:21 AM UTC 24 |
| Finished | Aug 21 07:53:24 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4059386974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.4059386974 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_phy_config_pinflip.4026472395 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 210835421 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 07:53:21 AM UTC 24 |
| Finished | Aug 21 07:53:24 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4026472395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.4026472395 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_phy_config_usb_ref_disable.1841216939 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 160176779 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:53:22 AM UTC 24 |
| Finished | Aug 21 07:53:24 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1841216939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.1841216939 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_phy_pins_sense.3515874560 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 41752261 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 07:53:22 AM UTC 24 |
| Finished | Aug 21 07:53:24 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3515874560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3515874560 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_pkt_buffer.3447295663 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 17886935423 ps |
| CPU time | 53.15 seconds |
| Started | Aug 21 07:53:23 AM UTC 24 |
| Finished | Aug 21 07:54:18 AM UTC 24 |
| Peak memory | 228516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3447295663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3447295663 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_pkt_received.156259004 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 184299922 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 07:53:23 AM UTC 24 |
| Finished | Aug 21 07:53:26 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=156259004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.156259004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_pkt_sent.1011848629 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 180801028 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:53:23 AM UTC 24 |
| Finished | Aug 21 07:53:26 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1011848629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1011848629 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_rand_bus_disconnects.1383902783 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 8153011707 ps |
| CPU time | 57.37 seconds |
| Started | Aug 21 07:53:25 AM UTC 24 |
| Finished | Aug 21 07:54:24 AM UTC 24 |
| Peak memory | 235196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1383902783 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.1383902783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_rand_bus_resets.2517217683 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 5817166364 ps |
| CPU time | 24.49 seconds |
| Started | Aug 21 07:53:25 AM UTC 24 |
| Finished | Aug 21 07:53:51 AM UTC 24 |
| Peak memory | 228580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2517217683 -assert nopostproc +UVM_TESTNAME=usbdev_ base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2517217683 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_rand_suspends.3509700281 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 5550523135 ps |
| CPU time | 43.85 seconds |
| Started | Aug 21 07:53:25 AM UTC 24 |
| Finished | Aug 21 07:54:10 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3509700281 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.3509700281 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_rand_suspends/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_random_length_in_transaction.693897351 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 242875566 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:53:25 AM UTC 24 |
| Finished | Aug 21 07:53:27 AM UTC 24 |
| Peak memory | 216296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=693897351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.693897351 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_random_length_out_transaction.2905862950 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 235936254 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 07:53:25 AM UTC 24 |
| Finished | Aug 21 07:53:27 AM UTC 24 |
| Peak memory | 216528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2905862950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.2905862950 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_resume_link_active.3221168668 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 20171588625 ps |
| CPU time | 34.13 seconds |
| Started | Aug 21 07:53:25 AM UTC 24 |
| Finished | Aug 21 07:54:01 AM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3221168668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_resume_link_active.3221168668 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_rx_crc_err.1039770529 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 190774177 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:53:25 AM UTC 24 |
| Finished | Aug 21 07:53:28 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1039770529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1039770529 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_rx_full.2789008846 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 272514440 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:53:25 AM UTC 24 |
| Finished | Aug 21 07:53:28 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2789008846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_full.2789008846 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_setup_stage.1546498150 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 154561451 ps |
| CPU time | 1.01 seconds |
| Started | Aug 21 07:53:25 AM UTC 24 |
| Finished | Aug 21 07:53:27 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1546498150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1546498150 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_setup_trans_ignored.3140045763 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 147639089 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 07:53:25 AM UTC 24 |
| Finished | Aug 21 07:53:28 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3140045763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3140045763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_smoke.2769462898 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 257500476 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 07:53:27 AM UTC 24 |
| Finished | Aug 21 07:53:29 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2769462898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2769462898 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_spurious_pids_ignored.3143051867 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 2061480069 ps |
| CPU time | 57.53 seconds |
| Started | Aug 21 07:53:27 AM UTC 24 |
| Finished | Aug 21 07:54:26 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3143051867 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3143051867 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_stall_priority_over_nak.887118704 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 161375589 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:53:27 AM UTC 24 |
| Finished | Aug 21 07:53:29 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=887118704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20 24_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.887118704 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_stall_trans.3469883633 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 152369663 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:53:28 AM UTC 24 |
| Finished | Aug 21 07:53:31 AM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3469883633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3469883633 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_stream_len_max.2402087540 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 674893823 ps |
| CPU time | 2.72 seconds |
| Started | Aug 21 07:53:28 AM UTC 24 |
| Finished | Aug 21 07:53:33 AM UTC 24 |
| Peak memory | 217972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2402087540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.2402087540 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_streaming_out.772749626 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 1983242234 ps |
| CPU time | 49.84 seconds |
| Started | Aug 21 07:53:28 AM UTC 24 |
| Finished | Aug 21 07:54:20 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=772749626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.772749626 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_timeout_missing_host_handshake.284512603 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 4747670132 ps |
| CPU time | 45.84 seconds |
| Started | Aug 21 07:53:14 AM UTC 24 |
| Finished | Aug 21 07:54:01 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=284512603 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_h ost_handshake.284512603 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/6.usbdev_tx_rx_disruption.1697691231 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 570894655 ps |
| CPU time | 2.35 seconds |
| Started | Aug 21 07:53:29 AM UTC 24 |
| Finished | Aug 21 07:53:32 AM UTC 24 |
| Peak memory | 218128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1697691231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.usbdev_tx_rx_disruption.1697691231 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/6.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/60.usbdev_endpoint_types.1771805838 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 239938989 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 08:05:24 AM UTC 24 |
| Finished | Aug 21 08:05:26 AM UTC 24 |
| Peak memory | 216028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1771805838 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_endpoint_types.1771805838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/60.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/60.usbdev_tx_rx_disruption.3209694816 |
| Short name | T3118 |
| Test name | |
| Test status | |
| Simulation time | 516857116 ps |
| CPU time | 2.14 seconds |
| Started | Aug 21 08:05:24 AM UTC 24 |
| Finished | Aug 21 08:05:27 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3209694816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 60.usbdev_tx_rx_disruption.3209694816 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/60.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/61.usbdev_endpoint_types.978360798 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 544142858 ps |
| CPU time | 2.04 seconds |
| Started | Aug 21 08:05:24 AM UTC 24 |
| Finished | Aug 21 08:05:27 AM UTC 24 |
| Peak memory | 218104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=978360798 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_endpoint_types.978360798 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/61.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/61.usbdev_tx_rx_disruption.2662315076 |
| Short name | T3115 |
| Test name | |
| Test status | |
| Simulation time | 629641377 ps |
| CPU time | 1.67 seconds |
| Started | Aug 21 08:05:24 AM UTC 24 |
| Finished | Aug 21 08:05:26 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2662315076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 61.usbdev_tx_rx_disruption.2662315076 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/61.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/62.usbdev_endpoint_types.2912322323 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 322044207 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 08:05:24 AM UTC 24 |
| Finished | Aug 21 08:05:26 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2912322323 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_endpoint_types.2912322323 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/62.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/62.usbdev_tx_rx_disruption.3924670392 |
| Short name | T3120 |
| Test name | |
| Test status | |
| Simulation time | 523293261 ps |
| CPU time | 2.13 seconds |
| Started | Aug 21 08:05:24 AM UTC 24 |
| Finished | Aug 21 08:05:27 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3924670392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 62.usbdev_tx_rx_disruption.3924670392 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/62.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/63.usbdev_endpoint_types.2654327998 |
| Short name | T3114 |
| Test name | |
| Test status | |
| Simulation time | 194842362 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:05:24 AM UTC 24 |
| Finished | Aug 21 08:05:26 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2654327998 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_endpoint_types.2654327998 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/63.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/63.usbdev_tx_rx_disruption.4065640374 |
| Short name | T3119 |
| Test name | |
| Test status | |
| Simulation time | 440828308 ps |
| CPU time | 1.9 seconds |
| Started | Aug 21 08:05:24 AM UTC 24 |
| Finished | Aug 21 08:05:27 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4065640374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 63.usbdev_tx_rx_disruption.4065640374 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/63.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/64.usbdev_tx_rx_disruption.2933119548 |
| Short name | T3116 |
| Test name | |
| Test status | |
| Simulation time | 503380918 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 08:05:24 AM UTC 24 |
| Finished | Aug 21 08:05:27 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2933119548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 64.usbdev_tx_rx_disruption.2933119548 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/64.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/65.usbdev_endpoint_types.121485144 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 176175785 ps |
| CPU time | 1.17 seconds |
| Started | Aug 21 08:05:24 AM UTC 24 |
| Finished | Aug 21 08:05:26 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=121485144 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_endpoint_types.121485144 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/65.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/65.usbdev_tx_rx_disruption.3500708341 |
| Short name | T3121 |
| Test name | |
| Test status | |
| Simulation time | 601569818 ps |
| CPU time | 2.2 seconds |
| Started | Aug 21 08:05:24 AM UTC 24 |
| Finished | Aug 21 08:05:27 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3500708341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 65.usbdev_tx_rx_disruption.3500708341 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/65.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/66.usbdev_endpoint_types.4038820370 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 266190737 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:28 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4038820370 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_endpoint_types.4038820370 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/66.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/66.usbdev_tx_rx_disruption.2040059574 |
| Short name | T3125 |
| Test name | |
| Test status | |
| Simulation time | 480286525 ps |
| CPU time | 1.78 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2040059574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 66.usbdev_tx_rx_disruption.2040059574 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/66.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/67.usbdev_endpoint_types.2630385925 |
| Short name | T3129 |
| Test name | |
| Test status | |
| Simulation time | 693103444 ps |
| CPU time | 2.1 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2630385925 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_endpoint_types.2630385925 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/67.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/67.usbdev_tx_rx_disruption.747501423 |
| Short name | T3126 |
| Test name | |
| Test status | |
| Simulation time | 627875718 ps |
| CPU time | 1.72 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=747501423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 67.usbdev_tx_rx_disruption.747501423 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/67.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/68.usbdev_endpoint_types.2194615154 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 273762525 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:28 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2194615154 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_endpoint_types.2194615154 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/68.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/68.usbdev_tx_rx_disruption.675519007 |
| Short name | T3130 |
| Test name | |
| Test status | |
| Simulation time | 540304060 ps |
| CPU time | 1.93 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=675519007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 68.usbdev_tx_rx_disruption.675519007 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/68.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/69.usbdev_endpoint_types.1713675532 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 616596525 ps |
| CPU time | 2.1 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 218040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1713675532 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_endpoint_types.1713675532 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/69.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/69.usbdev_tx_rx_disruption.2925716488 |
| Short name | T3127 |
| Test name | |
| Test status | |
| Simulation time | 484436849 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2925716488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 69.usbdev_tx_rx_disruption.2925716488 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/69.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_alert_test.38287529 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 47277054 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 07:53:59 AM UTC 24 |
| Finished | Aug 21 07:54:01 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38287529 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.38287529 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_aon_wake_disconnect.2550564313 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 12036246546 ps |
| CPU time | 26.05 seconds |
| Started | Aug 21 07:53:29 AM UTC 24 |
| Finished | Aug 21 07:53:56 AM UTC 24 |
| Peak memory | 218372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2550564313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbde v_aon_wake_disconnect.2550564313 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_aon_wake_reset.1738380212 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 14329259931 ps |
| CPU time | 20.42 seconds |
| Started | Aug 21 07:53:29 AM UTC 24 |
| Finished | Aug 21 07:53:51 AM UTC 24 |
| Peak memory | 228608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1738380212 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1738380212 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_aon_wake_resume.3830484162 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 29370948053 ps |
| CPU time | 41.12 seconds |
| Started | Aug 21 07:53:30 AM UTC 24 |
| Finished | Aug 21 07:54:13 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3830484162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbde v_aon_wake_resume.3830484162 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_av_buffer.2449008429 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 154578549 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 07:53:30 AM UTC 24 |
| Finished | Aug 21 07:53:32 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2449008429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2449008429 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_bitstuff_err.2861776589 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 164222720 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 07:53:30 AM UTC 24 |
| Finished | Aug 21 07:53:32 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2861776589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2861776589 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_data_toggle_clear.2638649561 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 308320980 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:53:31 AM UTC 24 |
| Finished | Aug 21 07:53:33 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2638649561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08 _20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.2638649561 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_data_toggle_restore.2128826745 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 593629936 ps |
| CPU time | 2.93 seconds |
| Started | Aug 21 07:53:31 AM UTC 24 |
| Finished | Aug 21 07:53:35 AM UTC 24 |
| Peak memory | 218068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2128826745 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2128826745 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_device_address.1712683737 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 12447641375 ps |
| CPU time | 23.39 seconds |
| Started | Aug 21 07:53:32 AM UTC 24 |
| Finished | Aug 21 07:53:57 AM UTC 24 |
| Peak memory | 218372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1712683737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.1712683737 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_device_timeout.2767729264 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 793241517 ps |
| CPU time | 6.84 seconds |
| Started | Aug 21 07:53:32 AM UTC 24 |
| Finished | Aug 21 07:53:41 AM UTC 24 |
| Peak memory | 218052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2767729264 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.2767729264 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_disable_endpoint.3089979988 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 824631481 ps |
| CPU time | 3.36 seconds |
| Started | Aug 21 07:53:34 AM UTC 24 |
| Finished | Aug 21 07:53:38 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3089979988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.3089979988 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_disconnected.1898206518 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 161584750 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:53:34 AM UTC 24 |
| Finished | Aug 21 07:53:37 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1898206518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.1898206518 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_enable.187764370 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 65505201 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 07:53:34 AM UTC 24 |
| Finished | Aug 21 07:53:36 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=187764370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.187764370 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_endpoint_access.869789068 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 858012261 ps |
| CPU time | 3.84 seconds |
| Started | Aug 21 07:53:34 AM UTC 24 |
| Finished | Aug 21 07:53:39 AM UTC 24 |
| Peak memory | 218068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=869789068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.869789068 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_endpoint_types.3138627173 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 325910792 ps |
| CPU time | 1.87 seconds |
| Started | Aug 21 07:53:34 AM UTC 24 |
| Finished | Aug 21 07:53:37 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3138627173 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_types.3138627173 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_fifo_rst.1271250825 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 193145684 ps |
| CPU time | 3.08 seconds |
| Started | Aug 21 07:53:36 AM UTC 24 |
| Finished | Aug 21 07:53:40 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1271250825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1271250825 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_in_iso.841010170 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 189858117 ps |
| CPU time | 1.73 seconds |
| Started | Aug 21 07:53:37 AM UTC 24 |
| Finished | Aug 21 07:53:40 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=841010170 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.841010170 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_in_stall.3466749317 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 138977835 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:53:37 AM UTC 24 |
| Finished | Aug 21 07:53:40 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3466749317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3466749317 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_in_trans.2094890116 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 200428953 ps |
| CPU time | 1.61 seconds |
| Started | Aug 21 07:53:38 AM UTC 24 |
| Finished | Aug 21 07:53:41 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2094890116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2094890116 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_invalid_sync.3505035356 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 3005102922 ps |
| CPU time | 24.88 seconds |
| Started | Aug 21 07:53:36 AM UTC 24 |
| Finished | Aug 21 07:54:02 AM UTC 24 |
| Peak memory | 228664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3505035356 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.3505035356 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_iso_retraction.1893027887 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 12069554051 ps |
| CPU time | 147.37 seconds |
| Started | Aug 21 07:53:39 AM UTC 24 |
| Finished | Aug 21 07:56:09 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1893027887 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.1893027887 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_link_in_err.3574751064 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 201892675 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:53:41 AM UTC 24 |
| Finished | Aug 21 07:53:43 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3574751064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.3574751064 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_link_resume.3775927887 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 26202705158 ps |
| CPU time | 46.52 seconds |
| Started | Aug 21 07:53:41 AM UTC 24 |
| Finished | Aug 21 07:54:29 AM UTC 24 |
| Peak memory | 228408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3775927887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.3775927887 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_link_suspend.1543753078 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 8884362626 ps |
| CPU time | 13.32 seconds |
| Started | Aug 21 07:53:41 AM UTC 24 |
| Finished | Aug 21 07:53:55 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1543753078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1543753078 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_low_speed_traffic.1057699934 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 2798302169 ps |
| CPU time | 77.71 seconds |
| Started | Aug 21 07:53:41 AM UTC 24 |
| Finished | Aug 21 07:55:00 AM UTC 24 |
| Peak memory | 228556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1057699934 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.1057699934 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_max_inter_pkt_delay.3970595033 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 2825077415 ps |
| CPU time | 28.6 seconds |
| Started | Aug 21 07:53:42 AM UTC 24 |
| Finished | Aug 21 07:54:12 AM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3970595033 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3970595033 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_max_length_in_transaction.2945083071 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 241409872 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 07:53:42 AM UTC 24 |
| Finished | Aug 21 07:53:45 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2945083071 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2945083071 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_max_length_out_transaction.2792992046 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 212331797 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:53:42 AM UTC 24 |
| Finished | Aug 21 07:53:45 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2792992046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2792992046 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_max_non_iso_usb_traffic.1908241180 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 2140328778 ps |
| CPU time | 56.29 seconds |
| Started | Aug 21 07:53:42 AM UTC 24 |
| Finished | Aug 21 07:54:40 AM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1908241180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_non_iso_usb_traffic.1908241180 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_max_usb_traffic.1157320108 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 1727502460 ps |
| CPU time | 17.07 seconds |
| Started | Aug 21 07:53:45 AM UTC 24 |
| Finished | Aug 21 07:54:03 AM UTC 24 |
| Peak memory | 230484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1157320108 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1157320108 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_min_inter_pkt_delay.3210467919 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 3769284779 ps |
| CPU time | 43.36 seconds |
| Started | Aug 21 07:53:45 AM UTC 24 |
| Finished | Aug 21 07:54:30 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3210467919 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.3210467919 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_min_length_in_transaction.4135701638 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 154026862 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:53:45 AM UTC 24 |
| Finished | Aug 21 07:53:47 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4135701638 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.4135701638 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_min_length_out_transaction.480038416 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 167023631 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:53:45 AM UTC 24 |
| Finished | Aug 21 07:53:47 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=480038416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.480038416 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_nak_trans.4158602726 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 176355287 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 07:53:45 AM UTC 24 |
| Finished | Aug 21 07:53:47 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4158602726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.4158602726 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_out_iso.2477873393 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 200796611 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 07:53:45 AM UTC 24 |
| Finished | Aug 21 07:53:47 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2477873393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2477873393 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_out_stall.3736510557 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 156132314 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:53:46 AM UTC 24 |
| Finished | Aug 21 07:53:49 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3736510557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3736510557 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_out_trans_nak.110162531 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 184919814 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:53:46 AM UTC 24 |
| Finished | Aug 21 07:53:49 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=110162531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.110162531 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_pending_in_trans.2769418654 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 146478586 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:53:46 AM UTC 24 |
| Finished | Aug 21 07:53:49 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2769418654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2769418654 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_phy_config_pinflip.1267446212 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 214801529 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 07:53:48 AM UTC 24 |
| Finished | Aug 21 07:53:51 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1267446212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1267446212 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_phy_config_usb_ref_disable.971758974 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 146316608 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:53:48 AM UTC 24 |
| Finished | Aug 21 07:53:51 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=971758974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0 _2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.971758974 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_phy_pins_sense.996681725 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 36978644 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 07:53:48 AM UTC 24 |
| Finished | Aug 21 07:53:51 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=996681725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.996681725 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_pkt_buffer.1819088108 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 8720795764 ps |
| CPU time | 27.04 seconds |
| Started | Aug 21 07:53:48 AM UTC 24 |
| Finished | Aug 21 07:54:17 AM UTC 24 |
| Peak memory | 228516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1819088108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1819088108 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_pkt_received.1846478403 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 158532509 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:53:48 AM UTC 24 |
| Finished | Aug 21 07:53:51 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1846478403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1846478403 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_pkt_sent.741535539 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 173673401 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:53:50 AM UTC 24 |
| Finished | Aug 21 07:53:52 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=741535539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.741535539 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_rand_bus_disconnects.3225579281 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 9052803490 ps |
| CPU time | 61.63 seconds |
| Started | Aug 21 07:53:50 AM UTC 24 |
| Finished | Aug 21 07:54:54 AM UTC 24 |
| Peak memory | 235192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3225579281 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3225579281 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_rand_bus_resets.2083611107 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 6079188162 ps |
| CPU time | 27.83 seconds |
| Started | Aug 21 07:53:51 AM UTC 24 |
| Finished | Aug 21 07:54:21 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2083611107 -assert nopostproc +UVM_TESTNAME=usbdev_ base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2083611107 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_rand_suspends.231535216 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 6302253483 ps |
| CPU time | 68.02 seconds |
| Started | Aug 21 07:53:51 AM UTC 24 |
| Finished | Aug 21 07:55:01 AM UTC 24 |
| Peak memory | 228384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=231535216 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.231535216 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_rand_suspends/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_random_length_in_transaction.1633312707 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 168920808 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:53:50 AM UTC 24 |
| Finished | Aug 21 07:53:53 AM UTC 24 |
| Peak memory | 216580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1633312707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.1633312707 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_random_length_out_transaction.2893323773 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 166463208 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:53:50 AM UTC 24 |
| Finished | Aug 21 07:53:53 AM UTC 24 |
| Peak memory | 216592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2893323773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2893323773 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_resume_link_active.3576143512 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 20243753920 ps |
| CPU time | 39.21 seconds |
| Started | Aug 21 07:53:53 AM UTC 24 |
| Finished | Aug 21 07:54:33 AM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3576143512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_resume_link_active.3576143512 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_rx_crc_err.3986109636 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 130600692 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 07:53:53 AM UTC 24 |
| Finished | Aug 21 07:53:55 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3986109636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.3986109636 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_rx_full.250931525 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 398771480 ps |
| CPU time | 2.15 seconds |
| Started | Aug 21 07:53:53 AM UTC 24 |
| Finished | Aug 21 07:53:56 AM UTC 24 |
| Peak memory | 217996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=250931525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_full.250931525 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_setup_stage.3583098340 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 158667727 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:53:53 AM UTC 24 |
| Finished | Aug 21 07:53:55 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3583098340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3583098340 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_setup_trans_ignored.2361440995 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 176842756 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:53:54 AM UTC 24 |
| Finished | Aug 21 07:53:56 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2361440995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2361440995 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_smoke.3701599490 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 213348272 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 07:53:54 AM UTC 24 |
| Finished | Aug 21 07:53:57 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3701599490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3701599490 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_spurious_pids_ignored.3914167181 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 3249749845 ps |
| CPU time | 31.6 seconds |
| Started | Aug 21 07:53:54 AM UTC 24 |
| Finished | Aug 21 07:54:27 AM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3914167181 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3914167181 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_stall_priority_over_nak.1837355072 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 174717199 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:53:57 AM UTC 24 |
| Finished | Aug 21 07:53:59 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1837355072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1837355072 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_stall_trans.2209815118 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 170345820 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:53:57 AM UTC 24 |
| Finished | Aug 21 07:53:59 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2209815118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2209815118 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_stream_len_max.1615794430 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 1204615113 ps |
| CPU time | 3.47 seconds |
| Started | Aug 21 07:53:57 AM UTC 24 |
| Finished | Aug 21 07:54:01 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1615794430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.1615794430 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_streaming_out.1235819987 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 3837641586 ps |
| CPU time | 36.15 seconds |
| Started | Aug 21 07:53:57 AM UTC 24 |
| Finished | Aug 21 07:54:34 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1235819987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1235819987 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_timeout_missing_host_handshake.692893101 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 5532164752 ps |
| CPU time | 36.81 seconds |
| Started | Aug 21 07:53:34 AM UTC 24 |
| Finished | Aug 21 07:54:12 AM UTC 24 |
| Peak memory | 218376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=692893101 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_h ost_handshake.692893101 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/7.usbdev_tx_rx_disruption.1818100265 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 486360923 ps |
| CPU time | 1.76 seconds |
| Started | Aug 21 07:53:57 AM UTC 24 |
| Finished | Aug 21 07:54:00 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1818100265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.usbdev_tx_rx_disruption.1818100265 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/7.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/70.usbdev_endpoint_types.1145280099 |
| Short name | T3122 |
| Test name | |
| Test status | |
| Simulation time | 152116083 ps |
| CPU time | 1.18 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:28 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1145280099 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_endpoint_types.1145280099 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/70.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/70.usbdev_tx_rx_disruption.3948807888 |
| Short name | T3128 |
| Test name | |
| Test status | |
| Simulation time | 623134123 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3948807888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 70.usbdev_tx_rx_disruption.3948807888 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/70.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/71.usbdev_endpoint_types.3974903293 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 198142520 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:28 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3974903293 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_endpoint_types.3974903293 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/71.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/71.usbdev_tx_rx_disruption.4038746311 |
| Short name | T3133 |
| Test name | |
| Test status | |
| Simulation time | 568290483 ps |
| CPU time | 1.83 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4038746311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 71.usbdev_tx_rx_disruption.4038746311 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/71.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/72.usbdev_endpoint_types.4094204410 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 203668862 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4094204410 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_endpoint_types.4094204410 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/72.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/72.usbdev_tx_rx_disruption.4171689523 |
| Short name | T3131 |
| Test name | |
| Test status | |
| Simulation time | 525746328 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 08:05:26 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=4171689523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 72.usbdev_tx_rx_disruption.4171689523 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/72.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/73.usbdev_endpoint_types.72130702 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 204997595 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 08:05:27 AM UTC 24 |
| Finished | Aug 21 08:05:29 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=72130702 -assert nopostproc +UVM_TESTNAME=usbdev _base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_endpoint_types.72130702 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/73.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/73.usbdev_tx_rx_disruption.1111405993 |
| Short name | T3136 |
| Test name | |
| Test status | |
| Simulation time | 471232029 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:05:28 AM UTC 24 |
| Finished | Aug 21 08:05:30 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1111405993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 73.usbdev_tx_rx_disruption.1111405993 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/73.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/74.usbdev_endpoint_types.3737073335 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 405946632 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 08:05:28 AM UTC 24 |
| Finished | Aug 21 08:05:30 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3737073335 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_endpoint_types.3737073335 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/74.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/74.usbdev_tx_rx_disruption.2416546512 |
| Short name | T3137 |
| Test name | |
| Test status | |
| Simulation time | 537092143 ps |
| CPU time | 1.67 seconds |
| Started | Aug 21 08:05:28 AM UTC 24 |
| Finished | Aug 21 08:05:31 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2416546512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 74.usbdev_tx_rx_disruption.2416546512 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/74.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/75.usbdev_endpoint_types.3554457793 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 187700632 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 08:05:28 AM UTC 24 |
| Finished | Aug 21 08:05:30 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3554457793 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_endpoint_types.3554457793 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/75.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/75.usbdev_tx_rx_disruption.2755460214 |
| Short name | T3138 |
| Test name | |
| Test status | |
| Simulation time | 582519611 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 08:05:28 AM UTC 24 |
| Finished | Aug 21 08:05:31 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2755460214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 75.usbdev_tx_rx_disruption.2755460214 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/75.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/76.usbdev_endpoint_types.2263925029 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 568611541 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:05:28 AM UTC 24 |
| Finished | Aug 21 08:05:31 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2263925029 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_endpoint_types.2263925029 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/76.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/76.usbdev_tx_rx_disruption.3516872473 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 515899414 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:05:28 AM UTC 24 |
| Finished | Aug 21 08:05:31 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3516872473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 76.usbdev_tx_rx_disruption.3516872473 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/76.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/77.usbdev_endpoint_types.3424630895 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 383530209 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 08:05:28 AM UTC 24 |
| Finished | Aug 21 08:05:31 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3424630895 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_endpoint_types.3424630895 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/77.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/77.usbdev_tx_rx_disruption.2688776007 |
| Short name | T3140 |
| Test name | |
| Test status | |
| Simulation time | 643493008 ps |
| CPU time | 1.73 seconds |
| Started | Aug 21 08:05:28 AM UTC 24 |
| Finished | Aug 21 08:05:31 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2688776007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 77.usbdev_tx_rx_disruption.2688776007 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/77.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/78.usbdev_endpoint_types.2169178710 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 765790072 ps |
| CPU time | 1.7 seconds |
| Started | Aug 21 08:05:28 AM UTC 24 |
| Finished | Aug 21 08:05:31 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2169178710 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_endpoint_types.2169178710 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/78.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/78.usbdev_tx_rx_disruption.2192603723 |
| Short name | T3141 |
| Test name | |
| Test status | |
| Simulation time | 515612320 ps |
| CPU time | 1.83 seconds |
| Started | Aug 21 08:05:28 AM UTC 24 |
| Finished | Aug 21 08:05:31 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2192603723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 78.usbdev_tx_rx_disruption.2192603723 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/78.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/79.usbdev_endpoint_types.4199352091 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 193904547 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 08:05:28 AM UTC 24 |
| Finished | Aug 21 08:05:31 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4199352091 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_endpoint_types.4199352091 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/79.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/79.usbdev_tx_rx_disruption.3456621415 |
| Short name | T3139 |
| Test name | |
| Test status | |
| Simulation time | 510403325 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 08:05:28 AM UTC 24 |
| Finished | Aug 21 08:05:31 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3456621415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 79.usbdev_tx_rx_disruption.3456621415 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/79.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_alert_test.2000005413 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 30072393 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 07:54:26 AM UTC 24 |
| Finished | Aug 21 07:54:28 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2000005413 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.2000005413 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_aon_wake_disconnect.2311867206 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 10476280921 ps |
| CPU time | 16.07 seconds |
| Started | Aug 21 07:53:59 AM UTC 24 |
| Finished | Aug 21 07:54:16 AM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2311867206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbde v_aon_wake_disconnect.2311867206 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_aon_wake_reset.520413058 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 14364759727 ps |
| CPU time | 24.43 seconds |
| Started | Aug 21 07:53:59 AM UTC 24 |
| Finished | Aug 21 07:54:24 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=520413058 -assert nopostp roc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.520413058 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_aon_wake_resume.3898738335 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 24528149842 ps |
| CPU time | 32.02 seconds |
| Started | Aug 21 07:54:01 AM UTC 24 |
| Finished | Aug 21 07:54:34 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3898738335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbde v_aon_wake_resume.3898738335 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_av_buffer.1515159271 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 209229038 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:54:01 AM UTC 24 |
| Finished | Aug 21 07:54:03 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1515159271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1515159271 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_bitstuff_err.83634583 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 153111673 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:54:01 AM UTC 24 |
| Finished | Aug 21 07:54:03 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=83634583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.83634583 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_data_toggle_clear.594480616 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 471670618 ps |
| CPU time | 2.73 seconds |
| Started | Aug 21 07:54:01 AM UTC 24 |
| Finished | Aug 21 07:54:04 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=594480616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.594480616 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_data_toggle_restore.1182701832 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 897636480 ps |
| CPU time | 4.12 seconds |
| Started | Aug 21 07:54:01 AM UTC 24 |
| Finished | Aug 21 07:54:06 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1182701832 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.1182701832 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_device_address.1024537550 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 16970890096 ps |
| CPU time | 33.51 seconds |
| Started | Aug 21 07:54:01 AM UTC 24 |
| Finished | Aug 21 07:54:36 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1024537550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.1024537550 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_device_timeout.2209745705 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 1946704814 ps |
| CPU time | 50.97 seconds |
| Started | Aug 21 07:54:02 AM UTC 24 |
| Finished | Aug 21 07:54:55 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2209745705 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.2209745705 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_disable_endpoint.732079084 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 919714556 ps |
| CPU time | 3.57 seconds |
| Started | Aug 21 07:54:02 AM UTC 24 |
| Finished | Aug 21 07:54:07 AM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=732079084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.732079084 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_disconnected.1363755863 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 155604460 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 07:54:02 AM UTC 24 |
| Finished | Aug 21 07:54:04 AM UTC 24 |
| Peak memory | 216432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1363755863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.1363755863 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_enable.1718999594 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 71598694 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 07:54:04 AM UTC 24 |
| Finished | Aug 21 07:54:06 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1718999594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1718999594 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_endpoint_access.1782254413 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 858420291 ps |
| CPU time | 3.38 seconds |
| Started | Aug 21 07:54:04 AM UTC 24 |
| Finished | Aug 21 07:54:08 AM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1782254413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1782254413 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_endpoint_types.3230126514 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 395485819 ps |
| CPU time | 2.06 seconds |
| Started | Aug 21 07:54:04 AM UTC 24 |
| Finished | Aug 21 07:54:07 AM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3230126514 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_types.3230126514 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_fifo_rst.1574480157 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 181449027 ps |
| CPU time | 2.64 seconds |
| Started | Aug 21 07:54:04 AM UTC 24 |
| Finished | Aug 21 07:54:07 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1574480157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1574480157 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_in_iso.606210012 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 287699283 ps |
| CPU time | 2.01 seconds |
| Started | Aug 21 07:54:05 AM UTC 24 |
| Finished | Aug 21 07:54:08 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=606210012 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.606210012 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_in_stall.1245520056 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 137338563 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 07:54:06 AM UTC 24 |
| Finished | Aug 21 07:54:08 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1245520056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1245520056 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_in_trans.2587383435 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 190593857 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:54:07 AM UTC 24 |
| Finished | Aug 21 07:54:10 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2587383435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2587383435 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_invalid_sync.682353464 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 4503574299 ps |
| CPU time | 124.91 seconds |
| Started | Aug 21 07:54:05 AM UTC 24 |
| Finished | Aug 21 07:56:12 AM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=682353464 -assert nopostproc +UVM_TESTNAME=usbdev_base_te st +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.682353464 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_iso_retraction.232975212 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 12169698988 ps |
| CPU time | 134.69 seconds |
| Started | Aug 21 07:54:08 AM UTC 24 |
| Finished | Aug 21 07:56:25 AM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=232975212 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.232975212 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_link_in_err.3458913434 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 183632994 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:54:08 AM UTC 24 |
| Finished | Aug 21 07:54:10 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3458913434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3458913434 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_link_resume.3945730046 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 25681709069 ps |
| CPU time | 43.77 seconds |
| Started | Aug 21 07:54:08 AM UTC 24 |
| Finished | Aug 21 07:54:53 AM UTC 24 |
| Peak memory | 218232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3945730046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.3945730046 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_link_suspend.306279449 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 8896776369 ps |
| CPU time | 14.12 seconds |
| Started | Aug 21 07:54:09 AM UTC 24 |
| Finished | Aug 21 07:54:24 AM UTC 24 |
| Peak memory | 218268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=306279449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.306279449 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_low_speed_traffic.1046395441 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 4853914441 ps |
| CPU time | 131.36 seconds |
| Started | Aug 21 07:54:09 AM UTC 24 |
| Finished | Aug 21 07:56:23 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1046395441 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.1046395441 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_max_inter_pkt_delay.517857302 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 2184871490 ps |
| CPU time | 53.52 seconds |
| Started | Aug 21 07:54:09 AM UTC 24 |
| Finished | Aug 21 07:55:04 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=517857302 -assert nopostproc +UVM _TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.517857302 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_max_length_in_transaction.925246955 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 242306095 ps |
| CPU time | 1.77 seconds |
| Started | Aug 21 07:54:09 AM UTC 24 |
| Finished | Aug 21 07:54:12 AM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=925246955 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.925246955 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_max_length_out_transaction.43265029 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 196676338 ps |
| CPU time | 1.57 seconds |
| Started | Aug 21 07:54:09 AM UTC 24 |
| Finished | Aug 21 07:54:12 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=43265029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_ 2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.43265029 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_max_non_iso_usb_traffic.3103807344 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 3088471699 ps |
| CPU time | 80.75 seconds |
| Started | Aug 21 07:54:11 AM UTC 24 |
| Finished | Aug 21 07:55:34 AM UTC 24 |
| Peak memory | 235312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3103807344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_non_iso_usb_traffic.3103807344 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_max_usb_traffic.1954262481 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 3501873316 ps |
| CPU time | 35.84 seconds |
| Started | Aug 21 07:54:12 AM UTC 24 |
| Finished | Aug 21 07:54:49 AM UTC 24 |
| Peak memory | 230476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1954262481 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.1954262481 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_min_inter_pkt_delay.2342864835 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 3428432064 ps |
| CPU time | 29.63 seconds |
| Started | Aug 21 07:54:12 AM UTC 24 |
| Finished | Aug 21 07:54:42 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2342864835 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2342864835 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_min_length_in_transaction.3101734063 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 201465030 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 07:54:13 AM UTC 24 |
| Finished | Aug 21 07:54:15 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3101734063 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3101734063 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_min_length_out_transaction.3894325310 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 161272182 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 07:54:13 AM UTC 24 |
| Finished | Aug 21 07:54:15 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3894325310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3894325310 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_nak_trans.1699768271 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 186653100 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 07:54:13 AM UTC 24 |
| Finished | Aug 21 07:54:16 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1699768271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1699768271 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_out_iso.1519937626 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 172215762 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:54:13 AM UTC 24 |
| Finished | Aug 21 07:54:15 AM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1519937626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1519937626 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_out_stall.1422228580 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 146271856 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 07:54:14 AM UTC 24 |
| Finished | Aug 21 07:54:16 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1422228580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1422228580 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_out_trans_nak.4098269797 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 238866544 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 07:54:15 AM UTC 24 |
| Finished | Aug 21 07:54:18 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4098269797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.4098269797 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_pending_in_trans.3614849269 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 201496001 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 07:54:17 AM UTC 24 |
| Finished | Aug 21 07:54:19 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3614849269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3614849269 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_phy_config_pinflip.3295858407 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 222164396 ps |
| CPU time | 1.64 seconds |
| Started | Aug 21 07:54:17 AM UTC 24 |
| Finished | Aug 21 07:54:19 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3295858407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3295858407 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_phy_config_usb_ref_disable.2514291251 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 151147085 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 07:54:17 AM UTC 24 |
| Finished | Aug 21 07:54:19 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2514291251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2514291251 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_phy_pins_sense.101535124 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 54497087 ps |
| CPU time | 1 seconds |
| Started | Aug 21 07:54:17 AM UTC 24 |
| Finished | Aug 21 07:54:19 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=101535124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.101535124 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_pkt_buffer.536084737 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 6771383173 ps |
| CPU time | 20.35 seconds |
| Started | Aug 21 07:54:17 AM UTC 24 |
| Finished | Aug 21 07:54:38 AM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=536084737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.536084737 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_pkt_received.4016177548 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 161888851 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 07:54:17 AM UTC 24 |
| Finished | Aug 21 07:54:19 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4016177548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.4016177548 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_pkt_sent.1868413567 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 232964474 ps |
| CPU time | 1.7 seconds |
| Started | Aug 21 07:54:19 AM UTC 24 |
| Finished | Aug 21 07:54:22 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1868413567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1868413567 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_rand_bus_disconnects.3484375981 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 4966255249 ps |
| CPU time | 42.12 seconds |
| Started | Aug 21 07:54:21 AM UTC 24 |
| Finished | Aug 21 07:55:04 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3484375981 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.3484375981 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_rand_suspends.1785940025 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 11138892521 ps |
| CPU time | 75.45 seconds |
| Started | Aug 21 07:54:21 AM UTC 24 |
| Finished | Aug 21 07:55:38 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1785940025 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1785940025 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_rand_suspends/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_random_length_in_transaction.1614378327 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 229530916 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 07:54:19 AM UTC 24 |
| Finished | Aug 21 07:54:21 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1614378327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1614378327 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_random_length_out_transaction.2312556786 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 173420217 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 07:54:19 AM UTC 24 |
| Finished | Aug 21 07:54:21 AM UTC 24 |
| Peak memory | 216592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2312556786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.2312556786 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_resume_link_active.2452347140 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 20191470268 ps |
| CPU time | 35.74 seconds |
| Started | Aug 21 07:54:21 AM UTC 24 |
| Finished | Aug 21 07:54:58 AM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2452347140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_resume_link_active.2452347140 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_rx_crc_err.2155774364 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 172310863 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 07:54:21 AM UTC 24 |
| Finished | Aug 21 07:54:23 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2155774364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2155774364 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_rx_full.1168805218 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 259736208 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 07:54:21 AM UTC 24 |
| Finished | Aug 21 07:54:24 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1168805218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_full.1168805218 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_setup_stage.508651549 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 174054429 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:54:21 AM UTC 24 |
| Finished | Aug 21 07:54:23 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=508651549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.508651549 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_setup_trans_ignored.3098442403 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 156431629 ps |
| CPU time | 1.44 seconds |
| Started | Aug 21 07:54:23 AM UTC 24 |
| Finished | Aug 21 07:54:26 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3098442403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.3098442403 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_smoke.1692883449 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 248728611 ps |
| CPU time | 1.81 seconds |
| Started | Aug 21 07:54:23 AM UTC 24 |
| Finished | Aug 21 07:54:26 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1692883449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1692883449 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_spurious_pids_ignored.321751279 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 2277439273 ps |
| CPU time | 58.68 seconds |
| Started | Aug 21 07:54:23 AM UTC 24 |
| Finished | Aug 21 07:55:23 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=321751279 -assert nopostproc +UVM_TESTNAME=usbdev_bas e_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.321751279 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_stall_priority_over_nak.1011407492 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 240625467 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:54:23 AM UTC 24 |
| Finished | Aug 21 07:54:26 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1011407492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1011407492 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_stall_trans.3223924085 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 155581089 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 07:54:23 AM UTC 24 |
| Finished | Aug 21 07:54:25 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3223924085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3223924085 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_stream_len_max.1765349513 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 1133002288 ps |
| CPU time | 4.25 seconds |
| Started | Aug 21 07:54:25 AM UTC 24 |
| Finished | Aug 21 07:54:30 AM UTC 24 |
| Peak memory | 218252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1765349513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.1765349513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_streaming_out.3550109027 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 2604086072 ps |
| CPU time | 68.48 seconds |
| Started | Aug 21 07:54:25 AM UTC 24 |
| Finished | Aug 21 07:55:35 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3550109027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3550109027 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_timeout_missing_host_handshake.218399560 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 1705873242 ps |
| CPU time | 37.88 seconds |
| Started | Aug 21 07:54:02 AM UTC 24 |
| Finished | Aug 21 07:54:41 AM UTC 24 |
| Peak memory | 217988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=218399560 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_h ost_handshake.218399560 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/8.usbdev_tx_rx_disruption.1707275685 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 467400896 ps |
| CPU time | 2.54 seconds |
| Started | Aug 21 07:54:25 AM UTC 24 |
| Finished | Aug 21 07:54:28 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1707275685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.usbdev_tx_rx_disruption.1707275685 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/8.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/80.usbdev_endpoint_types.1616372706 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 335685723 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 08:05:35 AM UTC 24 |
| Finished | Aug 21 08:05:37 AM UTC 24 |
| Peak memory | 216300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1616372706 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_endpoint_types.1616372706 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/80.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/80.usbdev_tx_rx_disruption.487091113 |
| Short name | T3148 |
| Test name | |
| Test status | |
| Simulation time | 539781899 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:05:35 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=487091113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 80.usbdev_tx_rx_disruption.487091113 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/80.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/81.usbdev_endpoint_types.1913281616 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 389380276 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 08:05:35 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1913281616 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_endpoint_types.1913281616 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/81.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/81.usbdev_tx_rx_disruption.535441297 |
| Short name | T3150 |
| Test name | |
| Test status | |
| Simulation time | 488069525 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:05:35 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=535441297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 81.usbdev_tx_rx_disruption.535441297 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/81.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/82.usbdev_endpoint_types.59552644 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 403815548 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:05:35 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=59552644 -assert nopostproc +UVM_TESTNAME=usbdev _base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_endpoint_types.59552644 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/82.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/82.usbdev_tx_rx_disruption.886995979 |
| Short name | T3153 |
| Test name | |
| Test status | |
| Simulation time | 636428214 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 08:05:35 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=886995979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 82.usbdev_tx_rx_disruption.886995979 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/82.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/83.usbdev_tx_rx_disruption.1459747931 |
| Short name | T3152 |
| Test name | |
| Test status | |
| Simulation time | 487971141 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:05:36 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1459747931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 83.usbdev_tx_rx_disruption.1459747931 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/83.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/84.usbdev_endpoint_types.3245963222 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 287672767 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 08:05:36 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3245963222 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_endpoint_types.3245963222 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/84.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/84.usbdev_tx_rx_disruption.3448019052 |
| Short name | T3155 |
| Test name | |
| Test status | |
| Simulation time | 568501988 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 08:05:36 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3448019052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 84.usbdev_tx_rx_disruption.3448019052 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/84.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/85.usbdev_endpoint_types.1087660419 |
| Short name | T3151 |
| Test name | |
| Test status | |
| Simulation time | 309356276 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:05:36 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1087660419 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_endpoint_types.1087660419 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/85.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/85.usbdev_tx_rx_disruption.1441237809 |
| Short name | T3158 |
| Test name | |
| Test status | |
| Simulation time | 561111356 ps |
| CPU time | 1.89 seconds |
| Started | Aug 21 08:05:36 AM UTC 24 |
| Finished | Aug 21 08:05:39 AM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1441237809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 85.usbdev_tx_rx_disruption.1441237809 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/85.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/86.usbdev_endpoint_types.912711767 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 288149717 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 08:05:36 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=912711767 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_endpoint_types.912711767 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/86.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/86.usbdev_tx_rx_disruption.3479950934 |
| Short name | T3156 |
| Test name | |
| Test status | |
| Simulation time | 408518004 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 08:05:36 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3479950934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 86.usbdev_tx_rx_disruption.3479950934 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/86.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/87.usbdev_endpoint_types.4016702438 |
| Short name | T3149 |
| Test name | |
| Test status | |
| Simulation time | 236551987 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 08:05:36 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4016702438 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_endpoint_types.4016702438 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/87.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/87.usbdev_tx_rx_disruption.2547600175 |
| Short name | T3154 |
| Test name | |
| Test status | |
| Simulation time | 521413876 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 08:05:36 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2547600175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 87.usbdev_tx_rx_disruption.2547600175 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/87.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/88.usbdev_endpoint_types.2535518596 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 523905268 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 08:05:36 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2535518596 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_endpoint_types.2535518596 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/88.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/88.usbdev_tx_rx_disruption.683618896 |
| Short name | T3157 |
| Test name | |
| Test status | |
| Simulation time | 543378394 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 08:05:36 AM UTC 24 |
| Finished | Aug 21 08:05:39 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=683618896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 88.usbdev_tx_rx_disruption.683618896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/88.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/89.usbdev_endpoint_types.1152575296 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 379060484 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 08:05:36 AM UTC 24 |
| Finished | Aug 21 08:05:38 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1152575296 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_endpoint_types.1152575296 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/89.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/89.usbdev_tx_rx_disruption.3492256839 |
| Short name | T3167 |
| Test name | |
| Test status | |
| Simulation time | 471407755 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 08:05:43 AM UTC 24 |
| Finished | Aug 21 08:05:45 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3492256839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 89.usbdev_tx_rx_disruption.3492256839 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/89.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_alert_test.343140802 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 43993178 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 07:54:53 AM UTC 24 |
| Finished | Aug 21 07:54:55 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=343140802 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.343140802 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_aon_wake_disconnect.1366354339 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 5198930064 ps |
| CPU time | 12.5 seconds |
| Started | Aug 21 07:54:26 AM UTC 24 |
| Finished | Aug 21 07:54:40 AM UTC 24 |
| Peak memory | 228540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1366354339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbde v_aon_wake_disconnect.1366354339 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_aon_wake_reset.1885199196 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 20516129074 ps |
| CPU time | 29.11 seconds |
| Started | Aug 21 07:54:26 AM UTC 24 |
| Finished | Aug 21 07:54:57 AM UTC 24 |
| Peak memory | 218244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1885199196 -assert nopost proc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.1885199196 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_aon_wake_resume.4132310828 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 31328405623 ps |
| CPU time | 46.69 seconds |
| Started | Aug 21 07:54:27 AM UTC 24 |
| Finished | Aug 21 07:55:16 AM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_s cb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4132310828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbde v_aon_wake_resume.4132310828 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_av_buffer.972477610 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 162394627 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:54:27 AM UTC 24 |
| Finished | Aug 21 07:54:30 AM UTC 24 |
| Peak memory | 216012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=972477610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.972477610 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_av_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_bitstuff_err.3023472889 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 162636118 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 07:54:28 AM UTC 24 |
| Finished | Aug 21 07:54:30 AM UTC 24 |
| Peak memory | 216412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3023472889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.3023472889 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_bitstuff_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_data_toggle_clear.153034950 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 572924629 ps |
| CPU time | 2.59 seconds |
| Started | Aug 21 07:54:28 AM UTC 24 |
| Finished | Aug 21 07:54:31 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=153034950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.153034950 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_data_toggle_restore.4255552047 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 842019892 ps |
| CPU time | 4.09 seconds |
| Started | Aug 21 07:54:28 AM UTC 24 |
| Finished | Aug 21 07:54:33 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4255552047 -assert nopostproc +UVM_TESTNAME=u sbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.4255552047 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_device_address.4083402890 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 25409985691 ps |
| CPU time | 52.59 seconds |
| Started | Aug 21 07:54:29 AM UTC 24 |
| Finished | Aug 21 07:55:23 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4083402890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.4083402890 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_device_address/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_device_timeout.2450756525 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 8420072150 ps |
| CPU time | 50.48 seconds |
| Started | Aug 21 07:54:29 AM UTC 24 |
| Finished | Aug 21 07:55:21 AM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2450756525 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.2450756525 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_device_timeout/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_disable_endpoint.1767811360 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 639140084 ps |
| CPU time | 2.57 seconds |
| Started | Aug 21 07:54:30 AM UTC 24 |
| Finished | Aug 21 07:54:34 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1767811360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1767811360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_disable_endpoint/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_disconnected.4102424062 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 181038751 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 07:54:30 AM UTC 24 |
| Finished | Aug 21 07:54:33 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4102424062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.4102424062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_disconnected/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_enable.4174911124 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 45128092 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 07:54:30 AM UTC 24 |
| Finished | Aug 21 07:54:33 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4174911124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usb dev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.4174911124 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_enable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_endpoint_access.1469546516 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 860121724 ps |
| CPU time | 4.15 seconds |
| Started | Aug 21 07:54:30 AM UTC 24 |
| Finished | Aug 21 07:54:36 AM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1469546516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_2 0_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.1469546516 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_endpoint_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_endpoint_types.4043618168 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 733647660 ps |
| CPU time | 2.16 seconds |
| Started | Aug 21 07:54:31 AM UTC 24 |
| Finished | Aug 21 07:54:34 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4043618168 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_types.4043618168 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_fifo_rst.413435550 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 296707535 ps |
| CPU time | 3.07 seconds |
| Started | Aug 21 07:54:31 AM UTC 24 |
| Finished | Aug 21 07:54:35 AM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=413435550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.413435550 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_fifo_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_in_iso.2611868383 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 156535805 ps |
| CPU time | 1.32 seconds |
| Started | Aug 21 07:54:33 AM UTC 24 |
| Finished | Aug 21 07:54:35 AM UTC 24 |
| Peak memory | 216304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2611868383 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2611868383 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_in_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_in_stall.399162838 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 140186814 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:54:33 AM UTC 24 |
| Finished | Aug 21 07:54:35 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=399162838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.399162838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_in_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_in_trans.2847197519 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 198403569 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 07:54:33 AM UTC 24 |
| Finished | Aug 21 07:54:36 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2847197519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2847197519 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_invalid_sync.4078159013 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 3839583076 ps |
| CPU time | 27.22 seconds |
| Started | Aug 21 07:54:33 AM UTC 24 |
| Finished | Aug 21 07:55:02 AM UTC 24 |
| Peak memory | 230624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4078159013 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0 _0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.4078159013 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_invalid_sync/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_iso_retraction.34209900 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 3930659138 ps |
| CPU time | 28.5 seconds |
| Started | Aug 21 07:54:35 AM UTC 24 |
| Finished | Aug 21 07:55:04 AM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34209900 -assert nopostproc +UVM_TESTNAME=usbdev _base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.34209900 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_iso_retraction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_link_in_err.2404195155 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 209596516 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 07:54:35 AM UTC 24 |
| Finished | Aug 21 07:54:37 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2404195155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2404195155 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_link_in_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_link_resume.3528785839 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 5573251703 ps |
| CPU time | 10.59 seconds |
| Started | Aug 21 07:54:35 AM UTC 24 |
| Finished | Aug 21 07:54:46 AM UTC 24 |
| Peak memory | 218232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3528785839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3528785839 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_link_resume/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_link_suspend.1368359360 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 9496097996 ps |
| CPU time | 19.39 seconds |
| Started | Aug 21 07:54:35 AM UTC 24 |
| Finished | Aug 21 07:54:55 AM UTC 24 |
| Peak memory | 218344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1368359360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.1368359360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_link_suspend/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_low_speed_traffic.1120427758 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 3254378850 ps |
| CPU time | 31.51 seconds |
| Started | Aug 21 07:54:35 AM UTC 24 |
| Finished | Aug 21 07:55:08 AM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1120427758 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.1120427758 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_max_inter_pkt_delay.2556689361 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 1953198741 ps |
| CPU time | 19.6 seconds |
| Started | Aug 21 07:54:35 AM UTC 24 |
| Finished | Aug 21 07:54:56 AM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2556689361 -assert nopostproc +UV M_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.2556689361 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_max_length_in_transaction.2102574894 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 271039207 ps |
| CPU time | 1.77 seconds |
| Started | Aug 21 07:54:37 AM UTC 24 |
| Finished | Aug 21 07:54:39 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2102574894 -assert nopostproc +UVM_TESTNAME=usbdev_base_ test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2102574894 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_max_length_out_transaction.1023510050 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 201233139 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:54:37 AM UTC 24 |
| Finished | Aug 21 07:54:39 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1023510050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1023510050 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_max_non_iso_usb_traffic.332917583 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 1890926682 ps |
| CPU time | 17.16 seconds |
| Started | Aug 21 07:54:37 AM UTC 24 |
| Finished | Aug 21 07:54:55 AM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=332917583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20 24_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_non_iso_usb_traffic.332917583 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_max_usb_traffic.1953429101 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 2230035893 ps |
| CPU time | 56.27 seconds |
| Started | Aug 21 07:54:37 AM UTC 24 |
| Finished | Aug 21 07:55:35 AM UTC 24 |
| Peak memory | 235164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1953429101 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.1953429101 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_min_inter_pkt_delay.4150136391 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 3548717230 ps |
| CPU time | 92.59 seconds |
| Started | Aug 21 07:54:37 AM UTC 24 |
| Finished | Aug 21 07:56:11 AM UTC 24 |
| Peak memory | 228528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4150136391 -assert nopostproc +UVM_ TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.4150136391 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_min_length_in_transaction.1023395020 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 207582683 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 07:54:37 AM UTC 24 |
| Finished | Aug 21 07:54:39 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1023395020 -assert nopostproc +UVM_TESTNAME=usbdev_base_t est +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.1023395020 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_min_length_out_transaction.4261628756 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 183638966 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:54:37 AM UTC 24 |
| Finished | Aug 21 07:54:39 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4261628756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.4261628756 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_nak_trans.2594823603 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 168256628 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 07:54:38 AM UTC 24 |
| Finished | Aug 21 07:54:41 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2594823603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2594823603 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_nak_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_out_iso.1398140078 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 212073777 ps |
| CPU time | 1.51 seconds |
| Started | Aug 21 07:54:38 AM UTC 24 |
| Finished | Aug 21 07:54:41 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1398140078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.1398140078 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_out_iso/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_out_stall.3414597622 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 177814938 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 07:54:40 AM UTC 24 |
| Finished | Aug 21 07:54:42 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3414597622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3414597622 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_out_stall/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_out_trans_nak.507178751 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 163475254 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:54:40 AM UTC 24 |
| Finished | Aug 21 07:54:42 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=507178751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.507178751 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_out_trans_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_pending_in_trans.2216020751 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 182285391 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:54:40 AM UTC 24 |
| Finished | Aug 21 07:54:42 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2216020751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_ 20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2216020751 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_pending_in_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_phy_config_pinflip.2270690406 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 204933057 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 07:54:41 AM UTC 24 |
| Finished | Aug 21 07:54:44 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2270690406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.2270690406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_phy_config_usb_ref_disable.3736831194 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 152940854 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 07:54:41 AM UTC 24 |
| Finished | Aug 21 07:54:43 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3736831194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_ 0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3736831194 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_phy_pins_sense.742298008 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 28464535 ps |
| CPU time | 1 seconds |
| Started | Aug 21 07:54:41 AM UTC 24 |
| Finished | Aug 21 07:54:43 AM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=742298008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.742298008 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_buffer.3040519647 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 10866250356 ps |
| CPU time | 25.52 seconds |
| Started | Aug 21 07:54:41 AM UTC 24 |
| Finished | Aug 21 07:55:08 AM UTC 24 |
| Peak memory | 228516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3040519647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3040519647 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_pkt_buffer/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_received.3933011165 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 160205607 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:54:41 AM UTC 24 |
| Finished | Aug 21 07:54:44 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3933011165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_R C0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3933011165 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_pkt_received/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_sent.4151684033 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 174624981 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:54:41 AM UTC 24 |
| Finished | Aug 21 07:54:44 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4151684033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/u sbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.4151684033 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_pkt_sent/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_rand_bus_disconnects.4091018070 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 10234553547 ps |
| CPU time | 184.92 seconds |
| Started | Aug 21 07:54:43 AM UTC 24 |
| Finished | Aug 21 07:57:50 AM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4091018070 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.4091018070 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_rand_bus_resets.2513588628 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 6307316911 ps |
| CPU time | 30.39 seconds |
| Started | Aug 21 07:54:44 AM UTC 24 |
| Finished | Aug 21 07:55:16 AM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2513588628 -assert nopostproc +UVM_TESTNAME=usbdev_ base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.2513588628 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_rand_suspends.1353905668 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 6214295722 ps |
| CPU time | 25.55 seconds |
| Started | Aug 21 07:54:44 AM UTC 24 |
| Finished | Aug 21 07:55:11 AM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1353905668 -assert nopos tproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1353905668 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_rand_suspends/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_random_length_in_transaction.1187700676 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 160098597 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 07:54:42 AM UTC 24 |
| Finished | Aug 21 07:54:45 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1187700676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_ RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.1187700676 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_random_length_out_transaction.1013718496 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 195599354 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 07:54:42 AM UTC 24 |
| Finished | Aug 21 07:54:45 AM UTC 24 |
| Peak memory | 216592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1013718496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.1013718496 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_resume_link_active.1158021940 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 20187009912 ps |
| CPU time | 35.76 seconds |
| Started | Aug 21 07:54:44 AM UTC 24 |
| Finished | Aug 21 07:55:21 AM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1158021940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_0 8_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_resume_link_active.1158021940 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_resume_link_active/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_rx_crc_err.3568033111 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 143665268 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 07:54:44 AM UTC 24 |
| Finished | Aug 21 07:54:46 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3568033111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3568033111 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_rx_crc_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_rx_full.3002183382 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 347185153 ps |
| CPU time | 1.95 seconds |
| Started | Aug 21 07:54:50 AM UTC 24 |
| Finished | Aug 21 07:54:53 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3002183382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/us bdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_full.3002183382 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_rx_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_setup_stage.600950540 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 154412031 ps |
| CPU time | 1.15 seconds |
| Started | Aug 21 07:54:50 AM UTC 24 |
| Finished | Aug 21 07:54:52 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=600950540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0 /usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.600950540 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_setup_stage/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_setup_trans_ignored.2385861490 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 151691454 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 07:54:50 AM UTC 24 |
| Finished | Aug 21 07:54:53 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2385861490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_ 08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2385861490 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_smoke.3179759081 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 233049063 ps |
| CPU time | 1.68 seconds |
| Started | Aug 21 07:54:50 AM UTC 24 |
| Finished | Aug 21 07:54:53 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3179759081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbd ev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3179759081 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_spurious_pids_ignored.3571408693 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 1770310856 ps |
| CPU time | 12.23 seconds |
| Started | Aug 21 07:54:50 AM UTC 24 |
| Finished | Aug 21 07:55:04 AM UTC 24 |
| Peak memory | 230480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3571408693 -assert nopostproc +UVM_TESTNAME=usbdev_ba se_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.3571408693 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_stall_priority_over_nak.3910194069 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 169905668 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 07:54:52 AM UTC 24 |
| Finished | Aug 21 07:54:54 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3910194069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2 024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3910194069 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_stall_trans.3940632583 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 230364560 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 07:54:52 AM UTC 24 |
| Finished | Aug 21 07:54:54 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3940632583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC 0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3940632583 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_stall_trans/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_stream_len_max.3880621591 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 947813354 ps |
| CPU time | 2.93 seconds |
| Started | Aug 21 07:54:52 AM UTC 24 |
| Finished | Aug 21 07:54:56 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3880621591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20 _RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3880621591 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_stream_len_max/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_streaming_out.4046852725 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 2542260704 ps |
| CPU time | 22.88 seconds |
| Started | Aug 21 07:54:52 AM UTC 24 |
| Finished | Aug 21 07:55:16 AM UTC 24 |
| Peak memory | 228676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4046852725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/ usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.4046852725 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_streaming_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_timeout_missing_host_handshake.2784275694 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 2474657587 ps |
| CPU time | 22.42 seconds |
| Started | Aug 21 07:54:29 AM UTC 24 |
| Finished | Aug 21 07:54:53 AM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2784275694 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_ host_handshake.2784275694 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/9.usbdev_tx_rx_disruption.2225159669 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 594018481 ps |
| CPU time | 1.76 seconds |
| Started | Aug 21 07:54:53 AM UTC 24 |
| Finished | Aug 21 07:54:56 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2225159669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.usbdev_tx_rx_disruption.2225159669 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/9.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/90.usbdev_endpoint_types.3766895900 |
| Short name | T3166 |
| Test name | |
| Test status | |
| Simulation time | 311330374 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 08:05:43 AM UTC 24 |
| Finished | Aug 21 08:05:45 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3766895900 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_endpoint_types.3766895900 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/90.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/90.usbdev_tx_rx_disruption.2164906370 |
| Short name | T3168 |
| Test name | |
| Test status | |
| Simulation time | 507234913 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 08:05:43 AM UTC 24 |
| Finished | Aug 21 08:05:45 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2164906370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 90.usbdev_tx_rx_disruption.2164906370 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/90.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/91.usbdev_endpoint_types.876516677 |
| Short name | T3169 |
| Test name | |
| Test status | |
| Simulation time | 191326991 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:46 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=876516677 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_endpoint_types.876516677 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/91.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/91.usbdev_tx_rx_disruption.3641351025 |
| Short name | T3172 |
| Test name | |
| Test status | |
| Simulation time | 493425993 ps |
| CPU time | 1.48 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3641351025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 91.usbdev_tx_rx_disruption.3641351025 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/91.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/92.usbdev_endpoint_types.3395665802 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 501955278 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:46 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3395665802 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_endpoint_types.3395665802 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/92.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/92.usbdev_tx_rx_disruption.3260883625 |
| Short name | T3174 |
| Test name | |
| Test status | |
| Simulation time | 595956044 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3260883625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 92.usbdev_tx_rx_disruption.3260883625 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/92.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/93.usbdev_endpoint_types.4123635802 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 281361125 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:46 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4123635802 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_endpoint_types.4123635802 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/93.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/93.usbdev_tx_rx_disruption.3404635768 |
| Short name | T3176 |
| Test name | |
| Test status | |
| Simulation time | 602307903 ps |
| CPU time | 1.6 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3404635768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 93.usbdev_tx_rx_disruption.3404635768 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/93.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/94.usbdev_endpoint_types.745449392 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 356834097 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:46 AM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=745449392 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_endpoint_types.745449392 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/94.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/94.usbdev_tx_rx_disruption.2289696570 |
| Short name | T3170 |
| Test name | |
| Test status | |
| Simulation time | 450216018 ps |
| CPU time | 1.23 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2289696570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 94.usbdev_tx_rx_disruption.2289696570 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/94.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/95.usbdev_endpoint_types.94330178 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 366634568 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=94330178 -assert nopostproc +UVM_TESTNAME=usbdev _base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_endpoint_types.94330178 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/95.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/95.usbdev_tx_rx_disruption.2004262949 |
| Short name | T3175 |
| Test name | |
| Test status | |
| Simulation time | 515415604 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=2004262949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 95.usbdev_tx_rx_disruption.2004262949 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/95.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/96.usbdev_endpoint_types.3872105065 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 301857817 ps |
| CPU time | 1.07 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3872105065 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_endpoint_types.3872105065 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/96.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/96.usbdev_tx_rx_disruption.490400258 |
| Short name | T3177 |
| Test name | |
| Test status | |
| Simulation time | 604646253 ps |
| CPU time | 1.53 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=490400258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 96.usbdev_tx_rx_disruption.490400258 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/96.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/97.usbdev_endpoint_types.3074716513 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 596606035 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3074716513 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_endpoint_types.3074716513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/97.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/97.usbdev_tx_rx_disruption.1929301745 |
| Short name | T3178 |
| Test name | |
| Test status | |
| Simulation time | 527790761 ps |
| CPU time | 1.49 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1929301745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 97.usbdev_tx_rx_disruption.1929301745 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/97.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/98.usbdev_endpoint_types.188670984 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 464906541 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=188670984 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_endpoint_types.188670984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/98.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/98.usbdev_tx_rx_disruption.3409195401 |
| Short name | T3180 |
| Test name | |
| Test status | |
| Simulation time | 646029211 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 08:05:44 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=3409195401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 98.usbdev_tx_rx_disruption.3409195401 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/98.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/99.usbdev_endpoint_types.3593462648 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 614291610 ps |
| CPU time | 1.55 seconds |
| Started | Aug 21 08:05:45 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 216460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3593462648 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_endpoint_types.3593462648 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/99.usbdev_endpoint_types/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/default/99.usbdev_tx_rx_disruption.1931294070 |
| Short name | T3179 |
| Test name | |
| Test status | |
| Simulation time | 492465319 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 08:05:45 AM UTC 24 |
| Finished | Aug 21 08:05:47 AM UTC 24 |
| Peak memory | 215984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/openti tan/hw/dv/tools/sim.tcl +ntb_random_seed=1931294070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 99.usbdev_tx_rx_disruption.1931294070 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/99.usbdev_tx_rx_disruption/latest |
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