Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	90010	1			T1	3		T2	4		T3	6
all_values[1]	90010	1			T1	3		T2	4		T3	6
all_values[2]	90010	1			T1	3		T2	4		T3	6
all_values[3]	90010	1			T1	3		T2	4		T3	6
all_values[4]	90010	1			T1	3		T2	4		T3	6
all_values[5]	90010	1			T1	3		T2	4		T3	6
all_values[6]	90010	1			T1	3		T2	4		T3	6
all_values[7]	90010	1			T1	3		T2	4		T3	6
all_values[8]	90010	1			T1	3		T2	4		T3	6
all_values[9]	90010	1			T1	3		T2	4		T3	6
all_values[10]	90010	1			T1	3		T2	4		T3	6
all_values[11]	90010	1			T1	3		T2	4		T3	6
all_values[12]	90010	1			T1	3		T2	4		T3	6
all_values[13]	90010	1			T1	3		T2	4		T3	6
all_values[14]	90010	1			T1	3		T2	4		T3	6
all_values[15]	90010	1			T1	3		T2	4		T3	6
all_values[16]	90010	1			T1	3		T2	4		T3	6
all_values[17]	90010	1			T1	3		T2	4		T3	6

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2870612

1

T1

96

T2

128

T3

189

auto[1]

9708

1

T3

3

T16

5

T17

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2410425

1

T1

87

T2

110

T3

177

auto[1]

469895

1

T1

9

T2

18

T3

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	62355	1			T1	3		T2	3		T3	3
all_values[0]	auto[0]	auto[1]	24325	1			T2	1		T3	3		T28	2
all_values[0]	auto[1]	auto[0]	3218	1			T45	3		T46	3		T47	3
all_values[0]	auto[1]	auto[1]	112	1			T441	1		T442	1		T443	1
all_values[1]	auto[0]	auto[0]	85561	1			T1	3		T2	4		T3	6
all_values[1]	auto[0]	auto[1]	3080	1			T18	2		T19	2		T30	1
all_values[1]	auto[1]	auto[0]	510	1			T27	2		T31	2		T48	2
all_values[1]	auto[1]	auto[1]	859	1			T27	12		T31	1		T48	1
all_values[2]	auto[0]	auto[0]	4388	1			T1	1		T2	1		T3	5
all_values[2]	auto[0]	auto[1]	85367	1			T1	2		T2	3		T3	1
all_values[2]	auto[1]	auto[0]	129	1			T21	1		T63	1		T64	1
all_values[2]	auto[1]	auto[1]	126	1			T21	1		T63	1		T64	1
all_values[3]	auto[0]	auto[0]	88064	1			T1	3		T2	4		T3	6
all_values[3]	auto[0]	auto[1]	291	1			T43	1		T5	1		T65	1
all_values[3]	auto[1]	auto[0]	1588	1			T43	1484		T221	4		T220	3
all_values[3]	auto[1]	auto[1]	67	1			T43	1		T217	3		T220	2
all_values[4]	auto[0]	auto[0]	4383	1			T1	1		T2	1		T3	5
all_values[4]	auto[0]	auto[1]	85476	1			T1	2		T2	3		T3	1
all_values[4]	auto[1]	auto[0]	92	1			T44	1		T217	1		T219	1
all_values[4]	auto[1]	auto[1]	59	1			T44	1		T221	1		T220	2
all_values[5]	auto[0]	auto[0]	89495	1			T1	2		T2	4		T3	6
all_values[5]	auto[0]	auto[1]	364	1			T1	1		T7	1		T59	1
all_values[5]	auto[1]	auto[0]	96	1			T217	1		T219	1		T220	4
all_values[5]	auto[1]	auto[1]	55	1			T217	3		T219	3		T221	2
all_values[6]	auto[0]	auto[0]	89575	1			T1	3		T2	4		T3	6
all_values[6]	auto[0]	auto[1]	235	1			T7	1		T59	1		T98	1
all_values[6]	auto[1]	auto[0]	88	1			T217	2		T220	1		T286	4
all_values[6]	auto[1]	auto[1]	112	1			T66	1		T67	1		T68	1
all_values[7]	auto[0]	auto[0]	35936	1			T1	2		T3	1		T16	5
all_values[7]	auto[0]	auto[1]	53938	1			T1	1		T2	4		T3	2
all_values[7]	auto[1]	auto[0]	81	1			T3	2		T49	2		T217	4
all_values[7]	auto[1]	auto[1]	55	1			T3	1		T49	1		T217	2
all_values[8]	auto[0]	auto[0]	89100	1			T1	3		T2	4		T3	6
all_values[8]	auto[0]	auto[1]	242	1			T28	2		T54	2		T279	2
all_values[8]	auto[1]	auto[0]	594	1			T50	10		T52	10		T53	10
all_values[8]	auto[1]	auto[1]	74	1			T50	1		T53	1		T55	1
all_values[9]	auto[0]	auto[0]	89754	1			T1	3		T2	4		T3	6
all_values[9]	auto[0]	auto[1]	55	1			T217	2		T221	1		T220	1
all_values[9]	auto[1]	auto[0]	123	1			T16	3		T61	3		T62	3
all_values[9]	auto[1]	auto[1]	78	1			T16	2		T61	2		T62	2
all_values[10]	auto[0]	auto[0]	89468	1			T1	3		T2	4		T3	6
all_values[10]	auto[0]	auto[1]	392	1			T19	1		T26	1		T32	2
all_values[10]	auto[1]	auto[0]	86	1			T217	4		T219	1		T221	1
all_values[10]	auto[1]	auto[1]	64	1			T217	1		T219	2		T221	4
all_values[11]	auto[0]	auto[0]	88980	1			T1	3		T2	4		T3	6
all_values[11]	auto[0]	auto[1]	741	1			T17	1		T29	4		T33	4
all_values[11]	auto[1]	auto[0]	154	1			T71	1		T72	1		T73	1
all_values[11]	auto[1]	auto[1]	135	1			T71	1		T72	1		T73	1
all_values[12]	auto[0]	auto[0]	89600	1			T1	3		T2	4		T3	6
all_values[12]	auto[0]	auto[1]	220	1			T76	1		T78	1		T79	1
all_values[12]	auto[1]	auto[0]	121	1			T74	2		T75	2		T77	2
all_values[12]	auto[1]	auto[1]	69	1			T74	1		T75	1		T77	1
all_values[13]	auto[0]	auto[0]	89677	1			T1	3		T2	4		T3	6
all_values[13]	auto[0]	auto[1]	59	1			T76	1		T78	1		T79	1
all_values[13]	auto[1]	auto[0]	156	1			T17	1		T80	1		T81	1
all_values[13]	auto[1]	auto[1]	118	1			T17	1		T80	1		T81	1
all_values[14]	auto[0]	auto[0]	18554	1			T1	3		T2	4		T3	6
all_values[14]	auto[0]	auto[1]	71284	1			T21	1		T43	1486		T4	1
all_values[14]	auto[1]	auto[0]	102	1			T217	1		T219	3		T221	1
all_values[14]	auto[1]	auto[1]	70	1			T217	2		T221	1		T220	3
all_values[15]	auto[0]	auto[0]	4439	1			T1	1		T2	1		T3	5
all_values[15]	auto[0]	auto[1]	85420	1			T1	2		T2	3		T3	1
all_values[15]	auto[1]	auto[0]	79	1			T217	1		T221	1		T220	1
all_values[15]	auto[1]	auto[1]	72	1			T217	1		T219	1		T284	1
all_values[16]	auto[0]	auto[0]	88915	1			T1	3		T2	4		T3	6
all_values[16]	auto[0]	auto[1]	903	1			T19	1		T60	1		T70	1
all_values[16]	auto[1]	auto[0]	126	1			T29	4		T33	4		T69	4
all_values[16]	auto[1]	auto[1]	66	1			T29	4		T33	4		T69	4
all_values[17]	auto[0]	auto[0]	34576	1			T1	2		T22	2		T84	2
all_values[17]	auto[0]	auto[1]	55260	1			T1	1		T2	4		T3	6
all_values[17]	auto[1]	auto[0]	122	1			T56	2		T57	2		T58	2
all_values[17]	auto[1]	auto[1]	52	1			T56	1		T57	1		T58	1