Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109879

1

T2

1

T3

1

T17

1

auto[1]

46179

1

T18

9

T19

6

T20

1

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	28621	1			T43	3		T34	2		T82	1
max_len_m1	792	1			T43	3		T4	4		T5	5
max_len_m2	821	1			T3	1		T27	2		T43	3
max_len_m3	869	1			T19	1		T29	1		T43	2
five	1147	1			T19	1		T43	3		T4	2
four	1119	1			T29	1		T43	2		T4	3
three	805	1			T43	5		T45	1		T101	12
one	845	1			T5	2		T69	1		T107	2
zero	11988	1			T17	1		T18	9		T19	2

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23012	1			T43	3		T34	1		T82	1
max_len	auto[1]	5609	1			T34	1		T5	2		T113	2
max_len_m1	auto[0]	565	1			T43	3		T4	2		T5	3
max_len_m1	auto[1]	227	1			T4	2		T5	2		T464	3
max_len_m2	auto[0]	556	1			T3	1		T27	1		T43	3
max_len_m2	auto[1]	265	1			T27	1		T162	1		T159	2
max_len_m3	auto[0]	600	1			T19	1		T29	1		T43	2
max_len_m3	auto[1]	269	1			T6	1		T464	1		T162	2
five	auto[0]	607	1			T19	1		T43	3		T4	2
five	auto[1]	540	1			T6	1		T153	1		T101	2
four	auto[0]	570	1			T29	1		T43	2		T4	2
four	auto[1]	549	1			T4	1		T98	1		T101	7
three	auto[0]	383	1			T43	5		T101	4		T154	1
three	auto[1]	422	1			T45	1		T101	8		T154	1
one	auto[0]	363	1			T5	2		T69	1		T107	1
one	auto[1]	482	1			T107	1		T101	8		T154	2
zero	auto[0]	579	1			T17	1		T43	3		T33	1
zero	auto[1]	11409	1			T18	9		T19	2		T20	1