Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	0	96	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136727

1

T2

2

T3

2

T18

8

auto[1]

78673

1

T18

18

T19

9

T20

2

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	16145	1			T20	2		T27	4		T85	26
endpoints[0x1]	15550	1			T27	4		T4	24		T47	6
endpoints[0x2]	16952	1			T18	26		T19	2		T27	4
endpoints[0x3]	21199	1			T19	1		T27	4		T34	4
endpoints[0x4]	18188	1			T19	2		T27	4		T33	21
endpoints[0x5]	19468	1			T19	4		T27	4		T30	2
endpoints[0x6]	17028	1			T19	3		T27	4		T32	4
endpoints[0x7]	18634	1			T3	2		T19	2		T27	4
endpoints[0x8]	17186	1			T2	2		T19	2		T60	1
endpoints[0x9]	18008	1			T19	4		T26	1		T27	4
endpoints[0xa]	21111	1			T27	4		T29	21		T4	32
endpoints[0xb]	15931	1			T19	1		T27	4		T28	16

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	1435	1			T19	1		T29	2		T33	2
ack	104088	1			T2	1		T3	1		T18	13
data1	50663	1			T18	4		T19	2		T29	5
data0	59140	1			T2	1		T3	1		T18	9

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	0	96	100.00

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[0]	endpoints[0x0]	118	1			T69	2		T65	13		T111	5
nak	auto[0]	endpoints[0x1]	153	1			T51	1		T465	1		T466	1
nak	auto[0]	endpoints[0x2]	117	1			T112	12		T467	1		T468	1
nak	auto[0]	endpoints[0x3]	114	1			T426	1		T65	15		T119	1
nak	auto[0]	endpoints[0x4]	96	1			T33	2		T112	10		T469	1
nak	auto[0]	endpoints[0x5]	106	1			T65	8		T356	1		T470	1
nak	auto[0]	endpoints[0x6]	89	1			T65	12		T175	21		T471	3
nak	auto[0]	endpoints[0x7]	125	1			T471	4		T139	1		T372	5
nak	auto[0]	endpoints[0x8]	101	1			T167	13		T472	4		T473	5
nak	auto[0]	endpoints[0x9]	96	1			T65	7		T145	1		T294	4
nak	auto[0]	endpoints[0xa]	75	1			T29	2		T70	1		T111	4
nak	auto[0]	endpoints[0xb]	66	1			T474	1		T475	1		T150	1
nak	auto[1]	endpoints[0x0]	24	1			T476	1		T477	2		T478	1
nak	auto[1]	endpoints[0x1]	12	1			T479	1		T477	1		T478	1
nak	auto[1]	endpoints[0x2]	19	1			T480	1		T481	1		T482	1
nak	auto[1]	endpoints[0x3]	7	1			T483	1		T484	2		T485	1
nak	auto[1]	endpoints[0x4]	18	1			T107	2		T486	1		T479	1
nak	auto[1]	endpoints[0x5]	7	1			T479	2		T482	1		T487	1
nak	auto[1]	endpoints[0x6]	13	1			T488	1		T489	1		T487	1
nak	auto[1]	endpoints[0x7]	19	1			T488	3		T482	1		T490	1
nak	auto[1]	endpoints[0x8]	15	1			T479	2		T482	2		T491	1
nak	auto[1]	endpoints[0x9]	11	1			T19	1		T109	1		T489	1
nak	auto[1]	endpoints[0xa]	18	1			T492	1		T482	1		T489	2
nak	auto[1]	endpoints[0xb]	16	1			T486	1		T478	1		T481	1
ack	auto[0]	endpoints[0x0]	4599	1			T27	1		T85	8		T69	8
ack	auto[0]	endpoints[0x1]	3860	1			T27	1		T47	2		T51	7
ack	auto[0]	endpoints[0x2]	5137	1			T18	4		T19	1		T27	1
ack	auto[0]	endpoints[0x3]	7040	1			T27	1		T34	1		T4	8
ack	auto[0]	endpoints[0x4]	5783	1			T19	1		T27	1		T33	8
ack	auto[0]	endpoints[0x5]	6278	1			T27	1		T30	1		T5	8
ack	auto[0]	endpoints[0x6]	4702	1			T19	1		T27	1		T32	1
ack	auto[0]	endpoints[0x7]	5969	1			T3	1		T19	1		T27	1
ack	auto[0]	endpoints[0x8]	4885	1			T2	1		T19	1		T27	1
ack	auto[0]	endpoints[0x9]	5516	1			T19	1		T27	1		T107	1
ack	auto[0]	endpoints[0xa]	7186	1			T27	1		T29	8		T4	8
ack	auto[0]	endpoints[0xb]	4397	1			T27	1		T28	8		T5	8
ack	auto[1]	endpoints[0x0]	3178	1			T20	1		T27	1		T85	5
ack	auto[1]	endpoints[0x1]	3511	1			T27	1		T4	8		T47	1
ack	auto[1]	endpoints[0x2]	3025	1			T18	9		T27	1		T5	8
ack	auto[1]	endpoints[0x3]	3283	1			T27	1		T34	1		T4	8
ack	auto[1]	endpoints[0x4]	3020	1			T27	1		T45	1		T113	51
ack	auto[1]	endpoints[0x5]	3146	1			T19	2		T27	1		T5	8
ack	auto[1]	endpoints[0x6]	3522	1			T27	1		T5	8		T153	7
ack	auto[1]	endpoints[0x7]	3050	1			T27	1		T107	2		T65	6
ack	auto[1]	endpoints[0x8]	3396	1			T27	1		T31	1		T93	1
ack	auto[1]	endpoints[0x9]	3219	1			T27	1		T98	5		T153	7
ack	auto[1]	endpoints[0xa]	3130	1			T27	1		T4	8		T5	8
ack	auto[1]	endpoints[0xb]	3256	1			T27	1		T5	8		T155	1
data1	auto[0]	endpoints[0x0]	2043	1			T85	3		T69	5		T6	6
data1	auto[0]	endpoints[0x1]	1611	1			T47	1		T51	4		T107	1
data1	auto[0]	endpoints[0x2]	2306	1			T5	4		T153	2		T101	11
data1	auto[0]	endpoints[0x3]	3152	1			T4	3		T5	4		T46	1
data1	auto[0]	endpoints[0x4]	2597	1			T33	5		T45	1		T65	4
data1	auto[0]	endpoints[0x5]	2900	1			T5	4		T107	1		T115	2
data1	auto[0]	endpoints[0x6]	2043	1			T5	1		T65	12		T153	3
data1	auto[0]	endpoints[0x7]	2746	1			T98	2		T101	11		T157	1
data1	auto[0]	endpoints[0x8]	2177	1			T93	1		T6	5		T101	12
data1	auto[0]	endpoints[0x9]	2511	1			T107	1		T65	7		T98	2
data1	auto[0]	endpoints[0xa]	3336	1			T29	5		T4	2		T5	2
data1	auto[0]	endpoints[0xb]	1885	1			T5	4		T155	1		T98	2
data1	auto[1]	endpoints[0x0]	1741	1			T85	5		T6	8		T65	7
data1	auto[1]	endpoints[0x1]	1964	1			T4	4		T47	1		T6	7
data1	auto[1]	endpoints[0x2]	1664	1			T18	4		T5	4		T65	6
data1	auto[1]	endpoints[0x3]	1838	1			T4	4		T5	4		T46	1
data1	auto[1]	endpoints[0x4]	1674	1			T45	1		T107	2		T113	32
data1	auto[1]	endpoints[0x5]	1724	1			T5	4		T115	2		T98	2
data1	auto[1]	endpoints[0x6]	1913	1			T19	1		T5	6		T153	4
data1	auto[1]	endpoints[0x7]	1678	1			T65	5		T98	2		T101	10
data1	auto[1]	endpoints[0x8]	1861	1			T93	1		T6	10		T65	6
data1	auto[1]	endpoints[0x9]	1766	1			T19	1		T107	1		T98	2
data1	auto[1]	endpoints[0xa]	1713	1			T4	6		T5	6		T153	5
data1	auto[1]	endpoints[0xb]	1820	1			T5	4		T155	1		T107	1
data0	auto[0]	endpoints[0x0]	2938	1			T27	1		T85	5		T69	6
data0	auto[0]	endpoints[0x1]	2813	1			T27	1		T4	8		T47	1
data0	auto[0]	endpoints[0x2]	3235	1			T18	4		T19	1		T27	1
data0	auto[0]	endpoints[0x3]	4226	1			T27	1		T34	1		T4	5
data0	auto[0]	endpoints[0x4]	3582	1			T19	1		T27	1		T33	6
data0	auto[0]	endpoints[0x5]	3765	1			T27	1		T30	1		T5	4
data0	auto[0]	endpoints[0x6]	3053	1			T19	1		T27	1		T32	1
data0	auto[0]	endpoints[0x7]	3607	1			T3	1		T19	1		T27	1
data0	auto[0]	endpoints[0x8]	3107	1			T2	1		T19	1		T60	1
data0	auto[0]	endpoints[0x9]	3323	1			T19	1		T27	1		T187	1
data0	auto[0]	endpoints[0xa]	4173	1			T27	1		T29	6		T4	6
data0	auto[0]	endpoints[0xb]	2966	1			T27	1		T28	8		T5	4
data0	auto[1]	endpoints[0x0]	1498	1			T20	1		T27	1		T493	1
data0	auto[1]	endpoints[0x1]	1622	1			T27	1		T4	4		T6	8
data0	auto[1]	endpoints[0x2]	1441	1			T18	5		T27	1		T5	4
data0	auto[1]	endpoints[0x3]	1533	1			T19	1		T27	1		T34	1
data0	auto[1]	endpoints[0x4]	1414	1			T27	1		T113	19		T98	3
data0	auto[1]	endpoints[0x5]	1536	1			T19	2		T27	1		T5	4
data0	auto[1]	endpoints[0x6]	1683	1			T27	1		T32	1		T5	2
data0	auto[1]	endpoints[0x7]	1436	1			T27	1		T107	2		T65	1
data0	auto[1]	endpoints[0x8]	1635	1			T27	1		T31	1		T48	1
data0	auto[1]	endpoints[0x9]	1559	1			T26	1		T27	1		T98	3
data0	auto[1]	endpoints[0xa]	1475	1			T27	1		T4	2		T5	2
data0	auto[1]	endpoints[0xb]	1520	1			T19	1		T27	1		T5	4