Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7909 1 T22 12 T84 1 T4 4
auto[1] 54705 1 T18 9 T19 6 T20 1


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 54910 1 T18 9 T19 6 T20 1
auto[1] 7704 1 T84 1 T30 1 T4 23


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 55976 1 T18 9 T19 6 T20 1
auto[1] 6638 1 T22 10 T36 1 T106 1


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4399 1 T22 3 T84 1 T4 7
pkt_types[PidTypeInToken] 58215 1 T18 9 T19 6 T20 1


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1219 1 T22 2 T65 30 T111 14
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 786 1 T22 1 T65 19 T111 7
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 102 1 T84 1 T4 4 T295 2
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 13 1 T401 1 T419 1 T382 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1325 1 T4 2 T65 38 T111 23
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 828 1 T65 2 T111 6 T251 2
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 109 1 T4 1 T189 6 T295 1
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 17 1 T364 1 T336 1 T401 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 3377 1 T22 2 T65 93 T226 3
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 2315 1 T22 7 T65 39 T226 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 47 1 T346 1 T366 1 T409 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 50 1 T362 1 T401 1 T413 2
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 42468 1 T18 9 T19 6 T20 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2592 1 T22 2 T36 1 T106 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7329 1 T30 1 T4 18 T6 32
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 37 1 T361 1 T494 1 T364 1

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