Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	54	0	54	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	0	54	100.00	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	20280	1			T60	1		T4	33		T5	100
solo	73380	1			T2	1		T3	1		T17	1
empty	4756	1			T22	3		T84	2		T28	8

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	20293	1			T4	33		T5	100		T6	45
solo	32809	1			T22	11		T84	2		T28	8
empty	45464	1			T2	1		T3	1		T17	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

out

75260

1

T2

1

T3

1

T17

1

setup

23402

1

T22

6

T84

2

T60

1

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rx

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	46	1			T54	1		T181	1		T495	1
solo	155	1			T28	1		T29	1		T33	1
empty	82473	1			T2	1		T3	1		T17	1

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	0	54	100.00

Automatically Generated Cross Bins for cr_fifo_X_pid

Bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	full	full	out	2	1			T184	1		T496	1		-	-
full	full	full	setup	2	1			T497	1		T498	1		-	-
full	full	solo	out	1	1			T499	1		-	-		-	-
full	full	solo	setup	1	1			T500	1		-	-		-	-
full	full	empty	out	15787	1			T4	26		T5	90		T6	32
full	full	empty	setup	4419	1			T4	7		T5	10		T6	13
full	solo	full	out	1	1			T501	1		-	-		-	-
full	solo	full	setup	3	1			T54	1		T502	1		T503	1
full	solo	solo	out	4	1			T504	1		T505	1		T506	1
full	solo	solo	setup	5	1			T507	1		T508	1		T509	1
full	solo	empty	out	2	1			T510	1		T511	1		-	-
full	solo	empty	setup	2	1			T512	1		T513	1		-	-
full	empty	full	out	2	1			T514	1		T515	1		-	-
full	empty	full	setup	5	1			T516	1		T517	1		T518	1
full	empty	solo	out	6	1			T519	1		T520	1		T521	1
full	empty	solo	setup	10	1			T522	1		T523	1		T524	1
full	empty	empty	out	2	1			T183	1		T525	1		-	-
full	empty	empty	setup	6	1			T526	1		T527	1		T528	1
solo	full	full	out	1	1			T529	1		-	-		-	-
solo	full	full	setup	2	1			T530	1		T531	1		-	-
solo	full	solo	out	1	1			T468	1		-	-		-	-
solo	full	solo	setup	2	1			T532	1		T533	1		-	-
solo	full	empty	out	8	1			T51	1		T465	1		T466	1
solo	full	empty	setup	4	1			T534	1		T535	1		T536	1
solo	solo	full	out	6	1			T495	1		T537	1		T538	1
solo	solo	full	setup	2	1			T539	1		T540	1		-	-
solo	solo	solo	out	7	1			T51	1		T465	1		T466	1
solo	solo	solo	setup	8	1			T51	1		T465	1		T466	1
solo	solo	empty	out	8194	1			T22	5		T106	1		T65	164
solo	solo	empty	setup	8169	1			T22	3		T74	1		T106	1
solo	empty	full	out	4	1			T541	1		T542	1		T543	1
solo	empty	full	setup	2	1			T544	1		T545	1		-	-
solo	empty	solo	out	2	1			T546	1		T547	1		-	-
solo	empty	solo	setup	75	1			T28	1		T54	1		T279	1
solo	empty	empty	out	5	1			T548	1		T549	1		T550	1
solo	empty	empty	setup	2134	1			T22	3		T84	2		T28	1
empty	full	full	out	3	1			T551	1		T552	1		T553	1
empty	full	full	setup	4	1			T554	1		T555	1		T556	1
empty	full	solo	out	1	1			T185	1		-	-		-	-
empty	full	solo	setup	2	1			T557	1		T558	1		-	-
empty	full	empty	out	4	1			T559	1		T560	1		T561	1
empty	full	empty	setup	3	1			T60	1		T562	1		T563	1
empty	solo	full	out	1	1			T564	1		-	-		-	-
empty	solo	full	setup	3	1			T565	1		T566	1		T567	1
empty	solo	solo	out	6	1			T568	1		T569	1		T570	1
empty	solo	solo	setup	3	1			T571	1		T572	1		T573	1
empty	solo	empty	out	43265	1			T2	1		T3	1		T17	1
empty	solo	empty	setup	1	1			T574	1		-	-		-	-
empty	empty	full	out	2	1			T575	1		T576	1		-	-
empty	empty	full	setup	1	1			T181	1		-	-		-	-
empty	empty	solo	out	2	1			T577	1		T578	1		-	-
empty	empty	solo	setup	4	1			T579	1		T580	1		T581	1
empty	empty	empty	out	259	1			T29	1		T43	131		T33	1
empty	empty	empty	setup	160	1			T187	1		T188	1		T582	1