Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	90010	1			T1	3		T2	4		T3	6
all_pins[1]	90010	1			T1	3		T2	4		T3	6
all_pins[2]	90010	1			T1	3		T2	4		T3	6
all_pins[3]	90010	1			T1	3		T2	4		T3	6
all_pins[4]	90010	1			T1	3		T2	4		T3	6
all_pins[5]	90010	1			T1	3		T2	4		T3	6
all_pins[6]	90010	1			T1	3		T2	4		T3	6
all_pins[7]	90010	1			T1	3		T2	4		T3	6
all_pins[8]	90010	1			T1	3		T2	4		T3	6
all_pins[9]	90010	1			T1	3		T2	4		T3	6
all_pins[10]	90010	1			T1	3		T2	4		T3	6
all_pins[11]	90010	1			T1	3		T2	4		T3	6
all_pins[12]	90010	1			T1	3		T2	4		T3	6
all_pins[13]	90010	1			T1	3		T2	4		T3	6
all_pins[14]	90010	1			T1	3		T2	4		T3	6
all_pins[15]	90010	1			T1	3		T2	4		T3	6
all_pins[16]	90010	1			T1	3		T2	4		T3	6
all_pins[17]	90010	1			T1	3		T2	4		T3	6

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2878077	1			T1	96		T2	128		T3	191
values[0x1]	2243	1			T3	1		T16	2		T17	1
transitions[0x0=>0x1]	1957	1			T3	1		T16	2		T17	1
transitions[0x1=>0x0]	1957	1			T3	1		T16	2		T17	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	89898	1			T1	3		T2	4		T3	6
all_pins[0]	values[0x1]	112	1			T441	1		T442	1		T443	1
all_pins[0]	transitions[0x0=>0x1]	97	1			T441	1		T442	1		T443	1
all_pins[0]	transitions[0x1=>0x0]	844	1			T27	12		T31	1		T48	1
all_pins[1]	values[0x0]	89151	1			T1	3		T2	4		T3	6
all_pins[1]	values[0x1]	859	1			T27	12		T31	1		T48	1
all_pins[1]	transitions[0x0=>0x1]	843	1			T27	12		T31	1		T48	1
all_pins[1]	transitions[0x1=>0x0]	110	1			T21	1		T63	1		T64	1
all_pins[2]	values[0x0]	89884	1			T1	3		T2	4		T3	6
all_pins[2]	values[0x1]	126	1			T21	1		T63	1		T64	1
all_pins[2]	transitions[0x0=>0x1]	110	1			T21	1		T63	1		T64	1
all_pins[2]	transitions[0x1=>0x0]	51	1			T43	1		T217	2		T220	2
all_pins[3]	values[0x0]	89943	1			T1	3		T2	4		T3	6
all_pins[3]	values[0x1]	67	1			T43	1		T217	3		T220	2
all_pins[3]	transitions[0x0=>0x1]	47	1			T43	1		T217	3		T286	3
all_pins[3]	transitions[0x1=>0x0]	39	1			T44	1		T221	1		T284	2
all_pins[4]	values[0x0]	89951	1			T1	3		T2	4		T3	6
all_pins[4]	values[0x1]	59	1			T44	1		T221	1		T220	2
all_pins[4]	transitions[0x0=>0x1]	49	1			T44	1		T220	2		T284	2
all_pins[4]	transitions[0x1=>0x0]	45	1			T217	3		T219	3		T221	1
all_pins[5]	values[0x0]	89955	1			T1	3		T2	4		T3	6
all_pins[5]	values[0x1]	55	1			T217	3		T219	3		T221	2
all_pins[5]	transitions[0x0=>0x1]	35	1			T217	2		T219	3		T221	2
all_pins[5]	transitions[0x1=>0x0]	92	1			T66	1		T67	1		T68	1
all_pins[6]	values[0x0]	89898	1			T1	3		T2	4		T3	6
all_pins[6]	values[0x1]	112	1			T66	1		T67	1		T68	1
all_pins[6]	transitions[0x0=>0x1]	99	1			T66	1		T67	1		T68	1
all_pins[6]	transitions[0x1=>0x0]	42	1			T3	1		T49	1		T217	1
all_pins[7]	values[0x0]	89955	1			T1	3		T2	4		T3	5
all_pins[7]	values[0x1]	55	1			T3	1		T49	1		T217	2
all_pins[7]	transitions[0x0=>0x1]	45	1			T3	1		T49	1		T217	2
all_pins[7]	transitions[0x1=>0x0]	64	1			T50	1		T53	1		T55	1
all_pins[8]	values[0x0]	89936	1			T1	3		T2	4		T3	6
all_pins[8]	values[0x1]	74	1			T50	1		T53	1		T55	1
all_pins[8]	transitions[0x0=>0x1]	62	1			T50	1		T53	1		T55	1
all_pins[8]	transitions[0x1=>0x0]	66	1			T16	2		T61	2		T62	2
all_pins[9]	values[0x0]	89932	1			T1	3		T2	4		T3	6
all_pins[9]	values[0x1]	78	1			T16	2		T61	2		T62	2
all_pins[9]	transitions[0x0=>0x1]	56	1			T16	2		T61	2		T62	2
all_pins[9]	transitions[0x1=>0x0]	42	1			T217	1		T219	2		T221	2
all_pins[10]	values[0x0]	89946	1			T1	3		T2	4		T3	6
all_pins[10]	values[0x1]	64	1			T217	1		T219	2		T221	4
all_pins[10]	transitions[0x0=>0x1]	42	1			T217	1		T219	2		T221	2
all_pins[10]	transitions[0x1=>0x0]	113	1			T71	1		T72	1		T73	1
all_pins[11]	values[0x0]	89875	1			T1	3		T2	4		T3	6
all_pins[11]	values[0x1]	135	1			T71	1		T72	1		T73	1
all_pins[11]	transitions[0x0=>0x1]	111	1			T71	1		T72	1		T73	1
all_pins[11]	transitions[0x1=>0x0]	45	1			T74	1		T75	1		T77	1
all_pins[12]	values[0x0]	89941	1			T1	3		T2	4		T3	6
all_pins[12]	values[0x1]	69	1			T74	1		T75	1		T77	1
all_pins[12]	transitions[0x0=>0x1]	54	1			T74	1		T75	1		T77	1
all_pins[12]	transitions[0x1=>0x0]	103	1			T17	1		T80	1		T81	1
all_pins[13]	values[0x0]	89892	1			T1	3		T2	4		T3	6
all_pins[13]	values[0x1]	118	1			T17	1		T80	1		T81	1
all_pins[13]	transitions[0x0=>0x1]	96	1			T17	1		T80	1		T81	1
all_pins[13]	transitions[0x1=>0x0]	48	1			T217	2		T221	1		T284	3
all_pins[14]	values[0x0]	89940	1			T1	3		T2	4		T3	6
all_pins[14]	values[0x1]	70	1			T217	2		T221	1		T220	3
all_pins[14]	transitions[0x0=>0x1]	52	1			T217	2		T221	1		T220	3
all_pins[14]	transitions[0x1=>0x0]	54	1			T217	1		T219	1		T285	1
all_pins[15]	values[0x0]	89938	1			T1	3		T2	4		T3	6
all_pins[15]	values[0x1]	72	1			T217	1		T219	1		T284	1
all_pins[15]	transitions[0x0=>0x1]	54	1			T217	1		T219	1		T284	1
all_pins[15]	transitions[0x1=>0x0]	48	1			T29	4		T33	4		T69	4
all_pins[16]	values[0x0]	89944	1			T1	3		T2	4		T3	6
all_pins[16]	values[0x1]	66	1			T29	4		T33	4		T69	4
all_pins[16]	transitions[0x0=>0x1]	53	1			T29	4		T33	4		T69	4
all_pins[16]	transitions[0x1=>0x0]	39	1			T56	1		T57	1		T58	1
all_pins[17]	values[0x0]	89958	1			T1	3		T2	4		T3	6
all_pins[17]	values[0x1]	52	1			T56	1		T57	1		T58	1
all_pins[17]	transitions[0x0=>0x1]	52	1			T56	1		T57	1		T58	1