Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4429	1			T5	13		T65	110		T110	11
invalid_ep[0xd]	4442	1			T5	16		T65	103		T110	13
invalid_ep[0xe]	4556	1			T5	10		T65	108		T110	14
invalid_ep[0xf]	4302	1			T5	13		T65	69		T110	19
endpoints[0x0]	12290	1			T20	1		T84	1		T27	2
endpoints[0x1]	12396	1			T22	9		T27	2		T4	20
endpoints[0x2]	13007	1			T18	13		T19	1		T84	1
endpoints[0x3]	14654	1			T19	1		T22	6		T27	2
endpoints[0x4]	13496	1			T19	1		T27	2		T33	11
endpoints[0x5]	14207	1			T19	2		T22	8		T27	2
endpoints[0x6]	12650	1			T19	2		T22	2		T27	2
endpoints[0x7]	13494	1			T3	1		T17	1		T19	1
endpoints[0x8]	13192	1			T2	1		T19	1		T22	1
endpoints[0x9]	13274	1			T19	2		T26	1		T27	2
endpoints[0xa]	14905	1			T22	2		T27	2		T29	11
endpoints[0xb]	12534	1			T19	1		T22	3		T84	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	23402	1			T22	6		T84	2		T60	1
pkt_types[PidTypeOutToken]	75260	1			T2	1		T3	1		T17	1
pkt_types[PidTypeInToken]	62096	1			T18	9		T19	6		T20	1

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	972	1			T65	31		T111	17		T112	15
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	981	1			T65	26		T111	12		T112	21
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	982	1			T65	27		T111	7		T112	19
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	933	1			T65	20		T111	10		T112	17
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1674	1			T84	1		T85	5		T50	8
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1786	1			T22	3		T47	1		T65	19
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1580	1			T65	20		T153	5		T226	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1770	1			T22	2		T4	2		T46	1
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1630	1			T87	1		T45	1		T65	22
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1541	1			T106	1		T65	13		T115	2
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1630	1			T5	6		T65	24		T153	3
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1594	1			T65	31		T157	4		T160	1
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1512	1			T60	1		T93	1		T74	1
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1544	1			T187	1		T65	24		T162	2
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1625	1			T4	5		T5	4		T65	24
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1648	1			T22	1		T84	1		T28	8
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1503	1			T5	13		T65	31		T110	11
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1526	1			T5	16		T65	19		T110	13
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1580	1			T5	10		T65	32		T110	14
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1473	1			T5	13		T65	13		T110	19
pkt_types[PidTypeOutToken]	endpoints[0x0]	4915	1			T27	1		T85	3		T69	11
pkt_types[PidTypeOutToken]	endpoints[0x1]	4142	1			T22	2		T27	1		T4	8
pkt_types[PidTypeOutToken]	endpoints[0x2]	5591	1			T18	4		T19	1		T27	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	7107	1			T22	1		T27	1		T34	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	6035	1			T19	1		T27	1		T33	11
pkt_types[PidTypeOutToken]	endpoints[0x5]	6677	1			T22	1		T27	1		T30	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	5005	1			T19	1		T27	1		T32	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	6300	1			T3	1		T17	1		T19	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	5285	1			T2	1		T19	1		T27	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	5821	1			T19	1		T27	1		T182	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	7522	1			T27	1		T29	11		T4	3
pkt_types[PidTypeOutToken]	endpoints[0xb]	4778	1			T22	1		T27	1		T43	131
pkt_types[PidTypeInToken]	invalid_ep[0xc]	972	1			T65	22		T111	14		T112	11
pkt_types[PidTypeInToken]	invalid_ep[0xd]	942	1			T65	29		T111	18		T112	19
pkt_types[PidTypeInToken]	invalid_ep[0xe]	996	1			T65	21		T111	21		T112	21
pkt_types[PidTypeInToken]	invalid_ep[0xf]	971	1			T65	16		T111	9		T112	19
pkt_types[PidTypeInToken]	endpoints[0x0]	4619	1			T20	1		T27	1		T36	1
pkt_types[PidTypeInToken]	endpoints[0x1]	5423	1			T22	2		T27	1		T4	9
pkt_types[PidTypeInToken]	endpoints[0x2]	4704	1			T18	9		T27	1		T4	9
pkt_types[PidTypeInToken]	endpoints[0x3]	4771	1			T19	1		T22	1		T27	1
pkt_types[PidTypeInToken]	endpoints[0x4]	4681	1			T27	1		T45	1		T107	2
pkt_types[PidTypeInToken]	endpoints[0x5]	4870	1			T19	2		T22	6		T27	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4897	1			T19	1		T22	2		T27	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4529	1			T27	1		T107	2		T65	23
pkt_types[PidTypeInToken]	endpoints[0x8]	5281	1			T27	1		T31	1		T93	1
pkt_types[PidTypeInToken]	endpoints[0x9]	4823	1			T19	1		T26	1		T27	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4649	1			T22	2		T27	1		T4	9
pkt_types[PidTypeInToken]	endpoints[0xb]	4968	1			T19	1		T22	1		T27	1