Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1			T217	7		T219	4		T221	4
all_values[1]	275	1			T217	7		T219	4		T221	4
all_values[2]	275	1			T217	7		T219	4		T221	4
all_values[3]	275	1			T217	7		T219	4		T221	4
all_values[4]	275	1			T217	7		T219	4		T221	4
all_values[5]	275	1			T217	7		T219	4		T221	4
all_values[6]	275	1			T217	7		T219	4		T221	4
all_values[7]	275	1			T217	7		T219	4		T221	4
all_values[8]	275	1			T217	7		T219	4		T221	4
all_values[9]	275	1			T217	7		T219	4		T221	4
all_values[10]	275	1			T217	7		T219	4		T221	4
all_values[11]	275	1			T217	7		T219	4		T221	4
all_values[12]	275	1			T217	7		T219	4		T221	4
all_values[13]	275	1			T217	7		T219	4		T221	4
all_values[14]	275	1			T217	7		T219	4		T221	4
all_values[15]	275	1			T217	7		T219	4		T221	4
all_values[16]	275	1			T217	7		T219	4		T221	4
all_values[17]	275	1			T217	7		T219	4		T221	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6597

1

T217

158

T219

103

T221

93

auto[1]

2203

1

T217

66

T219

25

T221

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6105

1

T217

156

T219

91

T221

88

auto[1]

2695

1

T217

68

T219

37

T221

40

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5269

1

T217

134

T219

82

T221

79

auto[1]

3531

1

T217

90

T219

46

T221

49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	95	1			T217	2		T219	2		T221	3
all_values[0]	auto[0]	auto[1]	auto[0]	76	1			T217	1		T219	2		T284	1
all_values[0]	auto[1]	auto[0]	auto[1]	54	1			T221	1		T284	1		T285	1
all_values[0]	auto[1]	auto[1]	auto[1]	50	1			T217	4		T220	2		T284	1
all_values[1]	auto[0]	auto[0]	auto[0]	105	1			T217	2		T219	1		T220	4
all_values[1]	auto[0]	auto[1]	auto[0]	69	1			T217	2		T219	1		T221	3
all_values[1]	auto[1]	auto[0]	auto[1]	60	1			T217	2		T219	2		T284	1
all_values[1]	auto[1]	auto[1]	auto[1]	41	1			T217	1		T221	1		T286	1
all_values[2]	auto[0]	auto[0]	auto[0]	35	1			T219	1		T221	1		T220	2
all_values[2]	auto[0]	auto[0]	auto[1]	64	1			T217	1		T219	2		T221	1
all_values[2]	auto[0]	auto[1]	auto[0]	38	1			T287	2		T288	3		T289	1
all_values[2]	auto[0]	auto[1]	auto[1]	27	1			T217	1		T221	1		T284	1
all_values[2]	auto[1]	auto[0]	auto[1]	55	1			T217	2		T219	1		T221	1
all_values[2]	auto[1]	auto[1]	auto[1]	56	1			T217	3		T284	1		T285	2
all_values[3]	auto[0]	auto[0]	auto[0]	62	1			T217	1		T219	2		T221	1
all_values[3]	auto[0]	auto[0]	auto[1]	24	1			T217	2		T219	1		T284	1
all_values[3]	auto[0]	auto[1]	auto[0]	48	1			T221	3		T220	1		T288	2
all_values[3]	auto[0]	auto[1]	auto[1]	28	1			T217	1		T220	1		T286	2
all_values[3]	auto[1]	auto[0]	auto[1]	57	1			T217	1		T219	1		T284	2
all_values[3]	auto[1]	auto[1]	auto[1]	56	1			T217	2		T220	1		T285	1
all_values[4]	auto[0]	auto[0]	auto[0]	68	1			T217	2		T219	2		T221	1
all_values[4]	auto[0]	auto[0]	auto[1]	26	1			T217	1		T221	1		T284	1
all_values[4]	auto[0]	auto[1]	auto[0]	48	1			T217	2		T219	2		T287	3
all_values[4]	auto[0]	auto[1]	auto[1]	26	1			T220	1		T285	2		T286	3
all_values[4]	auto[1]	auto[0]	auto[1]	66	1			T217	2		T221	1		T220	1
all_values[4]	auto[1]	auto[1]	auto[1]	41	1			T221	1		T284	2		T285	1
all_values[5]	auto[0]	auto[0]	auto[0]	60	1			T217	1		T221	1		T220	1
all_values[5]	auto[0]	auto[0]	auto[1]	29	1			T217	1		T219	1		T284	1
all_values[5]	auto[0]	auto[1]	auto[0]	54	1			T217	2		T220	1		T286	2
all_values[5]	auto[0]	auto[1]	auto[1]	20	1			T217	1		T219	1		T220	1
all_values[5]	auto[1]	auto[0]	auto[1]	63	1			T217	1		T219	2		T221	1
all_values[5]	auto[1]	auto[1]	auto[1]	49	1			T217	1		T221	2		T220	1
all_values[6]	auto[0]	auto[0]	auto[0]	64	1			T217	2		T221	4		T220	2
all_values[6]	auto[0]	auto[0]	auto[1]	30	1			T217	1		T219	1		T220	1
all_values[6]	auto[0]	auto[1]	auto[0]	43	1			T217	1		T286	2		T288	1
all_values[6]	auto[0]	auto[1]	auto[1]	26	1			T286	3		T287	1		T288	2
all_values[6]	auto[1]	auto[0]	auto[1]	69	1			T217	1		T219	3		T220	1
all_values[6]	auto[1]	auto[1]	auto[1]	43	1			T217	2		T288	2		T290	2
all_values[7]	auto[0]	auto[0]	auto[0]	107	1			T221	2		T220	2		T284	2
all_values[7]	auto[0]	auto[1]	auto[0]	64	1			T217	4		T219	1		T221	1
all_values[7]	auto[1]	auto[0]	auto[1]	59	1			T217	2		T219	3		T287	1
all_values[7]	auto[1]	auto[1]	auto[1]	45	1			T217	1		T221	1		T220	1
all_values[8]	auto[0]	auto[0]	auto[0]	88	1			T217	2		T219	1		T221	1
all_values[8]	auto[0]	auto[1]	auto[0]	69	1			T217	3		T219	1		T221	1
all_values[8]	auto[1]	auto[0]	auto[1]	74	1			T221	1		T220	1		T284	2
all_values[8]	auto[1]	auto[1]	auto[1]	44	1			T217	2		T219	2		T221	1
all_values[9]	auto[0]	auto[0]	auto[0]	68	1			T217	2		T219	3		T220	1
all_values[9]	auto[0]	auto[0]	auto[1]	27	1			T217	1		T220	1		T284	1
all_values[9]	auto[0]	auto[1]	auto[0]	55	1			T217	3		T219	1		T221	1
all_values[9]	auto[0]	auto[1]	auto[1]	30	1			T221	1		T286	1		T287	1
all_values[9]	auto[1]	auto[0]	auto[1]	51	1			T217	1		T221	1		T220	2
all_values[9]	auto[1]	auto[1]	auto[1]	44	1			T221	1		T286	2		T287	1
all_values[10]	auto[0]	auto[0]	auto[0]	76	1			T217	1		T219	1		T220	3
all_values[10]	auto[0]	auto[0]	auto[1]	32	1			T284	1		T288	2		T289	1
all_values[10]	auto[0]	auto[1]	auto[0]	43	1			T217	3		T290	3		T291	2
all_values[10]	auto[0]	auto[1]	auto[1]	24	1			T217	1		T219	1		T221	2
all_values[10]	auto[1]	auto[0]	auto[1]	60	1			T217	2		T219	2		T220	1
all_values[10]	auto[1]	auto[1]	auto[1]	40	1			T221	2		T286	3		T287	1
all_values[11]	auto[0]	auto[0]	auto[0]	48	1			T217	3		T219	1		T284	1
all_values[11]	auto[0]	auto[0]	auto[1]	31	1			T220	2		T284	1		T286	2
all_values[11]	auto[0]	auto[1]	auto[0]	50	1			T217	1		T219	3		T221	1
all_values[11]	auto[0]	auto[1]	auto[1]	37	1			T217	1		T221	1		T220	1
all_values[11]	auto[1]	auto[0]	auto[1]	56	1			T217	1		T221	1		T220	1
all_values[11]	auto[1]	auto[1]	auto[1]	53	1			T217	1		T221	1		T284	1
all_values[12]	auto[0]	auto[0]	auto[0]	47	1			T219	1		T284	1		T286	3
all_values[12]	auto[0]	auto[0]	auto[1]	28	1			T217	1		T220	2		T287	3
all_values[12]	auto[0]	auto[1]	auto[0]	61	1			T217	3		T219	3		T284	1
all_values[12]	auto[0]	auto[1]	auto[1]	24	1			T221	1		T284	1		T285	1
all_values[12]	auto[1]	auto[0]	auto[1]	60	1			T217	1		T220	2		T285	1
all_values[12]	auto[1]	auto[1]	auto[1]	55	1			T217	2		T221	3		T284	1
all_values[13]	auto[0]	auto[0]	auto[0]	74	1			T217	3		T219	1		T221	1
all_values[13]	auto[0]	auto[0]	auto[1]	23	1			T219	1		T221	1		T287	1
all_values[13]	auto[0]	auto[1]	auto[0]	53	1			T217	3		T285	2		T287	1
all_values[13]	auto[0]	auto[1]	auto[1]	26	1			T219	1		T220	2		T286	3
all_values[13]	auto[1]	auto[0]	auto[1]	54	1			T217	1		T221	1		T284	2
all_values[13]	auto[1]	auto[1]	auto[1]	45	1			T219	1		T221	1		T220	1
all_values[14]	auto[0]	auto[0]	auto[0]	41	1			T219	2		T284	1		T285	3
all_values[14]	auto[0]	auto[0]	auto[1]	28	1			T217	1		T221	1		T287	3
all_values[14]	auto[0]	auto[1]	auto[0]	50	1			T217	1		T219	1		T221	1
all_values[14]	auto[0]	auto[1]	auto[1]	29	1			T217	1		T220	2		T284	2
all_values[14]	auto[1]	auto[0]	auto[1]	77	1			T217	3		T219	1		T221	1
all_values[14]	auto[1]	auto[1]	auto[1]	50	1			T217	1		T221	1		T220	1
all_values[15]	auto[0]	auto[0]	auto[0]	59	1			T220	2		T284	2		T285	2
all_values[15]	auto[0]	auto[0]	auto[1]	30	1			T217	3		T219	2		T221	1
all_values[15]	auto[0]	auto[1]	auto[0]	43	1			T217	1		T221	1		T220	2
all_values[15]	auto[0]	auto[1]	auto[1]	26	1			T284	1		T291	1		T292	2
all_values[15]	auto[1]	auto[0]	auto[1]	66	1			T217	2		T219	2		T221	2
all_values[15]	auto[1]	auto[1]	auto[1]	51	1			T217	1		T284	1		T286	1
all_values[16]	auto[0]	auto[0]	auto[0]	54	1			T217	1		T221	1		T284	1
all_values[16]	auto[0]	auto[0]	auto[1]	24	1			T217	1		T221	1		T220	1
all_values[16]	auto[0]	auto[1]	auto[0]	64	1			T217	1		T221	1		T220	1
all_values[16]	auto[0]	auto[1]	auto[1]	18	1			T219	2		T285	1		T286	1
all_values[16]	auto[1]	auto[0]	auto[1]	63	1			T219	1		T221	1		T220	1
all_values[16]	auto[1]	auto[1]	auto[1]	52	1			T217	4		T219	1		T220	1
all_values[17]	auto[0]	auto[0]	auto[0]	100	1			T217	3		T219	1		T221	2
all_values[17]	auto[0]	auto[1]	auto[0]	76	1			T217	2		T219	1		T221	1
all_values[17]	auto[1]	auto[0]	auto[1]	56	1			T219	2		T221	1		T220	1
all_values[17]	auto[1]	auto[1]	auto[1]	43	1			T217	2		T220	1		T286	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal