Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	170867	1			T1	3		T2	7		T3	4
all_values[1]	170867	1			T1	3		T2	7		T3	4
all_values[2]	170867	1			T1	3		T2	7		T3	4
all_values[3]	170867	1			T1	3		T2	7		T3	4
all_values[4]	170867	1			T1	3		T2	7		T3	4
all_values[5]	170867	1			T1	3		T2	7		T3	4
all_values[6]	170867	1			T1	3		T2	7		T3	4
all_values[7]	170867	1			T1	3		T2	7		T3	4
all_values[8]	170867	1			T1	3		T2	7		T3	4
all_values[9]	170867	1			T1	3		T2	7		T3	4
all_values[10]	170867	1			T1	3		T2	7		T3	4
all_values[11]	170867	1			T1	3		T2	7		T3	4
all_values[12]	170867	1			T1	3		T2	7		T3	4
all_values[13]	170867	1			T1	3		T2	7		T3	4
all_values[14]	170867	1			T1	3		T2	7		T3	4
all_values[15]	170867	1			T1	3		T2	7		T3	4
all_values[16]	170867	1			T1	3		T2	7		T3	4
all_values[17]	170867	1			T1	3		T2	7		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5458474

1

T1

94

T2

219

T3

128

auto[1]

9270

1

T1

2

T2

5

T30

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4687658

1

T1

85

T2

210

T3

110

auto[1]

780086

1

T1

11

T2

14

T3

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142553	1			T1	3		T2	7		T3	3
all_values[0]	auto[0]	auto[1]	25204	1			T3	1		T30	3		T33	2
all_values[0]	auto[1]	auto[0]	3012	1			T50	3		T52	3		T53	3
all_values[0]	auto[1]	auto[1]	98	1			T235	1		T406	1		T407	1
all_values[1]	auto[0]	auto[0]	166549	1			T1	3		T2	7		T3	4
all_values[1]	auto[0]	auto[1]	2931	1			T31	2		T34	2		T37	1
all_values[1]	auto[1]	auto[0]	512	1			T35	2		T36	2		T54	2
all_values[1]	auto[1]	auto[1]	875	1			T35	12		T36	1		T54	1
all_values[2]	auto[0]	auto[0]	4348	1			T1	1		T2	6		T3	1
all_values[2]	auto[0]	auto[1]	166283	1			T1	2		T2	1		T3	3
all_values[2]	auto[1]	auto[0]	112	1			T42	1		T69	1		T70	1
all_values[2]	auto[1]	auto[1]	124	1			T42	1		T69	1		T70	1
all_values[3]	auto[0]	auto[0]	168968	1			T1	3		T2	7		T3	4
all_values[3]	auto[0]	auto[1]	275	1			T18	1		T71	1		T72	1
all_values[3]	auto[1]	auto[0]	1575	1			T18	1484		T209	2		T210	4
all_values[3]	auto[1]	auto[1]	49	1			T18	1		T209	1		T211	3
all_values[4]	auto[0]	auto[0]	4306	1			T1	1		T2	6		T3	1
all_values[4]	auto[0]	auto[1]	166408	1			T1	2		T2	1		T3	3
all_values[4]	auto[1]	auto[0]	105	1			T51	1		T209	2		T210	1
all_values[4]	auto[1]	auto[1]	48	1			T51	1		T292	1		T290	3
all_values[5]	auto[0]	auto[0]	170359	1			T1	3		T2	7		T3	4
all_values[5]	auto[0]	auto[1]	352	1			T7	1		T8	1		T63	1
all_values[5]	auto[1]	auto[0]	88	1			T209	1		T211	2		T292	2
all_values[5]	auto[1]	auto[1]	68	1			T210	1		T211	1		T292	2
all_values[6]	auto[0]	auto[0]	170466	1			T1	3		T2	7		T3	4
all_values[6]	auto[0]	auto[1]	221	1			T8	1		T63	1		T10	1
all_values[6]	auto[1]	auto[0]	94	1			T209	3		T210	4		T211	1
all_values[6]	auto[1]	auto[1]	86	1			T73	1		T74	1		T75	1
all_values[7]	auto[0]	auto[0]	115164	1			T1	3		T2	5		T42	2
all_values[7]	auto[0]	auto[1]	55547	1			T2	2		T3	4		T30	6
all_values[7]	auto[1]	auto[0]	110	1			T55	2		T56	2		T57	2
all_values[7]	auto[1]	auto[1]	46	1			T55	1		T56	1		T57	1
all_values[8]	auto[0]	auto[0]	169973	1			T1	3		T2	7		T3	4
all_values[8]	auto[0]	auto[1]	237	1			T33	2		T228	2		T225	2
all_values[8]	auto[1]	auto[0]	580	1			T21	10		T59	10		T60	10
all_values[8]	auto[1]	auto[1]	77	1			T59	1		T60	1		T62	1
all_values[9]	auto[0]	auto[0]	170618	1			T1	3		T2	2		T3	4
all_values[9]	auto[0]	auto[1]	54	1			T210	1		T211	1		T292	2
all_values[9]	auto[1]	auto[0]	122	1			T2	3		T67	3		T68	3
all_values[9]	auto[1]	auto[1]	73	1			T2	2		T67	2		T68	2
all_values[10]	auto[0]	auto[0]	170333	1			T1	3		T2	7		T3	4
all_values[10]	auto[0]	auto[1]	397	1			T34	1		T40	2		T64	1
all_values[10]	auto[1]	auto[0]	70	1			T209	2		T211	1		T292	2
all_values[10]	auto[1]	auto[1]	67	1			T209	3		T211	3		T294	1
all_values[11]	auto[0]	auto[0]	169994	1			T1	2		T2	7		T3	4
all_values[11]	auto[0]	auto[1]	628	1			T1	1		T39	4		T41	4
all_values[11]	auto[1]	auto[0]	131	1			T19	1		T79	1		T80	1
all_values[11]	auto[1]	auto[1]	114	1			T19	1		T79	1		T80	1
all_values[12]	auto[0]	auto[0]	170500	1			T1	3		T2	7		T3	4
all_values[12]	auto[0]	auto[1]	211	1			T81	3		T82	1		T85	3
all_values[12]	auto[1]	auto[0]	98	1			T20	2		T83	2		T84	2
all_values[12]	auto[1]	auto[1]	58	1			T20	1		T83	1		T84	1
all_values[13]	auto[0]	auto[0]	170547	1			T1	1		T2	7		T3	4
all_values[13]	auto[0]	auto[1]	68	1			T82	1		T88	1		T89	1
all_values[13]	auto[1]	auto[0]	135	1			T1	1		T86	1		T87	1
all_values[13]	auto[1]	auto[1]	117	1			T1	1		T86	1		T87	1
all_values[14]	auto[0]	auto[0]	35426	1			T1	3		T2	7		T3	4
all_values[14]	auto[0]	auto[1]	135275	1			T42	1		T65	1		T7	2
all_values[14]	auto[1]	auto[0]	97	1			T209	3		T210	3		T211	2
all_values[14]	auto[1]	auto[1]	69	1			T209	2		T210	1		T211	2
all_values[15]	auto[0]	auto[0]	4375	1			T1	1		T2	6		T3	1
all_values[15]	auto[0]	auto[1]	166345	1			T1	2		T2	1		T3	3
all_values[15]	auto[1]	auto[0]	89	1			T209	2		T211	4		T292	3
all_values[15]	auto[1]	auto[1]	58	1			T209	2		T210	1		T211	2
all_values[16]	auto[0]	auto[0]	169889	1			T1	3		T2	7		T3	4
all_values[16]	auto[0]	auto[1]	807	1			T34	1		T77	1		T78	1
all_values[16]	auto[1]	auto[0]	92	1			T39	4		T41	4		T76	4
all_values[16]	auto[1]	auto[1]	79	1			T39	4		T41	4		T76	4
all_values[17]	auto[0]	auto[0]	114034	1			T30	1		T44	2		T45	2
all_values[17]	auto[0]	auto[1]	56691	1			T1	3		T2	7		T3	4
all_values[17]	auto[1]	auto[0]	96	1			T30	2		T209	2		T210	2
all_values[17]	auto[1]	auto[1]	46	1			T30	1		T210	2		T211	1