Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1641	1			T119	8		T57	1		T120	7
range_16_to_126	150746	1			T3	1		T30	1		T31	17
fifteen	1435	1			T119	4		T117	3		T120	6
range_2_to_14	22537	1			T44	1		T45	3		T52	3
seven	1766	1			T7	2		T249	1		T119	5
one	2998	1			T199	9		T119	7		T117	6
zero	726	1			T1	1		T44	1		T86	1

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

13374

1

T44

6

T34

2

T35

2

three

11074

1

T30

1

T45

1

T35

2

---

Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	135	1			T120	1		T411	17		T186	1
range_127	three	116	1			T411	17		T436	1		T569	1
range_16_to_126	seven	11420	1			T44	6		T34	2		T35	2
range_16_to_126	three	9655	1			T30	1		T35	2		T38	1
fifteen	seven	105	1			T119	1		T117	1		T261	82
fifteen	three	102	1			T119	1		T261	69		T186	1
range_2_to_14	seven	1488	1			T249	1		T119	5		T409	1
range_2_to_14	three	1007	1			T45	1		T64	1		T119	5
seven	seven	48	1			T120	1		T186	1		T570	13
seven	three	72	1			T120	1		T410	1		T186	1
one	seven	151	1			T120	1		T186	1		T262	72
one	three	160	1			T117	1		T262	63		T571	13
zero	seven	75	1			T119	1		T572	1		T460	1
zero	three	34	1			T459	1		T573	1		T574	13