Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111911

1

T1

1

T3

1

T30

1

auto[1]

45683

1

T31

10

T32

2

T34

10

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	29466	1			T121	2		T91	1		T76	2
max_len_m1	821	1			T35	2		T41	1		T123	2
max_len_m2	854	1			T18	1		T24	1		T111	1
max_len_m3	847	1			T76	1		T18	3		T21	1
five	1095	1			T39	1		T41	1		T52	1
four	1054	1			T34	1		T35	2		T5	2
three	764	1			T41	1		T21	1		T58	1
one	821	1			T34	2		T18	3		T64	2
zero	11417	1			T1	1		T31	10		T32	2

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23808	1			T121	1		T91	1		T76	2
max_len	auto[1]	5658	1			T121	1		T6	2		T122	1
max_len_m1	auto[0]	562	1			T35	1		T41	1		T123	1
max_len_m1	auto[1]	259	1			T35	1		T123	1		T5	1
max_len_m2	auto[0]	596	1			T18	1		T24	1		T111	1
max_len_m2	auto[1]	258	1			T162	1		T168	2		T174	1
max_len_m3	auto[0]	583	1			T76	1		T18	3		T21	1
max_len_m3	auto[1]	264	1			T6	2		T168	1		T163	1
five	auto[0]	594	1			T39	1		T41	1		T52	1
five	auto[1]	501	1			T6	1		T182	2		T163	1
four	auto[0]	536	1			T34	1		T35	1		T5	1
four	auto[1]	518	1			T35	1		T5	1		T182	1
three	auto[0]	383	1			T41	1		T21	1		T58	1
three	auto[1]	381	1			T71	8		T199	1		T283	11
one	auto[0]	353	1			T34	1		T18	3		T64	2
one	auto[1]	468	1			T34	1		T258	1		T71	13
zero	auto[0]	548	1			T1	1		T41	1		T164	1
zero	auto[1]	10869	1			T31	10		T32	2		T34	7