Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	0	96	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137658

1

T3

2

T30

2

T31

14

auto[1]

77807

1

T31

20

T32

4

T34

19

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	18673	1			T34	2		T35	4		T91	2
endpoints[0x1]	21998	1			T35	4		T40	4		T121	4
endpoints[0x2]	17122	1			T34	4		T35	4		T78	1
endpoints[0x3]	12962	1			T30	2		T35	4		T39	21
endpoints[0x4]	17075	1			T3	2		T34	2		T35	4
endpoints[0x5]	19669	1			T34	3		T35	4		T63	4
endpoints[0x6]	15445	1			T32	4		T33	16		T34	2
endpoints[0x7]	18339	1			T34	4		T35	4		T37	2
endpoints[0x8]	14238	1			T34	8		T35	4		T41	21
endpoints[0x9]	23463	1			T31	34		T34	2		T35	4
endpoints[0xa]	16300	1			T34	2		T35	4		T77	2
endpoints[0xb]	20181	1			T34	10		T35	4		T76	21

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	1482	1			T34	5		T39	2		T41	2
ack	104015	1			T3	1		T30	1		T31	17
data1	50543	1			T31	2		T32	1		T34	9
data0	59350	1			T3	1		T30	1		T31	15

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	0	96	100.00

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[0]	endpoints[0x0]	76	1			T131	1		T133	1		T134	1
nak	auto[0]	endpoints[0x1]	97	1			T58	1		T61	1		T356	1
nak	auto[0]	endpoints[0x2]	136	1			T137	1		T581	1		T186	18
nak	auto[0]	endpoints[0x3]	64	1			T39	2		T132	1		T140	1
nak	auto[0]	endpoints[0x4]	104	1			T549	1		T119	15		T305	1
nak	auto[0]	endpoints[0x5]	82	1			T582	1		T583	7		T584	7
nak	auto[0]	endpoints[0x6]	66	1			T147	1		T585	12		T586	1
nak	auto[0]	endpoints[0x7]	112	1			T436	7		T150	1		T459	7
nak	auto[0]	endpoints[0x8]	172	1			T41	2		T120	22		T587	1
nak	auto[0]	endpoints[0x9]	117	1			T548	1		T459	9		T572	12
nak	auto[0]	endpoints[0xa]	119	1			T77	1		T583	11		T588	14
nak	auto[0]	endpoints[0xb]	157	1			T76	2		T589	1		T590	1
nak	auto[1]	endpoints[0x0]	13	1			T591	1		T592	1		T593	1
nak	auto[1]	endpoints[0x1]	13	1			T594	1		T593	1		T595	4
nak	auto[1]	endpoints[0x2]	21	1			T596	2		T597	1		T598	1
nak	auto[1]	endpoints[0x3]	18	1			T115	1		T596	2		T597	1
nak	auto[1]	endpoints[0x4]	11	1			T64	1		T599	1		T600	1
nak	auto[1]	endpoints[0x5]	11	1			T601	1		T598	1		T592	1
nak	auto[1]	endpoints[0x6]	18	1			T64	1		T115	1		T592	2
nak	auto[1]	endpoints[0x7]	17	1			T115	1		T597	1		T600	1
nak	auto[1]	endpoints[0x8]	17	1			T34	1		T597	1		T600	1
nak	auto[1]	endpoints[0x9]	12	1			T602	1		T598	1		T600	1
nak	auto[1]	endpoints[0xa]	16	1			T64	2		T600	1		T603	1
nak	auto[1]	endpoints[0xb]	13	1			T34	4		T64	1		T604	1
ack	auto[0]	endpoints[0x0]	6017	1			T35	1		T91	1		T131	1
ack	auto[0]	endpoints[0x1]	7160	1			T35	1		T40	1		T121	1
ack	auto[0]	endpoints[0x2]	5195	1			T34	2		T35	1		T52	2
ack	auto[0]	endpoints[0x3]	3286	1			T30	1		T35	1		T39	8
ack	auto[0]	endpoints[0x4]	5230	1			T3	1		T34	1		T35	1
ack	auto[0]	endpoints[0x5]	6366	1			T35	1		T63	1		T162	1
ack	auto[0]	endpoints[0x6]	4337	1			T33	8		T34	1		T35	1
ack	auto[0]	endpoints[0x7]	5070	1			T34	2		T35	1		T37	1
ack	auto[0]	endpoints[0x8]	3640	1			T34	2		T35	1		T41	8
ack	auto[0]	endpoints[0x9]	8318	1			T31	7		T34	1		T35	1
ack	auto[0]	endpoints[0xa]	4603	1			T35	1		T50	2		T53	2
ack	auto[0]	endpoints[0xb]	6486	1			T34	1		T35	1		T76	8
ack	auto[1]	endpoints[0x0]	3014	1			T34	1		T35	1		T54	1
ack	auto[1]	endpoints[0x1]	3572	1			T35	1		T121	1		T162	1
ack	auto[1]	endpoints[0x2]	3048	1			T35	1		T52	1		T4	4
ack	auto[1]	endpoints[0x3]	2930	1			T35	1		T162	1		T163	7
ack	auto[1]	endpoints[0x4]	3033	1			T35	1		T164	1		T165	1
ack	auto[1]	endpoints[0x5]	3195	1			T34	1		T35	1		T63	1
ack	auto[1]	endpoints[0x6]	3108	1			T32	2		T35	1		T4	4
ack	auto[1]	endpoints[0x7]	3759	1			T35	1		T81	2		T162	1
ack	auto[1]	endpoints[0x8]	3116	1			T34	1		T35	1		T25	1
ack	auto[1]	endpoints[0x9]	3126	1			T31	10		T35	1		T36	1
ack	auto[1]	endpoints[0xa]	3197	1			T34	1		T35	1		T50	1
ack	auto[1]	endpoints[0xb]	3209	1			T35	1		T4	4		T162	1
data1	auto[0]	endpoints[0x0]	2730	1			T131	1		T4	1		T6	2
data1	auto[0]	endpoints[0x1]	3296	1			T58	4		T64	2		T5	3
data1	auto[0]	endpoints[0x2]	2328	1			T34	2		T52	1		T4	1
data1	auto[0]	endpoints[0x3]	1359	1			T39	5		T163	3		T132	1
data1	auto[0]	endpoints[0x4]	2332	1			T165	1		T21	3		T4	2
data1	auto[0]	endpoints[0x5]	2875	1			T5	2		T168	2		T71	12
data1	auto[0]	endpoints[0x6]	1849	1			T34	1		T4	2		T81	1
data1	auto[0]	endpoints[0x7]	2206	1			T34	2		T81	2		T5	2
data1	auto[0]	endpoints[0x8]	1571	1			T41	5		T25	1		T64	1
data1	auto[0]	endpoints[0x9]	3940	1			T31	1		T4	2		T170	16
data1	auto[0]	endpoints[0xa]	2041	1			T50	1		T53	1		T580	1
data1	auto[0]	endpoints[0xb]	2895	1			T34	1		T76	5		T64	1
data1	auto[1]	endpoints[0x0]	1655	1			T34	1		T4	2		T6	5
data1	auto[1]	endpoints[0x1]	1946	1			T5	3		T168	4		T71	16
data1	auto[1]	endpoints[0x2]	1705	1			T52	1		T4	3		T111	1
data1	auto[1]	endpoints[0x3]	1576	1			T163	4		T71	18		T115	2
data1	auto[1]	endpoints[0x4]	1663	1			T165	1		T4	2		T64	1
data1	auto[1]	endpoints[0x5]	1792	1			T5	4		T168	6		T71	16
data1	auto[1]	endpoints[0x6]	1711	1			T32	1		T4	2		T81	1
data1	auto[1]	endpoints[0x7]	2097	1			T81	2		T5	5		T110	11
data1	auto[1]	endpoints[0x8]	1739	1			T34	1		T25	1		T6	5
data1	auto[1]	endpoints[0x9]	1705	1			T31	1		T4	2		T170	32
data1	auto[1]	endpoints[0xa]	1768	1			T50	1		T53	1		T4	2
data1	auto[1]	endpoints[0xb]	1764	1			T34	1		T4	3		T5	3
data0	auto[0]	endpoints[0x0]	3665	1			T35	1		T91	1		T131	1
data0	auto[0]	endpoints[0x1]	4207	1			T35	1		T40	1		T121	1
data0	auto[0]	endpoints[0x2]	3255	1			T35	1		T78	1		T52	1
data0	auto[0]	endpoints[0x3]	2326	1			T30	1		T35	1		T39	6
data0	auto[0]	endpoints[0x4]	3268	1			T3	1		T34	1		T35	1
data0	auto[0]	endpoints[0x5]	3874	1			T35	1		T63	1		T162	1
data0	auto[0]	endpoints[0x6]	2861	1			T33	8		T35	1		T568	1
data0	auto[0]	endpoints[0x7]	3307	1			T35	1		T37	1		T235	1
data0	auto[0]	endpoints[0x8]	2518	1			T34	2		T35	1		T41	6
data0	auto[0]	endpoints[0x9]	4759	1			T31	6		T34	1		T35	1
data0	auto[0]	endpoints[0xa]	3025	1			T35	1		T77	1		T50	1
data0	auto[0]	endpoints[0xb]	4136	1			T35	1		T76	6		T4	4
data0	auto[1]	endpoints[0x0]	1498	1			T35	1		T54	1		T4	2
data0	auto[1]	endpoints[0x1]	1698	1			T35	1		T40	1		T121	1
data0	auto[1]	endpoints[0x2]	1426	1			T35	1		T4	1		T111	6
data0	auto[1]	endpoints[0x3]	1399	1			T35	1		T162	1		T163	3
data0	auto[1]	endpoints[0x4]	1430	1			T35	1		T164	1		T7	1
data0	auto[1]	endpoints[0x5]	1464	1			T34	2		T35	1		T63	1
data0	auto[1]	endpoints[0x6]	1488	1			T32	1		T35	1		T4	2
data0	auto[1]	endpoints[0x7]	1767	1			T35	1		T162	1		T5	2
data0	auto[1]	endpoints[0x8]	1459	1			T34	1		T35	1		T162	1
data0	auto[1]	endpoints[0x9]	1480	1			T31	9		T35	1		T36	1
data0	auto[1]	endpoints[0xa]	1522	1			T34	1		T35	1		T123	1
data0	auto[1]	endpoints[0xb]	1518	1			T34	3		T35	1		T4	1