Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8845 1 T45 1 T82 1 T408 1
auto[1] 53671 1 T31 10 T32 2 T44 4


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 54895 1 T31 10 T32 2 T44 4
auto[1] 7621 1 T45 1 T37 1 T5 32


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 56256 1 T31 10 T32 2 T44 2
auto[1] 6260 1 T44 2 T45 2 T38 1


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4393 1 T244 1 T249 2 T163 2
pkt_types[PidTypeInToken] 58123 1 T31 10 T32 2 T44 4


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1402 1 T119 53 T117 8 T120 27
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 803 1 T408 1 T233 1 T119 41
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 82 1 T410 3 T472 2 T522 1
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 18 1 T142 1 T539 1 T412 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1291 1 T249 2 T119 12 T117 23
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 708 1 T244 1 T408 2 T119 6
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 77 1 T163 2 T605 2 T606 4
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 12 1 T506 1 T483 1 T442 2
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 4043 1 T82 1 T119 153 T117 45
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 2399 1 T119 100 T409 1 T120 102
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 49 1 T431 1 T534 1 T526 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 49 1 T45 1 T499 1 T531 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 42023 1 T31 10 T32 2 T44 2
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2226 1 T44 2 T45 1 T38 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7289 1 T37 1 T5 32 T108 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 45 1 T452 1 T526 1 T501 1

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