Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.92	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	54	2	52	96.30

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	2	52	96.30	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	20594	1			T21	1		T58	1		T4	28
solo	74778	1			T1	1		T31	7		T44	19
empty	4786	1			T3	1		T30	1		T44	1

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	20630	1			T4	28		T5	50		T6	36
solo	34041	1			T3	1		T30	1		T44	20
empty	45562	1			T1	1		T31	7		T34	10

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

out

75884

1

T1

1

T31

7

T44

8

setup

24477

1

T3

1

T30

1

T44

12

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rx

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	55	1			T228	1		T225	1		T305	1
solo	162	1			T33	1		T39	1		T41	1
empty	83510	1			T1	1		T3	1		T30	1

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	2	52	96.30	2

Automatically Generated Cross Bins for cr_fifo_X_pid

Uncovered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER	STATUS
[empty]	[full]	[solo]	[out]	0	1	1
[empty]	[empty]	[full]	[setup]	0	1	1

Covered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	full	full	out	4	1			T230	1		T306	1		T307	1
full	full	full	setup	4	1			T308	1		T309	1		T310	1
full	full	solo	out	3	1			T311	1		T312	1		T313	1
full	full	solo	setup	2	1			T314	1		T315	1		-	-
full	full	empty	out	15774	1			T4	20		T5	39		T6	19
full	full	empty	setup	4744	1			T4	8		T5	11		T6	17
full	solo	full	out	2	1			T316	1		T317	1		-	-
full	solo	full	setup	2	1			T318	1		T319	1		-	-
full	solo	solo	out	5	1			T320	1		T321	1		T322	1
full	solo	solo	setup	3	1			T323	1		T324	1		T325	1
full	solo	empty	out	4	1			T326	1		T327	1		T328	1
full	solo	empty	setup	5	1			T329	1		T330	1		T331	1
full	empty	full	out	4	1			T332	1		T333	1		T334	1
full	empty	full	setup	5	1			T225	1		T335	1		T336	1
full	empty	solo	out	5	1			T337	1		T338	1		T339	1
full	empty	solo	setup	8	1			T59	1		T340	1		T341	1
full	empty	empty	out	3	1			T342	1		T343	1		T344	1
full	empty	empty	setup	7	1			T340	1		T345	1		T346	1
solo	full	full	out	3	1			T228	1		T305	1		T347	1
solo	full	full	setup	3	1			T348	1		T349	1		T350	1
solo	full	solo	out	2	1			T351	1		T352	1		-	-
solo	full	solo	setup	3	1			T353	1		T354	1		T355	1
solo	full	empty	out	8	1			T58	1		T61	1		T356	1
solo	full	empty	setup	2	1			T357	1		T358	1		-	-
solo	solo	full	out	4	1			T359	1		T360	1		T361	1
solo	solo	full	setup	4	1			T362	1		T363	1		T364	1
solo	solo	solo	out	7	1			T58	1		T61	1		T356	1
solo	solo	solo	setup	8	1			T33	1		T58	1		T61	1
solo	solo	empty	out	8613	1			T44	8		T24	1		T249	7
solo	solo	empty	setup	8689	1			T44	11		T24	1		T244	2
solo	empty	full	out	1	1			T365	1		-	-		-	-
solo	empty	full	setup	3	1			T366	1		T367	1		T368	1
solo	empty	solo	out	2	1			T369	1		T370	1		-	-
solo	empty	solo	setup	76	1			T228	1		T225	1		T371	1
solo	empty	empty	out	2	1			T229	1		T372	1		-	-
solo	empty	empty	setup	2046	1			T3	1		T30	1		T44	1
empty	full	full	out	1	1			T373	1		-	-		-	-
empty	full	full	setup	3	1			T374	1		T375	1		T376	1
empty	full	solo	setup	3	1			T377	1		T378	1		T379	1
empty	full	empty	out	6	1			T380	1		T381	1		T382	1
empty	full	empty	setup	4	1			T383	1		T384	1		T385	1
empty	solo	full	out	7	1			T386	1		T387	1		T388	1
empty	solo	full	setup	4	1			T389	1		T390	1		T391	1
empty	solo	solo	out	5	1			T392	1		T393	1		T394	1
empty	solo	solo	setup	4	1			T226	1		T395	1		T396	1
empty	solo	empty	out	43175	1			T1	1		T31	7		T34	10
empty	solo	empty	setup	3	1			T224	1		T397	1		T398	1
empty	empty	full	out	1	1			T399	1		-	-		-	-
empty	empty	solo	out	2	1			T400	1		T401	1		-	-
empty	empty	solo	setup	5	1			T402	1		T403	1		T404	1
empty	empty	empty	out	237	1			T39	1		T41	1		T76	1
empty	empty	empty	setup	149	1			T23	1		T231	1		T405	1