Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	170867	1			T1	3		T2	7		T3	4
all_pins[1]	170867	1			T1	3		T2	7		T3	4
all_pins[2]	170867	1			T1	3		T2	7		T3	4
all_pins[3]	170867	1			T1	3		T2	7		T3	4
all_pins[4]	170867	1			T1	3		T2	7		T3	4
all_pins[5]	170867	1			T1	3		T2	7		T3	4
all_pins[6]	170867	1			T1	3		T2	7		T3	4
all_pins[7]	170867	1			T1	3		T2	7		T3	4
all_pins[8]	170867	1			T1	3		T2	7		T3	4
all_pins[9]	170867	1			T1	3		T2	7		T3	4
all_pins[10]	170867	1			T1	3		T2	7		T3	4
all_pins[11]	170867	1			T1	3		T2	7		T3	4
all_pins[12]	170867	1			T1	3		T2	7		T3	4
all_pins[13]	170867	1			T1	3		T2	7		T3	4
all_pins[14]	170867	1			T1	3		T2	7		T3	4
all_pins[15]	170867	1			T1	3		T2	7		T3	4
all_pins[16]	170867	1			T1	3		T2	7		T3	4
all_pins[17]	170867	1			T1	3		T2	7		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5465592	1			T1	95		T2	222		T3	128
values[0x1]	2152	1			T1	1		T2	2		T30	1
transitions[0x0=>0x1]	1933	1			T1	1		T2	2		T30	1
transitions[0x1=>0x0]	1933	1			T1	1		T2	2		T30	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	170769	1			T1	3		T2	7		T3	4
all_pins[0]	values[0x1]	98	1			T235	1		T406	1		T407	1
all_pins[0]	transitions[0x0=>0x1]	86	1			T235	1		T406	1		T407	1
all_pins[0]	transitions[0x1=>0x0]	863	1			T35	12		T36	1		T54	1
all_pins[1]	values[0x0]	169992	1			T1	3		T2	7		T3	4
all_pins[1]	values[0x1]	875	1			T35	12		T36	1		T54	1
all_pins[1]	transitions[0x0=>0x1]	863	1			T35	12		T36	1		T54	1
all_pins[1]	transitions[0x1=>0x0]	112	1			T42	1		T69	1		T70	1
all_pins[2]	values[0x0]	170743	1			T1	3		T2	7		T3	4
all_pins[2]	values[0x1]	124	1			T42	1		T69	1		T70	1
all_pins[2]	transitions[0x0=>0x1]	108	1			T42	1		T69	1		T70	1
all_pins[2]	transitions[0x1=>0x0]	33	1			T18	1		T209	1		T211	1
all_pins[3]	values[0x0]	170818	1			T1	3		T2	7		T3	4
all_pins[3]	values[0x1]	49	1			T18	1		T209	1		T211	3
all_pins[3]	transitions[0x0=>0x1]	33	1			T18	1		T209	1		T211	3
all_pins[3]	transitions[0x1=>0x0]	32	1			T51	1		T292	1		T290	2
all_pins[4]	values[0x0]	170819	1			T1	3		T2	7		T3	4
all_pins[4]	values[0x1]	48	1			T51	1		T292	1		T290	3
all_pins[4]	transitions[0x0=>0x1]	39	1			T51	1		T292	1		T290	3
all_pins[4]	transitions[0x1=>0x0]	59	1			T210	1		T211	1		T292	2
all_pins[5]	values[0x0]	170799	1			T1	3		T2	7		T3	4
all_pins[5]	values[0x1]	68	1			T210	1		T211	1		T292	2
all_pins[5]	transitions[0x0=>0x1]	64	1			T210	1		T292	2		T290	3
all_pins[5]	transitions[0x1=>0x0]	82	1			T73	1		T74	1		T75	1
all_pins[6]	values[0x0]	170781	1			T1	3		T2	7		T3	4
all_pins[6]	values[0x1]	86	1			T73	1		T74	1		T75	1
all_pins[6]	transitions[0x0=>0x1]	81	1			T73	1		T74	1		T75	1
all_pins[6]	transitions[0x1=>0x0]	41	1			T55	1		T56	1		T57	1
all_pins[7]	values[0x0]	170821	1			T1	3		T2	7		T3	4
all_pins[7]	values[0x1]	46	1			T55	1		T56	1		T57	1
all_pins[7]	transitions[0x0=>0x1]	35	1			T55	1		T56	1		T57	1
all_pins[7]	transitions[0x1=>0x0]	66	1			T59	1		T60	1		T62	1
all_pins[8]	values[0x0]	170790	1			T1	3		T2	7		T3	4
all_pins[8]	values[0x1]	77	1			T59	1		T60	1		T62	1
all_pins[8]	transitions[0x0=>0x1]	68	1			T59	1		T60	1		T62	1
all_pins[8]	transitions[0x1=>0x0]	64	1			T2	2		T67	2		T68	2
all_pins[9]	values[0x0]	170794	1			T1	3		T2	5		T3	4
all_pins[9]	values[0x1]	73	1			T2	2		T67	2		T68	2
all_pins[9]	transitions[0x0=>0x1]	60	1			T2	2		T67	2		T68	2
all_pins[9]	transitions[0x1=>0x0]	54	1			T209	3		T211	3		T294	1
all_pins[10]	values[0x0]	170800	1			T1	3		T2	7		T3	4
all_pins[10]	values[0x1]	67	1			T209	3		T211	3		T294	1
all_pins[10]	transitions[0x0=>0x1]	50	1			T209	3		T211	3		T301	3
all_pins[10]	transitions[0x1=>0x0]	97	1			T19	1		T79	1		T80	1
all_pins[11]	values[0x0]	170753	1			T1	3		T2	7		T3	4
all_pins[11]	values[0x1]	114	1			T19	1		T79	1		T80	1
all_pins[11]	transitions[0x0=>0x1]	100	1			T19	1		T79	1		T80	1
all_pins[11]	transitions[0x1=>0x0]	44	1			T20	1		T83	1		T84	1
all_pins[12]	values[0x0]	170809	1			T1	3		T2	7		T3	4
all_pins[12]	values[0x1]	58	1			T20	1		T83	1		T84	1
all_pins[12]	transitions[0x0=>0x1]	40	1			T20	1		T83	1		T84	1
all_pins[12]	transitions[0x1=>0x0]	99	1			T1	1		T86	1		T87	1
all_pins[13]	values[0x0]	170750	1			T1	2		T2	7		T3	4
all_pins[13]	values[0x1]	117	1			T1	1		T86	1		T87	1
all_pins[13]	transitions[0x0=>0x1]	95	1			T1	1		T86	1		T87	1
all_pins[13]	transitions[0x1=>0x0]	47	1			T209	2		T210	1		T293	2
all_pins[14]	values[0x0]	170798	1			T1	3		T2	7		T3	4
all_pins[14]	values[0x1]	69	1			T209	2		T210	1		T211	2
all_pins[14]	transitions[0x0=>0x1]	52	1			T209	1		T210	1		T211	2
all_pins[14]	transitions[0x1=>0x0]	41	1			T209	1		T210	1		T211	2
all_pins[15]	values[0x0]	170809	1			T1	3		T2	7		T3	4
all_pins[15]	values[0x1]	58	1			T209	2		T210	1		T211	2
all_pins[15]	transitions[0x0=>0x1]	46	1			T209	2		T210	1		T211	1
all_pins[15]	transitions[0x1=>0x0]	67	1			T39	4		T41	4		T76	4
all_pins[16]	values[0x0]	170788	1			T1	3		T2	7		T3	4
all_pins[16]	values[0x1]	79	1			T39	4		T41	4		T76	4
all_pins[16]	transitions[0x0=>0x1]	67	1			T39	4		T41	4		T76	4
all_pins[16]	transitions[0x1=>0x0]	34	1			T30	1		T210	2		T211	1
all_pins[17]	values[0x0]	170821	1			T1	3		T2	7		T3	4
all_pins[17]	values[0x1]	46	1			T30	1		T210	2		T211	1
all_pins[17]	transitions[0x0=>0x1]	46	1			T30	1		T210	2		T211	1