Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4618	1			T45	1		T168	7		T82	3
invalid_ep[0xd]	4649	1			T168	7		T82	1		T116	9
invalid_ep[0xe]	4586	1			T244	1		T168	9		T82	2
invalid_ep[0xf]	4625	1			T45	1		T244	1		T168	18
endpoints[0x0]	14243	1			T1	1		T45	1		T34	1
endpoints[0x1]	15228	1			T44	8		T35	2		T40	2
endpoints[0x2]	13279	1			T44	4		T34	2		T35	2
endpoints[0x3]	11074	1			T30	1		T45	1		T35	2
endpoints[0x4]	13058	1			T3	1		T44	7		T34	1
endpoints[0x5]	14471	1			T44	1		T34	2		T35	2
endpoints[0x6]	11757	1			T32	2		T33	8		T34	1
endpoints[0x7]	13374	1			T44	6		T34	2		T35	2
endpoints[0x8]	11729	1			T45	1		T34	4		T35	2
endpoints[0x9]	16398	1			T31	17		T34	1		T35	2
endpoints[0xa]	12580	1			T44	5		T34	1		T35	2
endpoints[0xb]	14414	1			T44	1		T45	2		T34	5

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	24477	1			T3	1		T30	1		T44	12
pkt_types[PidTypeOutToken]	75884	1			T1	1		T31	7		T44	8
pkt_types[PidTypeInToken]	62237	1			T31	10		T32	2		T44	4

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	989	1			T45	1		T233	1		T119	19
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	979	1			T119	27		T117	9		T120	25
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	997	1			T244	1		T233	1		T119	30
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1011	1			T45	1		T119	25		T117	7
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1656	1			T58	1		T4	2		T244	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1688	1			T24	1		T82	5		T166	2
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1792	1			T44	2		T52	1		T4	2
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1636	1			T30	1		T163	2		T104	4
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1671	1			T3	1		T44	3		T165	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1768	1			T44	1		T5	2		T168	4
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1648	1			T33	8		T93	1		T81	1
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1818	1			T44	3		T81	2		T5	4
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1777	1			T25	1		T6	3		T116	4
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1661	1			T23	1		T4	1		T170	22
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1637	1			T44	2		T50	1		T53	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1749	1			T44	1		T45	1		T4	3
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1614	1			T168	7		T82	3		T116	12
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1605	1			T168	7		T82	1		T116	9
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1517	1			T168	9		T82	2		T116	15
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1575	1			T168	18		T82	4		T116	6
pkt_types[PidTypeOutToken]	endpoints[0x0]	6470	1			T1	1		T35	1		T91	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	7394	1			T44	4		T35	1		T40	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	5516	1			T34	2		T35	1		T78	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	3707	1			T35	1		T39	11		T64	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	5652	1			T44	1		T34	1		T35	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	6624	1			T35	1		T63	1		T162	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	4708	1			T34	1		T35	1		T568	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	5288	1			T34	2		T35	1		T37	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	3921	1			T34	2		T35	1		T41	11
pkt_types[PidTypeOutToken]	endpoints[0x9]	8650	1			T31	7		T34	1		T35	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	4975	1			T44	3		T35	1		T77	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	6668	1			T34	1		T35	1		T76	11
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1005	1			T119	32		T117	8		T120	34
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1038	1			T119	33		T117	9		T120	28
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1027	1			T119	26		T117	10		T120	21
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1044	1			T244	1		T119	28		T117	10
pkt_types[PidTypeInToken]	endpoints[0x0]	4949	1			T45	1		T34	1		T35	1
pkt_types[PidTypeInToken]	endpoints[0x1]	5037	1			T44	1		T35	1		T40	1
pkt_types[PidTypeInToken]	endpoints[0x2]	4804	1			T44	2		T35	1		T52	1
pkt_types[PidTypeInToken]	endpoints[0x3]	4594	1			T35	1		T38	1		T162	1
pkt_types[PidTypeInToken]	endpoints[0x4]	4586	1			T35	1		T164	1		T165	1
pkt_types[PidTypeInToken]	endpoints[0x5]	4955	1			T34	2		T35	1		T63	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4369	1			T32	2		T35	1		T4	5
pkt_types[PidTypeInToken]	endpoints[0x7]	5175	1			T44	1		T35	1		T37	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4857	1			T34	2		T35	1		T25	1
pkt_types[PidTypeInToken]	endpoints[0x9]	4990	1			T31	10		T35	1		T36	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4924	1			T34	1		T35	1		T50	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4883	1			T45	1		T34	4		T35	1