Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	249	1			T209	7		T210	4		T211	7
all_values[1]	249	1			T209	7		T210	4		T211	7
all_values[2]	249	1			T209	7		T210	4		T211	7
all_values[3]	249	1			T209	7		T210	4		T211	7
all_values[4]	249	1			T209	7		T210	4		T211	7
all_values[5]	249	1			T209	7		T210	4		T211	7
all_values[6]	249	1			T209	7		T210	4		T211	7
all_values[7]	249	1			T209	7		T210	4		T211	7
all_values[8]	249	1			T209	7		T210	4		T211	7
all_values[9]	249	1			T209	7		T210	4		T211	7
all_values[10]	249	1			T209	7		T210	4		T211	7
all_values[11]	249	1			T209	7		T210	4		T211	7
all_values[12]	249	1			T209	7		T210	4		T211	7
all_values[13]	249	1			T209	7		T210	4		T211	7
all_values[14]	249	1			T209	7		T210	4		T211	7
all_values[15]	249	1			T209	7		T210	4		T211	7
all_values[16]	249	1			T209	7		T210	4		T211	7
all_values[17]	249	1			T209	7		T210	4		T211	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5984

1

T209

159

T210

97

T211

174

auto[1]

1984

1

T209

65

T210

31

T211

50

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5526

1

T209

157

T210

91

T211

140

auto[1]

2442

1

T209

67

T210

37

T211

84

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4811

1

T209

131

T210

76

T211

127

auto[1]

3157

1

T209

93

T210

52

T211

97

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	66	1			T209	1		T210	3		T211	2
all_values[0]	auto[0]	auto[1]	auto[0]	80	1			T209	3		T211	1		T292	3
all_values[0]	auto[1]	auto[0]	auto[1]	67	1			T209	3		T210	1		T211	1
all_values[0]	auto[1]	auto[1]	auto[1]	36	1			T211	3		T292	1		T290	1
all_values[1]	auto[0]	auto[0]	auto[0]	82	1			T209	1		T210	1		T211	2
all_values[1]	auto[0]	auto[1]	auto[0]	58	1			T209	1		T210	1		T211	1
all_values[1]	auto[1]	auto[0]	auto[1]	68	1			T209	4		T210	1		T211	2
all_values[1]	auto[1]	auto[1]	auto[1]	41	1			T209	1		T210	1		T211	2
all_values[2]	auto[0]	auto[0]	auto[0]	58	1			T209	2		T211	1		T293	2
all_values[2]	auto[0]	auto[0]	auto[1]	40	1			T209	2		T211	2		T292	1
all_values[2]	auto[0]	auto[1]	auto[0]	23	1			T209	2		T211	1		T294	1
all_values[2]	auto[0]	auto[1]	auto[1]	33	1			T210	2		T211	1		T292	1
all_values[2]	auto[1]	auto[0]	auto[1]	49	1			T210	2		T211	1		T292	1
all_values[2]	auto[1]	auto[1]	auto[1]	46	1			T209	1		T211	1		T292	1
all_values[3]	auto[0]	auto[0]	auto[0]	79	1			T209	3		T210	1		T292	4
all_values[3]	auto[0]	auto[0]	auto[1]	16	1			T211	1		T295	1		T296	1
all_values[3]	auto[0]	auto[1]	auto[0]	46	1			T209	1		T210	2		T293	2
all_values[3]	auto[0]	auto[1]	auto[1]	17	1			T211	1		T297	1		T298	1
all_values[3]	auto[1]	auto[0]	auto[1]	53	1			T211	4		T293	1		T290	2
all_values[3]	auto[1]	auto[1]	auto[1]	38	1			T209	3		T210	1		T211	1
all_values[4]	auto[0]	auto[0]	auto[0]	65	1			T209	2		T210	3		T211	2
all_values[4]	auto[0]	auto[0]	auto[1]	28	1			T209	1		T290	3		T299	1
all_values[4]	auto[0]	auto[1]	auto[0]	49	1			T209	2		T210	1		T211	1
all_values[4]	auto[0]	auto[1]	auto[1]	19	1			T292	1		T290	1		T294	1
all_values[4]	auto[1]	auto[0]	auto[1]	47	1			T209	1		T211	4		T293	1
all_values[4]	auto[1]	auto[1]	auto[1]	41	1			T209	1		T292	1		T290	1
all_values[5]	auto[0]	auto[0]	auto[0]	45	1			T209	3		T290	1		T300	2
all_values[5]	auto[0]	auto[0]	auto[1]	30	1			T209	2		T210	2		T211	2
all_values[5]	auto[0]	auto[1]	auto[0]	44	1			T211	2		T292	2		T293	2
all_values[5]	auto[0]	auto[1]	auto[1]	31	1			T292	1		T290	2		T301	1
all_values[5]	auto[1]	auto[0]	auto[1]	50	1			T209	1		T210	1		T211	3
all_values[5]	auto[1]	auto[1]	auto[1]	49	1			T209	1		T210	1		T292	1
all_values[6]	auto[0]	auto[0]	auto[0]	62	1			T209	2		T293	4		T290	1
all_values[6]	auto[0]	auto[0]	auto[1]	28	1			T211	2		T292	1		T290	1
all_values[6]	auto[0]	auto[1]	auto[0]	53	1			T209	1		T210	2		T211	1
all_values[6]	auto[0]	auto[1]	auto[1]	18	1			T211	1		T299	1		T294	1
all_values[6]	auto[1]	auto[0]	auto[1]	55	1			T210	1		T211	2		T292	1
all_values[6]	auto[1]	auto[1]	auto[1]	33	1			T209	4		T210	1		T211	1
all_values[7]	auto[0]	auto[0]	auto[0]	81	1			T209	1		T210	1		T211	1
all_values[7]	auto[0]	auto[1]	auto[0]	76	1			T210	1		T211	3		T293	2
all_values[7]	auto[1]	auto[0]	auto[1]	53	1			T209	4		T210	2		T211	2
all_values[7]	auto[1]	auto[1]	auto[1]	39	1			T209	2		T211	1		T293	2
all_values[8]	auto[0]	auto[0]	auto[0]	77	1			T210	1		T211	1		T292	1
all_values[8]	auto[0]	auto[1]	auto[0]	55	1			T209	3		T211	1		T292	1
all_values[8]	auto[1]	auto[0]	auto[1]	70	1			T209	1		T210	2		T211	3
all_values[8]	auto[1]	auto[1]	auto[1]	47	1			T209	3		T210	1		T211	2
all_values[9]	auto[0]	auto[0]	auto[0]	55	1			T209	2		T211	4		T292	2
all_values[9]	auto[0]	auto[0]	auto[1]	18	1			T211	1		T292	1		T290	1
all_values[9]	auto[0]	auto[1]	auto[0]	54	1			T209	2		T210	2		T290	2
all_values[9]	auto[0]	auto[1]	auto[1]	30	1			T211	1		T293	1		T290	1
all_values[9]	auto[1]	auto[0]	auto[1]	59	1			T209	1		T210	1		T211	1
all_values[9]	auto[1]	auto[1]	auto[1]	33	1			T209	2		T210	1		T293	1
all_values[10]	auto[0]	auto[0]	auto[0]	59	1			T209	1		T210	3		T211	1
all_values[10]	auto[0]	auto[0]	auto[1]	26	1			T211	1		T292	1		T290	1
all_values[10]	auto[0]	auto[1]	auto[0]	28	1			T209	2		T292	2		T293	1
all_values[10]	auto[0]	auto[1]	auto[1]	28	1			T209	2		T211	1		T301	2
all_values[10]	auto[1]	auto[0]	auto[1]	61	1			T209	1		T210	1		T211	1
all_values[10]	auto[1]	auto[1]	auto[1]	47	1			T209	1		T211	3		T293	1
all_values[11]	auto[0]	auto[0]	auto[0]	59	1			T210	1		T211	2		T292	4
all_values[11]	auto[0]	auto[0]	auto[1]	19	1			T211	1		T297	1		T302	1
all_values[11]	auto[0]	auto[1]	auto[0]	39	1			T209	1		T210	2		T211	1
all_values[11]	auto[0]	auto[1]	auto[1]	32	1			T209	1		T211	1		T290	3
all_values[11]	auto[1]	auto[0]	auto[1]	60	1			T209	3		T211	2		T290	2
all_values[11]	auto[1]	auto[1]	auto[1]	40	1			T209	2		T210	1		T293	2
all_values[12]	auto[0]	auto[0]	auto[0]	65	1			T210	3		T211	2		T290	3
all_values[12]	auto[0]	auto[0]	auto[1]	25	1			T209	1		T211	2		T299	1
all_values[12]	auto[0]	auto[1]	auto[0]	40	1			T209	4		T210	1		T292	3
all_values[12]	auto[0]	auto[1]	auto[1]	22	1			T294	1		T303	3		T296	1
all_values[12]	auto[1]	auto[0]	auto[1]	53	1			T209	2		T211	1		T290	1
all_values[12]	auto[1]	auto[1]	auto[1]	44	1			T211	2		T292	1		T293	2
all_values[13]	auto[0]	auto[0]	auto[0]	50	1			T209	1		T210	1		T211	2
all_values[13]	auto[0]	auto[0]	auto[1]	25	1			T210	1		T292	1		T299	1
all_values[13]	auto[0]	auto[1]	auto[0]	38	1			T209	1		T210	1		T211	2
all_values[13]	auto[0]	auto[1]	auto[1]	30	1			T211	2		T299	1		T303	2
all_values[13]	auto[1]	auto[0]	auto[1]	53	1			T209	3		T292	1		T293	1
all_values[13]	auto[1]	auto[1]	auto[1]	53	1			T209	2		T210	1		T211	1
all_values[14]	auto[0]	auto[0]	auto[0]	57	1			T211	1		T292	2		T293	1
all_values[14]	auto[0]	auto[0]	auto[1]	27	1			T211	3		T292	1		T290	1
all_values[14]	auto[0]	auto[1]	auto[0]	43	1			T209	1		T210	1		T294	3
all_values[14]	auto[0]	auto[1]	auto[1]	28	1			T209	1		T211	1		T293	1
all_values[14]	auto[1]	auto[0]	auto[1]	48	1			T209	3		T210	1		T211	1
all_values[14]	auto[1]	auto[1]	auto[1]	46	1			T209	2		T210	2		T211	1
all_values[15]	auto[0]	auto[0]	auto[0]	73	1			T209	2		T210	1		T292	2
all_values[15]	auto[0]	auto[0]	auto[1]	18	1			T210	1		T211	1		T301	1
all_values[15]	auto[0]	auto[1]	auto[0]	43	1			T209	2		T211	2		T292	2
all_values[15]	auto[0]	auto[1]	auto[1]	21	1			T209	1		T293	1		T294	1
all_values[15]	auto[1]	auto[0]	auto[1]	48	1			T210	1		T211	2		T290	1
all_values[15]	auto[1]	auto[1]	auto[1]	46	1			T209	2		T210	1		T211	2
all_values[16]	auto[0]	auto[0]	auto[0]	40	1			T209	3		T210	1		T211	1
all_values[16]	auto[0]	auto[0]	auto[1]	40	1			T210	1		T211	2		T290	1
all_values[16]	auto[0]	auto[1]	auto[0]	39	1			T209	4		T292	4		T294	1
all_values[16]	auto[0]	auto[1]	auto[1]	27	1			T211	1		T304	1		T295	1
all_values[16]	auto[1]	auto[0]	auto[1]	55	1			T211	2		T290	2		T299	2
all_values[16]	auto[1]	auto[1]	auto[1]	48	1			T210	2		T211	1		T293	2
all_values[17]	auto[0]	auto[0]	auto[0]	92	1			T209	2		T211	2		T293	3
all_values[17]	auto[0]	auto[1]	auto[0]	67	1			T209	3		T210	1		T211	2
all_values[17]	auto[1]	auto[0]	auto[1]	44	1			T209	2		T210	2		T211	2
all_values[17]	auto[1]	auto[1]	auto[1]	46	1			T210	1		T211	1		T292	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal