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 LINE       8941
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30,T44,T33
1	1	0	Not Covered
1	1	1	Covered	T30,T44,T33

 LINE       8942
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T31
1	1	0	Covered	T236,T242,T252
1	1	1	Covered	T1,T2,T31

 LINE       8945
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T30,T44
1	1	0	Covered	T202,T242,T253
1	1	1	Covered	T3,T30,T44

 LINE       8948
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T31,T34
1	1	0	Not Covered
1	1	1	Covered	T3,T31,T34

 LINE       8949
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T30,T44
1	1	0	Covered	T202,T242,T250
1	1	1	Covered	T3,T30,T44

 LINE       8974
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T31,T42
1	1	0	Covered	T202,T236,T250
1	1	1	Covered	T1,T31,T42

 LINE       8999
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T44,T45,T131
1	1	0	Covered	T202,T242,T250
1	1	1	Covered	T44,T45,T131

 LINE       9024
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T35,T36
1	1	0	Covered	T202,T236,T242
1	1	1	Covered	T32,T35,T36

 LINE       9049
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T44,T45,T35
1	1	0	Covered	T202,T236,T242
1	1	1	Covered	T44,T45,T78

 LINE       9074
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T44,T45,T38
1	1	0	Covered	T202,T236,T242
1	1	1	Covered	T44,T45,T38

 LINE       9099
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T45,T34,T35
1	1	0	Covered	T202,T236,T242
1	1	1	Covered	T45,T34,T35

 LINE       9110
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T44,T35,T40
1	1	0	Covered	T202,T250,T254
1	1	1	Covered	T44,T35,T40

 LINE       9121
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T44,T35,T52
1	1	0	Covered	T236,T242,T250
1	1	1	Covered	T44,T35,T52

 LINE       9132
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T35,T38,T4
1	1	0	Covered	T202,T236,T250
1	1	1	Covered	T35,T38,T162

 LINE       9143
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T35,T164,T165
1	1	0	Covered	T202,T236,T250
1	1	1	Covered	T35,T164,T165

 LINE       9154
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T35,T63
1	1	0	Covered	T202,T236,T250
1	1	1	Covered	T34,T35,T63

 LINE       9165
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T35,T93
1	1	0	Covered	T202,T236,T250
1	1	1	Covered	T32,T35,T93

 LINE       9176
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T44,T35,T37
1	1	0	Covered	T202,T236,T242
1	1	1	Covered	T44,T35,T37

 LINE       9187
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T35,T25
1	1	0	Covered	T236,T242,T250
1	1	1	Covered	T34,T35,T25

 LINE       9198
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T35,T36
1	1	0	Covered	T236,T242,T250
1	1	1	Covered	T31,T35,T36

 LINE       9209
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T35,T50
1	1	0	Covered	T202,T236,T253
1	1	1	Covered	T34,T35,T50

 LINE       9220
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T45,T34,T35
1	1	0	Covered	T202,T254,T251
1	1	1	Covered	T45,T34,T35

 LINE       9231
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T44,T45,T92
1	1	0	Covered	T202,T254,T251
1	1	1	Covered	T44,T45,T92

 LINE       9256
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T44,T45,T37
1	1	0	Covered	T202,T236,T242
1	1	1	Covered	T44,T45,T37

 LINE       9281
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T34,T39
1	1	0	Not Covered
1	1	1	Covered	T34,T64,T115

 LINE       9282
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T34,T39
1	1	0	Covered	T202,T236,T242
1	1	1	Covered	T31,T34,T39

 LINE       9287
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T32,T33
1	1	0	Not Covered
1	1	1	Covered	T32,T34,T64

 LINE       9288
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T32,T33
1	1	0	Covered	T202,T236,T242
1	1	1	Covered	T31,T34,T111

 LINE       9293
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T43,T29,T218
1	1	0	Not Covered
1	1	1	Covered	T43,T29,T218

 LINE       9294
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T223,T5
1	1	0	Covered	T202,T236,T250
1	1	1	Covered	T29,T26,T27

 LINE       9313
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T202,T236,T242
1	1	1	Covered	T1,T2,T3

 LINE       9326
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T235,T7,T8
1	1	0	Covered	T202,T236,T242
1	1	1	Covered	T7,T8,T9

 LINE       9329
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T44,T33,T45
1	1	0	Covered	T202,T242,T250
1	1	1	Covered	T44,T45,T34

 LINE       9336
 EXPRESSION (addr_hit[39] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T10,T163
1	1	0	Covered	T255
1	1	1	Covered	T214,T212,T201

 LINE       9337
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T10,T163
1	1	0	Covered	T202,T236,T242
1	1	1	Covered	T214,T201,T237

 LINE       9350
 EXPRESSION (addr_hit[40] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T163,T116
1	1	0	Not Covered
1	1	1	Covered	T214,T212,T201

 LINE       9351
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T163,T116
1	1	0	Covered	T202,T236,T242
1	1	1	Covered	T214,T212,T201

 LINE       9362
 EXPRESSION (addr_hit[41] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T223,T5,T163
1	1	0	Not Covered
1	1	1	Covered	T214,T212,T201

 LINE       9363
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T223,T5,T163
1	1	0	Covered	T202,T242,T256
1	1	1	Covered	T214,T212,T201

 LINE       9368
 EXPRESSION (addr_hit[42] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T5,T163
1	1	0	Not Covered
1	1	1	Covered	T214,T212,T201

 LINE       9369
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T5,T163
1	1	0	Covered	T202,T242,T250
1	1	1	Covered	T214,T212,T201

 LINE       9881
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T7,T8,T9