e3fb01b5e
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 17.986m | 5.554ms | 5 | 5 | 100.00 |
V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 17.986m | 5.554ms | 5 | 5 | 100.00 |
chip_sw_uart_tx_rx_idx1 | 15.703m | 5.782ms | 5 | 5 | 100.00 | ||
chip_sw_uart_tx_rx_idx2 | 15.767m | 5.992ms | 5 | 5 | 100.00 | ||
chip_sw_uart_tx_rx_idx3 | 17.924m | 5.672ms | 5 | 5 | 100.00 | ||
V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 1.041h | 23.023ms | 20 | 20 | 100.00 |
V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 36.776m | 13.160ms | 5 | 5 | 100.00 |
chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 26.870m | 14.155ms | 5 | 5 | 100.00 | ||
V1 | chip_sw_gpio_out | chip_sw_gpio | 8.433m | 4.030ms | 3 | 3 | 100.00 |
V1 | chip_sw_gpio_in | chip_sw_gpio | 8.433m | 4.030ms | 3 | 3 | 100.00 |
V1 | chip_sw_gpio_irq | chip_sw_gpio | 8.433m | 4.030ms | 3 | 3 | 100.00 |
V1 | chip_sw_example_tests | chip_sw_example_flash | 3.936m | 2.584ms | 3 | 3 | 100.00 |
chip_sw_example_rom | 2.252m | 2.282ms | 3 | 3 | 100.00 | ||
chip_sw_example_manufacturer | 4.160m | 2.627ms | 3 | 3 | 100.00 | ||
chip_sw_example_concurrency | 3.948m | 2.609ms | 3 | 3 | 100.00 | ||
chip_sw_uart_smoketest_signed | 33.242m | 8.907ms | 3 | 3 | 100.00 | ||
V1 | csr_hw_reset | chip_csr_hw_reset | 6.597m | 7.474ms | 5 | 5 | 100.00 |
V1 | csr_rw | chip_csr_rw | 8.891m | 5.760ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | chip_csr_bit_bash | 21.614m | 13.638ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | chip_csr_aliasing | 2.712h | 61.774ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 7.332m | 8.437ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.712h | 61.774ms | 5 | 5 | 100.00 |
chip_csr_rw | 8.891m | 5.760ms | 20 | 20 | 100.00 | ||
V1 | xbar_smoke | xbar_smoke | 11.270s | 239.260us | 100 | 100 | 100.00 |
V1 | TOTAL | 223 | 223 | 100.00 | |||
V2 | chip_sw_spi_device_tx_rx | chip_sw_spi_device_tx_rx | 8.184m | 3.277ms | 3 | 3 | 100.00 |
V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 3.029h | 69.902ms | 3 | 3 | 100.00 |
V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 12.179m | 6.451ms | 3 | 3 | 100.00 |
V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 10.035m | 4.410ms | 3 | 3 | 100.00 |
V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 7.293m | 3.187ms | 3 | 3 | 100.00 |
V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 4.218m | 2.532ms | 3 | 3 | 100.00 |
V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 11.312m | 4.956ms | 3 | 3 | 100.00 |
chip_sw_i2c_host_tx_rx_idx1 | 11.223m | 4.090ms | 3 | 3 | 100.00 | ||
chip_sw_i2c_host_tx_rx_idx2 | 8.559m | 3.856ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 10.397m | 3.789ms | 3 | 3 | 100.00 |
V2 | chip_sw_usbdev_dpi | chip_sw_usbdev_dpi | 26.593m | 7.573ms | 1 | 1 | 100.00 |
V2 | chip_pin_mux | chip_padctrl_attributes | 5.395m | 5.468ms | 10 | 10 | 100.00 |
V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.395m | 5.468ms | 10 | 10 | 100.00 |
V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.228m | 2.916ms | 3 | 3 | 100.00 |
V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 7.810m | 5.365ms | 3 | 3 | 100.00 |
V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 5.901m | 4.241ms | 3 | 3 | 100.00 |
V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 17.198m | 11.083ms | 5 | 5 | 100.00 |
chip_tap_straps_testunlock0 | 10.200m | 6.723ms | 5 | 5 | 100.00 | ||
chip_tap_straps_rma | 7.836m | 6.034ms | 5 | 5 | 100.00 | ||
chip_tap_straps_prod | 20.956m | 12.919ms | 5 | 5 | 100.00 | ||
V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 4.529m | 2.613ms | 3 | 3 | 100.00 |
V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 20.341m | 7.486ms | 3 | 3 | 100.00 |
V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 12.111m | 5.293ms | 6 | 6 | 100.00 |
V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 12.111m | 5.293ms | 6 | 6 | 100.00 |
V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 17.848m | 10.068ms | 3 | 3 | 100.00 |
V2 | chip_jtag_mem_access | chip_jtag_mem_access | 24.187m | 13.072ms | 3 | 3 | 100.00 |
V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 6.054m | 4.060ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 8.604m | 4.523ms | 3 | 3 | 100.00 |
V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 7.959m | 4.268ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 7.836m | 6.034ms | 5 | 5 | 100.00 |
V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 7.602m | 12.282ms | 3 | 3 | 100.00 |
V2 | chip_sw_timer | chip_sw_rv_timer_irq | 4.580m | 2.856ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 6.807m | 4.177ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 7.222m | 5.059ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 6.807m | 4.177ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 10.702m | 5.029ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.435m | 7.882ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.435m | 7.882ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 8.040m | 6.338ms | 5 | 5 | 100.00 |
V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs | 28.329m | 8.854ms | 3 | 3 | 100.00 |
V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.124m | 3.466ms | 3 | 3 | 100.00 |
V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 11.510m | 6.475ms | 3 | 3 | 100.00 |
chip_sw_aes_idle | 5.053m | 2.693ms | 3 | 3 | 100.00 | ||
chip_sw_hmac_enc_idle | 4.192m | 2.970ms | 3 | 3 | 100.00 | ||
chip_sw_kmac_idle | 5.107m | 2.647ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 7.437m | 4.703ms | 3 | 3 | 100.00 |
chip_sw_clkmgr_off_hmac_trans | 8.520m | 4.361ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_off_kmac_trans | 8.488m | 4.894ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_off_otbn_trans | 7.574m | 4.616ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 25.655m | 9.669ms | 3 | 3 | 100.00 |
V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_lc | 15.869m | 13.713ms | 3 | 3 | 100.00 |
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.463m | 4.152ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.512m | 4.691ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 9.978m | 3.952ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.537m | 5.036ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.350m | 4.099ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.171m | 5.002ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 15.869m | 13.713ms | 3 | 3 | 100.00 |
V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.463m | 4.152ms | 3 | 3 | 100.00 |
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.512m | 4.691ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 9.978m | 3.952ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.537m | 5.036ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.350m | 4.099ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.171m | 5.002ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 14.546m | 4.996ms | 3 | 3 | 100.00 |
chip_sw_flash_ctrl_access_jitter_en | 20.656m | 6.324ms | 3 | 3 | 100.00 | ||
chip_sw_otbn_ecdsa_op_irq_jitter_en | 54.730m | 21.912ms | 3 | 3 | 100.00 | ||
chip_sw_aes_enc_jitter_en | 4.502m | 3.229ms | 3 | 3 | 100.00 | ||
chip_sw_edn_entropy_reqs_jitter | 19.473m | 5.397ms | 3 | 3 | 100.00 | ||
chip_sw_hmac_enc_jitter_en | 4.822m | 3.179ms | 3 | 3 | 100.00 | ||
chip_sw_keymgr_key_derivation_jitter_en | 7.603m | 5.458ms | 3 | 3 | 100.00 | ||
chip_sw_kmac_mode_kmac_jitter_en | 5.692m | 2.972ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.490m | 3.960ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_jitter | 4.188m | 2.411ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.074m | 3.364ms | 3 | 3 | 100.00 |
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 15.214m | 6.642ms | 3 | 3 | 100.00 | ||
chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 22.275m | 7.660ms | 3 | 3 | 100.00 | ||
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 59.946m | 28.636ms | 3 | 3 | 100.00 | ||
chip_sw_aes_enc_jitter_en_reduced_freq | 5.421m | 3.298ms | 3 | 3 | 100.00 | ||
chip_sw_hmac_enc_jitter_en_reduced_freq | 4.739m | 3.119ms | 3 | 3 | 100.00 | ||
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 8.154m | 4.683ms | 3 | 3 | 100.00 | ||
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.153m | 2.545ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 8.482m | 4.862ms | 3 | 3 | 100.00 | ||
chip_sw_flash_init_reduced_freq | 33.474m | 23.767ms | 3 | 3 | 100.00 | ||
chip_sw_csrng_edn_concurrency_reduced_freq | 47.966m | 18.053ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 14.912m | 5.562ms | 3 | 3 | 100.00 |
V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 9.460m | 4.386ms | 3 | 3 | 100.00 |
V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 7.699m | 3.083ms | 3 | 3 | 100.00 |
V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 13.155m | 5.048ms | 100 | 100 | 100.00 |
V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 10.474m | 9.089ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 24.812m | 20.774ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 7.222m | 6.964ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 14.435m | 7.882ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 22.672m | 21.275ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 34.814m | 22.203ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 30.284m | 16.948ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 9.728m | 4.461ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 10.474m | 9.089ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 6.492m | 4.272ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 46.730m | 37.798ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 10.105m | 7.731ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 7.758m | 4.201ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 53.894m | 35.734ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 19.008m | 8.102ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 37.643m | 29.895ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 4.587m | 3.502ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 13.155m | 5.048ms | 100 | 100 | 100.00 |
V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 7.222m | 5.059ms | 3 | 3 | 100.00 |
V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 6.054m | 4.060ms | 3 | 3 | 100.00 |
V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 10.733m | 5.685ms | 3 | 3 | 100.00 |
V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 8.300m | 3.553ms | 3 | 3 | 100.00 |
V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 28.221m | 12.092ms | 3 | 3 | 100.00 |
V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 5.247m | 2.957ms | 3 | 3 | 100.00 |
V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 13.155m | 5.048ms | 100 | 100 | 100.00 |
V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 4.653m | 3.284ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.783m | 4.781ms | 3 | 3 | 100.00 |
V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 13.155m | 5.048ms | 100 | 100 | 100.00 |
V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 28.329m | 8.854ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 5.692m | 3.259ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 28.221m | 12.092ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 8.451m | 4.824ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.899m | 4.150ms | 90 | 90 | 100.00 |
V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 27.546m | 11.597ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 23.721m | 7.280ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 30.789m | 8.651ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.301h | 255.936ms | 3 | 3 | 100.00 |
V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.783m | 4.781ms | 3 | 3 | 100.00 |
V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 17.198m | 11.083ms | 5 | 5 | 100.00 |
chip_tap_straps_rma | 7.836m | 6.034ms | 5 | 5 | 100.00 | ||
chip_tap_straps_prod | 20.956m | 12.919ms | 5 | 5 | 100.00 | ||
V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 6.119m | 3.136ms | 3 | 3 | 100.00 |
V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 16.336m | 9.052ms | 15 | 15 | 100.00 |
V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 16.336m | 9.052ms | 15 | 15 | 100.00 |
V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 16.336m | 9.052ms | 15 | 15 | 100.00 |
V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 9.650m | 5.113ms | 3 | 3 | 100.00 |
V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 10.433m | 5.687ms | 3 | 3 | 100.00 |
chip_sw_flash_rma_unlocked | 1.240h | 44.575ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 9.684m | 4.445ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_lc_signals_dev | 18.384m | 8.074ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_lc_signals_prod | 21.513m | 6.993ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_lc_signals_rma | 22.780m | 9.406ms | 3 | 3 | 100.00 | ||
chip_sw_lc_ctrl_transition | 16.336m | 9.052ms | 15 | 15 | 100.00 | ||
chip_sw_keymgr_key_derivation | 10.601m | 5.021ms | 3 | 3 | 100.00 | ||
chip_sw_rom_ctrl_integrity_check | 9.905m | 9.452ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_execution_main | 13.030m | 6.747ms | 3 | 3 | 100.00 | ||
chip_prim_tl_access | 7.474m | 11.499ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_lc | 15.869m | 13.713ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.463m | 4.152ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.512m | 4.691ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 9.978m | 3.952ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.537m | 5.036ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.350m | 4.099ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.171m | 5.002ms | 3 | 3 | 100.00 | ||
chip_tap_straps_dev | 17.198m | 11.083ms | 5 | 5 | 100.00 | ||
chip_tap_straps_rma | 7.836m | 6.034ms | 5 | 5 | 100.00 | ||
chip_tap_straps_prod | 20.956m | 12.919ms | 5 | 5 | 100.00 | ||
chip_rv_dm_lc_disabled | 7.602m | 12.282ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 5.210m | 3.598ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 7.921m | 3.434ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 11.244m | 3.947ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 29.142m | 22.984ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_reset | chip_sw_sysrst_ctrl_reset | 29.142m | 22.984ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 29.142m | 22.984ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 49.319m | 20.607ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 49.319m | 20.607ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 10.052m | 6.017ms | 3 | 3 | 100.00 |
chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.155m | 18.777ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.155m | 18.777ms | 3 | 3 | 100.00 |
V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.155m | 18.777ms | 3 | 3 | 100.00 |
V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.329m | 3.303ms | 3 | 3 | 100.00 |
chip_sw_aes_enc_jitter_en | 4.502m | 3.229ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.261m | 3.006ms | 3 | 3 | 100.00 |
V2 | chip_sw_aes_idle | chip_sw_aes_idle | 5.053m | 2.693ms | 3 | 3 | 100.00 |
V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 11.245m | 5.120ms | 3 | 3 | 100.00 |
V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 4.984m | 3.122ms | 3 | 3 | 100.00 |
chip_sw_hmac_enc_jitter_en | 4.822m | 3.179ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.192m | 2.970ms | 3 | 3 | 100.00 |
V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 3.692m | 3.111ms | 3 | 3 | 100.00 |
chip_sw_kmac_mode_kmac | 5.514m | 2.988ms | 3 | 3 | 100.00 | ||
chip_sw_kmac_mode_kmac_jitter_en | 5.692m | 2.972ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 10.601m | 5.021ms | 3 | 3 | 100.00 |
V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 16.336m | 9.052ms | 15 | 15 | 100.00 |
V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 3.706m | 2.166ms | 3 | 3 | 100.00 |
V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.233m | 2.968ms | 3 | 3 | 100.00 |
V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 5.107m | 2.647ms | 3 | 3 | 100.00 |
V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 5.053m | 3.133ms | 3 | 3 | 100.00 |
V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 22.351m | 7.699ms | 3 | 3 | 100.00 |
V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 13.283m | 5.146ms | 3 | 3 | 100.00 |
V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.243m | 3.084ms | 3 | 3 | 100.00 |
V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 22.351m | 7.699ms | 3 | 3 | 100.00 |
V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 9.088m | 4.962ms | 3 | 3 | 100.00 |
V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 11.848m | 7.267ms | 3 | 3 | 100.00 |
V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 4.431m | 3.016ms | 3 | 3 | 100.00 |
V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 38.084m | 11.153ms | 3 | 3 | 100.00 |
chip_sw_edn_entropy_reqs | 19.367m | 5.859ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 10.601m | 5.021ms | 3 | 3 | 100.00 |
chip_sw_keymgr_key_derivation_jitter_en | 7.603m | 5.458ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 9.574m | 4.294ms | 3 | 3 | 100.00 |
V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 11.245m | 5.120ms | 3 | 3 | 100.00 |
V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 45.831m | 9.675ms | 3 | 3 | 100.00 |
V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 53.040m | 19.867ms | 3 | 3 | 100.00 |
chip_sw_otbn_ecdsa_op_irq_jitter_en | 54.730m | 21.912ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 11.510m | 6.475ms | 3 | 3 | 100.00 |
V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 11.510m | 6.475ms | 3 | 3 | 100.00 |
V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 11.510m | 6.475ms | 3 | 3 | 100.00 |
V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 8.571m | 3.361ms | 3 | 3 | 100.00 |
V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 9.905m | 9.452ms | 3 | 3 | 100.00 |
V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 9.905m | 9.452ms | 3 | 3 | 100.00 |
V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 9.696m | 4.415ms | 3 | 3 | 100.00 |
chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.490m | 3.960ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 22.009m | 13.120ms | 3 | 3 | 100.00 |
V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 13.030m | 6.747ms | 3 | 3 | 100.00 |
V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 13.155m | 5.048ms | 100 | 100 | 100.00 |
chip_sw_data_integrity_escalation | 12.111m | 5.293ms | 6 | 6 | 100.00 | ||
V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 16.336m | 9.052ms | 15 | 15 | 100.00 |
V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 40.084m | 22.936ms | 3 | 3 | 100.00 |
chip_sw_otbn_mem_scramble | 8.571m | 3.361ms | 3 | 3 | 100.00 | ||
chip_sw_keymgr_key_derivation | 10.601m | 5.021ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_scrambled_access | 9.696m | 4.415ms | 3 | 3 | 100.00 | ||
chip_sw_rv_core_ibex_icache_invalidate | 3.852m | 2.403ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 40.084m | 22.936ms | 3 | 3 | 100.00 |
chip_sw_otbn_mem_scramble | 8.571m | 3.361ms | 3 | 3 | 100.00 | ||
chip_sw_keymgr_key_derivation | 10.601m | 5.021ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_scrambled_access | 9.696m | 4.415ms | 3 | 3 | 100.00 | ||
chip_sw_rv_core_ibex_icache_invalidate | 3.852m | 2.403ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 16.336m | 9.052ms | 15 | 15 | 100.00 |
V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 7.801m | 4.652ms | 3 | 3 | 100.00 |
V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 6.119m | 3.136ms | 3 | 3 | 100.00 |
V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 9.684m | 4.445ms | 3 | 3 | 100.00 |
chip_sw_otp_ctrl_lc_signals_dev | 18.384m | 8.074ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_lc_signals_prod | 21.513m | 6.993ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_lc_signals_rma | 22.780m | 9.406ms | 3 | 3 | 100.00 | ||
chip_sw_lc_ctrl_transition | 16.336m | 9.052ms | 15 | 15 | 100.00 | ||
chip_prim_tl_access | 7.474m | 11.499ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 7.474m | 11.499ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_init | chip_sw_flash_init | 40.084m | 22.936ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 16.434m | 5.827ms | 3 | 3 | 100.00 |
chip_sw_flash_ctrl_access_jitter_en | 20.656m | 6.324ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 15.225m | 4.619ms | 3 | 3 | 100.00 |
chip_sw_flash_ctrl_ops_jitter_en | 14.546m | 4.996ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.240h | 44.575ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_scramble | chip_sw_flash_init | 40.084m | 22.936ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.940m | 3.438ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 10.601m | 5.021ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 10.433m | 5.687ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.240h | 44.575ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 10.433m | 5.687ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 10.433m | 5.687ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 10.433m | 5.687ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 10.433m | 5.687ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 13.155m | 5.048ms | 100 | 100 | 100.00 |
V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 7.474m | 11.499ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 17.551m | 5.667ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 13.053m | 4.962ms | 3 | 3 | 100.00 |
V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 14.912m | 5.562ms | 3 | 3 | 100.00 |
V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 11.832m | 11.098ms | 3 | 3 | 100.00 |
V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 14.546m | 4.996ms | 3 | 3 | 100.00 |
chip_sw_flash_ctrl_access_jitter_en | 20.656m | 6.324ms | 3 | 3 | 100.00 | ||
chip_sw_otbn_ecdsa_op_irq_jitter_en | 54.730m | 21.912ms | 3 | 3 | 100.00 | ||
chip_sw_aes_enc_jitter_en | 4.502m | 3.229ms | 3 | 3 | 100.00 | ||
chip_sw_edn_entropy_reqs_jitter | 19.473m | 5.397ms | 3 | 3 | 100.00 | ||
chip_sw_hmac_enc_jitter_en | 4.822m | 3.179ms | 3 | 3 | 100.00 | ||
chip_sw_keymgr_key_derivation_jitter_en | 7.603m | 5.458ms | 3 | 3 | 100.00 | ||
chip_sw_kmac_mode_kmac_jitter_en | 5.692m | 2.972ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.490m | 3.960ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_jitter | 4.188m | 2.411ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 4.438m | 3.147ms | 1 | 1 | 100.00 |
V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 30.132m | 11.464ms | 5 | 5 | 100.00 |
V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 30.132m | 11.464ms | 5 | 5 | 100.00 |
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.049m | 4.898ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.886m | 3.269ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.049m | 4.898ms | 3 | 3 | 100.00 |
V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 13.376m | 4.516ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 15.962m | 5.495ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 5.062m | 3.505ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 3.852m | 2.403ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 10.733m | 5.685ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 10.733m | 5.685ms | 3 | 3 | 100.00 |
V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 3.784m | 2.438ms | 3 | 3 | 100.00 |
chip_sw_aes_smoketest | 4.763m | 3.102ms | 3 | 3 | 100.00 | ||
chip_sw_aon_timer_smoketest | 4.826m | 3.434ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_smoketest | 3.993m | 2.948ms | 3 | 3 | 100.00 | ||
chip_sw_csrng_smoketest | 4.308m | 3.226ms | 3 | 3 | 100.00 | ||
chip_sw_entropy_src_smoketest | 9.648m | 3.922ms | 3 | 3 | 100.00 | ||
chip_sw_gpio_smoketest | 4.198m | 2.932ms | 3 | 3 | 100.00 | ||
chip_sw_hmac_smoketest | 5.151m | 3.244ms | 3 | 3 | 100.00 | ||
chip_sw_kmac_smoketest | 5.022m | 3.391ms | 3 | 3 | 100.00 | ||
chip_sw_otbn_smoketest | 35.541m | 10.041ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_smoketest | 4.296m | 2.273ms | 3 | 3 | 100.00 | ||
chip_sw_pwrmgr_smoketest | 7.222m | 5.059ms | 3 | 3 | 100.00 | ||
chip_sw_pwrmgr_usbdev_smoketest | 9.059m | 5.698ms | 3 | 3 | 100.00 | ||
chip_sw_rv_plic_smoketest | 4.196m | 2.782ms | 3 | 3 | 100.00 | ||
chip_sw_rv_timer_smoketest | 4.974m | 2.873ms | 3 | 3 | 100.00 | ||
chip_sw_rstmgr_smoketest | 3.851m | 3.120ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_smoketest | 4.365m | 3.231ms | 3 | 3 | 100.00 | ||
chip_sw_uart_smoketest | 5.527m | 3.569ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_rom_functests | rom_keymgr_functest | 9.775m | 4.918ms | 3 | 3 | 100.00 |
V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 33.242m | 8.907ms | 3 | 3 | 100.00 |
V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.029h | 69.902ms | 3 | 3 | 100.00 |
V2 | chip_sw_secure_boot | rom_e2e_smoke | 32.154m | 8.548ms | 3 | 3 | 100.00 |
V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 4.501m | 3.054ms | 1 | 1 | 100.00 |
chip_sw_lc_ctrl_raw_to_scrap | 2.499m | 2.426ms | 1 | 1 | 100.00 | ||
chip_sw_lc_ctrl_test_locked0_to_scrap | 2.234m | 3.014ms | 1 | 1 | 100.00 | ||
chip_sw_lc_ctrl_rand_to_scrap | 2.923m | 3.259ms | 3 | 3 | 100.00 | ||
V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 31.271m | 27.147ms | 3 | 3 | 100.00 |
chip_rv_dm_lc_disabled | 7.602m | 12.282ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.437h | 49.385ms | 3 | 3 | 100.00 |
chip_sw_lc_walkthrough_prod | 1.289h | 51.676ms | 3 | 3 | 100.00 | ||
chip_sw_lc_walkthrough_prodend | 17.138m | 9.259ms | 3 | 3 | 100.00 | ||
chip_sw_lc_walkthrough_rma | 1.359h | 45.265ms | 3 | 3 | 100.00 | ||
chip_sw_lc_walkthrough_testunlocks | 31.271m | 27.147ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 4.811m | 3.781ms | 3 | 3 | 100.00 |
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 5.677m | 4.691ms | 2 | 3 | 66.67 | ||
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_96mhz | 5.514m | 3.609ms | 3 | 3 | 100.00 | ||
rom_volatile_raw_unlock | 5.622h | 116.583ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 11.035m | 4.460ms | 3 | 3 | 100.00 |
V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 8.728m | 10.927ms | 3 | 3 | 100.00 |
V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.701h | 58.053ms | 2 | 3 | 66.67 |
V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.384h | 64.667ms | 3 | 3 | 100.00 |
V2 | tl_d_oob_addr_access | chip_tl_errors | 10.281m | 6.729ms | 30 | 30 | 100.00 |
V2 | tl_d_illegal_access | chip_tl_errors | 10.281m | 6.729ms | 30 | 30 | 100.00 |
V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.712h | 61.774ms | 5 | 5 | 100.00 |
chip_same_csr_outstanding | 1.138h | 29.180ms | 20 | 20 | 100.00 | ||
chip_csr_hw_reset | 6.597m | 7.474ms | 5 | 5 | 100.00 | ||
chip_csr_rw | 8.891m | 5.760ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | chip_csr_aliasing | 2.712h | 61.774ms | 5 | 5 | 100.00 |
chip_same_csr_outstanding | 1.138h | 29.180ms | 20 | 20 | 100.00 | ||
chip_csr_hw_reset | 6.597m | 7.474ms | 5 | 5 | 100.00 | ||
chip_csr_rw | 8.891m | 5.760ms | 20 | 20 | 100.00 | ||
V2 | xbar_base_random_sequence | xbar_random | 1.581m | 2.366ms | 100 | 100 | 100.00 |
V2 | xbar_random_delay | xbar_smoke_zero_delays | 6.830s | 51.573us | 100 | 100 | 100.00 |
xbar_smoke_large_delays | 1.983m | 11.089ms | 100 | 100 | 100.00 | ||
xbar_smoke_slow_rsp | 1.975m | 6.755ms | 100 | 100 | 100.00 | ||
xbar_random_zero_delays | 56.220s | 573.766us | 100 | 100 | 100.00 | ||
xbar_random_large_delays | 23.607m | 115.455ms | 100 | 100 | 100.00 | ||
xbar_random_slow_rsp | 21.145m | 65.786ms | 100 | 100 | 100.00 | ||
V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.043m | 1.465ms | 100 | 100 | 100.00 |
xbar_error_and_unmapped_addr | 57.290s | 1.379ms | 100 | 100 | 100.00 | ||
V2 | xbar_error_cases | xbar_error_random | 1.598m | 2.537ms | 100 | 100 | 100.00 |
xbar_error_and_unmapped_addr | 57.290s | 1.379ms | 100 | 100 | 100.00 | ||
V2 | xbar_all_access_same_device | xbar_access_same_device | 2.470m | 3.634ms | 100 | 100 | 100.00 |
xbar_access_same_device_slow_rsp | 44.678m | 148.850ms | 100 | 100 | 100.00 | ||
V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.405m | 2.705ms | 100 | 100 | 100.00 |
V2 | xbar_stress_all | xbar_stress_all | 12.811m | 19.531ms | 100 | 100 | 100.00 |
xbar_stress_all_with_error | 12.677m | 18.738ms | 100 | 100 | 100.00 | ||
V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 19.552m | 25.823ms | 100 | 100 | 100.00 |
xbar_stress_all_with_reset_error | 16.073m | 8.731ms | 100 | 100 | 100.00 | ||
V2 | rom_e2e_smoke | rom_e2e_smoke | 32.154m | 8.548ms | 3 | 3 | 100.00 |
V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 47.244m | 23.678ms | 2 | 3 | 66.67 |
V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 34.697m | 8.076ms | 3 | 3 | 100.00 |
V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 3.961h | 77.570ms | 1 | 1 | 100.00 |
rom_e2e_boot_policy_valid_a_good_b_good_dev | 25.079m | 8.371ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_good_prod | 29.842m | 8.838ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 33.123m | 8.753ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_good_rma | 31.180m | 8.153ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 3.760h | 77.858ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_bad_dev | 32.692m | 8.503ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_bad_prod | 30.364m | 9.093ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 29.808m | 8.742ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_bad_rma | 28.793m | 8.821ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 7.357h | 151.587ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_bad_b_good_dev | 48.484m | 12.047ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_bad_b_good_prod | 42.163m | 12.611ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 42.114m | 11.967ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_bad_b_good_rma | 43.157m | 12.154ms | 1 | 1 | 100.00 | ||
V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 7.730h | 151.560ms | 1 | 1 | 100.00 |
rom_e2e_sigverify_always_a_bad_b_bad_dev | 40.809m | 11.774ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_bad_prod | 47.989m | 12.004ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 39.080m | 12.141ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_bad_rma | 50.785m | 11.336ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 3.900h | 77.172ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_nothing_dev | 29.728m | 8.818ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_nothing_prod | 30.540m | 8.250ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 33.549m | 8.654ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_nothing_rma | 32.447m | 9.110ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 3.986h | 77.232ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_nothing_b_bad_dev | 32.310m | 8.221ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_nothing_b_bad_prod | 32.157m | 8.146ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 31.472m | 9.392ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_nothing_b_bad_rma | 32.850m | 8.416ms | 1 | 1 | 100.00 | ||
V2 | rom_e2e_sigverify_mod_exp | rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 4.174h | 76.824ms | 3 | 3 | 100.00 |
rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 3.803h | 76.827ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_dev_otbn | 32.944m | 8.519ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_dev_sw | 35.589m | 9.254ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_prod_otbn | 31.588m | 8.745ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_prod_sw | 32.393m | 8.784ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_prod_end_otbn | 29.857m | 8.964ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_prod_end_sw | 34.790m | 8.566ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_rma_otbn | 31.669m | 8.740ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_rma_sw | 35.516m | 8.653ms | 3 | 3 | 100.00 | ||
V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 3.742h | 77.808ms | 0 | 3 | 0.00 |
rom_e2e_asm_init_dev | 33.831m | 8.413ms | 0 | 3 | 0.00 | ||
rom_e2e_asm_init_prod | 32.881m | 9.077ms | 0 | 3 | 0.00 | ||
rom_e2e_asm_init_prod_end | 31.771m | 8.805ms | 0 | 3 | 0.00 | ||
rom_e2e_asm_init_rma | 31.220m | 8.747ms | 0 | 3 | 0.00 | ||
V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 35.269m | 9.396ms | 3 | 3 | 100.00 |
rom_e2e_keymgr_init_rom_ext_no_meas | 33.547m | 8.740ms | 3 | 3 | 100.00 | ||
rom_e2e_keymgr_init_rom_ext_invalid_meas | 31.053m | 8.652ms | 3 | 3 | 100.00 | ||
V2 | rom_e2e_static_critical | rom_e2e_static_critical | 36.271m | 10.827ms | 3 | 3 | 100.00 |
V2 | TOTAL | 2633 | 2651 | 99.32 | |||
V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 4.458m | 2.999ms | 3 | 3 | 100.00 |
V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 3.901m | 3.091ms | 3 | 3 | 100.00 |
V2S | TOTAL | 6 | 6 | 100.00 | |||
V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
V3 | chip_sw_usb_fs_tx_rx | chip_sw_usbdev_stream | 39.746m | 13.429ms | 1 | 1 | 100.00 |
V3 | chip_sw_usb_vbus | chip_sw_usb_vbus | 0 | 0 | -- | ||
V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
V3 | chip_usb_sof | chip_usb_sof | 0 | 0 | -- | ||
V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
V3 | chip_usb_enumeration | chip_usb_enumeration | 0 | 0 | -- | ||
V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 32.172m | 11.152ms | 1 | 1 | 100.00 |
rom_e2e_jtag_debug_dev | 28.135m | 11.428ms | 1 | 1 | 100.00 | ||
rom_e2e_jtag_debug_rma | 30.625m | 11.340ms | 1 | 1 | 100.00 | ||
V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 9.402m | 5.576ms | 3 | 3 | 100.00 |
V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 13.155m | 5.048ms | 100 | 100 | 100.00 |
V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | ||
V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.173m | 3.002ms | 3 | 3 | 100.00 |
V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 8.942m | 4.845ms | 1 | 1 | 100.00 |
V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
V3 | chip_sw_coremark | chip_sw_coremark | 3.140s | 0 | 1 | 0.00 | |
V3 | chip_sw_power_max_load | chip_sw_power_virus | 34.637m | 8.745ms | 3 | 3 | 100.00 |
V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 32.172m | 11.152ms | 1 | 1 | 100.00 |
rom_e2e_jtag_debug_dev | 28.135m | 11.428ms | 1 | 1 | 100.00 | ||
rom_e2e_jtag_debug_rma | 30.625m | 11.340ms | 1 | 1 | 100.00 | ||
V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 1.028h | 32.101ms | 1 | 1 | 100.00 |
rom_e2e_jtag_inject_dev | 49.317m | 32.445ms | 1 | 1 | 100.00 | ||
rom_e2e_jtag_inject_rma | 56.561m | 34.117ms | 1 | 1 | 100.00 | ||
V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
V3 | TOTAL | 17 | 18 | 94.44 | |||
Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 9.796m | 4.724ms | 3 | 3 | 100.00 | |
TOTAL | 2882 | 2901 | 99.35 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
N.A. | 1 | 1 | 1 | 100.00 |
V1 | 19 | 19 | 19 | 100.00 |
V2 | 270 | 270 | 262 | 97.04 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 26 | 12 | 11 | 42.31 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
96.70 | 95.65 | 94.14 | 98.20 | -- | 94.65 | 97.93 | 99.66 |
UVM_ERROR @ * us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[*] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (* [*] vs * [*])
has 15 failures:
0.rom_e2e_asm_init_test_unlocked0.2736732677
Line 1103, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log
UVM_ERROR @ 77807.604592 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 77807.604592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_test_unlocked0.248826193
Line 1098, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest/run.log
UVM_ERROR @ 77609.460072 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 77609.460072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_dev.454704799
Line 1101, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log
UVM_ERROR @ 8413.457562 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8413.457562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_dev.2657354907
Line 1100, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log
UVM_ERROR @ 8894.472984 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8894.472984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_prod.2668260806
Line 1099, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log
UVM_ERROR @ 9077.463158 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 9077.463158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_prod.1284278846
Line 1097, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest/run.log
UVM_ERROR @ 8962.975336 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8962.975336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_prod_end.790163385
Line 1099, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log
UVM_ERROR @ 8970.862600 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8970.862600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_prod_end.3906181004
Line 1097, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest/run.log
UVM_ERROR @ 8805.332170 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8805.332170 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_rma.1146312494
Line 1101, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log
UVM_ERROR @ 8746.521298 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8746.521298 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_rma.3542597473
Line 1094, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest/run.log
UVM_ERROR @ 8634.916596 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8634.916596 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 2 failures:
Test rom_e2e_shutdown_output has 1 failures.
0.rom_e2e_shutdown_output.1336696514
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
Job ID: smart:1d61c888-3975-4861-920d-67a5a2062d84
Test chip_sw_exit_test_unlocked_bootstrap has 1 failures.
2.chip_sw_exit_test_unlocked_bootstrap.1011710976
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job ID: smart:de3bdb38-458b-4131-b6a6-14738d288a35
UVM_FATAL @ * us: (uart_logger.sv:25) [m_logger] Check failed (!logs_output_fd) Failed to open log for writing
has 1 failures:
0.chip_sw_coremark.4205394758
Line 1044, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
UVM_FATAL @ 0.000000 us: (uart_logger.sv:25) [uvm_test_top.env.m_uart_agent0.m_logger] Check failed (!logs_output_fd) Failed to open uvm_test_top.env.m_uart_agent0.m_logger.log for writing
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:716) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (status_val) >> dummy.num() == * (* [*] vs * [*]) Unexpected status error *cdf*
has 1 failures:
2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.494916199
Line 1066, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log
UVM_ERROR @ 1994.853859 us: (chip_sw_base_vseq.sv:716) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Check failed (status_val) >> dummy.num() == 0 (44 [0x2c] vs 0 [0x0]) Unexpected status error 2cdf0
UVM_INFO @ 1994.853859 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---