94eb0df12
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 14.317m | 5.140ms | 5 | 5 | 100.00 |
V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 14.317m | 5.140ms | 5 | 5 | 100.00 |
chip_sw_uart_tx_rx_idx1 | 16.413m | 5.974ms | 5 | 5 | 100.00 | ||
chip_sw_uart_tx_rx_idx2 | 16.579m | 5.405ms | 5 | 5 | 100.00 | ||
chip_sw_uart_tx_rx_idx3 | 15.400m | 5.740ms | 5 | 5 | 100.00 | ||
V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 1.002h | 23.473ms | 20 | 20 | 100.00 |
V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 1.060h | 23.230ms | 5 | 5 | 100.00 |
chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 26.448m | 14.364ms | 5 | 5 | 100.00 | ||
V1 | chip_sw_gpio_out | chip_sw_gpio | 7.413m | 4.102ms | 3 | 3 | 100.00 |
V1 | chip_sw_gpio_in | chip_sw_gpio | 7.413m | 4.102ms | 3 | 3 | 100.00 |
V1 | chip_sw_gpio_irq | chip_sw_gpio | 7.413m | 4.102ms | 3 | 3 | 100.00 |
V1 | chip_sw_example_tests | chip_sw_example_flash | 5.069m | 2.714ms | 3 | 3 | 100.00 |
chip_sw_example_rom | 2.156m | 2.422ms | 3 | 3 | 100.00 | ||
chip_sw_example_manufacturer | 4.309m | 2.300ms | 3 | 3 | 100.00 | ||
chip_sw_example_concurrency | 5.368m | 2.654ms | 3 | 3 | 100.00 | ||
chip_sw_uart_smoketest_signed | 35.298m | 8.702ms | 3 | 3 | 100.00 | ||
V1 | csr_hw_reset | chip_csr_hw_reset | 6.072m | 7.243ms | 5 | 5 | 100.00 |
V1 | csr_rw | chip_csr_rw | 10.379m | 5.574ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | chip_csr_bit_bash | 24.445m | 13.869ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | chip_csr_aliasing | 2.171h | 51.223ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 6.720m | 9.208ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.171h | 51.223ms | 5 | 5 | 100.00 |
chip_csr_rw | 10.379m | 5.574ms | 20 | 20 | 100.00 | ||
V1 | xbar_smoke | xbar_smoke | 10.820s | 246.819us | 100 | 100 | 100.00 |
V1 | TOTAL | 223 | 223 | 100.00 | |||
V2 | chip_sw_spi_device_tx_rx | chip_sw_spi_device_tx_rx | 7.521m | 3.602ms | 3 | 3 | 100.00 |
V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 3.218h | 70.487ms | 3 | 3 | 100.00 |
V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 12.876m | 7.466ms | 3 | 3 | 100.00 |
V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 8.878m | 4.632ms | 3 | 3 | 100.00 |
V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 7.752m | 3.652ms | 3 | 3 | 100.00 |
V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 4.930m | 2.973ms | 3 | 3 | 100.00 |
V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 9.104m | 4.493ms | 3 | 3 | 100.00 |
chip_sw_i2c_host_tx_rx_idx1 | 8.804m | 3.607ms | 3 | 3 | 100.00 | ||
chip_sw_i2c_host_tx_rx_idx2 | 10.096m | 3.857ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 10.898m | 3.985ms | 3 | 3 | 100.00 |
V2 | chip_sw_usbdev_dpi | chip_sw_usbdev_dpi | 26.396m | 7.374ms | 1 | 1 | 100.00 |
V2 | chip_pin_mux | chip_padctrl_attributes | 6.223m | 4.724ms | 10 | 10 | 100.00 |
V2 | chip_padctrl_attributes | chip_padctrl_attributes | 6.223m | 4.724ms | 10 | 10 | 100.00 |
V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.439m | 3.140ms | 3 | 3 | 100.00 |
V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 4.551m | 3.359ms | 3 | 3 | 100.00 |
V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 5.107m | 2.802ms | 3 | 3 | 100.00 |
V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 29.279m | 15.499ms | 5 | 5 | 100.00 |
chip_tap_straps_testunlock0 | 8.361m | 5.203ms | 5 | 5 | 100.00 | ||
chip_tap_straps_rma | 12.252m | 7.238ms | 5 | 5 | 100.00 | ||
chip_tap_straps_prod | 16.372m | 11.639ms | 5 | 5 | 100.00 | ||
V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 4.071m | 2.781ms | 3 | 3 | 100.00 |
V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 22.993m | 8.221ms | 3 | 3 | 100.00 |
V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 12.924m | 6.268ms | 6 | 6 | 100.00 |
V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 12.924m | 6.268ms | 6 | 6 | 100.00 |
V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 36.374m | 19.085ms | 3 | 3 | 100.00 |
V2 | chip_jtag_mem_access | chip_jtag_mem_access | 22.895m | 13.160ms | 3 | 3 | 100.00 |
V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 8.399m | 4.440ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 8.492m | 5.068ms | 3 | 3 | 100.00 |
V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 9.593m | 4.919ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 12.252m | 7.238ms | 5 | 5 | 100.00 |
V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 7.344m | 11.570ms | 3 | 3 | 100.00 |
V2 | chip_sw_timer | chip_sw_rv_timer_irq | 4.219m | 2.863ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 6.929m | 3.800ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 6.513m | 4.462ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 6.929m | 3.800ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 12.325m | 4.909ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 12.174m | 7.615ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 12.174m | 7.615ms | 3 | 3 | 100.00 |
V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 7.522m | 6.044ms | 5 | 5 | 100.00 |
V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs | 21.923m | 8.608ms | 3 | 3 | 100.00 |
V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 4.228m | 2.635ms | 3 | 3 | 100.00 |
V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 11.790m | 5.693ms | 3 | 3 | 100.00 |
chip_sw_aes_idle | 4.462m | 2.497ms | 3 | 3 | 100.00 | ||
chip_sw_hmac_enc_idle | 5.255m | 3.622ms | 3 | 3 | 100.00 | ||
chip_sw_kmac_idle | 4.717m | 2.739ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.585m | 5.858ms | 3 | 3 | 100.00 |
chip_sw_clkmgr_off_hmac_trans | 9.868m | 3.855ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_off_kmac_trans | 9.711m | 4.359ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_off_otbn_trans | 7.807m | 4.966ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 27.262m | 10.020ms | 3 | 3 | 100.00 |
V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_lc | 11.529m | 8.512ms | 3 | 3 | 100.00 |
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.180m | 4.090ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 9.292m | 4.903ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 9.902m | 4.248ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 9.218m | 4.543ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.848m | 4.302ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.140m | 5.058ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 11.529m | 8.512ms | 3 | 3 | 100.00 |
V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.180m | 4.090ms | 3 | 3 | 100.00 |
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 9.292m | 4.903ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 9.902m | 4.248ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 9.218m | 4.543ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.848m | 4.302ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.140m | 5.058ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 17.994m | 5.056ms | 3 | 3 | 100.00 |
chip_sw_flash_ctrl_access_jitter_en | 21.685m | 6.600ms | 3 | 3 | 100.00 | ||
chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.050h | 21.661ms | 3 | 3 | 100.00 | ||
chip_sw_aes_enc_jitter_en | 4.851m | 3.403ms | 3 | 3 | 100.00 | ||
chip_sw_edn_entropy_reqs_jitter | 16.315m | 5.130ms | 3 | 3 | 100.00 | ||
chip_sw_hmac_enc_jitter_en | 5.720m | 3.331ms | 3 | 3 | 100.00 | ||
chip_sw_keymgr_key_derivation_jitter_en | 7.516m | 5.019ms | 3 | 3 | 100.00 | ||
chip_sw_kmac_mode_kmac_jitter_en | 5.630m | 3.474ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.207m | 5.591ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_jitter | 4.656m | 2.505ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 3.531m | 2.751ms | 3 | 3 | 100.00 |
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 15.327m | 6.132ms | 3 | 3 | 100.00 | ||
chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 18.375m | 7.993ms | 3 | 3 | 100.00 | ||
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.042h | 28.222ms | 3 | 3 | 100.00 | ||
chip_sw_aes_enc_jitter_en_reduced_freq | 4.927m | 2.798ms | 3 | 3 | 100.00 | ||
chip_sw_hmac_enc_jitter_en_reduced_freq | 4.799m | 2.941ms | 3 | 3 | 100.00 | ||
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 7.205m | 4.234ms | 3 | 3 | 100.00 | ||
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 4.598m | 2.822ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 6.936m | 3.916ms | 3 | 3 | 100.00 | ||
chip_sw_flash_init_reduced_freq | 25.913m | 18.290ms | 3 | 3 | 100.00 | ||
chip_sw_csrng_edn_concurrency_reduced_freq | 43.160m | 18.772ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 17.056m | 6.827ms | 3 | 3 | 100.00 |
V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 9.475m | 4.588ms | 3 | 3 | 100.00 |
V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 8.467m | 3.768ms | 3 | 3 | 100.00 |
V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 14.383m | 5.654ms | 99 | 100 | 99.00 |
V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 8.760m | 8.095ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 31.344m | 23.125ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 7.663m | 7.646ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 12.174m | 7.615ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 25.857m | 20.575ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 43.509m | 28.375ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 30.083m | 13.665ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 9.278m | 3.771ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 8.760m | 8.095ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 7.493m | 5.596ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 58.202m | 39.556ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 8.467m | 5.770ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 7.905m | 6.030ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 51.990m | 38.356ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 17.054m | 8.193ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 42.381m | 27.746ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 4.475m | 2.893ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 14.383m | 5.654ms | 99 | 100 | 99.00 |
V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 6.513m | 4.462ms | 3 | 3 | 100.00 |
V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 8.399m | 4.440ms | 3 | 3 | 100.00 |
V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 11.721m | 7.024ms | 3 | 3 | 100.00 |
V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 8.156m | 5.373ms | 3 | 3 | 100.00 |
V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 26.265m | 10.079ms | 3 | 3 | 100.00 |
V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 5.003m | 2.704ms | 3 | 3 | 100.00 |
V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 14.383m | 5.654ms | 99 | 100 | 99.00 |
V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 5.432m | 3.289ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 8.653m | 4.819ms | 3 | 3 | 100.00 |
V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 14.383m | 5.654ms | 99 | 100 | 99.00 |
V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 21.923m | 8.608ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 5.588m | 3.667ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 26.265m | 10.079ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 7.270m | 4.171ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 10.700m | 4.143ms | 90 | 90 | 100.00 |
V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 30.428m | 12.247ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 31.924m | 8.248ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 30.915m | 8.443ms | 3 | 3 | 100.00 |
V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.224h | 254.670ms | 3 | 3 | 100.00 |
V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 8.653m | 4.819ms | 3 | 3 | 100.00 |
V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 29.279m | 15.499ms | 5 | 5 | 100.00 |
chip_tap_straps_rma | 12.252m | 7.238ms | 5 | 5 | 100.00 | ||
chip_tap_straps_prod | 16.372m | 11.639ms | 5 | 5 | 100.00 | ||
V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 4.854m | 3.248ms | 3 | 3 | 100.00 |
V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 18.287m | 10.885ms | 15 | 15 | 100.00 |
V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 18.287m | 10.885ms | 15 | 15 | 100.00 |
V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 18.287m | 10.885ms | 15 | 15 | 100.00 |
V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 8.815m | 3.536ms | 3 | 3 | 100.00 |
V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 9.223m | 4.597ms | 3 | 3 | 100.00 |
chip_sw_flash_rma_unlocked | 1.308h | 43.661ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.120m | 4.076ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_lc_signals_dev | 19.859m | 9.341ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_lc_signals_prod | 19.507m | 7.680ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_lc_signals_rma | 18.702m | 8.402ms | 3 | 3 | 100.00 | ||
chip_sw_lc_ctrl_transition | 18.287m | 10.885ms | 15 | 15 | 100.00 | ||
chip_sw_keymgr_key_derivation | 9.227m | 3.945ms | 3 | 3 | 100.00 | ||
chip_sw_rom_ctrl_integrity_check | 9.512m | 8.917ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_execution_main | 17.761m | 9.548ms | 3 | 3 | 100.00 | ||
chip_prim_tl_access | 5.426m | 7.862ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_lc | 11.529m | 8.512ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.180m | 4.090ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 9.292m | 4.903ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 9.902m | 4.248ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 9.218m | 4.543ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.848m | 4.302ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.140m | 5.058ms | 3 | 3 | 100.00 | ||
chip_tap_straps_dev | 29.279m | 15.499ms | 5 | 5 | 100.00 | ||
chip_tap_straps_rma | 12.252m | 7.238ms | 5 | 5 | 100.00 | ||
chip_tap_straps_prod | 16.372m | 11.639ms | 5 | 5 | 100.00 | ||
chip_rv_dm_lc_disabled | 7.344m | 11.570ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 5.707m | 3.276ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 6.932m | 3.378ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 9.033m | 4.656ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 31.788m | 24.610ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_reset | chip_sw_sysrst_ctrl_reset | 31.788m | 24.610ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 31.788m | 24.610ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 57.808m | 20.598ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 57.808m | 20.598ms | 3 | 3 | 100.00 |
V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 9.659m | 6.115ms | 3 | 3 | 100.00 |
chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.303m | 18.796ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.303m | 18.796ms | 3 | 3 | 100.00 |
V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.303m | 18.796ms | 3 | 3 | 100.00 |
V2 | chip_sw_aes_enc | chip_sw_aes_enc | 4.612m | 2.817ms | 3 | 3 | 100.00 |
chip_sw_aes_enc_jitter_en | 4.851m | 3.403ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.716m | 2.674ms | 3 | 3 | 100.00 |
V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.462m | 2.497ms | 3 | 3 | 100.00 |
V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 8.322m | 4.947ms | 3 | 3 | 100.00 |
V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.293m | 2.870ms | 3 | 3 | 100.00 |
chip_sw_hmac_enc_jitter_en | 5.720m | 3.331ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.255m | 3.622ms | 3 | 3 | 100.00 |
V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.833m | 2.879ms | 3 | 3 | 100.00 |
chip_sw_kmac_mode_kmac | 4.688m | 2.895ms | 3 | 3 | 100.00 | ||
chip_sw_kmac_mode_kmac_jitter_en | 5.630m | 3.474ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 9.227m | 3.945ms | 3 | 3 | 100.00 |
V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 18.287m | 10.885ms | 15 | 15 | 100.00 |
V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 3.803m | 3.216ms | 3 | 3 | 100.00 |
V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.609m | 3.357ms | 3 | 3 | 100.00 |
V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.717m | 2.739ms | 3 | 3 | 100.00 |
V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 5.361m | 3.150ms | 3 | 3 | 100.00 |
V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 30.026m | 8.281ms | 3 | 3 | 100.00 |
V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 8.690m | 5.008ms | 3 | 3 | 100.00 |
V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.624m | 2.879ms | 3 | 3 | 100.00 |
V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 30.026m | 8.281ms | 3 | 3 | 100.00 |
V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 8.864m | 4.535ms | 3 | 3 | 100.00 |
V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 12.018m | 7.270ms | 3 | 3 | 100.00 |
V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.112m | 3.139ms | 3 | 3 | 100.00 |
V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 1.195h | 16.841ms | 3 | 3 | 100.00 |
chip_sw_edn_entropy_reqs | 18.682m | 6.010ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 9.227m | 3.945ms | 3 | 3 | 100.00 |
chip_sw_keymgr_key_derivation_jitter_en | 7.516m | 5.019ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 8.705m | 4.500ms | 3 | 3 | 100.00 |
V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 8.322m | 4.947ms | 3 | 3 | 100.00 |
V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 43.649m | 9.750ms | 3 | 3 | 100.00 |
V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 51.466m | 20.032ms | 3 | 3 | 100.00 |
chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.050h | 21.661ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 11.790m | 5.693ms | 3 | 3 | 100.00 |
V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 11.790m | 5.693ms | 3 | 3 | 100.00 |
V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 11.790m | 5.693ms | 3 | 3 | 100.00 |
V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 8.718m | 3.012ms | 3 | 3 | 100.00 |
V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 9.512m | 8.917ms | 3 | 3 | 100.00 |
V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 9.512m | 8.917ms | 3 | 3 | 100.00 |
V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 8.349m | 5.607ms | 3 | 3 | 100.00 |
chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.207m | 5.591ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 16.598m | 11.611ms | 3 | 3 | 100.00 |
V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 17.761m | 9.548ms | 3 | 3 | 100.00 |
V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 14.383m | 5.654ms | 99 | 100 | 99.00 |
chip_sw_data_integrity_escalation | 12.924m | 6.268ms | 6 | 6 | 100.00 | ||
V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 18.287m | 10.885ms | 15 | 15 | 100.00 |
V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 31.397m | 19.078ms | 3 | 3 | 100.00 |
chip_sw_otbn_mem_scramble | 8.718m | 3.012ms | 3 | 3 | 100.00 | ||
chip_sw_keymgr_key_derivation | 9.227m | 3.945ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_scrambled_access | 8.349m | 5.607ms | 3 | 3 | 100.00 | ||
chip_sw_rv_core_ibex_icache_invalidate | 5.006m | 2.729ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 31.397m | 19.078ms | 3 | 3 | 100.00 |
chip_sw_otbn_mem_scramble | 8.718m | 3.012ms | 3 | 3 | 100.00 | ||
chip_sw_keymgr_key_derivation | 9.227m | 3.945ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_scrambled_access | 8.349m | 5.607ms | 3 | 3 | 100.00 | ||
chip_sw_rv_core_ibex_icache_invalidate | 5.006m | 2.729ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 18.287m | 10.885ms | 15 | 15 | 100.00 |
V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 9.570m | 5.163ms | 3 | 3 | 100.00 |
V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 4.854m | 3.248ms | 3 | 3 | 100.00 |
V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.120m | 4.076ms | 3 | 3 | 100.00 |
chip_sw_otp_ctrl_lc_signals_dev | 19.859m | 9.341ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_lc_signals_prod | 19.507m | 7.680ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_lc_signals_rma | 18.702m | 8.402ms | 3 | 3 | 100.00 | ||
chip_sw_lc_ctrl_transition | 18.287m | 10.885ms | 15 | 15 | 100.00 | ||
chip_prim_tl_access | 5.426m | 7.862ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 5.426m | 7.862ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_init | chip_sw_flash_init | 31.397m | 19.078ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 19.122m | 6.161ms | 3 | 3 | 100.00 |
chip_sw_flash_ctrl_access_jitter_en | 21.685m | 6.600ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 16.175m | 5.308ms | 3 | 3 | 100.00 |
chip_sw_flash_ctrl_ops_jitter_en | 17.994m | 5.056ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.308h | 43.661ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_scramble | chip_sw_flash_init | 31.397m | 19.078ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.353m | 3.031ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 9.227m | 3.945ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.223m | 4.597ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.308h | 43.661ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.223m | 4.597ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.223m | 4.597ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 9.223m | 4.597ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.223m | 4.597ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 14.383m | 5.654ms | 99 | 100 | 99.00 |
V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 5.426m | 7.862ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 19.549m | 5.904ms | 3 | 3 | 100.00 |
V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 11.905m | 6.204ms | 3 | 3 | 100.00 |
V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 17.056m | 6.827ms | 3 | 3 | 100.00 |
V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 10.415m | 11.414ms | 3 | 3 | 100.00 |
V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 17.994m | 5.056ms | 3 | 3 | 100.00 |
chip_sw_flash_ctrl_access_jitter_en | 21.685m | 6.600ms | 3 | 3 | 100.00 | ||
chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.050h | 21.661ms | 3 | 3 | 100.00 | ||
chip_sw_aes_enc_jitter_en | 4.851m | 3.403ms | 3 | 3 | 100.00 | ||
chip_sw_edn_entropy_reqs_jitter | 16.315m | 5.130ms | 3 | 3 | 100.00 | ||
chip_sw_hmac_enc_jitter_en | 5.720m | 3.331ms | 3 | 3 | 100.00 | ||
chip_sw_keymgr_key_derivation_jitter_en | 7.516m | 5.019ms | 3 | 3 | 100.00 | ||
chip_sw_kmac_mode_kmac_jitter_en | 5.630m | 3.474ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.207m | 5.591ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_jitter | 4.656m | 2.505ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 4.781m | 2.946ms | 1 | 1 | 100.00 |
V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 34.908m | 14.247ms | 5 | 5 | 100.00 |
V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 34.908m | 14.247ms | 5 | 5 | 100.00 |
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.586m | 4.711ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.857m | 3.094ms | 3 | 3 | 100.00 |
V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.586m | 4.711ms | 3 | 3 | 100.00 |
V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 12.930m | 4.424ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 17.122m | 5.309ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 5.108m | 2.464ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 5.006m | 2.729ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 11.721m | 7.024ms | 3 | 3 | 100.00 |
V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 11.721m | 7.024ms | 3 | 3 | 100.00 |
V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.126m | 3.002ms | 3 | 3 | 100.00 |
chip_sw_aes_smoketest | 4.952m | 2.984ms | 3 | 3 | 100.00 | ||
chip_sw_aon_timer_smoketest | 5.021m | 2.877ms | 3 | 3 | 100.00 | ||
chip_sw_clkmgr_smoketest | 3.249m | 3.018ms | 3 | 3 | 100.00 | ||
chip_sw_csrng_smoketest | 4.083m | 2.521ms | 3 | 3 | 100.00 | ||
chip_sw_entropy_src_smoketest | 7.960m | 3.745ms | 3 | 3 | 100.00 | ||
chip_sw_gpio_smoketest | 4.383m | 2.954ms | 3 | 3 | 100.00 | ||
chip_sw_hmac_smoketest | 7.152m | 3.412ms | 3 | 3 | 100.00 | ||
chip_sw_kmac_smoketest | 4.812m | 3.187ms | 3 | 3 | 100.00 | ||
chip_sw_otbn_smoketest | 36.036m | 11.087ms | 3 | 3 | 100.00 | ||
chip_sw_otp_ctrl_smoketest | 5.135m | 2.528ms | 3 | 3 | 100.00 | ||
chip_sw_pwrmgr_smoketest | 6.513m | 4.462ms | 3 | 3 | 100.00 | ||
chip_sw_pwrmgr_usbdev_smoketest | 8.198m | 4.383ms | 3 | 3 | 100.00 | ||
chip_sw_rv_plic_smoketest | 5.143m | 2.404ms | 3 | 3 | 100.00 | ||
chip_sw_rv_timer_smoketest | 4.540m | 2.685ms | 3 | 3 | 100.00 | ||
chip_sw_rstmgr_smoketest | 4.444m | 2.819ms | 3 | 3 | 100.00 | ||
chip_sw_sram_ctrl_smoketest | 3.745m | 3.390ms | 3 | 3 | 100.00 | ||
chip_sw_uart_smoketest | 5.251m | 3.169ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_rom_functests | rom_keymgr_functest | 11.882m | 4.718ms | 3 | 3 | 100.00 |
V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 35.298m | 8.702ms | 3 | 3 | 100.00 |
V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.218h | 70.487ms | 3 | 3 | 100.00 |
V2 | chip_sw_secure_boot | rom_e2e_smoke | 31.603m | 8.649ms | 3 | 3 | 100.00 |
V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 4.524m | 2.949ms | 1 | 1 | 100.00 |
chip_sw_lc_ctrl_raw_to_scrap | 2.595m | 3.347ms | 1 | 1 | 100.00 | ||
chip_sw_lc_ctrl_test_locked0_to_scrap | 2.174m | 3.475ms | 1 | 1 | 100.00 | ||
chip_sw_lc_ctrl_rand_to_scrap | 2.794m | 3.175ms | 3 | 3 | 100.00 | ||
V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 35.359m | 30.923ms | 3 | 3 | 100.00 |
chip_rv_dm_lc_disabled | 7.344m | 11.570ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.484h | 51.126ms | 3 | 3 | 100.00 |
chip_sw_lc_walkthrough_prod | 1.442h | 47.239ms | 3 | 3 | 100.00 | ||
chip_sw_lc_walkthrough_prodend | 19.071m | 8.993ms | 3 | 3 | 100.00 | ||
chip_sw_lc_walkthrough_rma | 1.273h | 45.751ms | 3 | 3 | 100.00 | ||
chip_sw_lc_walkthrough_testunlocks | 35.359m | 30.923ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 5.217m | 5.119ms | 3 | 3 | 100.00 |
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 5.156m | 3.787ms | 3 | 3 | 100.00 | ||
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_96mhz | 5.548m | 2.968ms | 3 | 3 | 100.00 | ||
rom_volatile_raw_unlock | 5.258h | 114.123ms | 3 | 3 | 100.00 | ||
V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 8.155m | 4.084ms | 3 | 3 | 100.00 |
V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 11.345m | 10.989ms | 3 | 3 | 100.00 |
V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.631h | 58.728ms | 2 | 3 | 66.67 |
V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 2.844h | 64.135ms | 3 | 3 | 100.00 |
V2 | tl_d_oob_addr_access | chip_tl_errors | 9.531m | 5.331ms | 30 | 30 | 100.00 |
V2 | tl_d_illegal_access | chip_tl_errors | 9.531m | 5.331ms | 30 | 30 | 100.00 |
V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.171h | 51.223ms | 5 | 5 | 100.00 |
chip_same_csr_outstanding | 1.148h | 25.794ms | 20 | 20 | 100.00 | ||
chip_csr_hw_reset | 6.072m | 7.243ms | 5 | 5 | 100.00 | ||
chip_csr_rw | 10.379m | 5.574ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | chip_csr_aliasing | 2.171h | 51.223ms | 5 | 5 | 100.00 |
chip_same_csr_outstanding | 1.148h | 25.794ms | 20 | 20 | 100.00 | ||
chip_csr_hw_reset | 6.072m | 7.243ms | 5 | 5 | 100.00 | ||
chip_csr_rw | 10.379m | 5.574ms | 20 | 20 | 100.00 | ||
V2 | xbar_base_random_sequence | xbar_random | 1.750m | 2.632ms | 100 | 100 | 100.00 |
V2 | xbar_random_delay | xbar_smoke_zero_delays | 7.980s | 55.117us | 100 | 100 | 100.00 |
xbar_smoke_large_delays | 2.035m | 11.453ms | 100 | 100 | 100.00 | ||
xbar_smoke_slow_rsp | 2.019m | 7.219ms | 100 | 100 | 100.00 | ||
xbar_random_zero_delays | 55.110s | 489.969us | 100 | 100 | 100.00 | ||
xbar_random_large_delays | 20.746m | 101.473ms | 100 | 100 | 100.00 | ||
xbar_random_slow_rsp | 21.884m | 68.284ms | 100 | 100 | 100.00 | ||
V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.128m | 1.384ms | 100 | 100 | 100.00 |
xbar_error_and_unmapped_addr | 1.054m | 1.384ms | 100 | 100 | 100.00 | ||
V2 | xbar_error_cases | xbar_error_random | 1.610m | 2.206ms | 100 | 100 | 100.00 |
xbar_error_and_unmapped_addr | 1.054m | 1.384ms | 100 | 100 | 100.00 | ||
V2 | xbar_all_access_same_device | xbar_access_same_device | 2.695m | 4.055ms | 100 | 100 | 100.00 |
xbar_access_same_device_slow_rsp | 52.174m | 169.398ms | 100 | 100 | 100.00 | ||
V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.776m | 2.541ms | 100 | 100 | 100.00 |
V2 | xbar_stress_all | xbar_stress_all | 13.607m | 17.744ms | 100 | 100 | 100.00 |
xbar_stress_all_with_error | 13.363m | 18.556ms | 100 | 100 | 100.00 | ||
V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 16.939m | 16.309ms | 100 | 100 | 100.00 |
xbar_stress_all_with_reset_error | 14.699m | 17.585ms | 100 | 100 | 100.00 | ||
V2 | rom_e2e_smoke | rom_e2e_smoke | 31.603m | 8.649ms | 3 | 3 | 100.00 |
V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 47.026m | 21.209ms | 2 | 3 | 66.67 |
V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 29.960m | 9.063ms | 3 | 3 | 100.00 |
V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 3.774h | 77.111ms | 1 | 1 | 100.00 |
rom_e2e_boot_policy_valid_a_good_b_good_dev | 25.240m | 8.523ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_good_prod | 36.860m | 8.743ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 31.210m | 8.632ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_good_rma | 36.028m | 8.773ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 3.954h | 77.204ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_bad_dev | 36.380m | 9.228ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_bad_prod | 32.852m | 8.848ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 33.219m | 8.921ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_good_b_bad_rma | 24.414m | 8.399ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 7.329h | 151.673ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_bad_b_good_dev | 46.057m | 12.420ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_bad_b_good_prod | 50.981m | 12.324ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 47.899m | 11.692ms | 1 | 1 | 100.00 | ||
rom_e2e_boot_policy_valid_a_bad_b_good_rma | 46.425m | 11.909ms | 1 | 1 | 100.00 | ||
V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 7.662h | 150.554ms | 1 | 1 | 100.00 |
rom_e2e_sigverify_always_a_bad_b_bad_dev | 42.215m | 11.529ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_bad_prod | 34.903m | 11.562ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 48.499m | 11.634ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_bad_rma | 47.085m | 11.732ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 3.909h | 76.798ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_nothing_dev | 27.470m | 8.141ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_nothing_prod | 31.208m | 8.956ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 30.426m | 8.288ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_bad_b_nothing_rma | 30.674m | 8.707ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 3.893h | 77.814ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_nothing_b_bad_dev | 32.592m | 7.487ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_nothing_b_bad_prod | 32.256m | 9.049ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 30.538m | 8.451ms | 1 | 1 | 100.00 | ||
rom_e2e_sigverify_always_a_nothing_b_bad_rma | 34.328m | 7.940ms | 1 | 1 | 100.00 | ||
V2 | rom_e2e_sigverify_mod_exp | rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 4.125h | 79.331ms | 3 | 3 | 100.00 |
rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 4.100h | 78.980ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_dev_otbn | 29.683m | 9.278ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_dev_sw | 36.701m | 8.918ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_prod_otbn | 35.148m | 8.928ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_prod_sw | 34.681m | 8.586ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_prod_end_otbn | 37.371m | 8.078ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_prod_end_sw | 34.043m | 8.842ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_rma_otbn | 34.039m | 8.412ms | 3 | 3 | 100.00 | ||
rom_e2e_sigverify_mod_exp_rma_sw | 35.662m | 8.457ms | 3 | 3 | 100.00 | ||
V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 3.870h | 76.521ms | 3 | 3 | 100.00 |
rom_e2e_asm_init_dev | 32.733m | 8.993ms | 3 | 3 | 100.00 | ||
rom_e2e_asm_init_prod | 33.590m | 8.714ms | 3 | 3 | 100.00 | ||
rom_e2e_asm_init_prod_end | 36.865m | 9.084ms | 3 | 3 | 100.00 | ||
rom_e2e_asm_init_rma | 32.615m | 9.100ms | 3 | 3 | 100.00 | ||
V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 26.495m | 8.839ms | 3 | 3 | 100.00 |
rom_e2e_keymgr_init_rom_ext_no_meas | 36.452m | 8.921ms | 3 | 3 | 100.00 | ||
rom_e2e_keymgr_init_rom_ext_invalid_meas | 33.281m | 8.839ms | 3 | 3 | 100.00 | ||
V2 | rom_e2e_static_critical | rom_e2e_static_critical | 36.783m | 11.145ms | 3 | 3 | 100.00 |
V2 | TOTAL | 2648 | 2651 | 99.89 | |||
V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 4.359m | 2.574ms | 3 | 3 | 100.00 |
V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 4.326m | 2.811ms | 3 | 3 | 100.00 |
V2S | TOTAL | 6 | 6 | 100.00 | |||
V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
V3 | chip_sw_usb_fs_tx_rx | chip_sw_usbdev_stream | 0 | 1 | 0.00 | ||
V3 | chip_sw_usb_vbus | chip_sw_usb_vbus | 0 | 0 | -- | ||
V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
V3 | chip_usb_sof | chip_usb_sof | 0 | 0 | -- | ||
V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
V3 | chip_usb_enumeration | chip_usb_enumeration | 0 | 0 | -- | ||
V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 33.877m | 10.982ms | 1 | 1 | 100.00 |
rom_e2e_jtag_debug_dev | 31.195m | 9.921ms | 1 | 1 | 100.00 | ||
rom_e2e_jtag_debug_rma | 34.215m | 10.497ms | 1 | 1 | 100.00 | ||
V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 11.369m | 5.538ms | 3 | 3 | 100.00 |
V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 14.383m | 5.654ms | 99 | 100 | 99.00 |
V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | ||
V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 3.596m | 3.386ms | 3 | 3 | 100.00 |
V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 11.846m | 5.473ms | 1 | 1 | 100.00 |
V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
V3 | chip_sw_coremark | chip_sw_coremark | 3.440s | 0 | 1 | 0.00 | |
V3 | chip_sw_power_max_load | chip_sw_power_virus | 35.235m | 9.678ms | 3 | 3 | 100.00 |
V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 33.877m | 10.982ms | 1 | 1 | 100.00 |
rom_e2e_jtag_debug_dev | 31.195m | 9.921ms | 1 | 1 | 100.00 | ||
rom_e2e_jtag_debug_rma | 34.215m | 10.497ms | 1 | 1 | 100.00 | ||
V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 1.025h | 32.476ms | 1 | 1 | 100.00 |
rom_e2e_jtag_inject_dev | 51.773m | 42.796ms | 1 | 1 | 100.00 | ||
rom_e2e_jtag_inject_rma | 51.328m | 31.941ms | 1 | 1 | 100.00 | ||
V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
V3 | TOTAL | 16 | 18 | 88.89 | |||
Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 11.973m | 5.015ms | 3 | 3 | 100.00 | |
TOTAL | 2896 | 2901 | 99.83 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
N.A. | 1 | 1 | 1 | 100.00 |
V1 | 19 | 19 | 19 | 100.00 |
V2 | 270 | 270 | 267 | 98.89 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 26 | 12 | 10 | 38.46 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
96.72 | 95.66 | 94.18 | 98.19 | -- | 94.70 | 97.93 | 99.64 |
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 3 failures:
Test chip_sw_usbdev_stream has 1 failures.
0.chip_sw_usbdev_stream.372921994
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_stream/latest/run.log
Job ID: smart:5821f95e-74ac-4b19-ad2d-577784a38a90
Test chip_sw_exit_test_unlocked_bootstrap has 1 failures.
2.chip_sw_exit_test_unlocked_bootstrap.1459458363
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job ID: smart:41c3aeb8-a23a-453f-8054-7133ee55f53c
Test rom_e2e_shutdown_output has 1 failures.
2.rom_e2e_shutdown_output.2172665048
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_output/latest/run.log
Job ID: smart:0319e4bf-109e-468c-856b-d85f7f74281f
UVM_FATAL @ * us: (uart_logger.sv:25) [m_logger] Check failed (!logs_output_fd) Failed to open log for writing
has 1 failures:
0.chip_sw_coremark.2779836428
Line 1044, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
UVM_FATAL @ 0.000000 us: (uart_logger.sv:25) [uvm_test_top.env.m_uart_agent0.m_logger] Check failed (!logs_output_fd) Failed to open uvm_test_top.env.m_uart_agent0.m_logger.log for writing
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:523) [all_escalation_resets_test_prog_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:359)] CHECK-fail: For lc_ctrl got codes *, expected *
has 1 failures:
76.chip_sw_all_escalation_resets.2416698798
Line 1090, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/76.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3007.462280 us: (sw_logger_if.sv:523) [all_escalation_resets_test_prog_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:359)] CHECK-fail: For lc_ctrl got codes 0x0, expected 0x200
UVM_INFO @ 3007.462280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---