213e792ea| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 15.876m | 5.551ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 15.876m | 5.551ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 16.502m | 5.526ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 16.633m | 5.314ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 15.152m | 6.116ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 59.565m | 22.978ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 1.068h | 23.172ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 36.944m | 23.804ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 8.982m | 3.938ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 8.982m | 3.938ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 8.982m | 3.938ms | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_flash | 3.106m | 2.076ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.435m | 2.141ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 2.891m | 2.258ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.016m | 2.788ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 35.181m | 8.421ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 6.418m | 5.792ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 8.476m | 4.992ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 54.892m | 31.045ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 1.422h | 32.376ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 6.588m | 8.477ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 1.422h | 32.376ms | 5 | 5 | 100.00 |
| chip_csr_rw | 8.476m | 4.992ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 10.570s | 277.626us | 100 | 100 | 100.00 |
| V1 | TOTAL | 223 | 223 | 100.00 | |||
| V2 | chip_sw_spi_device_tx_rx | chip_sw_spi_device_tx_rx | 7.222m | 2.939ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 3.090h | 70.469ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 13.751m | 7.347ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 10.159m | 4.900ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 6.704m | 3.264ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 4.543m | 3.044ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 11.266m | 3.819ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 10.818m | 3.890ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 8.837m | 3.647ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 11.297m | 4.093ms | 3 | 3 | 100.00 |
| V2 | chip_sw_usbdev_dpi | chip_sw_usbdev_dpi | 27.721m | 7.157ms | 1 | 1 | 100.00 |
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.361m | 3.911ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.361m | 3.911ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 6.050m | 3.430ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 5.183m | 4.962ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 4.769m | 3.462ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 20.586m | 13.859ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 16.466m | 11.104ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 7.131m | 4.701ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 2.699m | 2.755ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 4.746m | 2.789ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 21.983m | 8.997ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 12.644m | 4.570ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 12.644m | 4.570ms | 6 | 6 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 32.544m | 21.797ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 26.547m | 12.691ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 5.856m | 4.000ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 8.154m | 4.559ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 7.397m | 4.947ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 7.131m | 4.701ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 7.112m | 11.494ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 4.659m | 2.994ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 9.593m | 4.008ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 5.978m | 5.413ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 9.593m | 4.008ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 11.646m | 4.903ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 11.617m | 8.085ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 11.617m | 8.085ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 7.700m | 7.856ms | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs | 22.367m | 7.514ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.095m | 3.515ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 10.883m | 5.201ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 5.246m | 2.830ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 4.871m | 3.329ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.271m | 3.073ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 10.384m | 4.591ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 8.741m | 5.349ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 8.635m | 4.957ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 8.673m | 4.409ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 23.273m | 11.985ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_lc | 7.677m | 5.703ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.832m | 4.221ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 12.015m | 4.542ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.870m | 4.389ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.375m | 3.827ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.728m | 4.461ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.302m | 4.906ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 7.677m | 5.703ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.832m | 4.221ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 12.015m | 4.542ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.870m | 4.389ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.375m | 3.827ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.728m | 4.461ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.302m | 4.906ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 16.748m | 4.917ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 18.188m | 5.616ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.041h | 21.150ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.516m | 2.697ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 14.198m | 4.768ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.995m | 3.411ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 9.333m | 3.871ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 4.749m | 2.533ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.178m | 5.056ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.050m | 2.300ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.734m | 2.916ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 16.405m | 6.371ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 17.207m | 7.443ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.104h | 28.585ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.182m | 3.358ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.798m | 3.574ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 8.404m | 4.616ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.257m | 3.881ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 8.153m | 4.813ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 34.490m | 24.044ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 48.045m | 17.484ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 17.751m | 6.752ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.754m | 4.194ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 6.982m | 3.502ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 14.093m | 6.328ms | 100 | 100 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 10.323m | 8.351ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 27.661m | 19.541ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 7.728m | 6.810ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 11.617m | 8.085ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 21.853m | 18.280ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 35.597m | 27.252ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 32.763m | 17.897ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 8.933m | 4.305ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 10.323m | 8.351ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 8.956m | 4.085ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 55.215m | 31.518ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 7.744m | 5.306ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 9.507m | 5.922ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 52.866m | 38.333ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 18.383m | 6.075ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 35.209m | 24.852ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.060m | 2.724ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 14.093m | 6.328ms | 100 | 100 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 5.978m | 5.413ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 5.856m | 4.000ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 10.546m | 4.553ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 6.011m | 4.399ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 27.541m | 12.801ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 5.382m | 2.653ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 14.093m | 6.328ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 5.689m | 3.196ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 8.090m | 4.614ms | 3 | 3 | 100.00 |
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 14.093m | 6.328ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 22.367m | 7.514ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 5.673m | 3.208ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 27.541m | 12.801ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 8.615m | 5.190ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.653m | 3.695ms | 90 | 90 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 29.947m | 12.193ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 31.040m | 9.349ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 28.061m | 8.248ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.326h | 255.053ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 8.090m | 4.614ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 20.586m | 13.859ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 7.131m | 4.701ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 2.699m | 2.755ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 5.042m | 2.467ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 17.001m | 11.407ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 17.001m | 11.407ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 17.001m | 11.407ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 9.453m | 4.746ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 7.987m | 4.618ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.321h | 43.932ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.303m | 4.766ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 19.553m | 7.697ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 22.536m | 7.827ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 27.061m | 8.540ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 17.001m | 11.407ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 7.437m | 3.485ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 11.528m | 8.354ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 12.326m | 6.409ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 5.432m | 10.479ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 7.677m | 5.703ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.832m | 4.221ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 12.015m | 4.542ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.870m | 4.389ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.375m | 3.827ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.728m | 4.461ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.302m | 4.906ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 20.586m | 13.859ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 7.131m | 4.701ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 2.699m | 2.755ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 7.112m | 11.494ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 6.065m | 3.605ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 5.898m | 3.171ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 9.045m | 4.724ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 26.846m | 24.327ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_sysrst_ctrl_reset | 26.846m | 24.327ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 26.846m | 24.327ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 53.837m | 20.971ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 53.837m | 20.971ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 8.399m | 5.658ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.417m | 18.323ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.417m | 18.323ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.417m | 18.323ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.274m | 2.891ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.516m | 2.697ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.351m | 3.007ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 5.246m | 2.830ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 8.619m | 5.309ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.613m | 2.917ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 4.995m | 3.411ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.871m | 3.329ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.510m | 2.978ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 4.755m | 2.958ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 4.749m | 2.533ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 7.437m | 3.485ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 17.001m | 11.407ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.033m | 3.069ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.797m | 3.070ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.271m | 3.073ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 5.178m | 2.836ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 23.069m | 8.046ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 10.190m | 4.760ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.770m | 2.687ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 23.069m | 8.046ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 7.184m | 3.378ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 11.090m | 6.800ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 4.763m | 2.702ms | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 57.753m | 12.804ms | 3 | 3 | 100.00 |
| chip_sw_edn_entropy_reqs | 20.083m | 5.655ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 7.437m | 3.485ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 9.333m | 3.871ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 7.782m | 3.293ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 8.619m | 5.309ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 33.943m | 9.935ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 59.390m | 19.474ms | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.041h | 21.150ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 10.883m | 5.201ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 10.883m | 5.201ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 10.883m | 5.201ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 6.604m | 3.296ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 11.528m | 8.354ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 11.528m | 8.354ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 9.241m | 4.227ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.178m | 5.056ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 19.244m | 12.319ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 12.326m | 6.409ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 14.093m | 6.328ms | 100 | 100 | 100.00 |
| chip_sw_data_integrity_escalation | 12.644m | 4.570ms | 6 | 6 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 17.001m | 11.407ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 36.657m | 25.410ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 6.604m | 3.296ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 7.437m | 3.485ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 9.241m | 4.227ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.128m | 3.040ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 36.657m | 25.410ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 6.604m | 3.296ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 7.437m | 3.485ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 9.241m | 4.227ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.128m | 3.040ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 17.001m | 11.407ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 8.607m | 4.852ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 5.042m | 2.467ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.303m | 4.766ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 19.553m | 7.697ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 22.536m | 7.827ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 27.061m | 8.540ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 17.001m | 11.407ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 5.432m | 10.479ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 5.432m | 10.479ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_init | chip_sw_flash_init | 36.657m | 25.410ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 17.811m | 6.013ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 18.188m | 5.616ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 16.517m | 4.778ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 16.748m | 4.917ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.321h | 43.932ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 36.657m | 25.410ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.423m | 3.266ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 7.437m | 3.485ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 7.987m | 4.618ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.321h | 43.932ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 7.987m | 4.618ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 7.987m | 4.618ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 7.987m | 4.618ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 7.987m | 4.618ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 14.093m | 6.328ms | 100 | 100 | 100.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 5.432m | 10.479ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 17.575m | 5.760ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 11.617m | 5.110ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 17.751m | 6.752ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 13.264m | 11.804ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 16.748m | 4.917ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 18.188m | 5.616ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.041h | 21.150ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.516m | 2.697ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 14.198m | 4.768ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.995m | 3.411ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 9.333m | 3.871ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 4.749m | 2.533ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.178m | 5.056ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.050m | 2.300ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.088m | 2.495ms | 1 | 1 | 100.00 |
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 32.029m | 13.092ms | 5 | 5 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 32.029m | 13.092ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 6.915m | 5.103ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 3.744m | 2.262ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 6.915m | 5.103ms | 3 | 3 | 100.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 10.419m | 4.841ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 17.783m | 5.404ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 4.073m | 2.366ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 5.128m | 3.040ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 10.546m | 4.553ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 10.546m | 4.553ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.978m | 2.455ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.725m | 3.108ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 4.555m | 2.704ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.034m | 2.935ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 3.509m | 1.961ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 8.694m | 3.914ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 4.101m | 2.852ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 5.762m | 3.171ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 5.253m | 2.855ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 35.362m | 10.689ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 4.798m | 2.644ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 5.978m | 5.413ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 6.873m | 5.859ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.915m | 3.148ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.166m | 3.159ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.256m | 3.301ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 3.709m | 2.980ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 4.830m | 3.001ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 8.474m | 5.241ms | 3 | 3 | 100.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 35.181m | 8.421ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.090h | 70.469ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 33.349m | 8.932ms | 3 | 3 | 100.00 |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 4.211m | 2.916ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.883m | 3.529ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.945m | 3.328ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 3.002m | 3.537ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 35.538m | 27.477ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 7.112m | 11.494ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.458h | 50.600ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.435h | 46.705ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 16.623m | 10.186ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.492h | 47.601ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 35.538m | 27.477ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 5.531m | 3.891ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 4.532m | 3.919ms | 2 | 3 | 66.67 | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_96mhz | 6.550m | 4.390ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 5.302h | 111.660ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 12.962m | 4.153ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 10.907m | 10.217ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.725h | 61.171ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 2.823h | 65.675ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 6.772m | 5.059ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 6.772m | 5.059ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 1.422h | 32.376ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.088h | 27.377ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.418m | 5.792ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 8.476m | 4.992ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 1.422h | 32.376ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.088h | 27.377ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.418m | 5.792ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 8.476m | 4.992ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.683m | 2.728ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 6.930s | 45.771us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 1.926m | 10.698ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 1.896m | 6.436ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 57.170s | 553.686us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 21.889m | 111.505ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 22.576m | 63.835ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 59.360s | 1.497ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 59.100s | 1.414ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.502m | 2.576ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 59.100s | 1.414ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.650m | 3.692ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 49.644m | 159.251ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.312m | 2.597ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 11.028m | 14.894ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 12.936m | 20.881ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 16.788m | 7.392ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 13.831m | 8.127ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 33.349m | 8.932ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 43.477m | 20.659ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 31.238m | 8.800ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 3.800h | 75.326ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 29.612m | 8.723ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 27.788m | 8.836ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 30.453m | 8.074ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 30.428m | 7.931ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 3.438h | 74.908ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 37.036m | 8.208ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 28.612m | 8.651ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 31.230m | 8.384ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 29.652m | 8.324ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 7.444h | 147.417ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 50.022m | 12.282ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 44.872m | 11.994ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 38.196m | 11.650ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 51.933m | 12.182ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 6.944h | 146.749ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 45.790m | 11.791ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 46.350m | 11.398ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 46.225m | 11.636ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 38.636m | 12.135ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 3.737h | 75.374ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 22.245m | 8.804ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 24.848m | 8.506ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 27.038m | 8.903ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 32.045m | 8.406ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 3.637h | 74.296ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 30.620m | 8.774ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 35.149m | 9.120ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 29.199m | 9.104ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 32.862m | 8.164ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_mod_exp | rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 3.769h | 74.174ms | 3 | 3 | 100.00 |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 4.071h | 74.328ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 34.587m | 8.930ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 36.040m | 8.550ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 39.766m | 8.983ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 34.982m | 9.284ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 34.836m | 8.754ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 33.401m | 8.904ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 33.279m | 8.685ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 33.463m | 9.141ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 3.951h | 75.488ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 34.743m | 8.276ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 34.954m | 9.130ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 28.616m | 8.464ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 31.399m | 8.837ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 34.080m | 8.636ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 31.653m | 8.320ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 35.589m | 9.075ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 40.053m | 10.601ms | 3 | 3 | 100.00 |
| V2 | TOTAL | 2650 | 2651 | 99.96 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.383m | 2.423ms | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 4.758m | 2.847ms | 2 | 3 | 66.67 |
| V2S | TOTAL | 5 | 6 | 83.33 | |||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_usb_fs_tx_rx | chip_sw_usbdev_stream | 0 | 1 | 0.00 | ||
| V3 | chip_sw_usb_vbus | chip_sw_usb_vbus | 0 | 0 | -- | ||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_sof | chip_usb_sof | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_usb_enumeration | chip_usb_enumeration | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 31.527m | 11.794ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 31.247m | 10.699ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 30.526m | 11.588ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 9.337m | 4.908ms | 3 | 3 | 100.00 |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 14.093m | 6.328ms | 100 | 100 | 100.00 |
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 3.445m | 2.714ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 8.829m | 4.961ms | 1 | 1 | 100.00 |
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.230s | 0 | 1 | 0.00 | |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 31.171m | 8.124ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 31.527m | 11.794ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 31.247m | 10.699ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 30.526m | 11.588ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 54.691m | 31.911ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 48.761m | 40.874ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 47.450m | 42.663ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | TOTAL | 16 | 18 | 88.89 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 11.931m | 5.682ms | 3 | 3 | 100.00 | |
| TOTAL | 2897 | 2901 | 99.86 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 19 | 19 | 19 | 100.00 |
| V2 | 270 | 270 | 269 | 99.63 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 26 | 12 | 10 | 38.46 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.87 | 95.70 | 94.57 | 98.16 | -- | 95.24 | 97.93 | 99.61 |
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
0.chip_sw_usbdev_stream.2476485832
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_stream/latest/run.log
Job ID: smart:2f1a8796-19be-40c2-9e13-c655dd408b0c
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:716) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (status_val) >> dummy.num() == * (* [*] vs * [*]) Unexpected status error *be has 1 failures:
0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1354948328
Line 1075, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log
UVM_ERROR @ 1299.290085 us: (chip_sw_base_vseq.sv:716) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Check failed (status_val) >> dummy.num() == 0 (131077 [0x20005] vs 0 [0x0]) Unexpected status error 200059be
UVM_INFO @ 1299.290085 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uart_logger.sv:25) [m_logger] Check failed (!logs_output_fd) Failed to open log for writing has 1 failures:
0.chip_sw_coremark.2471133957
Line 1044, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
UVM_FATAL @ 0.000000 us: (uart_logger.sv:25) [uvm_test_top.env.m_uart_agent0.m_logger] Check failed (!logs_output_fd) Failed to open uvm_test_top.env.m_uart_agent0.m_logger.log for writing
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === ((pend_req[d2h.d_source].opcode == Get) ? AccessAckData : AccessAck))' has 1 failures:
2.chip_sw_rv_core_ibex_lockstep_glitch.825948287
Line 1085, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
Offending '(d2h.d_opcode === ((pend_req[d2h.d_source].opcode == Get) ? AccessAckData : AccessAck))'
UVM_ERROR @ 2752.460232 us: (tlul_assert.sv:253) [ASSERT FAILED] respOpcode_M
UVM_INFO @ 2752.460232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---