c06cc3921| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 16.661m | 5.301ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 16.661m | 5.301ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 15.821m | 5.667ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 16.494m | 5.558ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 16.173m | 5.470ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 59.860m | 23.754ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 32.630m | 13.851ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 11.867m | 5.709ms | 4 | 5 | 80.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 8.524m | 4.293ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 8.524m | 4.293ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 8.524m | 4.293ms | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.706m | 2.765ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.232m | 2.480ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 3.834m | 3.287ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.304m | 3.124ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 28.986m | 9.225ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 6.842m | 7.569ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 10.273m | 5.588ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.127h | 36.000ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.590h | 64.696ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 6.407m | 8.269ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.590h | 64.696ms | 5 | 5 | 100.00 |
| chip_csr_rw | 10.273m | 5.588ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 9.960s | 237.061us | 100 | 100 | 100.00 |
| V1 | TOTAL | 222 | 223 | 99.55 | |||
| V2 | chip_sw_spi_device_tx_rx | chip_sw_spi_device_tx_rx | 8.127m | 3.399ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 3.120h | 70.715ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 11.532m | 5.946ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 11.902m | 4.613ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 6.681m | 3.304ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 4.625m | 2.864ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 9.352m | 3.818ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 9.696m | 4.164ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 10.452m | 3.905ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 11.597m | 4.495ms | 3 | 3 | 100.00 |
| V2 | chip_sw_usbdev_dpi | chip_sw_usbdev_dpi | 25.829m | 7.270ms | 1 | 1 | 100.00 |
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.869m | 5.245ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.869m | 5.245ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 4.682m | 2.862ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 4.136m | 3.391ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 5.055m | 3.893ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 25.863m | 17.207ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 8.925m | 6.274ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 11.221m | 7.156ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 28.209m | 18.432ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.315m | 2.845ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 22.271m | 8.199ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 12.830m | 5.047ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 12.830m | 5.047ms | 6 | 6 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 38.112m | 21.574ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 26.915m | 13.114ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 7.740m | 4.891ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 5.962m | 5.116ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 8.204m | 4.866ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 11.221m | 7.156ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 6.626m | 10.870ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 4.619m | 2.912ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 7.764m | 4.038ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 6.681m | 4.429ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 7.764m | 4.038ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 9.855m | 5.090ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 17.075m | 9.245ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 17.075m | 9.245ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 10.107m | 8.159ms | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs | 27.899m | 8.807ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 4.452m | 3.343ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 9.696m | 5.627ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.650m | 2.830ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 4.546m | 3.003ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.203m | 3.270ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 9.035m | 4.670ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 9.130m | 5.991ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 8.816m | 4.977ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 8.748m | 4.688ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 23.774m | 11.118ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_lc | 12.205m | 9.844ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.092m | 4.464ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.352m | 4.701ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.538m | 3.936ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.940m | 4.514ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 9.763m | 3.694ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 9.902m | 4.624ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 12.205m | 9.844ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.092m | 4.464ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.352m | 4.701ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.538m | 3.936ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.940m | 4.514ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 9.763m | 3.694ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 9.902m | 4.624ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.874m | 4.929ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 16.569m | 6.313ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 52.753m | 21.066ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.500m | 3.108ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 18.346m | 6.155ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 6.396m | 3.157ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 8.401m | 4.762ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.236m | 3.453ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.621m | 4.990ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.643m | 2.857ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 3.866m | 2.511ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 13.514m | 5.438ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 23.180m | 7.348ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.001h | 28.831ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.210m | 2.875ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.864m | 2.749ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 8.612m | 5.025ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.072m | 3.132ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 8.369m | 4.597ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 33.657m | 23.424ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 41.393m | 11.992ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 15.706m | 6.255ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.447m | 4.219ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 5.985m | 3.457ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 14.265m | 5.633ms | 100 | 100 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 8.709m | 9.989ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 25.742m | 17.259ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 6.023m | 7.089ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 17.075m | 9.245ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 23.161m | 18.545ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 30.869m | 30.150ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 36.038m | 19.429ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 10.365m | 5.319ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 8.709m | 9.989ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 7.013m | 5.077ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 47.366m | 34.373ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 6.114m | 5.259ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 8.824m | 5.000ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 53.170m | 42.633ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 17.824m | 8.429ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 39.616m | 31.782ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 4.150m | 3.077ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 14.265m | 5.633ms | 100 | 100 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 6.681m | 4.429ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 7.740m | 4.891ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 10.708m | 5.107ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 8.148m | 4.354ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 31.278m | 15.945ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.416m | 2.531ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 14.265m | 5.633ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 5.740m | 2.895ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 8.344m | 5.430ms | 3 | 3 | 100.00 |
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 14.265m | 5.633ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 27.899m | 8.807ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 6.250m | 3.461ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 31.278m | 15.945ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 9.193m | 5.422ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 10.430m | 4.120ms | 90 | 90 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 33.627m | 13.639ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 27.347m | 7.244ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 26.637m | 8.446ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.496h | 254.126ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 8.344m | 5.430ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 25.863m | 17.207ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 11.221m | 7.156ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 28.209m | 18.432ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 4.349m | 3.305ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 18.018m | 9.341ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 18.018m | 9.341ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 18.018m | 9.341ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 9.657m | 3.720ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 8.885m | 4.764ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.344h | 43.436ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.009m | 4.949ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 18.242m | 8.034ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 19.682m | 7.597ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 17.524m | 8.678ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.018m | 9.341ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 7.686m | 3.884ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 9.188m | 9.641ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 14.861m | 7.547ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 8.165m | 11.372ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 12.205m | 9.844ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.092m | 4.464ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.352m | 4.701ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.538m | 3.936ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.940m | 4.514ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 9.763m | 3.694ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 9.902m | 4.624ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 25.863m | 17.207ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 11.221m | 7.156ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 28.209m | 18.432ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 6.626m | 10.870ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 5.046m | 3.182ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 6.097m | 3.936ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 8.832m | 4.311ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 25.448m | 22.611ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_sysrst_ctrl_reset | 25.448m | 22.611ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 25.448m | 22.611ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 46.901m | 20.774ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 46.901m | 20.774ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 8.916m | 4.754ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.530m | 18.292ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.530m | 18.292ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.530m | 18.292ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 4.748m | 2.828ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 4.500m | 3.108ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.359m | 2.920ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.650m | 2.830ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 9.333m | 4.070ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.153m | 2.722ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 6.396m | 3.157ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.546m | 3.003ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 5.603m | 3.100ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 6.154m | 2.858ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.236m | 3.453ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 7.686m | 3.884ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 18.018m | 9.341ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.765m | 3.101ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.661m | 2.336ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.203m | 3.270ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.369m | 3.203ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 20.260m | 5.717ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 11.619m | 5.545ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.314m | 2.806ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 20.260m | 5.717ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 8.287m | 5.004ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 11.958m | 5.590ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.484m | 3.153ms | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 58.088m | 16.171ms | 3 | 3 | 100.00 |
| chip_sw_edn_entropy_reqs | 17.694m | 5.713ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 7.686m | 3.884ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 8.401m | 4.762ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 10.367m | 5.305ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 9.333m | 4.070ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 46.569m | 8.853ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 1.009h | 19.410ms | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 52.753m | 21.066ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 9.696m | 5.627ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 9.696m | 5.627ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 9.696m | 5.627ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 8.267m | 3.684ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 9.188m | 9.641ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 9.188m | 9.641ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 8.089m | 5.103ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.621m | 4.990ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 21.322m | 14.319ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 14.861m | 7.547ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 14.265m | 5.633ms | 100 | 100 | 100.00 |
| chip_sw_data_integrity_escalation | 12.830m | 5.047ms | 6 | 6 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 18.018m | 9.341ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 35.310m | 24.150ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.267m | 3.684ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 7.686m | 3.884ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 8.089m | 5.103ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.605m | 2.894ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 35.310m | 24.150ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.267m | 3.684ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 7.686m | 3.884ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 8.089m | 5.103ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.605m | 2.894ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 18.018m | 9.341ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 8.280m | 5.653ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 4.349m | 3.305ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.009m | 4.949ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 18.242m | 8.034ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 19.682m | 7.597ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 17.524m | 8.678ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.018m | 9.341ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 8.165m | 11.372ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 8.165m | 11.372ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_init | chip_sw_flash_init | 35.310m | 24.150ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 17.065m | 6.079ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 16.569m | 6.313ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 15.388m | 4.872ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 13.874m | 4.929ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.344h | 43.436ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 35.310m | 24.150ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 5.828m | 3.038ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 7.686m | 3.884ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 8.885m | 4.764ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.344h | 43.436ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 8.885m | 4.764ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 8.885m | 4.764ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 8.885m | 4.764ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 8.885m | 4.764ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 14.265m | 5.633ms | 100 | 100 | 100.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 8.165m | 11.372ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 16.113m | 5.591ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 11.646m | 5.074ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 15.706m | 6.255ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 12.526m | 10.797ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.874m | 4.929ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 16.569m | 6.313ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 52.753m | 21.066ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.500m | 3.108ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 18.346m | 6.155ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 6.396m | 3.157ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 8.401m | 4.762ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.236m | 3.453ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.621m | 4.990ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.643m | 2.857ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 6.912m | 3.452ms | 1 | 1 | 100.00 |
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 31.807m | 15.340ms | 5 | 5 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 31.807m | 15.340ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.737m | 5.245ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.952m | 3.621ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.737m | 5.245ms | 3 | 3 | 100.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 14.872m | 4.486ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 16.015m | 5.397ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 4.987m | 3.639ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 4.605m | 2.894ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 10.708m | 5.107ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 10.708m | 5.107ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.429m | 2.978ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.391m | 2.471ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 4.412m | 2.708ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.288m | 2.546ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 5.183m | 2.875ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 9.722m | 3.845ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 5.120m | 2.722ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.082m | 4.029ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 4.786m | 2.831ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 34.421m | 10.359ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 4.705m | 2.750ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 6.681m | 4.429ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 7.009m | 5.358ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.353m | 2.419ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.867m | 2.936ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.036m | 2.280ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.096m | 2.484ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 4.911m | 2.743ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 10.385m | 5.749ms | 3 | 3 | 100.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 28.986m | 9.225ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.120h | 70.715ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 24.935m | 8.377ms | 3 | 3 | 100.00 |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 3.186m | 3.260ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 3.109m | 3.473ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.634m | 2.765ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 2.756m | 3.076ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 33.470m | 20.452ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 6.626m | 10.870ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.385h | 50.837ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.573h | 49.116ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 13.937m | 8.568ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.378h | 47.072ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 33.470m | 20.452ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 5.170m | 4.839ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 5.889m | 4.453ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_96mhz | 6.047m | 4.600ms | 2 | 3 | 66.67 | ||
| rom_volatile_raw_unlock | 5.419h | 111.855ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 10.100m | 4.071ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 8.363m | 9.467ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.425h | 60.192ms | 2 | 3 | 66.67 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 2.945h | 66.608ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 6.267m | 4.128ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 6.267m | 4.128ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.590h | 64.696ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.059h | 26.544ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.842m | 7.569ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 10.273m | 5.588ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.590h | 64.696ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.059h | 26.544ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.842m | 7.569ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 10.273m | 5.588ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.484m | 2.546ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 7.080s | 43.181us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 1.937m | 11.503ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.322m | 7.680ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 59.080s | 562.432us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 21.728m | 98.013ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 22.031m | 70.974ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 59.580s | 1.459ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 54.500s | 1.386ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.544m | 2.491ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 54.500s | 1.386ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.477m | 3.324ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 50.773m | 157.291ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.298m | 2.485ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 13.813m | 18.946ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 10.883m | 16.756ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 17.490m | 7.030ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 14.894m | 10.239ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 24.935m | 8.377ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 44.753m | 23.284ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 31.100m | 8.636ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 3.724h | 75.401ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 27.966m | 8.849ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 29.922m | 8.012ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 27.575m | 8.440ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 33.767m | 9.117ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 3.703h | 75.218ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 28.300m | 8.381ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 24.769m | 8.848ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 25.774m | 8.805ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 28.227m | 8.200ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 6.971h | 146.474ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 42.549m | 12.234ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 54.635m | 12.290ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 40.321m | 12.351ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 45.119m | 11.900ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 7.294h | 146.215ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 34.687m | 12.052ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 39.716m | 11.866ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 49.318m | 12.393ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 51.221m | 12.172ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 3.603h | 74.897ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 30.354m | 8.431ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 30.251m | 8.669ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 31.329m | 9.078ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 29.417m | 7.703ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 3.626h | 74.457ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 24.361m | 8.500ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 27.278m | 8.718ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 28.984m | 8.309ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 27.023m | 8.604ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_mod_exp | rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 3.608h | 74.240ms | 3 | 3 | 100.00 |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 3.956h | 74.248ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 35.143m | 9.010ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 28.937m | 8.718ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 28.877m | 9.231ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 33.485m | 8.995ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 34.312m | 8.422ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 34.013m | 8.723ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 30.472m | 8.641ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 35.662m | 9.117ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 3.791h | 74.707ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 28.058m | 9.123ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 36.336m | 8.902ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 29.259m | 9.187ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 27.344m | 8.213ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 26.201m | 8.247ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 25.182m | 9.015ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 36.917m | 9.384ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 38.103m | 10.593ms | 3 | 3 | 100.00 |
| V2 | TOTAL | 2649 | 2651 | 99.92 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.553m | 2.762ms | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 2.619m | 2.876ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 6 | 6 | 100.00 | |||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_usb_fs_tx_rx | chip_sw_usbdev_stream | 0 | 1 | 0.00 | ||
| V3 | chip_sw_usb_vbus | chip_sw_usb_vbus | 0 | 0 | -- | ||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_sof | chip_usb_sof | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_usb_enumeration | chip_usb_enumeration | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 29.235m | 11.825ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 28.805m | 11.689ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 22.988m | 10.666ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 9.079m | 6.046ms | 3 | 3 | 100.00 |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 14.265m | 5.633ms | 100 | 100 | 100.00 |
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 2.208m | 2.183ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 11.920m | 6.163ms | 1 | 1 | 100.00 |
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.530s | 0 | 1 | 0.00 | |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 33.834m | 8.306ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 29.235m | 11.825ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 28.805m | 11.689ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 22.988m | 10.666ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 47.766m | 42.141ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 56.273m | 43.240ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 43.406m | 31.806ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | TOTAL | 16 | 18 | 88.89 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 11.822m | 5.489ms | 3 | 3 | 100.00 | |
| TOTAL | 2896 | 2901 | 99.83 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 19 | 19 | 18 | 94.74 |
| V2 | 270 | 270 | 268 | 99.26 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 26 | 12 | 10 | 38.46 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.85 | 95.74 | 94.51 | 98.09 | -- | 95.15 | 97.93 | 99.67 |
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
Test chip_sw_usbdev_stream has 1 failures.
0.chip_sw_usbdev_stream.2774852051
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_stream/latest/run.log
Job ID: smart:8f8d07af-1b3e-4333-b32c-8269abc27da4
Test chip_sw_exit_test_unlocked_bootstrap has 1 failures.
0.chip_sw_exit_test_unlocked_bootstrap.2189851686
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job ID: smart:6636b876-bf6d-4c6b-bbce-8cc7198c09c8
Test chip_sw_uart_tx_rx_alt_clk_freq_low_speed has 1 failures.
2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3011915094
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest/run.log
Job ID: smart:00978f2f-4ee7-41af-91c2-a4c42da64ab0
UVM_FATAL @ * us: (uart_logger.sv:25) [m_logger] Check failed (!logs_output_fd) Failed to open log for writing has 1 failures:
0.chip_sw_coremark.3133562712
Line 1047, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
UVM_FATAL @ 0.000000 us: (uart_logger.sv:25) [uvm_test_top.env.m_uart_agent0.m_logger] Check failed (!logs_output_fd) Failed to open uvm_test_top.env.m_uart_agent0.m_logger.log for writing
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:716) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (status_val) >> dummy.num() == * (* [*] vs * [*]) Unexpected status error *cdf* has 1 failures:
2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_96mhz.2724620273
Line 1069, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_96mhz/latest/run.log
UVM_ERROR @ 1673.851851 us: (chip_sw_base_vseq.sv:716) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Check failed (status_val) >> dummy.num() == 0 (44 [0x2c] vs 0 [0x0]) Unexpected status error 2cdf0
UVM_INFO @ 1673.851851 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---