Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	107	21	16.41

User Defined Bins for cp_num_of_outstanding

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[22]	0	1	1
values[23]	0	1	1
values[24]	0	1	1
values[25]	0	1	1
values[26]	0	1	1
values[27]	0	1	1
values[28]	0	1	1
values[29]	0	1	1
values[30]	0	1	1
values[31]	0	1	1
values[32]	0	1	1
values[33]	0	1	1
values[34]	0	1	1
values[35]	0	1	1
values[36]	0	1	1
values[37]	0	1	1
values[38]	0	1	1
values[39]	0	1	1
values[40]	0	1	1
values[41]	0	1	1
values[42]	0	1	1
values[43]	0	1	1
values[44]	0	1	1
values[45]	0	1	1
values[46]	0	1	1
values[47]	0	1	1
values[48]	0	1	1
values[49]	0	1	1
values[50]	0	1	1
values[51]	0	1	1
values[52]	0	1	1
values[53]	0	1	1
values[54]	0	1	1
values[55]	0	1	1
values[56]	0	1	1
values[57]	0	1	1
values[58]	0	1	1
values[59]	0	1	1
values[60]	0	1	1
values[61]	0	1	1
values[62]	0	1	1
values[63]	0	1	1
values[64]	0	1	1
values[65]	0	1	1
values[66]	0	1	1
values[67]	0	1	1
values[68]	0	1	1
values[69]	0	1	1
values[70]	0	1	1
values[71]	0	1	1
values[72]	0	1	1
values[73]	0	1	1
values[74]	0	1	1
values[75]	0	1	1
values[76]	0	1	1
values[77]	0	1	1
values[78]	0	1	1
values[79]	0	1	1
values[80]	0	1	1
values[81]	0	1	1
values[82]	0	1	1
values[83]	0	1	1
values[84]	0	1	1
values[85]	0	1	1
values[86]	0	1	1
values[87]	0	1	1
values[88]	0	1	1
values[89]	0	1	1
values[90]	0	1	1
values[91]	0	1	1
values[92]	0	1	1
values[93]	0	1	1
values[94]	0	1	1
values[95]	0	1	1
values[96]	0	1	1
values[97]	0	1	1
values[98]	0	1	1
values[99]	0	1	1
values[100]	0	1	1
values[101]	0	1	1
values[102]	0	1	1
values[103]	0	1	1
values[104]	0	1	1
values[105]	0	1	1
values[106]	0	1	1
values[107]	0	1	1
values[108]	0	1	1
values[109]	0	1	1
values[110]	0	1	1
values[111]	0	1	1
values[112]	0	1	1
values[113]	0	1	1
values[114]	0	1	1
values[115]	0	1	1
values[116]	0	1	1
values[117]	0	1	1
values[118]	0	1	1
values[119]	0	1	1
values[120]	0	1	1
values[121]	0	1	1
values[122]	0	1	1
values[123]	0	1	1
values[124]	0	1	1
values[125]	0	1	1
values[126]	0	1	1
values[127]	0	1	1
values[128]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	324100	1			T4	205		T5	101		T21	205
values[2]	57500	1			T5	1		T49	1		T46	2
values[3]	31700	1			T51	110		T59	207		T60	207
values[4]	15900	1			T51	49		T59	110		T60	110
values[5]	6500	1			T51	25		T59	40		T60	40
values[6]	4000	1			T51	14		T59	26		T60	26
values[7]	5500	1			T51	23		T59	32		T60	32
values[8]	5400	1			T51	21		T59	33		T60	33
values[9]	6500	1			T51	40		T59	25		T60	25
values[10]	4800	1			T51	37		T59	11		T60	11
values[11]	6400	1			T51	63		T59	1		T60	1
values[12]	4400	1			T51	44		T76	44		T88	44
values[13]	3600	1			T51	36		T76	36		T88	36
values[14]	4300	1			T51	43		T76	43		T88	43
values[15]	2600	1			T51	26		T76	26		T88	26
values[16]	1400	1			T51	14		T76	14		T88	14
values[17]	1100	1			T51	11		T76	11		T88	11
values[18]	600	1			T51	6		T76	6		T88	6
values[19]	500	1			T51	5		T76	5		T88	5
values[20]	600	1			T51	6		T76	6		T88	6
values[21]	200	1			T51	2		T76	2		T88	2