Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_max_outstanding

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	63	65	50.78

User Defined Bins for cp_num_of_outstanding

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[66]	0	1	1
values[67]	0	1	1
values[68]	0	1	1
values[69]	0	1	1
values[70]	0	1	1
values[71]	0	1	1
values[72]	0	1	1
values[73]	0	1	1
values[74]	0	1	1
values[75]	0	1	1
values[76]	0	1	1
values[77]	0	1	1
values[78]	0	1	1
values[79]	0	1	1
values[80]	0	1	1
values[81]	0	1	1
values[82]	0	1	1
values[83]	0	1	1
values[84]	0	1	1
values[85]	0	1	1
values[86]	0	1	1
values[87]	0	1	1
values[88]	0	1	1
values[89]	0	1	1
values[90]	0	1	1
values[91]	0	1	1
values[92]	0	1	1
values[93]	0	1	1
values[94]	0	1	1
values[95]	0	1	1
values[96]	0	1	1
values[97]	0	1	1
values[98]	0	1	1
values[99]	0	1	1
values[100]	0	1	1
values[101]	0	1	1
values[102]	0	1	1
values[103]	0	1	1
values[104]	0	1	1
values[105]	0	1	1
values[106]	0	1	1
values[107]	0	1	1
values[108]	0	1	1
values[109]	0	1	1
values[110]	0	1	1
values[111]	0	1	1
values[112]	0	1	1
values[113]	0	1	1
values[114]	0	1	1
values[115]	0	1	1
values[116]	0	1	1
values[117]	0	1	1
values[118]	0	1	1
values[119]	0	1	1
values[120]	0	1	1
values[121]	0	1	1
values[122]	0	1	1
values[123]	0	1	1
values[124]	0	1	1
values[125]	0	1	1
values[126]	0	1	1
values[127]	0	1	1
values[128]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
values[1]	224200	1		T4	192	T5	96	T21	192
values[2]	10500	1		T4	2	T5	1	T21	2
values[3]	2300	1		T50	1	T51	11	T58	2
values[4]	2300	1		T51	10	T59	13	T60	13
values[5]	1200	1		T51	6	T59	6	T60	6
values[6]	1400	1		T51	6	T59	8	T60	8
values[7]	2400	1		T51	10	T59	14	T60	14
values[8]	1700	1		T51	5	T59	12	T60	12
values[9]	1700	1		T51	7	T59	10	T60	10
values[10]	800	1		T51	3	T59	5	T60	5
values[11]	1800	1		T51	10	T59	8	T60	8
values[12]	3600	1		T51	28	T59	8	T60	8
values[13]	900	1		T51	5	T59	4	T60	4
values[14]	900	1		T51	5	T59	4	T60	4
values[15]	1200	1		T51	6	T59	6	T60	6
values[16]	2500	1		T51	10	T59	15	T60	15
values[17]	2200	1		T51	16	T59	6	T60	6
values[18]	1200	1		T51	4	T59	8	T60	8
values[19]	1100	1		T51	2	T59	9	T60	9
values[20]	1100	1		T51	6	T59	5	T60	5
values[21]	900	1		T51	3	T59	6	T60	6
values[22]	1100	1		T51	6	T59	5	T60	5
values[23]	1700	1		T51	10	T59	7	T60	7
values[24]	900	1		T51	6	T59	3	T60	3
values[25]	1300	1		T51	5	T59	8	T60	8
values[26]	1800	1		T51	2	T59	16	T60	16
values[27]	1400	1		T51	4	T59	10	T60	10
values[28]	1100	1		T51	6	T59	5	T60	5
values[29]	1600	1		T51	10	T59	6	T60	6
values[30]	2600	1		T51	15	T59	11	T60	11
values[31]	2500	1		T51	11	T59	14	T60	14
values[32]	2800	1		T51	8	T59	20	T60	20
values[33]	1500	1		T51	5	T59	10	T60	10
values[34]	1300	1		T51	7	T59	6	T60	6
values[35]	1400	1		T51	3	T59	11	T60	11
values[36]	1100	1		T51	6	T59	5	T60	5
values[37]	1500	1		T51	6	T59	9	T60	9
values[38]	1200	1		T51	5	T59	7	T60	7
values[39]	1200	1		T51	9	T59	3	T60	3
values[40]	1300	1		T51	7	T59	6	T60	6
values[41]	1200	1		T51	5	T59	7	T60	7
values[42]	700	1		T51	6	T59	1	T60	1
values[43]	800	1		T51	7	T59	1	T60	1
values[44]	600	1		T51	5	T59	1	T60	1
values[45]	700	1		T51	7	T76	7	T88	7
values[46]	600	1		T51	6	T76	6	T88	6
values[47]	600	1		T51	6	T76	6	T88	6
values[48]	600	1		T51	6	T76	6	T88	6
values[49]	1000	1		T51	10	T76	10	T88	10
values[50]	1000	1		T51	10	T76	10	T88	10
values[51]	1300	1		T51	13	T76	13	T88	13
values[52]	1100	1		T51	11	T76	11	T88	11
values[53]	1000	1		T51	10	T76	10	T88	10
values[54]	400	1		T51	4	T76	4	T88	4
values[55]	400	1		T51	4	T76	4	T88	4
values[56]	1600	1		T51	16	T76	16	T88	16
values[57]	400	1		T51	4	T76	4	T88	4
values[58]	100	1		T51	1	T76	1	T88	1
values[59]	100	1		T51	1	T76	1	T88	1
values[60]	400	1		T51	4	T76	4	T88	4
values[61]	900	1		T51	9	T76	9	T88	9
values[62]	500	1		T51	5	T76	5	T88	5
values[63]	800	1		T51	8	T76	8	T88	8
values[64]	1500	1		T51	15	T76	15	T88	15
values[65]	300	1		T51	3	T76	3	T88	3