Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	317600	1			T4	177		T5	83		T6	90
values[2]	52400	1			T4	5		T6	97		T21	5
values[3]	23800	1			T6	56		T51	85		T58	3
values[4]	13300	1			T6	54		T51	42		T70	1
values[5]	8300	1			T6	25		T51	27		T70	1
values[6]	4000	1			T6	16		T51	10		T70	1
values[7]	600	1			T6	4		T51	1		T70	1
values[8]	300	1			T6	2		T70	1		T74	2
values[9]	100	1			T70	1		T79	1		T92	1
values[10]	100	1			T70	1		T79	1		T92	1
values[11]	100	1			T70	1		T79	1		T92	1
values[12]	100	1			T70	1		T79	1		T92	1
values[13]	100	1			T70	1		T79	1		T92	1
values[14]	100	1			T70	1		T79	1		T92	1
values[15]	100	1			T70	1		T79	1		T92	1
values[16]	100	1			T70	1		T79	1		T92	1
values[17]	100	1			T70	1		T79	1		T92	1
values[18]	100	1			T70	1		T79	1		T92	1
values[19]	100	1			T70	1		T79	1		T92	1
values[20]	100	1			T70	1		T79	1		T92	1
values[21]	100	1			T70	1		T79	1		T92	1
values[22]	100	1			T70	1		T79	1		T92	1
values[23]	100	1			T70	1		T79	1		T92	1
values[24]	100	1			T70	1		T79	1		T92	1
values[25]	100	1			T70	1		T79	1		T92	1
values[26]	100	1			T70	1		T79	1		T92	1
values[27]	100	1			T70	1		T79	1		T92	1
values[28]	100	1			T70	1		T79	1		T92	1
values[29]	100	1			T70	1		T79	1		T92	1
values[30]	100	1			T70	1		T79	1		T92	1
values[31]	100	1			T70	1		T79	1		T92	1
values[32]	100	1			T70	1		T79	1		T92	1
values[33]	100	1			T70	1		T79	1		T92	1
values[34]	100	1			T70	1		T79	1		T92	1
values[35]	100	1			T70	1		T79	1		T92	1
values[36]	100	1			T70	1		T79	1		T92	1
values[37]	100	1			T70	1		T79	1		T92	1
values[38]	100	1			T70	1		T79	1		T92	1
values[39]	100	1			T70	1		T79	1		T92	1
values[40]	100	1			T70	1		T79	1		T92	1
values[41]	100	1			T70	1		T79	1		T92	1
values[42]	100	1			T70	1		T79	1		T92	1
values[43]	100	1			T70	1		T79	1		T92	1
values[44]	100	1			T70	1		T79	1		T92	1
values[45]	100	1			T70	1		T79	1		T92	1
values[46]	100	1			T70	1		T79	1		T92	1
values[47]	100	1			T70	1		T79	1		T92	1
values[48]	100	1			T70	1		T79	1		T92	1
values[49]	100	1			T70	1		T79	1		T92	1
values[50]	100	1			T70	1		T79	1		T92	1
values[51]	100	1			T70	1		T79	1		T92	1
values[52]	100	1			T70	1		T79	1		T92	1
values[53]	100	1			T70	1		T79	1		T92	1
values[54]	100	1			T70	1		T79	1		T92	1
values[55]	100	1			T70	1		T79	1		T92	1
values[56]	100	1			T70	1		T79	1		T92	1
values[57]	100	1			T70	1		T79	1		T92	1
values[58]	100	1			T70	1		T79	1		T92	1
values[59]	100	1			T70	1		T79	1		T92	1
values[60]	100	1			T70	1		T79	1		T92	1
values[61]	100	1			T70	1		T79	1		T92	1
values[62]	100	1			T70	1		T79	1		T92	1
values[63]	100	1			T70	1		T79	1		T92	1
values[64]	100	1			T70	1		T79	1		T92	1
values[65]	100	1			T70	1		T79	1		T92	1
values[66]	100	1			T70	1		T79	1		T92	1
values[67]	100	1			T70	1		T79	1		T92	1
values[68]	100	1			T70	1		T79	1		T92	1
values[69]	100	1			T70	1		T79	1		T92	1
values[70]	100	1			T70	1		T79	1		T92	1
values[71]	100	1			T70	1		T79	1		T92	1
values[72]	100	1			T70	1		T79	1		T92	1
values[73]	100	1			T70	1		T79	1		T92	1
values[74]	100	1			T70	1		T79	1		T92	1
values[75]	100	1			T70	1		T79	1		T92	1
values[76]	100	1			T70	1		T79	1		T92	1
values[77]	100	1			T70	1		T79	1		T92	1
values[78]	100	1			T70	1		T79	1		T92	1
values[79]	100	1			T70	1		T79	1		T92	1
values[80]	100	1			T70	1		T79	1		T92	1
values[81]	100	1			T70	1		T79	1		T92	1
values[82]	100	1			T70	1		T79	1		T92	1
values[83]	100	1			T70	1		T79	1		T92	1
values[84]	100	1			T70	1		T79	1		T92	1
values[85]	100	1			T70	1		T79	1		T92	1
values[86]	100	1			T70	1		T79	1		T92	1
values[87]	100	1			T70	1		T79	1		T92	1
values[88]	100	1			T70	1		T79	1		T92	1
values[89]	100	1			T70	1		T79	1		T92	1
values[90]	100	1			T70	1		T79	1		T92	1
values[91]	100	1			T70	1		T79	1		T92	1
values[92]	100	1			T70	1		T79	1		T92	1
values[93]	100	1			T70	1		T79	1		T92	1
values[94]	100	1			T70	1		T79	1		T92	1
values[95]	100	1			T70	1		T79	1		T92	1
values[96]	100	1			T70	1		T79	1		T92	1
values[97]	100	1			T70	1		T79	1		T92	1
values[98]	100	1			T70	1		T79	1		T92	1
values[99]	100	1			T70	1		T79	1		T92	1
values[100]	100	1			T70	1		T79	1		T92	1
values[101]	100	1			T70	1		T79	1		T92	1
values[102]	100	1			T70	1		T79	1		T92	1
values[103]	200	1			T70	2		T79	2		T92	2
values[104]	100	1			T70	1		T79	1		T92	1
values[105]	100	1			T70	1		T79	1		T92	1
values[106]	100	1			T70	1		T79	1		T92	1
values[107]	100	1			T70	1		T79	1		T92	1
values[108]	200	1			T70	2		T79	2		T92	2
values[109]	100	1			T70	1		T79	1		T92	1
values[110]	100	1			T70	1		T79	1		T92	1
values[111]	100	1			T70	1		T79	1		T92	1
values[112]	100	1			T70	1		T79	1		T92	1
values[113]	100	1			T70	1		T79	1		T92	1
values[114]	100	1			T70	1		T79	1		T92	1
values[115]	100	1			T70	1		T79	1		T92	1
values[116]	100	1			T70	1		T79	1		T92	1
values[117]	100	1			T70	1		T79	1		T92	1
values[118]	100	1			T70	1		T79	1		T92	1
values[119]	100	1			T70	1		T79	1		T92	1
values[120]	100	1			T70	1		T79	1		T92	1
values[121]	100	1			T70	1		T79	1		T92	1
values[122]	100	1			T70	1		T79	1		T92	1
values[123]	100	1			T70	1		T79	1		T92	1
values[124]	300	1			T70	3		T79	3		T92	3
values[125]	200	1			T70	2		T79	2		T92	2
values[126]	400	1			T70	4		T79	4		T92	4
values[127]	7500	1			T70	75		T79	75		T92	75
values[128]	34300	1			T70	343		T79	343		T92	343