Unified Coverage Report :: Group Instance : rv_core_ibex__cfg

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T50	1		T58	1		T71	1
small_delay	1100	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T50	1		T78	1		T95	1
small_delay	1400	1			T4	1		T5	1		T6	1
zero	200	1			T62	1		T93	1		T94	1