Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	1	49	98.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	1	49	98.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	1	49	98.00

User Defined Bins for cp_dev

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_values[8]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	400	1			T4	1		T6	1		T21	1
all_values[1]	1400	1			T4	5		T21	5		T46	5
all_values[2]	800	1			T4	4		T21	4		T46	4
all_values[3]	1000	1			T4	4		T6	1		T21	4
all_values[4]	200	1			T4	1		T21	1		T46	1
all_values[5]	400	1			T4	2		T21	2		T46	2
all_values[6]	800	1			T4	1		T6	1		T21	1
all_values[7]	1600	1			T4	4		T6	1		T21	4
all_values[9]	1200	1			T4	5		T21	5		T46	5
all_values[10]	800	1			T4	3		T21	3		T46	3
all_values[11]	600	1			T4	3		T21	3		T46	3
all_values[12]	1600	1			T4	4		T6	2		T21	4
all_values[13]	800	1			T4	1		T21	1		T46	1
all_values[14]	800	1			T4	3		T6	1		T21	3
all_values[15]	200	1			T51	1		T59	1		T60	1
all_values[16]	600	1			T4	1		T6	1		T21	1
all_values[17]	1000	1			T4	3		T6	1		T21	3
all_values[18]	800	1			T4	4		T21	4		T46	4
all_values[19]	600	1			T4	3		T21	3		T46	3
all_values[20]	600	1			T51	3		T59	3		T60	3
all_values[21]	400	1			T4	2		T21	2		T46	2
all_values[22]	800	1			T4	1		T6	1		T21	1
all_values[23]	200	1			T4	1		T21	1		T46	1
all_values[24]	1000	1			T4	5		T21	5		T46	5
all_values[25]	800	1			T4	2		T21	2		T46	2
all_values[26]	1400	1			T4	6		T6	1		T21	6
all_values[27]	400	1			T4	2		T21	2		T46	2
all_values[28]	600	1			T4	3		T21	3		T46	3
all_values[29]	400	1			T4	1		T6	1		T21	1
all_values[30]	800	1			T4	4		T21	4		T46	4
all_values[31]	600	1			T4	1		T21	1		T46	1
all_values[32]	1000	1			T4	4		T6	1		T21	4
all_values[33]	400	1			T4	2		T21	2		T46	2
all_values[34]	1600	1			T4	6		T21	6		T46	6
all_values[35]	200	1			T4	1		T21	1		T46	1
all_values[36]	200	1			T4	1		T21	1		T46	1
all_values[37]	800	1			T4	2		T21	2		T46	2
all_values[38]	400	1			T4	2		T21	2		T46	2
all_values[39]	600	1			T4	2		T6	1		T21	2
all_values[40]	1200	1			T4	3		T6	1		T21	3
all_values[41]	400	1			T4	2		T21	2		T46	2
all_values[42]	200	1			T4	1		T21	1		T46	1
all_values[43]	600	1			T4	1		T6	1		T21	1
all_values[44]	600	1			T4	2		T6	1		T21	2
all_values[45]	1000	1			T4	5		T21	5		T46	5
all_values[46]	800	1			T4	3		T21	3		T46	3
all_values[47]	200	1			T4	1		T21	1		T46	1
all_values[48]	400	1			T4	2		T21	2		T46	2
all_values[49]	600	1			T4	2		T6	1		T21	2