Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	5800	1			T4	28		T5	2		T21	28
all_values[1]	5200	1			T4	21		T5	2		T21	21
all_values[2]	5300	1			T4	23		T5	1		T21	23
all_values[3]	5500	1			T4	21		T5	3		T21	21
all_values[4]	3900	1			T4	15		T5	3		T21	15
all_values[5]	3900	1			T4	18		T5	3		T21	18
all_values[6]	5400	1			T4	20		T5	2		T21	20
all_values[7]	5200	1			T4	23		T21	23		T46	23
all_values[8]	4500	1			T4	21		T5	3		T21	21
all_values[9]	7100	1			T4	31		T5	1		T21	31
all_values[10]	5300	1			T4	22		T5	3		T21	22
all_values[11]	5200	1			T4	20		T5	10		T21	20
all_values[12]	4600	1			T4	20		T5	4		T21	20
all_values[13]	4500	1			T4	19		T5	3		T21	19
all_values[14]	4700	1			T4	19		T5	5		T21	19
all_values[15]	5200	1			T4	23		T5	6		T21	23
all_values[16]	5100	1			T4	24		T5	3		T21	24
all_values[17]	3200	1			T4	14		T5	2		T21	14
all_values[18]	4400	1			T4	19		T21	19		T46	19
all_values[19]	4800	1			T4	19		T5	4		T21	19
all_values[20]	5600	1			T4	27		T5	2		T21	27
all_values[21]	4800	1			T4	22		T21	22		T46	22
all_values[22]	5300	1			T4	25		T5	3		T21	25
all_values[23]	6400	1			T4	26		T5	4		T21	26
all_values[24]	5000	1			T4	19		T5	4		T21	19
all_values[25]	4100	1			T4	19		T5	1		T21	19
all_values[26]	4700	1			T4	21		T5	3		T21	21
all_values[27]	3800	1			T4	16		T5	6		T21	16
all_values[28]	4900	1			T4	21		T5	5		T21	21
all_values[29]	6400	1			T4	27		T5	6		T21	27
all_values[30]	4700	1			T4	21		T5	3		T21	21
all_values[31]	5600	1			T4	23		T5	4		T21	23
all_values[32]	4400	1			T4	18		T5	4		T21	18
all_values[33]	5700	1			T4	25		T5	1		T21	25
all_values[34]	6300	1			T4	26		T5	3		T21	26
all_values[35]	3200	1			T4	15		T21	15		T46	15
all_values[36]	4800	1			T4	22		T5	2		T21	22
all_values[37]	4200	1			T4	16		T5	4		T21	16
all_values[38]	5700	1			T4	24		T5	5		T21	24
all_values[39]	6700	1			T4	30		T5	1		T21	30
all_values[40]	5000	1			T4	22		T5	4		T21	22
all_values[41]	6700	1			T4	29		T5	3		T21	29
all_values[42]	4200	1			T4	17		T5	2		T21	17
all_values[43]	4600	1			T4	21		T5	2		T21	21
all_values[44]	5200	1			T4	24		T5	2		T21	24
all_values[45]	4100	1			T4	18		T5	1		T21	18
all_values[46]	6500	1			T4	25		T5	7		T21	25
all_values[47]	3600	1			T4	15		T5	2		T21	15
all_values[48]	4200	1			T4	19		T5	2		T21	19
all_values[49]	3600	1			T4	17		T21	17		T46	17
all_values[50]	4200	1			T4	20		T5	2		T21	20
all_values[51]	4800	1			T4	17		T5	2		T21	17
all_values[52]	5300	1			T4	24		T5	3		T21	24
all_values[53]	5400	1			T4	23		T5	4		T21	23
all_values[54]	5100	1			T4	22		T5	7		T21	22
all_values[55]	6200	1			T4	28		T5	2		T21	28
all_values[56]	6800	1			T4	30		T5	6		T21	30
all_values[57]	5600	1			T4	23		T5	2		T21	23
all_values[58]	4100	1			T4	17		T5	3		T21	17
all_values[59]	8300	1			T4	38		T5	3		T21	38
all_values[60]	4500	1			T4	21		T5	1		T21	21
all_values[61]	4300	1			T4	17		T5	1		T21	17
all_values[62]	5900	1			T4	25		T5	1		T21	25
all_values[63]	4700	1			T4	22		T5	1		T21	22