Unified Coverage Report :: Cond split page

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 LINE       61
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       73
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       80
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Not Covered
0	1	0	Covered	T46,T47,T51
1	0	0	Not Covered

 LINE       122
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T46,T47,T51
0	1	0	Covered	T1,T3,T45
1	0	0	Covered	T4,T5,T6

 LINE       122
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       16563
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO0_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       16564
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO1_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16565
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO2_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16566
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO3_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16567
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO4_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16568
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO5_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16569
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO6_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16570
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO7_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16571
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO8_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16572
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO9_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16573
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO10_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16574
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO11_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16575
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO12_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16576
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO13_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16577
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO14_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16578
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO15_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16579
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO16_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16580
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO17_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16581
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO18_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16582
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO19_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16583
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO20_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16584
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO21_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16585
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO22_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16586
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO23_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16587
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO24_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16588
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO25_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16589
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO26_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16590
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO27_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16591
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO28_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16592
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO29_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16593
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO30_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16594
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO31_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16595
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO32_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16596
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO33_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16597
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO34_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16598
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO35_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16599
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO36_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16600
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO37_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16601
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO38_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16602
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO39_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16603
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO40_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16604
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO41_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16605
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO42_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16606
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO43_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16607
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO44_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16608
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO45_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16609
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO46_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16610
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO47_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16611
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO48_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16612
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO49_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16613
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO50_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16614
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO51_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16615
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO52_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16616
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO53_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16617
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO54_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16618
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO55_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16619
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO56_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16620
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO57_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16621
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO58_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16622
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO59_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16623
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO60_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16624
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO61_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16625
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO62_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16626
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO63_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16627
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO64_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16628
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO65_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16629
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO66_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16630
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO67_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16631
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO68_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16632
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO69_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16633
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO70_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16634
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO71_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16635
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO72_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16636
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO73_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16637
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO74_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16638
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO75_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16639
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO76_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16640
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO77_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16641
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO78_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16642
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO79_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16643
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO80_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16644
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO81_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16645
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO82_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16646
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO83_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16647
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO84_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16648
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO85_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16649
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO86_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16650
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO87_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16651
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO88_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16652
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO89_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16653
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO90_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16654
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO91_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16655
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO92_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16656
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO93_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16657
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO94_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16658
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO95_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16659
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO96_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16660
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO97_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16661
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO98_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16662
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO99_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16663
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO100_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16664
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO101_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16665
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO102_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16666
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO103_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16667
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO104_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16668
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO105_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16669
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO106_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16670
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO107_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16671
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO108_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16672
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO109_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16673
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO110_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16674
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO111_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16675
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO112_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16676
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO113_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16677
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO114_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16678
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO115_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16679
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO116_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16680
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO117_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16681
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO118_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16682
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO119_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16683
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO120_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16684
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO121_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16685
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO122_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7

 LINE       16686
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO123_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16687
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO124_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16688
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO125_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16689
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO126_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16690
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO127_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16691
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO128_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16692
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO129_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16693
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO130_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16694
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO131_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       16695
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO132_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T7