Unified Coverage Report :: Cond split page

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 LINE       31792
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31793
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31794
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31795
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T49,T46

 LINE       31796
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31797
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31798
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31799
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       31800
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31801
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31802
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31803
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31804
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T49

 LINE       31805
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31806
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31807
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       31808
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31809
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       31810
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31811
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31812
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31813
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31814
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31815
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T50,T1,T51

 LINE       31816
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31817
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T51,T2

 LINE       31818
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31819
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31820
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T50

 LINE       31821
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31822
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T49

 LINE       31823
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T49,T1

 LINE       31824
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31825
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31826
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31827
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31828
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31829
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31830
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31831
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       31832
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31833
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T49

 LINE       31834
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       31835
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T50

 LINE       31836
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T21,T50

 LINE       31837
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31838
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31839
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31840
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31841
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       31842
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T51

 LINE       31843
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31844
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31845
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T49

 LINE       31846
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T49,T46

 LINE       31847
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31848
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31849
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31850
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31851
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T50,T1

 LINE       31852
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T46,T1,T47

 LINE       31853
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31854
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T50

 LINE       31855
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31856
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T49

 LINE       31857
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31858
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       31859
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T21,T50

 LINE       31860
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T50

 LINE       31861
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31862
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T51

 LINE       31863
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T50,T1

 LINE       31864
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31865
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31866
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T50

 LINE       31867
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T21,T46

 LINE       31868
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31869
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31870
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T49

 LINE       31871
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T21,T46

 LINE       31872
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31873
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T46,T50,T1

 LINE       31874
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31875
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31876
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T50,T1

 LINE       31877
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31878
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31879
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31880
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31881
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T21,T50

 LINE       31882
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31883
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T46,T50,T1

 LINE       31884
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T49

 LINE       31885
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31886
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31887
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T50

 LINE       31888
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31889
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31890
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T46,T1,T47

 LINE       31891
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T49

 LINE       31892
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31893
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T49

 LINE       31894
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31895
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31896
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31897
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T21,T1

 LINE       31898
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       31899
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T46,T1,T47

 LINE       31900
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31901
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T21,T1

 LINE       31902
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31903
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T49,T50

 LINE       31904
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31905
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31906
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T50

 LINE       31907
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31908
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T46,T50,T1

 LINE       31909
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31910
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T50

 LINE       31911
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T21,T1

 LINE       31912
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T49

 LINE       31913
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       31914
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T46,T1,T47

 LINE       31915
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T1

 LINE       31916
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T21,T46

 LINE       31917
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T51,T58

 LINE       31918
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       31919
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T50,T1,T51

 LINE       31920
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T46,T1,T47

 LINE       31921
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       31922
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T50

 LINE       31923
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T51,T2

 LINE       31924
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T46,T1,T47