Unified Coverage Report :: Cond split page

Go back

 LINE       31976
 SUB-EXPRESSION (addr_hit[285] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T49,T46
1	1	Covered	T6,T50,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[286] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T49,T50
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[287] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T49,T51
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[288] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T49,T46
1	1	Covered	T4,T21,T50

 LINE       31976
 SUB-EXPRESSION (addr_hit[289] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T47,T51
1	1	Covered	T5,T6,T49

 LINE       31976
 SUB-EXPRESSION (addr_hit[290] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T49,T51
1	1	Covered	T46,T1,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[291] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T4,T5,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[292] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T49,T51
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[293] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T51,T2,T73
1	1	Covered	T1,T51,T58

 LINE       31976
 SUB-EXPRESSION (addr_hit[294] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T50,T51,T57
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[295] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T2
1	1	Covered	T6,T50,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[296] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T51,T2,T73
1	1	Covered	T5,T6,T49

 LINE       31976
 SUB-EXPRESSION (addr_hit[297] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T47,T77
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[298] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T46,T47
1	1	Covered	T5,T6,T49

 LINE       31976
 SUB-EXPRESSION (addr_hit[299] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T49,T46
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[300] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T51,T2,T76
1	1	Covered	T6,T46,T50

 LINE       31976
 SUB-EXPRESSION (addr_hit[301] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T50
1	1	Covered	T5,T49,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[302] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T59,T60
1	1	Covered	T4,T5,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[303] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T51,T2
1	1	Covered	T4,T21,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[304] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T51
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[305] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T21
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[306] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T1,T47
1	1	Covered	T4,T21,T50

 LINE       31976
 SUB-EXPRESSION (addr_hit[307] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T50,T51,T78
1	1	Covered	T4,T21,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[308] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T46,T47
1	1	Covered	T6,T1,T51

 LINE       31976
 SUB-EXPRESSION (addr_hit[309] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T51,T2,T76
1	1	Covered	T4,T5,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[310] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T21
1	1	Covered	T46,T1,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[311] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T49,T51
1	1	Covered	T4,T21,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[312] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T50
1	1	Covered	T6,T1,T51

 LINE       31976
 SUB-EXPRESSION (addr_hit[313] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T51,T70
1	1	Covered	T1,T51,T3

 LINE       31976
 SUB-EXPRESSION (addr_hit[314] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T50,T51,T57
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[315] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T51,T2,T59
1	1	Covered	T6,T50,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[316] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T47,T51
1	1	Covered	T5,T6,T49

 LINE       31976
 SUB-EXPRESSION (addr_hit[317] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T1,T47
1	1	Covered	T6,T1,T51

 LINE       31976
 SUB-EXPRESSION (addr_hit[318] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T51,T2,T72
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[319] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T46,T1
1	1	Covered	T5,T6,T49

 LINE       31976
 SUB-EXPRESSION (addr_hit[320] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T70,T2
1	1	Covered	T4,T21,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[321] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T51
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[322] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T51
1	1	Covered	T4,T21,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[323] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T47,T2
1	1	Covered	T4,T21,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[324] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T47,T70
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[325] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T7,T42
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[326] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T51,T62,T2
1	1	Covered	T4,T5,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[327] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T46
1	1	Covered	T6,T50,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[328] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T1
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[329] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T47,T2
1	1	Covered	T4,T21,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[330] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T51,T57
1	1	Covered	T1,T51,T2

 LINE       31976
 SUB-EXPRESSION (addr_hit[331] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T1,T47
1	1	Covered	T4,T21,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[332] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T2
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[333] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T51,T2,T72
1	1	Covered	T50,T1,T51

 LINE       31976
 SUB-EXPRESSION (addr_hit[334] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T47,T2
1	1	Covered	T6,T46,T50

 LINE       31976
 SUB-EXPRESSION (addr_hit[335] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T51,T2,T76
1	1	Covered	T5,T49,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[336] & ((|(4'b0011 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T46
1	1	Covered	T4,T21,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[337] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T1
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[338] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T49
1	1	Covered	T4,T21,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[339] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T51,T70
1	1	Covered	T5,T6,T49

 LINE       31976
 SUB-EXPRESSION (addr_hit[340] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T57,T70
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[341] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T1,T47
1	1	Covered	T6,T1,T51

 LINE       31976
 SUB-EXPRESSION (addr_hit[342] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T49,T50
1	1	Covered	T5,T6,T49

 LINE       31976
 SUB-EXPRESSION (addr_hit[343] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T1,T47
1	1	Covered	T6,T50,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[344] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T51,T70
1	1	Covered	T6,T1,T57

 LINE       31976
 SUB-EXPRESSION (addr_hit[345] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T46,T50
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[346] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T46,T1
1	1	Covered	T1,T51,T2

 LINE       31976
 SUB-EXPRESSION (addr_hit[347] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T46,T1
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[348] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T49,T51
1	1	Covered	T5,T49,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[349] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T47,T51
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[350] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T50,T47
1	1	Covered	T4,T21,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[351] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T47,T51
1	1	Covered	T1,T51,T3

 LINE       31976
 SUB-EXPRESSION (addr_hit[352] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T21
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[353] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T47,T51
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[354] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T51,T2,T59
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[355] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T46,T47
1	1	Covered	T1,T51,T58

 LINE       31976
 SUB-EXPRESSION (addr_hit[356] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T47,T51
1	1	Covered	T4,T21,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[357] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T49
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[358] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T51
1	1	Covered	T4,T21,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[359] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T1,T47
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[360] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T46
1	1	Covered	T5,T6,T49

 LINE       31976
 SUB-EXPRESSION (addr_hit[361] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T46,T50,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[362] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T21
1	1	Covered	T5,T6,T49

 LINE       31976
 SUB-EXPRESSION (addr_hit[363] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T49
1	1	Covered	T6,T46,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[364] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T21
1	1	Covered	T6,T46,T50

 LINE       31976
 SUB-EXPRESSION (addr_hit[365] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T51,T2,T72
1	1	Covered	T4,T21,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[366] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T21
1	1	Covered	T1,T51,T2

 LINE       31976
 SUB-EXPRESSION (addr_hit[367] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T70,T2
1	1	Covered	T6,T50,T1

 LINE       31976
 SUB-EXPRESSION (addr_hit[368] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T51,T2,T59
1	1	Covered	T4,T21,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[369] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T50,T51,T62
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[370] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T49,T51
1	1	Covered	T6,T1,T51

 LINE       31976
 SUB-EXPRESSION (addr_hit[371] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T51
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[372] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T49
1	1	Covered	T46,T1,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[373] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T21
1	1	Covered	T5,T6,T49

 LINE       31976
 SUB-EXPRESSION (addr_hit[374] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T49,T51
1	1	Covered	T6,T46,T50

 LINE       31976
 SUB-EXPRESSION (addr_hit[375] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T46
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[376] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T21,T51
1	1	Covered	T4,T6,T21

 LINE       31976
 SUB-EXPRESSION (addr_hit[377] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T1,T47
1	1	Covered	T1,T51,T3

 LINE       31976
 SUB-EXPRESSION (addr_hit[378] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T49
1	1	Covered	T4,T21,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[379] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T51,T2
1	1	Covered	T6,T1,T51