Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	159655	1			T4	51		T5	317		T6	56
values[2]	5246	1			T4	1		T5	4		T46	1
values[3]	2586	1			T48	16		T148	24		T68	1
values[4]	1982	1			T48	9		T148	42		T72	5
values[5]	1523	1			T48	6		T148	38		T72	1
values[6]	1206	1			T48	5		T148	48		T72	3
values[7]	1021	1			T48	5		T148	29		T72	5
values[8]	1016	1			T48	6		T148	28		T72	4
values[9]	909	1			T48	12		T148	12		T72	3
values[10]	876	1			T48	14		T148	13		T72	1
values[11]	763	1			T48	20		T148	18		T72	4
values[12]	709	1			T48	7		T148	57		T72	7
values[13]	552	1			T48	14		T148	64		T72	4
values[14]	474	1			T48	12		T148	35		T72	2
values[15]	391	1			T48	21		T148	19		T72	3
values[16]	400	1			T48	13		T148	18		T72	5
values[17]	432	1			T48	6		T148	11		T72	3
values[18]	375	1			T48	1		T72	2		T286	27
values[19]	335	1			T72	4		T286	8		T299	1
values[20]	313	1			T72	4		T286	7		T299	1
values[21]	277	1			T72	4		T286	8		T299	1
values[22]	290	1			T72	2		T286	15		T299	1
values[23]	284	1			T72	5		T286	17		T299	1
values[24]	220	1			T72	1		T286	10		T299	1
values[25]	177	1			T72	4		T286	3		T299	1
values[26]	174	1			T72	1		T299	1		T300	1
values[27]	147	1			T72	2		T299	1		T300	1
values[28]	138	1			T72	1		T299	1		T300	1
values[29]	159	1			T72	1		T299	1		T300	1
values[30]	148	1			T72	2		T299	1		T300	1
values[31]	117	1			T72	3		T299	1		T300	1
values[32]	120	1			T72	3		T299	1		T300	1
values[33]	111	1			T72	4		T299	1		T300	1
values[34]	82	1			T72	3		T299	1		T300	1
values[35]	98	1			T72	3		T299	1		T300	1
values[36]	102	1			T72	1		T299	1		T300	1
values[37]	76	1			T72	5		T299	1		T300	1
values[38]	59	1			T72	3		T299	1		T300	1
values[39]	57	1			T72	1		T299	1		T300	1
values[40]	61	1			T72	4		T299	1		T300	1
values[41]	63	1			T72	2		T299	1		T300	1
values[42]	38	1			T72	2		T299	1		T300	1
values[43]	51	1			T72	10		T299	1		T300	1
values[44]	43	1			T72	7		T299	1		T300	1
values[45]	44	1			T72	5		T299	1		T300	1
values[46]	35	1			T72	2		T299	1		T300	1
values[47]	37	1			T72	3		T299	1		T300	1
values[48]	43	1			T72	1		T299	1		T300	1
values[49]	39	1			T72	1		T299	1		T300	1
values[50]	42	1			T72	5		T299	1		T300	1
values[51]	40	1			T72	2		T299	1		T300	1
values[52]	37	1			T72	2		T299	1		T300	1
values[53]	36	1			T72	1		T299	1		T300	1
values[54]	64	1			T72	3		T299	1		T300	1
values[55]	56	1			T72	2		T299	1		T300	1
values[56]	63	1			T72	2		T299	1		T300	1
values[57]	75	1			T72	2		T299	1		T300	1
values[58]	71	1			T72	3		T299	1		T300	1
values[59]	68	1			T72	7		T299	1		T300	1
values[60]	55	1			T72	3		T299	1		T300	1
values[61]	51	1			T72	1		T299	1		T300	1
values[62]	48	1			T72	1		T299	1		T300	1
values[63]	41	1			T72	2		T299	1		T300	1
values[64]	34	1			T72	2		T299	1		T300	1
values[65]	37	1			T72	1		T299	1		T300	1
values[66]	45	1			T72	4		T299	1		T300	1
values[67]	44	1			T72	2		T299	1		T300	1
values[68]	65	1			T72	1		T299	1		T300	1
values[69]	58	1			T72	2		T299	1		T300	1
values[70]	60	1			T72	7		T299	1		T300	1
values[71]	43	1			T72	6		T299	1		T300	1
values[72]	36	1			T72	2		T299	1		T300	1
values[73]	48	1			T72	3		T299	1		T300	3
values[74]	52	1			T72	4		T299	1		T300	4
values[75]	47	1			T72	2		T299	1		T300	8
values[76]	41	1			T72	2		T299	1		T300	2
values[77]	46	1			T72	2		T299	1		T300	3
values[78]	49	1			T72	1		T299	1		T300	5
values[79]	49	1			T72	2		T299	1		T300	5
values[80]	46	1			T72	1		T299	1		T300	5
values[81]	58	1			T72	5		T299	1		T300	3
values[82]	51	1			T72	3		T299	1		T300	2
values[83]	48	1			T72	2		T299	1		T300	2
values[84]	52	1			T72	4		T299	1		T300	2
values[85]	52	1			T72	2		T299	1		T300	2
values[86]	43	1			T72	1		T299	1		T300	3
values[87]	59	1			T72	1		T299	1		T300	4
values[88]	53	1			T72	6		T299	1		T300	1
values[89]	44	1			T72	4		T299	1		T300	1
values[90]	48	1			T72	4		T299	1		T300	1
values[91]	56	1			T72	4		T299	1		T300	2
values[92]	58	1			T72	3		T299	1		T300	5
values[93]	47	1			T72	3		T299	1		T300	2
values[94]	45	1			T72	1		T299	1		T300	1
values[95]	50	1			T72	4		T299	1		T300	3
values[96]	57	1			T72	8		T299	1		T300	3
values[97]	60	1			T72	4		T299	1		T300	1
values[98]	57	1			T72	3		T299	1		T300	3
values[99]	49	1			T72	2		T299	4		T300	4
values[100]	68	1			T72	8		T299	1		T300	5
values[101]	63	1			T72	1		T299	1		T300	8
values[102]	74	1			T72	3		T299	2		T300	1
values[103]	73	1			T72	5		T299	3		T300	3
values[104]	85	1			T72	4		T299	4		T300	3
values[105]	67	1			T72	3		T299	3		T300	1
values[106]	66	1			T72	4		T299	5		T300	3
values[107]	60	1			T72	3		T299	1		T300	1
values[108]	62	1			T72	2		T299	2		T300	4
values[109]	49	1			T72	2		T299	3		T300	3
values[110]	71	1			T72	4		T299	4		T300	6
values[111]	71	1			T72	9		T299	4		T300	3
values[112]	68	1			T72	5		T299	3		T300	3
values[113]	69	1			T72	7		T299	1		T300	5
values[114]	65	1			T72	4		T299	2		T300	3
values[115]	57	1			T72	2		T299	1		T300	1
values[116]	63	1			T72	4		T299	1		T300	2
values[117]	87	1			T72	8		T299	1		T300	3
values[118]	77	1			T72	7		T299	1		T300	3
values[119]	74	1			T72	5		T299	5		T300	4
values[120]	63	1			T72	5		T299	1		T300	2
values[121]	65	1			T72	4		T299	1		T300	2
values[122]	83	1			T72	4		T299	2		T300	2
values[123]	84	1			T72	4		T299	2		T300	2
values[124]	158	1			T72	3		T299	2		T300	1
values[125]	327	1			T72	19		T299	3		T300	1
values[126]	602	1			T72	18		T299	11		T300	7
values[127]	2084	1			T72	3		T299	101		T300	82
values[128]	3661	1			T72	2		T299	159		T300	173