Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143269	1			T4	49		T5	341		T6	83
values[2]	9782	1			T4	1		T46	1		T61	2
values[3]	3932	1			T47	3		T48	34		T148	97
values[4]	2294	1			T48	24		T148	53		T204	3
values[5]	1342	1			T48	15		T148	31		T204	12
values[6]	987	1			T48	13		T148	13		T204	6
values[7]	676	1			T48	9		T148	16		T204	14
values[8]	478	1			T48	6		T148	11		T204	2
values[9]	407	1			T48	6		T204	4		T206	1
values[10]	406	1			T48	7		T204	15		T206	1
values[11]	365	1			T48	15		T204	5		T206	1
values[12]	317	1			T48	4		T204	5		T206	1
values[13]	292	1			T48	4		T204	14		T206	1
values[14]	306	1			T48	6		T204	5		T206	1
values[15]	358	1			T48	11		T204	8		T206	1
values[16]	321	1			T48	19		T204	9		T206	1
values[17]	324	1			T48	18		T204	10		T206	1
values[18]	327	1			T48	17		T204	8		T206	1
values[19]	311	1			T48	19		T204	5		T206	1
values[20]	277	1			T48	17		T204	7		T206	1
values[21]	262	1			T48	9		T204	8		T206	1
values[22]	283	1			T48	11		T204	2		T206	1
values[23]	325	1			T48	8		T204	12		T206	1
values[24]	277	1			T48	8		T204	5		T206	1
values[25]	325	1			T48	7		T204	3		T206	1
values[26]	293	1			T48	4		T204	8		T206	1
values[27]	257	1			T48	4		T204	3		T206	1
values[28]	243	1			T48	6		T204	4		T206	1
values[29]	288	1			T48	11		T204	10		T206	1
values[30]	275	1			T48	11		T204	9		T206	1
values[31]	277	1			T48	8		T204	5		T206	1
values[32]	250	1			T48	5		T204	12		T206	1
values[33]	304	1			T48	6		T204	6		T206	1
values[34]	299	1			T48	5		T204	14		T206	1
values[35]	292	1			T48	5		T204	6		T206	1
values[36]	288	1			T48	7		T204	5		T206	1
values[37]	267	1			T48	4		T204	4		T206	1
values[38]	246	1			T48	4		T204	6		T206	1
values[39]	274	1			T48	8		T204	7		T206	1
values[40]	259	1			T48	9		T204	7		T206	1
values[41]	288	1			T48	12		T204	4		T206	1
values[42]	302	1			T48	9		T204	7		T206	1
values[43]	283	1			T48	7		T204	3		T206	1
values[44]	242	1			T48	9		T204	7		T206	1
values[45]	244	1			T48	10		T204	15		T206	2
values[46]	238	1			T48	5		T204	5		T206	1
values[47]	183	1			T48	3		T204	7		T206	1
values[48]	234	1			T48	7		T204	9		T206	1
values[49]	266	1			T48	6		T204	14		T206	1
values[50]	253	1			T48	4		T204	4		T206	1
values[51]	212	1			T48	4		T204	5		T206	1
values[52]	221	1			T48	16		T204	12		T206	1
values[53]	268	1			T48	11		T204	16		T206	1
values[54]	199	1			T48	8		T204	11		T206	1
values[55]	176	1			T48	6		T204	4		T206	1
values[56]	235	1			T48	8		T204	7		T206	1
values[57]	218	1			T48	7		T204	8		T206	1
values[58]	227	1			T48	6		T204	2		T206	1
values[59]	208	1			T48	5		T204	4		T206	1
values[60]	198	1			T48	3		T204	4		T206	1
values[61]	198	1			T48	7		T204	3		T206	1
values[62]	160	1			T48	13		T204	3		T206	1
values[63]	155	1			T48	10		T204	4		T206	1
values[64]	170	1			T48	12		T204	6		T206	1
values[65]	187	1			T48	12		T204	14		T206	1
values[66]	163	1			T48	7		T204	12		T206	1
values[67]	170	1			T48	10		T204	20		T206	1
values[68]	200	1			T48	9		T204	17		T206	1
values[69]	163	1			T48	7		T204	8		T206	1
values[70]	124	1			T48	8		T204	6		T206	1
values[71]	137	1			T48	24		T206	1		T71	5
values[72]	118	1			T48	8		T206	1		T71	2
values[73]	100	1			T48	4		T206	1		T85	4
values[74]	79	1			T48	3		T206	1		T85	7
values[75]	58	1			T48	2		T206	1		T85	6
values[76]	85	1			T48	2		T206	1		T85	10
values[77]	85	1			T48	12		T206	1		T85	16
values[78]	83	1			T48	11		T206	1		T85	7
values[79]	60	1			T48	4		T206	1		T85	7
values[80]	83	1			T48	3		T206	1		T85	6
values[81]	73	1			T48	2		T206	1		T85	9
values[82]	75	1			T48	4		T206	1		T85	2
values[83]	75	1			T48	4		T206	1		T85	2
values[84]	75	1			T48	4		T206	1		T85	5
values[85]	79	1			T48	9		T206	1		T85	14
values[86]	73	1			T48	10		T206	1		T85	9
values[87]	70	1			T48	6		T206	1		T85	8
values[88]	76	1			T48	2		T206	1		T85	4
values[89]	77	1			T48	2		T206	1		T85	4
values[90]	82	1			T48	4		T206	1		T85	9
values[91]	88	1			T48	5		T206	1		T85	4
values[92]	96	1			T48	10		T206	1		T85	3
values[93]	77	1			T48	5		T206	1		T85	7
values[94]	69	1			T48	5		T206	1		T85	6
values[95]	76	1			T48	10		T206	1		T289	1
values[96]	66	1			T48	4		T206	1		T289	1
values[97]	68	1			T48	3		T206	1		T289	1
values[98]	89	1			T48	5		T206	1		T289	4
values[99]	68	1			T48	4		T206	1		T289	3
values[100]	75	1			T48	6		T206	1		T289	8
values[101]	77	1			T48	8		T206	1		T289	2
values[102]	98	1			T48	13		T206	1		T289	5
values[103]	80	1			T48	12		T206	1		T289	8
values[104]	87	1			T48	7		T206	1		T289	5
values[105]	73	1			T48	9		T206	1		T289	4
values[106]	82	1			T48	11		T206	1		T289	4
values[107]	72	1			T48	8		T206	1		T289	2
values[108]	61	1			T48	8		T206	1		T289	1
values[109]	52	1			T48	6		T206	1		T289	1
values[110]	82	1			T48	18		T206	2		T289	1
values[111]	103	1			T48	12		T206	11		T289	1
values[112]	73	1			T48	9		T206	2		T289	2
values[113]	55	1			T48	6		T206	2		T289	5
values[114]	72	1			T48	6		T206	1		T289	1
values[115]	61	1			T48	4		T206	3		T289	2
values[116]	53	1			T48	8		T206	1		T289	2
values[117]	65	1			T48	8		T206	1		T289	1
values[118]	72	1			T48	6		T206	3		T289	4
values[119]	72	1			T48	5		T206	2		T289	3
values[120]	78	1			T48	9		T206	2		T289	1
values[121]	64	1			T48	6		T206	7		T289	3
values[122]	70	1			T48	7		T206	2		T289	1
values[123]	58	1			T48	6		T206	1		T289	1
values[124]	77	1			T48	6		T206	1		T289	1
values[125]	94	1			T48	20		T206	6		T289	2
values[126]	138	1			T48	45		T206	1		T289	1
values[127]	731	1			T48	104		T206	34		T289	32
values[128]	5249	1			T48	57		T206	343		T289	266