Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141079	1			T4	49		T5	652		T6	82
values[2]	10367	1			T4	1		T5	136		T6	1
values[3]	4328	1			T5	44		T84	1		T204	10
values[4]	2565	1			T5	17		T204	5		T311	20
values[5]	1723	1			T5	10		T204	5		T311	9
values[6]	974	1			T5	5		T204	11		T311	5
values[7]	713	1			T204	4		T311	5		T71	18
values[8]	562	1			T204	11		T311	5		T71	24
values[9]	442	1			T204	6		T311	10		T71	11
values[10]	382	1			T204	5		T311	5		T71	10
values[11]	374	1			T204	11		T71	7		T95	11
values[12]	385	1			T204	9		T71	14		T95	6
values[13]	365	1			T204	7		T71	23		T95	17
values[14]	380	1			T204	4		T71	15		T95	26
values[15]	354	1			T204	9		T71	10		T95	12
values[16]	361	1			T204	7		T71	13		T95	6
values[17]	359	1			T204	8		T71	21		T95	28
values[18]	305	1			T204	14		T71	10		T95	15
values[19]	306	1			T204	6		T71	14		T95	17
values[20]	390	1			T204	5		T71	17		T95	18
values[21]	321	1			T204	3		T71	25		T95	11
values[22]	342	1			T204	7		T71	28		T95	13
values[23]	291	1			T204	8		T71	6		T95	20
values[24]	273	1			T204	5		T71	9		T95	13
values[25]	315	1			T204	6		T71	11		T95	17
values[26]	285	1			T204	13		T71	12		T95	12
values[27]	316	1			T204	19		T71	8		T95	14
values[28]	316	1			T204	6		T71	11		T95	25
values[29]	272	1			T204	3		T71	10		T95	8
values[30]	318	1			T204	3		T71	26		T95	17
values[31]	312	1			T204	4		T71	12		T95	12
values[32]	296	1			T204	4		T71	26		T95	5
values[33]	289	1			T204	5		T71	20		T95	12
values[34]	287	1			T204	5		T71	26		T95	7
values[35]	288	1			T204	5		T71	7		T95	28
values[36]	248	1			T204	5		T71	6		T95	25
values[37]	253	1			T204	16		T71	13		T95	21
values[38]	270	1			T204	4		T71	20		T95	11
values[39]	296	1			T204	7		T71	24		T95	27
values[40]	260	1			T204	3		T71	15		T95	15
values[41]	245	1			T204	4		T71	20		T95	8
values[42]	241	1			T204	2		T71	19		T95	13
values[43]	236	1			T204	5		T71	26		T95	8
values[44]	264	1			T204	6		T71	15		T95	22
values[45]	243	1			T204	3		T71	15		T95	16
values[46]	356	1			T204	6		T71	20		T95	14
values[47]	288	1			T204	6		T71	17		T95	10
values[48]	311	1			T204	8		T71	14		T95	16
values[49]	288	1			T204	3		T71	17		T95	13
values[50]	296	1			T204	5		T71	13		T95	10
values[51]	344	1			T204	17		T71	13		T95	16
values[52]	229	1			T204	11		T71	18		T95	9
values[53]	262	1			T71	19		T95	9		T88	1
values[54]	211	1			T71	8		T95	12		T88	1
values[55]	255	1			T71	12		T95	11		T88	1
values[56]	242	1			T71	6		T95	15		T88	1
values[57]	238	1			T71	7		T95	14		T88	1
values[58]	211	1			T71	8		T95	9		T88	1
values[59]	189	1			T71	6		T95	8		T88	1
values[60]	187	1			T71	3		T95	14		T88	1
values[61]	187	1			T71	17		T95	10		T88	1
values[62]	186	1			T71	4		T95	8		T88	1
values[63]	204	1			T71	6		T95	20		T88	1
values[64]	203	1			T71	8		T95	5		T88	1
values[65]	158	1			T71	4		T95	11		T88	1
values[66]	117	1			T71	7		T95	5		T88	1
values[67]	141	1			T71	8		T95	14		T88	1
values[68]	106	1			T71	4		T95	5		T88	1
values[69]	123	1			T71	12		T95	4		T88	1
values[70]	119	1			T71	14		T95	13		T88	1
values[71]	111	1			T71	11		T95	2		T88	2
values[72]	84	1			T71	2		T95	2		T88	1
values[73]	86	1			T71	4		T88	1		T297	1
values[74]	82	1			T71	4		T88	1		T297	1
values[75]	70	1			T71	5		T88	1		T297	1
values[76]	64	1			T71	8		T88	1		T297	1
values[77]	72	1			T88	1		T297	1		T288	1
values[78]	66	1			T88	1		T297	1		T288	1
values[79]	60	1			T88	1		T297	1		T288	1
values[80]	63	1			T88	1		T297	1		T288	1
values[81]	69	1			T88	1		T297	1		T288	1
values[82]	62	1			T88	1		T297	1		T288	1
values[83]	68	1			T88	1		T297	1		T288	1
values[84]	76	1			T88	1		T297	1		T288	1
values[85]	68	1			T88	1		T297	1		T288	1
values[86]	62	1			T88	1		T297	1		T288	1
values[87]	71	1			T88	1		T297	1		T288	2
values[88]	71	1			T88	2		T297	1		T288	2
values[89]	72	1			T88	6		T297	1		T288	3
values[90]	61	1			T88	7		T297	1		T288	5
values[91]	58	1			T88	5		T297	1		T288	3
values[92]	83	1			T88	2		T297	2		T288	4
values[93]	87	1			T88	2		T297	1		T288	4
values[94]	70	1			T88	2		T297	1		T288	1
values[95]	70	1			T88	1		T297	1		T288	2
values[96]	63	1			T88	1		T297	1		T288	1
values[97]	70	1			T88	5		T297	1		T288	2
values[98]	93	1			T88	4		T297	1		T288	6
values[99]	85	1			T88	2		T297	1		T288	4
values[100]	75	1			T88	1		T297	1		T288	1
values[101]	65	1			T88	2		T297	1		T288	1
values[102]	75	1			T88	2		T297	1		T288	1
values[103]	75	1			T88	2		T297	1		T288	2
values[104]	76	1			T88	1		T297	1		T288	1
values[105]	96	1			T88	4		T297	1		T288	1
values[106]	68	1			T88	2		T297	1		T288	2
values[107]	55	1			T88	1		T297	1		T288	1
values[108]	80	1			T88	2		T297	1		T288	1
values[109]	82	1			T88	8		T297	1		T288	2
values[110]	76	1			T88	3		T297	1		T288	1
values[111]	51	1			T88	1		T297	1		T288	1
values[112]	66	1			T88	1		T297	1		T288	2
values[113]	75	1			T88	1		T297	1		T288	2
values[114]	63	1			T88	3		T297	1		T288	2
values[115]	72	1			T88	11		T297	1		T288	2
values[116]	69	1			T88	1		T297	1		T288	3
values[117]	61	1			T88	4		T297	1		T288	1
values[118]	65	1			T88	3		T297	1		T288	3
values[119]	66	1			T88	3		T297	1		T288	1
values[120]	52	1			T88	1		T297	1		T288	1
values[121]	65	1			T88	1		T297	1		T288	1
values[122]	48	1			T88	3		T297	1		T288	2
values[123]	55	1			T88	2		T297	1		T288	1
values[124]	54	1			T88	1		T297	4		T288	3
values[125]	93	1			T88	1		T297	2		T288	2
values[126]	169	1			T88	2		T297	2		T288	1
values[127]	767	1			T88	28		T297	30		T288	30
values[128]	5483	1			T88	300		T297	349		T288	283