Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143820	1			T4	60		T5	294		T6	80
values[2]	8455	1			T4	2		T5	4		T46	3
values[3]	3804	1			T48	4		T148	65		T205	2
values[4]	2210	1			T48	3		T148	32		T149	19
values[5]	1393	1			T48	3		T148	18		T149	6
values[6]	1072	1			T48	2		T148	38		T149	16
values[7]	739	1			T48	1		T148	50		T149	6
values[8]	579	1			T48	2		T148	60		T149	15
values[9]	605	1			T48	5		T148	39		T149	9
values[10]	518	1			T48	9		T148	39		T149	4
values[11]	482	1			T48	14		T148	14		T149	5
values[12]	409	1			T48	15		T148	1		T149	6
values[13]	454	1			T48	12		T149	16		T306	10
values[14]	345	1			T48	6		T149	8		T306	8
values[15]	369	1			T48	3		T149	15		T306	6
values[16]	363	1			T48	5		T149	9		T306	6
values[17]	407	1			T48	4		T149	5		T306	25
values[18]	333	1			T48	3		T149	8		T306	5
values[19]	334	1			T48	4		T149	12		T306	14
values[20]	352	1			T48	3		T149	15		T306	29
values[21]	364	1			T48	4		T149	7		T306	10
values[22]	349	1			T48	4		T149	3		T306	10
values[23]	289	1			T48	4		T149	10		T306	12
values[24]	295	1			T48	3		T149	8		T306	8
values[25]	351	1			T48	7		T149	10		T306	9
values[26]	324	1			T48	5		T149	12		T306	6
values[27]	282	1			T48	7		T149	11		T306	10
values[28]	288	1			T48	4		T149	5		T306	3
values[29]	284	1			T48	16		T149	4		T306	14
values[30]	345	1			T48	12		T149	10		T306	13
values[31]	317	1			T48	8		T149	4		T306	11
values[32]	257	1			T48	9		T149	4		T306	13
values[33]	275	1			T48	12		T149	26		T306	7
values[34]	316	1			T48	12		T149	13		T306	15
values[35]	310	1			T48	1		T149	8		T306	8
values[36]	236	1			T48	4		T149	6		T306	11
values[37]	256	1			T48	3		T149	6		T306	19
values[38]	237	1			T48	2		T149	24		T306	3
values[39]	218	1			T48	2		T149	7		T306	8
values[40]	245	1			T149	13		T306	13		T77	1
values[41]	222	1			T149	4		T77	1		T95	17
values[42]	210	1			T149	7		T77	1		T95	12
values[43]	239	1			T149	25		T77	1		T95	16
values[44]	203	1			T149	7		T77	1		T95	5
values[45]	194	1			T149	15		T77	1		T95	9
values[46]	169	1			T149	8		T77	2		T95	13
values[47]	161	1			T149	8		T77	1		T95	11
values[48]	123	1			T149	6		T77	1		T95	10
values[49]	155	1			T149	10		T77	1		T95	12
values[50]	118	1			T149	12		T77	1		T95	5
values[51]	104	1			T149	10		T77	1		T88	1
values[52]	114	1			T149	5		T77	1		T88	1
values[53]	113	1			T149	7		T77	1		T88	1
values[54]	85	1			T149	1		T77	1		T88	1
values[55]	83	1			T77	1		T88	1		T297	1
values[56]	74	1			T77	1		T88	1		T297	1
values[57]	51	1			T77	1		T88	1		T297	1
values[58]	56	1			T77	1		T88	1		T297	1
values[59]	50	1			T77	1		T88	1		T297	1
values[60]	59	1			T77	1		T88	1		T297	1
values[61]	62	1			T77	1		T88	1		T297	1
values[62]	53	1			T77	1		T88	1		T297	1
values[63]	60	1			T77	1		T88	1		T297	1
values[64]	73	1			T77	1		T88	1		T297	1
values[65]	60	1			T77	1		T88	1		T297	2
values[66]	56	1			T77	1		T88	1		T297	1
values[67]	63	1			T77	1		T88	1		T297	1
values[68]	74	1			T77	1		T88	1		T297	1
values[69]	89	1			T77	1		T88	1		T297	1
values[70]	64	1			T77	1		T88	1		T297	1
values[71]	52	1			T77	1		T88	1		T297	1
values[72]	39	1			T77	1		T88	1		T297	1
values[73]	48	1			T77	2		T88	1		T297	1
values[74]	68	1			T77	1		T88	1		T297	1
values[75]	54	1			T77	1		T88	1		T297	1
values[76]	73	1			T77	1		T88	1		T297	1
values[77]	65	1			T77	1		T88	1		T297	1
values[78]	68	1			T77	1		T88	1		T297	1
values[79]	48	1			T77	1		T88	1		T297	1
values[80]	40	1			T77	1		T88	1		T297	1
values[81]	40	1			T77	1		T88	1		T297	1
values[82]	56	1			T77	1		T88	1		T297	1
values[83]	47	1			T77	1		T88	1		T297	1
values[84]	57	1			T77	1		T88	1		T297	1
values[85]	47	1			T77	1		T88	1		T297	1
values[86]	57	1			T77	1		T88	1		T297	2
values[87]	70	1			T77	1		T88	1		T297	7
values[88]	56	1			T77	1		T88	1		T297	5
values[89]	71	1			T77	1		T88	1		T297	11
values[90]	52	1			T77	1		T88	1		T297	3
values[91]	54	1			T77	1		T88	1		T297	4
values[92]	41	1			T77	1		T88	1		T297	1
values[93]	58	1			T77	2		T88	1		T297	1
values[94]	61	1			T77	1		T88	1		T297	2
values[95]	45	1			T77	2		T88	1		T297	1
values[96]	78	1			T77	3		T88	1		T297	7
values[97]	79	1			T77	1		T88	1		T297	2
values[98]	72	1			T77	3		T88	1		T297	1
values[99]	67	1			T77	3		T88	1		T297	2
values[100]	66	1			T77	5		T88	1		T297	2
values[101]	94	1			T77	2		T88	1		T297	5
values[102]	61	1			T77	1		T88	1		T297	4
values[103]	53	1			T77	6		T88	1		T297	3
values[104]	41	1			T77	5		T88	1		T297	3
values[105]	46	1			T77	5		T88	1		T297	4
values[106]	42	1			T77	3		T88	1		T297	4
values[107]	36	1			T77	1		T88	1		T297	3
values[108]	52	1			T77	1		T88	1		T297	1
values[109]	39	1			T77	4		T88	1		T297	3
values[110]	49	1			T77	4		T88	2		T297	1
values[111]	43	1			T77	1		T88	4		T297	1
values[112]	41	1			T77	2		T88	2		T297	2
values[113]	44	1			T77	1		T88	1		T297	2
values[114]	38	1			T77	3		T88	1		T297	1
values[115]	39	1			T77	1		T88	1		T297	1
values[116]	44	1			T77	2		T88	4		T297	1
values[117]	40	1			T77	1		T88	5		T297	1
values[118]	45	1			T77	2		T88	3		T297	1
values[119]	56	1			T77	2		T88	4		T297	1
values[120]	45	1			T77	2		T88	1		T297	1
values[121]	39	1			T77	1		T88	2		T297	1
values[122]	38	1			T77	3		T88	4		T297	2
values[123]	55	1			T77	11		T88	2		T297	2
values[124]	41	1			T77	2		T88	2		T297	1
values[125]	28	1			T77	1		T88	1		T297	1
values[126]	70	1			T77	7		T88	4		T297	1
values[127]	1069	1			T77	55		T88	77		T297	49
values[128]	5138	1			T77	266		T88	310		T297	267