Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	164329	1			T4	59		T5	299		T6	79
values[2]	5437	1			T4	2		T5	1		T46	2
values[3]	2974	1			T148	7		T88	1		T108	109
values[4]	1995	1			T148	6		T88	1		T108	51
values[5]	1554	1			T148	9		T88	1		T108	29
values[6]	1334	1			T148	8		T88	1		T108	15
values[7]	1155	1			T148	16		T88	1		T108	16
values[8]	939	1			T148	17		T88	1		T108	13
values[9]	689	1			T148	20		T88	1		T108	8
values[10]	695	1			T148	43		T88	1		T108	11
values[11]	582	1			T148	33		T88	1		T108	4
values[12]	650	1			T148	18		T88	1		T108	8
values[13]	639	1			T148	18		T88	1		T108	3
values[14]	651	1			T148	14		T88	1		T318	27
values[15]	607	1			T148	18		T88	1		T318	32
values[16]	517	1			T148	6		T88	1		T318	53
values[17]	447	1			T148	4		T88	1		T318	34
values[18]	403	1			T88	1		T318	11		T315	1
values[19]	395	1			T88	1		T318	11		T315	4
values[20]	295	1			T88	1		T318	1		T315	1
values[21]	292	1			T88	1		T315	3		T287	1
values[22]	272	1			T88	1		T315	2		T287	1
values[23]	213	1			T88	1		T315	3		T287	1
values[24]	179	1			T88	1		T315	3		T287	1
values[25]	188	1			T88	1		T315	3		T287	1
values[26]	168	1			T88	1		T315	2		T287	1
values[27]	225	1			T88	1		T315	8		T287	1
values[28]	240	1			T88	1		T315	6		T287	1
values[29]	202	1			T88	1		T315	7		T287	1
values[30]	211	1			T88	1		T315	1		T287	1
values[31]	240	1			T88	1		T315	2		T287	1
values[32]	229	1			T88	1		T315	4		T287	1
values[33]	211	1			T88	1		T315	3		T287	1
values[34]	213	1			T88	1		T315	2		T287	1
values[35]	199	1			T88	1		T315	6		T287	1
values[36]	193	1			T88	1		T315	4		T287	1
values[37]	176	1			T88	1		T315	1		T287	1
values[38]	174	1			T88	1		T315	2		T287	1
values[39]	166	1			T88	1		T315	2		T287	1
values[40]	155	1			T88	1		T315	4		T287	1
values[41]	135	1			T88	1		T315	1		T287	1
values[42]	112	1			T88	1		T315	2		T287	1
values[43]	94	1			T88	1		T315	2		T287	1
values[44]	84	1			T88	1		T315	2		T287	1
values[45]	69	1			T88	1		T315	1		T287	1
values[46]	70	1			T88	1		T315	1		T287	1
values[47]	55	1			T88	1		T315	1		T287	1
values[48]	57	1			T88	1		T315	2		T287	1
values[49]	76	1			T88	1		T315	2		T287	1
values[50]	62	1			T88	1		T315	3		T287	1
values[51]	66	1			T88	1		T315	4		T287	1
values[52]	79	1			T88	1		T315	3		T287	1
values[53]	77	1			T88	1		T315	9		T287	1
values[54]	69	1			T88	1		T315	6		T287	1
values[55]	50	1			T88	1		T315	1		T287	1
values[56]	51	1			T88	1		T315	1		T287	1
values[57]	45	1			T88	1		T315	2		T287	1
values[58]	61	1			T88	1		T315	2		T287	1
values[59]	57	1			T88	1		T315	1		T287	1
values[60]	66	1			T88	1		T315	1		T287	1
values[61]	58	1			T88	1		T315	3		T287	1
values[62]	47	1			T88	1		T315	3		T287	1
values[63]	56	1			T88	1		T315	5		T287	1
values[64]	63	1			T88	1		T315	3		T287	1
values[65]	66	1			T88	1		T315	5		T287	1
values[66]	51	1			T88	1		T315	2		T287	1
values[67]	65	1			T88	1		T315	2		T287	1
values[68]	44	1			T88	1		T315	2		T287	1
values[69]	54	1			T88	1		T315	1		T287	1
values[70]	47	1			T88	1		T315	1		T287	1
values[71]	58	1			T88	1		T315	4		T287	1
values[72]	66	1			T88	1		T315	2		T287	1
values[73]	51	1			T88	1		T315	1		T287	1
values[74]	48	1			T88	1		T315	2		T287	1
values[75]	46	1			T88	1		T315	2		T287	1
values[76]	49	1			T88	2		T315	1		T287	1
values[77]	54	1			T88	1		T315	1		T287	1
values[78]	52	1			T88	1		T315	1		T287	1
values[79]	55	1			T88	1		T315	5		T287	1
values[80]	52	1			T88	1		T315	1		T287	1
values[81]	60	1			T88	1		T315	5		T287	1
values[82]	71	1			T88	1		T315	2		T287	1
values[83]	60	1			T88	1		T315	9		T287	1
values[84]	63	1			T88	1		T315	9		T287	1
values[85]	60	1			T88	1		T315	5		T287	1
values[86]	65	1			T88	1		T315	1		T287	1
values[87]	65	1			T88	1		T315	5		T287	1
values[88]	64	1			T88	1		T315	2		T287	1
values[89]	53	1			T88	1		T315	3		T287	1
values[90]	72	1			T88	1		T315	2		T287	1
values[91]	74	1			T88	1		T315	6		T287	1
values[92]	64	1			T88	1		T315	4		T287	1
values[93]	69	1			T88	1		T315	5		T287	1
values[94]	74	1			T88	1		T315	5		T287	1
values[95]	77	1			T88	1		T315	6		T287	1
values[96]	78	1			T88	1		T315	3		T287	1
values[97]	73	1			T88	1		T315	1		T287	1
values[98]	85	1			T88	1		T315	1		T287	1
values[99]	76	1			T88	1		T315	3		T287	1
values[100]	71	1			T88	1		T315	1		T287	1
values[101]	75	1			T88	1		T315	2		T287	1
values[102]	83	1			T88	1		T315	2		T287	1
values[103]	102	1			T88	1		T315	1		T287	1
values[104]	109	1			T88	4		T315	2		T287	1
values[105]	95	1			T88	2		T315	1		T287	1
values[106]	101	1			T88	4		T315	1		T287	1
values[107]	97	1			T88	6		T315	3		T287	2
values[108]	77	1			T88	2		T315	2		T287	1
values[109]	71	1			T88	3		T315	2		T287	2
values[110]	88	1			T88	2		T315	4		T287	2
values[111]	91	1			T88	3		T315	3		T287	2
values[112]	97	1			T88	3		T315	2		T287	2
values[113]	98	1			T88	2		T315	1		T287	2
values[114]	101	1			T88	1		T315	4		T287	1
values[115]	111	1			T88	1		T315	2		T287	2
values[116]	108	1			T88	1		T315	1		T287	1
values[117]	85	1			T88	1		T315	3		T287	1
values[118]	116	1			T88	1		T315	20		T287	5
values[119]	139	1			T88	3		T315	13		T287	2
values[120]	116	1			T88	2		T315	6		T287	2
values[121]	116	1			T88	1		T315	4		T287	2
values[122]	111	1			T88	1		T315	7		T287	2
values[123]	120	1			T88	1		T315	5		T287	3
values[124]	196	1			T88	1		T315	10		T287	6
values[125]	309	1			T88	1		T315	16		T287	1
values[126]	723	1			T88	9		T315	36		T287	5
values[127]	2581	1			T88	84		T315	15		T287	94
values[128]	4995	1			T88	193		T315	1		T287	200