Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145409	1			T4	52		T5	332		T6	68
values[2]	11517	1			T4	1		T5	6		T46	3
values[3]	4459	1			T148	1		T308	6		T72	1
values[4]	2522	1			T148	1		T308	7		T72	2
values[5]	1456	1			T148	5		T308	4		T72	5
values[6]	889	1			T148	4		T72	3		T306	6
values[7]	701	1			T148	6		T72	6		T306	8
values[8]	548	1			T148	2		T72	6		T306	11
values[9]	416	1			T148	1		T72	5		T306	8
values[10]	400	1			T148	2		T72	2		T306	3
values[11]	327	1			T148	2		T72	1		T306	5
values[12]	317	1			T148	1		T72	2		T306	6
values[13]	322	1			T148	2		T72	1		T306	8
values[14]	276	1			T148	1		T72	5		T306	3
values[15]	243	1			T148	2		T72	4		T306	7
values[16]	251	1			T148	1		T72	4		T306	3
values[17]	266	1			T148	3		T72	7		T306	3
values[18]	283	1			T148	2		T72	3		T306	7
values[19]	256	1			T148	1		T72	5		T306	6
values[20]	241	1			T148	2		T72	3		T306	21
values[21]	235	1			T148	5		T72	2		T306	4
values[22]	236	1			T148	1		T72	2		T306	8
values[23]	253	1			T148	3		T72	5		T306	3
values[24]	223	1			T148	1		T72	4		T306	14
values[25]	259	1			T148	2		T72	3		T306	17
values[26]	256	1			T148	1		T72	2		T306	4
values[27]	205	1			T148	1		T72	2		T306	4
values[28]	204	1			T148	4		T72	4		T306	3
values[29]	233	1			T148	1		T72	2		T306	9
values[30]	235	1			T148	1		T72	5		T306	4
values[31]	238	1			T148	3		T72	1		T306	7
values[32]	227	1			T148	2		T72	2		T306	13
values[33]	265	1			T148	2		T72	1		T306	16
values[34]	202	1			T148	1		T72	2		T306	3
values[35]	241	1			T148	3		T72	6		T306	7
values[36]	249	1			T148	6		T72	8		T306	7
values[37]	214	1			T148	3		T72	3		T306	6
values[38]	245	1			T148	3		T72	2		T306	3
values[39]	224	1			T148	3		T72	3		T306	7
values[40]	251	1			T148	2		T72	1		T306	20
values[41]	215	1			T148	3		T72	4		T306	13
values[42]	190	1			T148	5		T72	2		T306	11
values[43]	186	1			T148	2		T72	1		T306	4
values[44]	186	1			T148	2		T72	2		T306	7
values[45]	219	1			T148	1		T72	2		T306	4
values[46]	217	1			T148	3		T72	8		T306	6
values[47]	200	1			T148	3		T72	11		T306	5
values[48]	197	1			T148	8		T72	8		T306	6
values[49]	158	1			T148	11		T72	2		T306	5
values[50]	184	1			T148	12		T72	3		T306	10
values[51]	169	1			T148	6		T72	2		T306	6
values[52]	211	1			T148	1		T72	3		T306	7
values[53]	183	1			T148	1		T72	1		T306	6
values[54]	205	1			T148	4		T72	2		T306	6
values[55]	167	1			T148	6		T72	5		T306	10
values[56]	182	1			T148	6		T72	2		T306	8
values[57]	168	1			T148	4		T72	1		T306	6
values[58]	143	1			T148	3		T72	1		T306	9
values[59]	149	1			T148	2		T72	5		T306	3
values[60]	155	1			T148	3		T72	1		T321	1
values[61]	157	1			T148	5		T72	1		T321	1
values[62]	166	1			T148	5		T72	3		T321	1
values[63]	140	1			T148	4		T72	4		T321	1
values[64]	134	1			T148	2		T72	3		T321	1
values[65]	113	1			T148	7		T72	6		T321	1
values[66]	108	1			T148	6		T72	5		T321	1
values[67]	99	1			T148	7		T72	4		T321	1
values[68]	82	1			T148	9		T72	2		T321	1
values[69]	99	1			T148	1		T72	1		T321	1
values[70]	94	1			T148	1		T72	2		T321	1
values[71]	82	1			T148	2		T72	2		T321	1
values[72]	70	1			T148	3		T72	2		T321	1
values[73]	55	1			T148	1		T72	2		T321	1
values[74]	68	1			T148	2		T72	7		T321	1
values[75]	56	1			T148	2		T72	6		T321	1
values[76]	50	1			T148	3		T72	2		T321	1
values[77]	53	1			T148	5		T72	3		T321	1
values[78]	63	1			T148	5		T72	12		T321	1
values[79]	64	1			T148	5		T72	7		T321	1
values[80]	38	1			T148	1		T72	4		T321	1
values[81]	56	1			T148	9		T72	4		T321	1
values[82]	55	1			T148	4		T72	7		T321	1
values[83]	44	1			T148	7		T72	2		T321	1
values[84]	58	1			T148	8		T72	8		T321	1
values[85]	60	1			T148	7		T72	7		T321	1
values[86]	54	1			T148	3		T72	5		T321	1
values[87]	54	1			T148	4		T72	7		T321	1
values[88]	57	1			T148	5		T72	6		T321	1
values[89]	56	1			T148	2		T72	10		T321	1
values[90]	45	1			T148	2		T72	2		T321	1
values[91]	65	1			T148	7		T72	6		T321	1
values[92]	66	1			T148	6		T72	6		T321	1
values[93]	52	1			T148	6		T72	3		T321	2
values[94]	42	1			T148	3		T72	2		T321	1
values[95]	56	1			T148	6		T72	4		T321	1
values[96]	67	1			T148	4		T72	10		T321	1
values[97]	73	1			T148	3		T72	7		T321	1
values[98]	80	1			T148	7		T72	4		T321	1
values[99]	74	1			T148	7		T72	5		T321	1
values[100]	80	1			T148	4		T72	5		T321	1
values[101]	55	1			T148	6		T72	6		T321	1
values[102]	50	1			T148	3		T72	2		T321	1
values[103]	66	1			T148	8		T72	4		T321	1
values[104]	54	1			T148	5		T72	5		T321	1
values[105]	68	1			T148	7		T72	7		T321	1
values[106]	75	1			T148	4		T72	2		T321	1
values[107]	60	1			T148	5		T72	1		T321	1
values[108]	53	1			T148	5		T72	2		T321	1
values[109]	71	1			T148	5		T72	6		T321	1
values[110]	63	1			T148	5		T72	6		T321	1
values[111]	63	1			T148	5		T72	6		T321	1
values[112]	58	1			T148	9		T72	8		T321	1
values[113]	69	1			T148	3		T72	4		T321	1
values[114]	47	1			T148	3		T72	1		T321	1
values[115]	45	1			T148	1		T72	2		T321	3
values[116]	58	1			T148	3		T72	3		T321	1
values[117]	55	1			T148	1		T72	3		T321	1
values[118]	57	1			T148	6		T72	1		T321	2
values[119]	55	1			T148	4		T72	1		T321	2
values[120]	46	1			T148	3		T72	3		T321	2
values[121]	50	1			T148	4		T72	1		T321	5
values[122]	54	1			T148	2		T72	7		T321	2
values[123]	63	1			T148	1		T72	5		T321	1
values[124]	77	1			T148	4		T72	6		T321	1
values[125]	64	1			T148	2		T72	6		T321	1
values[126]	126	1			T148	11		T72	13		T321	2
values[127]	649	1			T148	26		T72	8		T321	33
values[128]	4498	1			T148	9		T72	4		T321	327